drivers/gpu/drm/nouveau/nv50_graph.c

   1 /*
   2  * Copyright (C) 2007 Ben Skeggs.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining
   6  * a copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sublicense, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the
  14  * next paragraph) shall be included in all copies or substantial
  15  * portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  18  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  19  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  20  * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  21  * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  22  * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  23  * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  24  *
  25  */
  26
  27 #include "drmP.h"
  28 #include "drm.h"
  29 #include "nouveau_drv.h"
  30 #include "nouveau_ramht.h"
  31 #include "nouveau_grctx.h"
  32 #include "nouveau_dma.h"
  33 #include "nv50_evo.h"
  34
  35 static int nv50_graph_register(struct drm_device *);
  36
  37 static void
  38 nv50_graph_init_reset(struct drm_device *dev)
  39 {
  40         uint32_t pmc_e = NV_PMC_ENABLE_PGRAPH | (1 << 21);
  41
  42         NV_DEBUG(dev, "\n");
  43
  44         nv_wr32(dev, NV03_PMC_ENABLE, nv_rd32(dev, NV03_PMC_ENABLE) & ~pmc_e);
  45         nv_wr32(dev, NV03_PMC_ENABLE, nv_rd32(dev, NV03_PMC_ENABLE) |  pmc_e);
  46 }
  47
  48 static void
  49 nv50_graph_init_intr(struct drm_device *dev)
  50 {
  51         NV_DEBUG(dev, "\n");
  52
  53         nv_wr32(dev, NV03_PGRAPH_INTR, 0xffffffff);
  54         nv_wr32(dev, 0x400138, 0xffffffff);
  55         nv_wr32(dev, NV40_PGRAPH_INTR_EN, 0xffffffff);
  56 }
  57
  58 static void
  59 nv50_graph_init_regs__nv(struct drm_device *dev)
  60 {
  61         struct drm_nouveau_private *dev_priv = dev->dev_private;
  62         uint32_t units = nv_rd32(dev, 0x1540);
  63         int i;
  64
  65         NV_DEBUG(dev, "\n");
  66
  67         nv_wr32(dev, 0x400804, 0xc0000000);
  68         nv_wr32(dev, 0x406800, 0xc0000000);
  69         nv_wr32(dev, 0x400c04, 0xc0000000);
  70         nv_wr32(dev, 0x401800, 0xc0000000);
  71         nv_wr32(dev, 0x405018, 0xc0000000);
  72         nv_wr32(dev, 0x402000, 0xc0000000);
  73
  74         for (i = 0; i < 16; i++) {
  75                 if (units & 1 << i) {
  76                         if (dev_priv->chipset < 0xa0) {
  77                                 nv_wr32(dev, 0x408900 + (i << 12), 0xc0000000);
  78                                 nv_wr32(dev, 0x408e08 + (i << 12), 0xc0000000);
  79                                 nv_wr32(dev, 0x408314 + (i << 12), 0xc0000000);
  80                         } else {
  81                                 nv_wr32(dev, 0x408600 + (i << 11), 0xc0000000);
  82                                 nv_wr32(dev, 0x408708 + (i << 11), 0xc0000000);
  83                                 nv_wr32(dev, 0x40831c + (i << 11), 0xc0000000);
  84                         }
  85                 }
  86         }
  87
  88         nv_wr32(dev, 0x400108, 0xffffffff);
  89
  90         nv_wr32(dev, 0x400824, 0x00004000);
  91         nv_wr32(dev, 0x400500, 0x00010001);
  92 }
  93
  94 static void
  95 nv50_graph_init_regs(struct drm_device *dev)
  96 {
  97         NV_DEBUG(dev, "\n");
  98
  99         nv_wr32(dev, NV04_PGRAPH_DEBUG_3,
 100                                 (1 << 2) /* HW_CONTEXT_SWITCH_ENABLED */);
 101         nv_wr32(dev, 0x402ca8, 0x800);
 102 }
 103
 104 static int
 105 nv50_graph_init_ctxctl(struct drm_device *dev)
 106 {
 107         struct drm_nouveau_private *dev_priv = dev->dev_private;
 108         struct nouveau_grctx ctx = {};
 109         uint32_t *cp;
 110         int i;
 111
 112         NV_DEBUG(dev, "\n");
 113
 114         cp = kmalloc(512 * 4, GFP_KERNEL);
 115         if (!cp) {
 116                 NV_ERROR(dev, "failed to allocate ctxprog\n");
 117                 dev_priv->engine.graph.accel_blocked = true;
 118                 return 0;
 119         }
 120
 121         ctx.dev = dev;
 122         ctx.mode = NOUVEAU_GRCTX_PROG;
 123         ctx.data = cp;
 124         ctx.ctxprog_max = 512;
 125         if (!nv50_grctx_init(&ctx)) {
 126                 dev_priv->engine.graph.grctx_size = ctx.ctxvals_pos * 4;
 127
 128                 nv_wr32(dev, NV40_PGRAPH_CTXCTL_UCODE_INDEX, 0);
 129                 for (i = 0; i < ctx.ctxprog_len; i++)
 130                         nv_wr32(dev, NV40_PGRAPH_CTXCTL_UCODE_DATA, cp[i]);
 131         } else {
 132                 dev_priv->engine.graph.accel_blocked = true;
 133         }
 134         kfree(cp);
 135
 136         nv_wr32(dev, 0x400320, 4);
 137         nv_wr32(dev, NV40_PGRAPH_CTXCTL_CUR, 0);
 138         nv_wr32(dev, NV20_PGRAPH_CHANNEL_CTX_POINTER, 0);
 139         return 0;
 140 }
 141
 142 int
 143 nv50_graph_init(struct drm_device *dev)
 144 {
 145         int ret;
 146
 147         NV_DEBUG(dev, "\n");
 148
 149         nv50_graph_init_reset(dev);
 150         nv50_graph_init_regs__nv(dev);
 151         nv50_graph_init_regs(dev);
 152
 153         ret = nv50_graph_init_ctxctl(dev);
 154         if (ret)
 155                 return ret;
 156
 157         ret = nv50_graph_register(dev);
 158         if (ret)
 159                 return ret;
 160         nv50_graph_init_intr(dev);
 161         return 0;
 162 }
 163
 164 void
 165 nv50_graph_takedown(struct drm_device *dev)
 166 {
 167         NV_DEBUG(dev, "\n");
 168 }
 169
 170 void
 171 nv50_graph_fifo_access(struct drm_device *dev, bool enabled)
 172 {
 173         const uint32_t mask = 0x00010001;
 174
 175         if (enabled)
 176                 nv_wr32(dev, 0x400500, nv_rd32(dev, 0x400500) | mask);
 177         else
 178                 nv_wr32(dev, 0x400500, nv_rd32(dev, 0x400500) & ~mask);
 179 }
 180
 181 struct nouveau_channel *
 182 nv50_graph_channel(struct drm_device *dev)
 183 {
 184         struct drm_nouveau_private *dev_priv = dev->dev_private;
 185         uint32_t inst;
 186         int i;
 187
 188         /* Be sure we're not in the middle of a context switch or bad things
 189          * will happen, such as unloading the wrong pgraph context.
 190          */
 191         if (!nv_wait(dev, 0x400300, 0x00000001, 0x00000000))
 192                 NV_ERROR(dev, "Ctxprog is still running\n");
 193
 194         inst = nv_rd32(dev, NV50_PGRAPH_CTXCTL_CUR);
 195         if (!(inst & NV50_PGRAPH_CTXCTL_CUR_LOADED))
 196                 return NULL;
 197         inst = (inst & NV50_PGRAPH_CTXCTL_CUR_INSTANCE) << 12;
 198
 199         for (i = 0; i < dev_priv->engine.fifo.channels; i++) {
 200                 struct nouveau_channel *chan = dev_priv->channels.ptr[i];
 201
 202                 if (chan && chan->ramin && chan->ramin->vinst == inst)
 203                         return chan;
 204         }
 205
 206         return NULL;
 207 }
 208
 209 int
 210 nv50_graph_create_context(struct nouveau_channel *chan)
 211 {
 212         struct drm_device *dev = chan->dev;
 213         struct drm_nouveau_private *dev_priv = dev->dev_private;
 214         struct nouveau_gpuobj *ramin = chan->ramin;
 215         struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
 216         struct nouveau_grctx ctx = {};
 217         int hdr, ret;
 218
 219         NV_DEBUG(dev, "ch%d\n", chan->id);
 220
 221         ret = nouveau_gpuobj_new(dev, chan, pgraph->grctx_size, 0,
 222                                  NVOBJ_FLAG_ZERO_ALLOC |
 223                                  NVOBJ_FLAG_ZERO_FREE, &chan->ramin_grctx);
 224         if (ret)
 225                 return ret;
 226
 227         hdr = (dev_priv->chipset == 0x50) ? 0x200 : 0x20;
 228         nv_wo32(ramin, hdr + 0x00, 0x00190002);
 229         nv_wo32(ramin, hdr + 0x04, chan->ramin_grctx->vinst +
 230                                    pgraph->grctx_size - 1);
 231         nv_wo32(ramin, hdr + 0x08, chan->ramin_grctx->vinst);
 232         nv_wo32(ramin, hdr + 0x0c, 0);
 233         nv_wo32(ramin, hdr + 0x10, 0);
 234         nv_wo32(ramin, hdr + 0x14, 0x00010000);
 235
 236         ctx.dev = chan->dev;
 237         ctx.mode = NOUVEAU_GRCTX_VALS;
 238         ctx.data = chan->ramin_grctx;
 239         nv50_grctx_init(&ctx);
 240
 241         nv_wo32(chan->ramin_grctx, 0x00000, chan->ramin->vinst >> 12);
 242
 243         dev_priv->engine.instmem.flush(dev);
 244         return 0;
 245 }
 246
 247 void
 248 nv50_graph_destroy_context(struct nouveau_channel *chan)
 249 {
 250         struct drm_device *dev = chan->dev;
 251         struct drm_nouveau_private *dev_priv = dev->dev_private;
 252         struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
 253         int i, hdr = (dev_priv->chipset == 0x50) ? 0x200 : 0x20;
 254         unsigned long flags;
 255
 256         NV_DEBUG(dev, "ch%d\n", chan->id);
 257
 258         if (!chan->ramin)
 259                 return;
 260
 261         spin_lock_irqsave(&dev_priv->context_switch_lock, flags);
 262         pgraph->fifo_access(dev, false);
 263
 264         if (pgraph->channel(dev) == chan)
 265                 pgraph->unload_context(dev);
 266
 267         for (i = hdr; i < hdr + 24; i += 4)
 268                 nv_wo32(chan->ramin, i, 0);
 269         dev_priv->engine.instmem.flush(dev);
 270
 271         pgraph->fifo_access(dev, true);
 272         spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags);
 273
 274         nouveau_gpuobj_ref(NULL, &chan->ramin_grctx);
 275 }
 276
 277 static int
 278 nv50_graph_do_load_context(struct drm_device *dev, uint32_t inst)
 279 {
 280         uint32_t fifo = nv_rd32(dev, 0x400500);
 281
 282         nv_wr32(dev, 0x400500, fifo & ~1);
 283         nv_wr32(dev, 0x400784, inst);
 284         nv_wr32(dev, 0x400824, nv_rd32(dev, 0x400824) | 0x40);
 285         nv_wr32(dev, 0x400320, nv_rd32(dev, 0x400320) | 0x11);
 286         nv_wr32(dev, 0x400040, 0xffffffff);
 287         (void)nv_rd32(dev, 0x400040);
 288         nv_wr32(dev, 0x400040, 0x00000000);
 289         nv_wr32(dev, 0x400304, nv_rd32(dev, 0x400304) | 1);
 290
 291         if (nouveau_wait_for_idle(dev))
 292                 nv_wr32(dev, 0x40032c, inst | (1<<31));
 293         nv_wr32(dev, 0x400500, fifo);
 294
 295         return 0;
 296 }
 297
 298 int
 299 nv50_graph_load_context(struct nouveau_channel *chan)
 300 {
 301         uint32_t inst = chan->ramin->vinst >> 12;
 302
 303         NV_DEBUG(chan->dev, "ch%d\n", chan->id);
 304         return nv50_graph_do_load_context(chan->dev, inst);
 305 }
 306
 307 int
 308 nv50_graph_unload_context(struct drm_device *dev)
 309 {
 310         uint32_t inst;
 311
 312         inst  = nv_rd32(dev, NV50_PGRAPH_CTXCTL_CUR);
 313         if (!(inst & NV50_PGRAPH_CTXCTL_CUR_LOADED))
 314                 return 0;
 315         inst &= NV50_PGRAPH_CTXCTL_CUR_INSTANCE;
 316
 317         nouveau_wait_for_idle(dev);
 318         nv_wr32(dev, 0x400784, inst);
 319         nv_wr32(dev, 0x400824, nv_rd32(dev, 0x400824) | 0x20);
 320         nv_wr32(dev, 0x400304, nv_rd32(dev, 0x400304) | 0x01);
 321         nouveau_wait_for_idle(dev);
 322
 323         nv_wr32(dev, NV50_PGRAPH_CTXCTL_CUR, inst);
 324         return 0;
 325 }
 326
 327 void
 328 nv50_graph_context_switch(struct drm_device *dev)
 329 {
 330         uint32_t inst;
 331
 332         nv50_graph_unload_context(dev);
 333
 334         inst  = nv_rd32(dev, NV50_PGRAPH_CTXCTL_NEXT);
 335         inst &= NV50_PGRAPH_CTXCTL_NEXT_INSTANCE;
 336         nv50_graph_do_load_context(dev, inst);
 337
 338         nv_wr32(dev, NV40_PGRAPH_INTR_EN, nv_rd32(dev,
 339                 NV40_PGRAPH_INTR_EN) | NV_PGRAPH_INTR_CONTEXT_SWITCH);
 340 }
 341
 342 static int
 343 nv50_graph_nvsw_dma_vblsem(struct nouveau_channel *chan,
 344                            u32 class, u32 mthd, u32 data)
 345 {
 346         struct nouveau_gpuobj *gpuobj;
 347
 348         gpuobj = nouveau_ramht_find(chan, data);
 349         if (!gpuobj)
 350                 return -ENOENT;
 351
 352         if (nouveau_notifier_offset(gpuobj, NULL))
 353                 return -EINVAL;
 354
 355         chan->nvsw.vblsem = gpuobj;
 356         chan->nvsw.vblsem_offset = ~0;
 357         return 0;
 358 }
 359
 360 static int
 361 nv50_graph_nvsw_vblsem_offset(struct nouveau_channel *chan,
 362                               u32 class, u32 mthd, u32 data)
 363 {
 364         if (nouveau_notifier_offset(chan->nvsw.vblsem, &data))
 365                 return -ERANGE;
 366
 367         chan->nvsw.vblsem_offset = data >> 2;
 368         return 0;
 369 }
 370
 371 static int
 372 nv50_graph_nvsw_vblsem_release_val(struct nouveau_channel *chan,
 373                                    u32 class, u32 mthd, u32 data)
 374 {
 375         chan->nvsw.vblsem_rval = data;
 376         return 0;
 377 }
 378
 379 static int
 380 nv50_graph_nvsw_vblsem_release(struct nouveau_channel *chan,
 381                                u32 class, u32 mthd, u32 data)
 382 {
 383         struct drm_device *dev = chan->dev;
 384         struct drm_nouveau_private *dev_priv = dev->dev_private;
 385
 386         if (!chan->nvsw.vblsem || chan->nvsw.vblsem_offset == ~0 || data > 1)
 387                 return -EINVAL;
 388
 389         drm_vblank_get(dev, data);
 390
 391         chan->nvsw.vblsem_head = data;
 392         list_add(&chan->nvsw.vbl_wait, &dev_priv->vbl_waiting);
 393
 394         return 0;
 395 }
 396
 397 static int
 398 nv50_graph_nvsw_mthd_page_flip(struct nouveau_channel *chan,
 399                                u32 class, u32 mthd, u32 data)
 400 {
 401         struct nouveau_page_flip_state s;
 402
 403         if (!nouveau_finish_page_flip(chan, &s)) {
 404                 /* XXX - Do something here */
 405         }
 406
 407         return 0;
 408 }
 409
 410 static int
 411 nv50_graph_register(struct drm_device *dev)
 412 {
 413         struct drm_nouveau_private *dev_priv = dev->dev_private;
 414
 415         if (dev_priv->engine.graph.registered)
 416                 return 0;
 417
 418         NVOBJ_CLASS(dev, 0x506e, SW); /* nvsw */
 419         NVOBJ_MTHD (dev, 0x506e, 0x018c, nv50_graph_nvsw_dma_vblsem);
 420         NVOBJ_MTHD (dev, 0x506e, 0x0400, nv50_graph_nvsw_vblsem_offset);
 421         NVOBJ_MTHD (dev, 0x506e, 0x0404, nv50_graph_nvsw_vblsem_release_val);
 422         NVOBJ_MTHD (dev, 0x506e, 0x0408, nv50_graph_nvsw_vblsem_release);
 423         NVOBJ_MTHD (dev, 0x506e, 0x0500, nv50_graph_nvsw_mthd_page_flip);
 424
 425         NVOBJ_CLASS(dev, 0x0030, GR); /* null */
 426         NVOBJ_CLASS(dev, 0x5039, GR); /* m2mf */
 427         NVOBJ_CLASS(dev, 0x502d, GR); /* 2d */
 428
 429         /* tesla */
 430         if (dev_priv->chipset == 0x50)
 431                 NVOBJ_CLASS(dev, 0x5097, GR); /* tesla (nv50) */
 432         else
 433         if (dev_priv->chipset < 0xa0)
 434                 NVOBJ_CLASS(dev, 0x8297, GR); /* tesla (nv8x/nv9x) */
 435         else {
 436                 switch (dev_priv->chipset) {
 437                 case 0xa0:
 438                 case 0xaa:
 439                 case 0xac:
 440                         NVOBJ_CLASS(dev, 0x8397, GR);
 441                         break;
 442                 case 0xa3:
 443                 case 0xa5:
 444                 case 0xa8:
 445                         NVOBJ_CLASS(dev, 0x8597, GR);
 446                         break;
 447                 case 0xaf:
 448                         NVOBJ_CLASS(dev, 0x8697, GR);
 449                         break;
 450                 }
 451         }
 452
 453         /* compute */
 454         NVOBJ_CLASS(dev, 0x50c0, GR);
 455         if (dev_priv->chipset  > 0xa0 &&
 456             dev_priv->chipset != 0xaa &&
 457             dev_priv->chipset != 0xac)
 458                 NVOBJ_CLASS(dev, 0x85c0, GR);
 459
 460         dev_priv->engine.graph.registered = true;
 461         return 0;
 462 }
 463
 464 void
 465 nv50_graph_tlb_flush(struct drm_device *dev)
 466 {
 467         nv50_vm_flush(dev, 0);
 468 }
 469
 470 void
 471 nv86_graph_tlb_flush(struct drm_device *dev)
 472 {
 473         struct drm_nouveau_private *dev_priv = dev->dev_private;
 474         struct nouveau_timer_engine *ptimer = &dev_priv->engine.timer;
 475         bool idle, timeout = false;
 476         unsigned long flags;
 477         u64 start;
 478         u32 tmp;
 479
 480         spin_lock_irqsave(&dev_priv->context_switch_lock, flags);
 481         nv_mask(dev, 0x400500, 0x00000001, 0x00000000);
 482
 483         start = ptimer->read(dev);
 484         do {
 485                 idle = true;
 486
 487                 for (tmp = nv_rd32(dev, 0x400380); tmp && idle; tmp >>= 3) {
 488                         if ((tmp & 7) == 1)
 489                                 idle = false;
 490                 }
 491
 492                 for (tmp = nv_rd32(dev, 0x400384); tmp && idle; tmp >>= 3) {
 493                         if ((tmp & 7) == 1)
 494                                 idle = false;
 495                 }
 496
 497                 for (tmp = nv_rd32(dev, 0x400388); tmp && idle; tmp >>= 3) {
 498                         if ((tmp & 7) == 1)
 499                                 idle = false;
 500                 }
 501         } while (!idle && !(timeout = ptimer->read(dev) - start > 2000000000));
 502
 503         if (timeout) {
 504                 NV_ERROR(dev, "PGRAPH TLB flush idle timeout fail: "
 505                               "0x%08x 0x%08x 0x%08x 0x%08x\n",
 506                          nv_rd32(dev, 0x400700), nv_rd32(dev, 0x400380),
 507                          nv_rd32(dev, 0x400384), nv_rd32(dev, 0x400388));
 508         }
 509
 510         nv50_vm_flush(dev, 0);
 511
 512         nv_mask(dev, 0x400500, 0x00000001, 0x00000001);
 513         spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags);
 514 }