drivers/gpu/drm/nouveau/nv50_graph.c

   1 /*
   2  * Copyright (C) 2007 Ben Skeggs.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining
   6  * a copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sublicense, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the
  14  * next paragraph) shall be included in all copies or substantial
  15  * portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  18  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  19  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  20  * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  21  * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  22  * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  23  * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  24  *
  25  */
  26
  27 #include "drmP.h"
  28 #include "drm.h"
  29 #include "nouveau_drv.h"
  30 #include "nouveau_ramht.h"
  31 #include "nouveau_grctx.h"
  32
  33 static int nv50_graph_register(struct drm_device *);
  34
  35 static void
  36 nv50_graph_init_reset(struct drm_device *dev)
  37 {
  38         uint32_t pmc_e = NV_PMC_ENABLE_PGRAPH | (1 << 21);
  39
  40         NV_DEBUG(dev, "\n");
  41
  42         nv_wr32(dev, NV03_PMC_ENABLE, nv_rd32(dev, NV03_PMC_ENABLE) & ~pmc_e);
  43         nv_wr32(dev, NV03_PMC_ENABLE, nv_rd32(dev, NV03_PMC_ENABLE) |  pmc_e);
  44 }
  45
  46 static void
  47 nv50_graph_init_intr(struct drm_device *dev)
  48 {
  49         NV_DEBUG(dev, "\n");
  50
  51         nv_wr32(dev, NV03_PGRAPH_INTR, 0xffffffff);
  52         nv_wr32(dev, 0x400138, 0xffffffff);
  53         nv_wr32(dev, NV40_PGRAPH_INTR_EN, 0xffffffff);
  54 }
  55
  56 static void
  57 nv50_graph_init_regs__nv(struct drm_device *dev)
  58 {
  59         struct drm_nouveau_private *dev_priv = dev->dev_private;
  60         uint32_t units = nv_rd32(dev, 0x1540);
  61         int i;
  62
  63         NV_DEBUG(dev, "\n");
  64
  65         nv_wr32(dev, 0x400804, 0xc0000000);
  66         nv_wr32(dev, 0x406800, 0xc0000000);
  67         nv_wr32(dev, 0x400c04, 0xc0000000);
  68         nv_wr32(dev, 0x401800, 0xc0000000);
  69         nv_wr32(dev, 0x405018, 0xc0000000);
  70         nv_wr32(dev, 0x402000, 0xc0000000);
  71
  72         for (i = 0; i < 16; i++) {
  73                 if (units & 1 << i) {
  74                         if (dev_priv->chipset < 0xa0) {
  75                                 nv_wr32(dev, 0x408900 + (i << 12), 0xc0000000);
  76                                 nv_wr32(dev, 0x408e08 + (i << 12), 0xc0000000);
  77                                 nv_wr32(dev, 0x408314 + (i << 12), 0xc0000000);
  78                         } else {
  79                                 nv_wr32(dev, 0x408600 + (i << 11), 0xc0000000);
  80                                 nv_wr32(dev, 0x408708 + (i << 11), 0xc0000000);
  81                                 nv_wr32(dev, 0x40831c + (i << 11), 0xc0000000);
  82                         }
  83                 }
  84         }
  85
  86         nv_wr32(dev, 0x400108, 0xffffffff);
  87
  88         nv_wr32(dev, 0x400824, 0x00004000);
  89         nv_wr32(dev, 0x400500, 0x00010001);
  90 }
  91
  92 static void
  93 nv50_graph_init_regs(struct drm_device *dev)
  94 {
  95         NV_DEBUG(dev, "\n");
  96
  97         nv_wr32(dev, NV04_PGRAPH_DEBUG_3,
  98                                 (1 << 2) /* HW_CONTEXT_SWITCH_ENABLED */);
  99         nv_wr32(dev, 0x402ca8, 0x800);
 100 }
 101
 102 static int
 103 nv50_graph_init_ctxctl(struct drm_device *dev)
 104 {
 105         struct drm_nouveau_private *dev_priv = dev->dev_private;
 106         struct nouveau_grctx ctx = {};
 107         uint32_t *cp;
 108         int i;
 109
 110         NV_DEBUG(dev, "\n");
 111
 112         cp = kmalloc(512 * 4, GFP_KERNEL);
 113         if (!cp) {
 114                 NV_ERROR(dev, "failed to allocate ctxprog\n");
 115                 dev_priv->engine.graph.accel_blocked = true;
 116                 return 0;
 117         }
 118
 119         ctx.dev = dev;
 120         ctx.mode = NOUVEAU_GRCTX_PROG;
 121         ctx.data = cp;
 122         ctx.ctxprog_max = 512;
 123         if (!nv50_grctx_init(&ctx)) {
 124                 dev_priv->engine.graph.grctx_size = ctx.ctxvals_pos * 4;
 125
 126                 nv_wr32(dev, NV40_PGRAPH_CTXCTL_UCODE_INDEX, 0);
 127                 for (i = 0; i < ctx.ctxprog_len; i++)
 128                         nv_wr32(dev, NV40_PGRAPH_CTXCTL_UCODE_DATA, cp[i]);
 129         } else {
 130                 dev_priv->engine.graph.accel_blocked = true;
 131         }
 132         kfree(cp);
 133
 134         nv_wr32(dev, 0x400320, 4);
 135         nv_wr32(dev, NV40_PGRAPH_CTXCTL_CUR, 0);
 136         nv_wr32(dev, NV20_PGRAPH_CHANNEL_CTX_POINTER, 0);
 137         return 0;
 138 }
 139
 140 int
 141 nv50_graph_init(struct drm_device *dev)
 142 {
 143         int ret;
 144
 145         NV_DEBUG(dev, "\n");
 146
 147         nv50_graph_init_reset(dev);
 148         nv50_graph_init_regs__nv(dev);
 149         nv50_graph_init_regs(dev);
 150
 151         ret = nv50_graph_init_ctxctl(dev);
 152         if (ret)
 153                 return ret;
 154
 155         ret = nv50_graph_register(dev);
 156         if (ret)
 157                 return ret;
 158         nv50_graph_init_intr(dev);
 159         return 0;
 160 }
 161
 162 void
 163 nv50_graph_takedown(struct drm_device *dev)
 164 {
 165         NV_DEBUG(dev, "\n");
 166 }
 167
 168 void
 169 nv50_graph_fifo_access(struct drm_device *dev, bool enabled)
 170 {
 171         const uint32_t mask = 0x00010001;
 172
 173         if (enabled)
 174                 nv_wr32(dev, 0x400500, nv_rd32(dev, 0x400500) | mask);
 175         else
 176                 nv_wr32(dev, 0x400500, nv_rd32(dev, 0x400500) & ~mask);
 177 }
 178
 179 struct nouveau_channel *
 180 nv50_graph_channel(struct drm_device *dev)
 181 {
 182         struct drm_nouveau_private *dev_priv = dev->dev_private;
 183         uint32_t inst;
 184         int i;
 185
 186         /* Be sure we're not in the middle of a context switch or bad things
 187          * will happen, such as unloading the wrong pgraph context.
 188          */
 189         if (!nv_wait(dev, 0x400300, 0x00000001, 0x00000000))
 190                 NV_ERROR(dev, "Ctxprog is still running\n");
 191
 192         inst = nv_rd32(dev, NV50_PGRAPH_CTXCTL_CUR);
 193         if (!(inst & NV50_PGRAPH_CTXCTL_CUR_LOADED))
 194                 return NULL;
 195         inst = (inst & NV50_PGRAPH_CTXCTL_CUR_INSTANCE) << 12;
 196
 197         for (i = 0; i < dev_priv->engine.fifo.channels; i++) {
 198                 struct nouveau_channel *chan = dev_priv->channels.ptr[i];
 199
 200                 if (chan && chan->ramin && chan->ramin->vinst == inst)
 201                         return chan;
 202         }
 203
 204         return NULL;
 205 }
 206
 207 int
 208 nv50_graph_create_context(struct nouveau_channel *chan)
 209 {
 210         struct drm_device *dev = chan->dev;
 211         struct drm_nouveau_private *dev_priv = dev->dev_private;
 212         struct nouveau_gpuobj *ramin = chan->ramin;
 213         struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
 214         struct nouveau_grctx ctx = {};
 215         int hdr, ret;
 216
 217         NV_DEBUG(dev, "ch%d\n", chan->id);
 218
 219         ret = nouveau_gpuobj_new(dev, chan, pgraph->grctx_size, 0,
 220                                  NVOBJ_FLAG_ZERO_ALLOC |
 221                                  NVOBJ_FLAG_ZERO_FREE, &chan->ramin_grctx);
 222         if (ret)
 223                 return ret;
 224
 225         hdr = (dev_priv->chipset == 0x50) ? 0x200 : 0x20;
 226         nv_wo32(ramin, hdr + 0x00, 0x00190002);
 227         nv_wo32(ramin, hdr + 0x04, chan->ramin_grctx->vinst +
 228                                    pgraph->grctx_size - 1);
 229         nv_wo32(ramin, hdr + 0x08, chan->ramin_grctx->vinst);
 230         nv_wo32(ramin, hdr + 0x0c, 0);
 231         nv_wo32(ramin, hdr + 0x10, 0);
 232         nv_wo32(ramin, hdr + 0x14, 0x00010000);
 233
 234         ctx.dev = chan->dev;
 235         ctx.mode = NOUVEAU_GRCTX_VALS;
 236         ctx.data = chan->ramin_grctx;
 237         nv50_grctx_init(&ctx);
 238
 239         nv_wo32(chan->ramin_grctx, 0x00000, chan->ramin->vinst >> 12);
 240
 241         dev_priv->engine.instmem.flush(dev);
 242         return 0;
 243 }
 244
 245 void
 246 nv50_graph_destroy_context(struct nouveau_channel *chan)
 247 {
 248         struct drm_device *dev = chan->dev;
 249         struct drm_nouveau_private *dev_priv = dev->dev_private;
 250         struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
 251         int i, hdr = (dev_priv->chipset == 0x50) ? 0x200 : 0x20;
 252         unsigned long flags;
 253
 254         NV_DEBUG(dev, "ch%d\n", chan->id);
 255
 256         if (!chan->ramin)
 257                 return;
 258
 259         spin_lock_irqsave(&dev_priv->context_switch_lock, flags);
 260         pgraph->fifo_access(dev, false);
 261
 262         if (pgraph->channel(dev) == chan)
 263                 pgraph->unload_context(dev);
 264
 265         for (i = hdr; i < hdr + 24; i += 4)
 266                 nv_wo32(chan->ramin, i, 0);
 267         dev_priv->engine.instmem.flush(dev);
 268
 269         pgraph->fifo_access(dev, true);
 270         spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags);
 271
 272         nouveau_gpuobj_ref(NULL, &chan->ramin_grctx);
 273 }
 274
 275 static int
 276 nv50_graph_do_load_context(struct drm_device *dev, uint32_t inst)
 277 {
 278         uint32_t fifo = nv_rd32(dev, 0x400500);
 279
 280         nv_wr32(dev, 0x400500, fifo & ~1);
 281         nv_wr32(dev, 0x400784, inst);
 282         nv_wr32(dev, 0x400824, nv_rd32(dev, 0x400824) | 0x40);
 283         nv_wr32(dev, 0x400320, nv_rd32(dev, 0x400320) | 0x11);
 284         nv_wr32(dev, 0x400040, 0xffffffff);
 285         (void)nv_rd32(dev, 0x400040);
 286         nv_wr32(dev, 0x400040, 0x00000000);
 287         nv_wr32(dev, 0x400304, nv_rd32(dev, 0x400304) | 1);
 288
 289         if (nouveau_wait_for_idle(dev))
 290                 nv_wr32(dev, 0x40032c, inst | (1<<31));
 291         nv_wr32(dev, 0x400500, fifo);
 292
 293         return 0;
 294 }
 295
 296 int
 297 nv50_graph_load_context(struct nouveau_channel *chan)
 298 {
 299         uint32_t inst = chan->ramin->vinst >> 12;
 300
 301         NV_DEBUG(chan->dev, "ch%d\n", chan->id);
 302         return nv50_graph_do_load_context(chan->dev, inst);
 303 }
 304
 305 int
 306 nv50_graph_unload_context(struct drm_device *dev)
 307 {
 308         uint32_t inst;
 309
 310         inst  = nv_rd32(dev, NV50_PGRAPH_CTXCTL_CUR);
 311         if (!(inst & NV50_PGRAPH_CTXCTL_CUR_LOADED))
 312                 return 0;
 313         inst &= NV50_PGRAPH_CTXCTL_CUR_INSTANCE;
 314
 315         nouveau_wait_for_idle(dev);
 316         nv_wr32(dev, 0x400784, inst);
 317         nv_wr32(dev, 0x400824, nv_rd32(dev, 0x400824) | 0x20);
 318         nv_wr32(dev, 0x400304, nv_rd32(dev, 0x400304) | 0x01);
 319         nouveau_wait_for_idle(dev);
 320
 321         nv_wr32(dev, NV50_PGRAPH_CTXCTL_CUR, inst);
 322         return 0;
 323 }
 324
 325 void
 326 nv50_graph_context_switch(struct drm_device *dev)
 327 {
 328         uint32_t inst;
 329
 330         nv50_graph_unload_context(dev);
 331
 332         inst  = nv_rd32(dev, NV50_PGRAPH_CTXCTL_NEXT);
 333         inst &= NV50_PGRAPH_CTXCTL_NEXT_INSTANCE;
 334         nv50_graph_do_load_context(dev, inst);
 335
 336         nv_wr32(dev, NV40_PGRAPH_INTR_EN, nv_rd32(dev,
 337                 NV40_PGRAPH_INTR_EN) | NV_PGRAPH_INTR_CONTEXT_SWITCH);
 338 }
 339
 340 static int
 341 nv50_graph_nvsw_dma_vblsem(struct nouveau_channel *chan,
 342                            u32 class, u32 mthd, u32 data)
 343 {
 344         struct nouveau_gpuobj *gpuobj;
 345
 346         gpuobj = nouveau_ramht_find(chan, data);
 347         if (!gpuobj)
 348                 return -ENOENT;
 349
 350         if (nouveau_notifier_offset(gpuobj, NULL))
 351                 return -EINVAL;
 352
 353         chan->nvsw.vblsem = gpuobj;
 354         chan->nvsw.vblsem_offset = ~0;
 355         return 0;
 356 }
 357
 358 static int
 359 nv50_graph_nvsw_vblsem_offset(struct nouveau_channel *chan,
 360                               u32 class, u32 mthd, u32 data)
 361 {
 362         if (nouveau_notifier_offset(chan->nvsw.vblsem, &data))
 363                 return -ERANGE;
 364
 365         chan->nvsw.vblsem_offset = data >> 2;
 366         return 0;
 367 }
 368
 369 static int
 370 nv50_graph_nvsw_vblsem_release_val(struct nouveau_channel *chan,
 371                                    u32 class, u32 mthd, u32 data)
 372 {
 373         chan->nvsw.vblsem_rval = data;
 374         return 0;
 375 }
 376
 377 static int
 378 nv50_graph_nvsw_vblsem_release(struct nouveau_channel *chan,
 379                                u32 class, u32 mthd, u32 data)
 380 {
 381         struct drm_device *dev = chan->dev;
 382         struct drm_nouveau_private *dev_priv = dev->dev_private;
 383
 384         if (!chan->nvsw.vblsem || chan->nvsw.vblsem_offset == ~0 || data > 1)
 385                 return -EINVAL;
 386
 387         if (!(nv_rd32(dev, NV50_PDISPLAY_INTR_EN_1) &
 388                            NV50_PDISPLAY_INTR_EN_1_VBLANK_CRTC_(data))) {
 389                 nv_wr32(dev, NV50_PDISPLAY_INTR_1,
 390                              NV50_PDISPLAY_INTR_1_VBLANK_CRTC_(data));
 391                 nv_mask(dev, NV50_PDISPLAY_INTR_EN_1, 0,
 392                              NV50_PDISPLAY_INTR_EN_1_VBLANK_CRTC_(data));
 393         }
 394
 395         list_add(&chan->nvsw.vbl_wait, &dev_priv->vbl_waiting);
 396         return 0;
 397 }
 398
 399 static int
 400 nv50_graph_register(struct drm_device *dev)
 401 {
 402         struct drm_nouveau_private *dev_priv = dev->dev_private;
 403
 404         if (dev_priv->engine.graph.registered)
 405                 return 0;
 406
 407         NVOBJ_CLASS(dev, 0x506e, SW); /* nvsw */
 408         NVOBJ_MTHD (dev, 0x506e, 0x018c, nv50_graph_nvsw_dma_vblsem);
 409         NVOBJ_MTHD (dev, 0x506e, 0x0400, nv50_graph_nvsw_vblsem_offset);
 410         NVOBJ_MTHD (dev, 0x506e, 0x0404, nv50_graph_nvsw_vblsem_release_val);
 411         NVOBJ_MTHD (dev, 0x506e, 0x0408, nv50_graph_nvsw_vblsem_release);
 412
 413         NVOBJ_CLASS(dev, 0x0030, GR); /* null */
 414         NVOBJ_CLASS(dev, 0x5039, GR); /* m2mf */
 415         NVOBJ_CLASS(dev, 0x502d, GR); /* 2d */
 416         NVOBJ_CLASS(dev, 0x50c0, GR); /* compute */
 417         NVOBJ_CLASS(dev, 0x85c0, GR); /* compute (nva3, nva5, nva8) */
 418
 419         /* tesla */
 420         if (dev_priv->chipset == 0x50)
 421                 NVOBJ_CLASS(dev, 0x5097, GR); /* tesla (nv50) */
 422         else
 423         if (dev_priv->chipset < 0xa0)
 424                 NVOBJ_CLASS(dev, 0x8297, GR); /* tesla (nv8x/nv9x) */
 425         else {
 426                 switch (dev_priv->chipset) {
 427                 case 0xa0:
 428                 case 0xaa:
 429                 case 0xac:
 430                         NVOBJ_CLASS(dev, 0x8397, GR);
 431                         break;
 432                 case 0xa3:
 433                 case 0xa5:
 434                 case 0xa8:
 435                         NVOBJ_CLASS(dev, 0x8597, GR);
 436                         break;
 437                 case 0xaf:
 438                         NVOBJ_CLASS(dev, 0x8697, GR);
 439                         break;
 440                 }
 441         }
 442
 443         dev_priv->engine.graph.registered = true;
 444         return 0;
 445 }
 446
 447 void
 448 nv50_graph_tlb_flush(struct drm_device *dev)
 449 {
 450         nv50_vm_flush(dev, 0);
 451 }
 452
 453 void
 454 nv86_graph_tlb_flush(struct drm_device *dev)
 455 {
 456         struct drm_nouveau_private *dev_priv = dev->dev_private;
 457         struct nouveau_timer_engine *ptimer = &dev_priv->engine.timer;
 458         bool idle, timeout = false;
 459         unsigned long flags;
 460         u64 start;
 461         u32 tmp;
 462
 463         spin_lock_irqsave(&dev_priv->context_switch_lock, flags);
 464         nv_mask(dev, 0x400500, 0x00000001, 0x00000000);
 465
 466         start = ptimer->read(dev);
 467         do {
 468                 idle = true;
 469
 470                 for (tmp = nv_rd32(dev, 0x400380); tmp && idle; tmp >>= 3) {
 471                         if ((tmp & 7) == 1)
 472                                 idle = false;
 473                 }
 474
 475                 for (tmp = nv_rd32(dev, 0x400384); tmp && idle; tmp >>= 3) {
 476                         if ((tmp & 7) == 1)
 477                                 idle = false;
 478                 }
 479
 480                 for (tmp = nv_rd32(dev, 0x400388); tmp && idle; tmp >>= 3) {
 481                         if ((tmp & 7) == 1)
 482                                 idle = false;
 483                 }
 484         } while (!idle && !(timeout = ptimer->read(dev) - start > 2000000000));
 485
 486         if (timeout) {
 487                 NV_ERROR(dev, "PGRAPH TLB flush idle timeout fail: "
 488                               "0x%08x 0x%08x 0x%08x 0x%08x\n",
 489                          nv_rd32(dev, 0x400700), nv_rd32(dev, 0x400380),
 490                          nv_rd32(dev, 0x400384), nv_rd32(dev, 0x400388));
 491         }
 492
 493         nv50_vm_flush(dev, 0);
 494
 495         nv_mask(dev, 0x400500, 0x00000001, 0x00000001);
 496         spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags);
 497 }