2 * Copyright (C) 2007 Ben Skeggs.
5 * Permission is hereby granted, free of charge, to any person obtaining
6 * a copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial
15 * portions of the Software.
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
18 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
21 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
22 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
23 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
29 #include "nouveau_drv.h"
30 #include "nouveau_ramht.h"
31 #include "nouveau_grctx.h"
32 #include "nouveau_dma.h"
33 #include "nouveau_vm.h"
36 static int nv50_graph_register(struct drm_device *);
37 static void nv50_graph_isr(struct drm_device *);
40 nv50_graph_init_reset(struct drm_device *dev)
42 uint32_t pmc_e = NV_PMC_ENABLE_PGRAPH | (1 << 21);
46 nv_wr32(dev, NV03_PMC_ENABLE, nv_rd32(dev, NV03_PMC_ENABLE) & ~pmc_e);
47 nv_wr32(dev, NV03_PMC_ENABLE, nv_rd32(dev, NV03_PMC_ENABLE) | pmc_e);
51 nv50_graph_init_intr(struct drm_device *dev)
55 nouveau_irq_register(dev, 12, nv50_graph_isr);
56 nv_wr32(dev, NV03_PGRAPH_INTR, 0xffffffff);
57 nv_wr32(dev, 0x400138, 0xffffffff);
58 nv_wr32(dev, NV40_PGRAPH_INTR_EN, 0xffffffff);
62 nv50_graph_init_regs__nv(struct drm_device *dev)
64 struct drm_nouveau_private *dev_priv = dev->dev_private;
65 uint32_t units = nv_rd32(dev, 0x1540);
70 nv_wr32(dev, 0x400804, 0xc0000000);
71 nv_wr32(dev, 0x406800, 0xc0000000);
72 nv_wr32(dev, 0x400c04, 0xc0000000);
73 nv_wr32(dev, 0x401800, 0xc0000000);
74 nv_wr32(dev, 0x405018, 0xc0000000);
75 nv_wr32(dev, 0x402000, 0xc0000000);
77 for (i = 0; i < 16; i++) {
79 if (dev_priv->chipset < 0xa0) {
80 nv_wr32(dev, 0x408900 + (i << 12), 0xc0000000);
81 nv_wr32(dev, 0x408e08 + (i << 12), 0xc0000000);
82 nv_wr32(dev, 0x408314 + (i << 12), 0xc0000000);
84 nv_wr32(dev, 0x408600 + (i << 11), 0xc0000000);
85 nv_wr32(dev, 0x408708 + (i << 11), 0xc0000000);
86 nv_wr32(dev, 0x40831c + (i << 11), 0xc0000000);
91 nv_wr32(dev, 0x400108, 0xffffffff);
93 nv_wr32(dev, 0x400824, 0x00004000);
94 nv_wr32(dev, 0x400500, 0x00010001);
98 nv50_graph_init_regs(struct drm_device *dev)
102 nv_wr32(dev, NV04_PGRAPH_DEBUG_3,
103 (1 << 2) /* HW_CONTEXT_SWITCH_ENABLED */);
104 nv_wr32(dev, 0x402ca8, 0x800);
108 nv50_graph_init_ctxctl(struct drm_device *dev)
110 struct drm_nouveau_private *dev_priv = dev->dev_private;
111 struct nouveau_grctx ctx = {};
117 cp = kmalloc(512 * 4, GFP_KERNEL);
119 NV_ERROR(dev, "failed to allocate ctxprog\n");
120 dev_priv->engine.graph.accel_blocked = true;
125 ctx.mode = NOUVEAU_GRCTX_PROG;
127 ctx.ctxprog_max = 512;
128 if (!nv50_grctx_init(&ctx)) {
129 dev_priv->engine.graph.grctx_size = ctx.ctxvals_pos * 4;
131 nv_wr32(dev, NV40_PGRAPH_CTXCTL_UCODE_INDEX, 0);
132 for (i = 0; i < ctx.ctxprog_len; i++)
133 nv_wr32(dev, NV40_PGRAPH_CTXCTL_UCODE_DATA, cp[i]);
135 dev_priv->engine.graph.accel_blocked = true;
139 nv_wr32(dev, 0x400320, 4);
140 nv_wr32(dev, NV40_PGRAPH_CTXCTL_CUR, 0);
141 nv_wr32(dev, NV20_PGRAPH_CHANNEL_CTX_POINTER, 0);
146 nv50_graph_init(struct drm_device *dev)
152 nv50_graph_init_reset(dev);
153 nv50_graph_init_regs__nv(dev);
154 nv50_graph_init_regs(dev);
156 ret = nv50_graph_init_ctxctl(dev);
160 ret = nv50_graph_register(dev);
163 nv50_graph_init_intr(dev);
168 nv50_graph_takedown(struct drm_device *dev)
171 nv_wr32(dev, 0x40013c, 0x00000000);
172 nouveau_irq_unregister(dev, 12);
176 nv50_graph_fifo_access(struct drm_device *dev, bool enabled)
178 const uint32_t mask = 0x00010001;
181 nv_wr32(dev, 0x400500, nv_rd32(dev, 0x400500) | mask);
183 nv_wr32(dev, 0x400500, nv_rd32(dev, 0x400500) & ~mask);
186 struct nouveau_channel *
187 nv50_graph_channel(struct drm_device *dev)
189 struct drm_nouveau_private *dev_priv = dev->dev_private;
193 /* Be sure we're not in the middle of a context switch or bad things
194 * will happen, such as unloading the wrong pgraph context.
196 if (!nv_wait(dev, 0x400300, 0x00000001, 0x00000000))
197 NV_ERROR(dev, "Ctxprog is still running\n");
199 inst = nv_rd32(dev, NV50_PGRAPH_CTXCTL_CUR);
200 if (!(inst & NV50_PGRAPH_CTXCTL_CUR_LOADED))
202 inst = (inst & NV50_PGRAPH_CTXCTL_CUR_INSTANCE) << 12;
204 for (i = 0; i < dev_priv->engine.fifo.channels; i++) {
205 struct nouveau_channel *chan = dev_priv->channels.ptr[i];
207 if (chan && chan->ramin && chan->ramin->vinst == inst)
215 nv50_graph_create_context(struct nouveau_channel *chan)
217 struct drm_device *dev = chan->dev;
218 struct drm_nouveau_private *dev_priv = dev->dev_private;
219 struct nouveau_gpuobj *ramin = chan->ramin;
220 struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
221 struct nouveau_grctx ctx = {};
224 NV_DEBUG(dev, "ch%d\n", chan->id);
226 ret = nouveau_gpuobj_new(dev, chan, pgraph->grctx_size, 0,
227 NVOBJ_FLAG_ZERO_ALLOC |
228 NVOBJ_FLAG_ZERO_FREE, &chan->ramin_grctx);
232 hdr = (dev_priv->chipset == 0x50) ? 0x200 : 0x20;
233 nv_wo32(ramin, hdr + 0x00, 0x00190002);
234 nv_wo32(ramin, hdr + 0x04, chan->ramin_grctx->vinst +
235 pgraph->grctx_size - 1);
236 nv_wo32(ramin, hdr + 0x08, chan->ramin_grctx->vinst);
237 nv_wo32(ramin, hdr + 0x0c, 0);
238 nv_wo32(ramin, hdr + 0x10, 0);
239 nv_wo32(ramin, hdr + 0x14, 0x00010000);
242 ctx.mode = NOUVEAU_GRCTX_VALS;
243 ctx.data = chan->ramin_grctx;
244 nv50_grctx_init(&ctx);
246 nv_wo32(chan->ramin_grctx, 0x00000, chan->ramin->vinst >> 12);
248 dev_priv->engine.instmem.flush(dev);
249 atomic_inc(&chan->vm->pgraph_refs);
254 nv50_graph_destroy_context(struct nouveau_channel *chan)
256 struct drm_device *dev = chan->dev;
257 struct drm_nouveau_private *dev_priv = dev->dev_private;
258 struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
259 int i, hdr = (dev_priv->chipset == 0x50) ? 0x200 : 0x20;
262 NV_DEBUG(dev, "ch%d\n", chan->id);
267 spin_lock_irqsave(&dev_priv->context_switch_lock, flags);
268 pgraph->fifo_access(dev, false);
270 if (pgraph->channel(dev) == chan)
271 pgraph->unload_context(dev);
273 for (i = hdr; i < hdr + 24; i += 4)
274 nv_wo32(chan->ramin, i, 0);
275 dev_priv->engine.instmem.flush(dev);
277 pgraph->fifo_access(dev, true);
278 spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags);
280 nouveau_gpuobj_ref(NULL, &chan->ramin_grctx);
282 atomic_dec(&chan->vm->pgraph_refs);
286 nv50_graph_do_load_context(struct drm_device *dev, uint32_t inst)
288 uint32_t fifo = nv_rd32(dev, 0x400500);
290 nv_wr32(dev, 0x400500, fifo & ~1);
291 nv_wr32(dev, 0x400784, inst);
292 nv_wr32(dev, 0x400824, nv_rd32(dev, 0x400824) | 0x40);
293 nv_wr32(dev, 0x400320, nv_rd32(dev, 0x400320) | 0x11);
294 nv_wr32(dev, 0x400040, 0xffffffff);
295 (void)nv_rd32(dev, 0x400040);
296 nv_wr32(dev, 0x400040, 0x00000000);
297 nv_wr32(dev, 0x400304, nv_rd32(dev, 0x400304) | 1);
299 if (nouveau_wait_for_idle(dev))
300 nv_wr32(dev, 0x40032c, inst | (1<<31));
301 nv_wr32(dev, 0x400500, fifo);
307 nv50_graph_load_context(struct nouveau_channel *chan)
309 uint32_t inst = chan->ramin->vinst >> 12;
311 NV_DEBUG(chan->dev, "ch%d\n", chan->id);
312 return nv50_graph_do_load_context(chan->dev, inst);
316 nv50_graph_unload_context(struct drm_device *dev)
320 inst = nv_rd32(dev, NV50_PGRAPH_CTXCTL_CUR);
321 if (!(inst & NV50_PGRAPH_CTXCTL_CUR_LOADED))
323 inst &= NV50_PGRAPH_CTXCTL_CUR_INSTANCE;
325 nouveau_wait_for_idle(dev);
326 nv_wr32(dev, 0x400784, inst);
327 nv_wr32(dev, 0x400824, nv_rd32(dev, 0x400824) | 0x20);
328 nv_wr32(dev, 0x400304, nv_rd32(dev, 0x400304) | 0x01);
329 nouveau_wait_for_idle(dev);
331 nv_wr32(dev, NV50_PGRAPH_CTXCTL_CUR, inst);
336 nv50_graph_context_switch(struct drm_device *dev)
340 nv50_graph_unload_context(dev);
342 inst = nv_rd32(dev, NV50_PGRAPH_CTXCTL_NEXT);
343 inst &= NV50_PGRAPH_CTXCTL_NEXT_INSTANCE;
344 nv50_graph_do_load_context(dev, inst);
346 nv_wr32(dev, NV40_PGRAPH_INTR_EN, nv_rd32(dev,
347 NV40_PGRAPH_INTR_EN) | NV_PGRAPH_INTR_CONTEXT_SWITCH);
351 nv50_graph_nvsw_dma_vblsem(struct nouveau_channel *chan,
352 u32 class, u32 mthd, u32 data)
354 struct nouveau_gpuobj *gpuobj;
356 gpuobj = nouveau_ramht_find(chan, data);
360 if (nouveau_notifier_offset(gpuobj, NULL))
363 chan->nvsw.vblsem = gpuobj;
364 chan->nvsw.vblsem_offset = ~0;
369 nv50_graph_nvsw_vblsem_offset(struct nouveau_channel *chan,
370 u32 class, u32 mthd, u32 data)
372 if (nouveau_notifier_offset(chan->nvsw.vblsem, &data))
375 chan->nvsw.vblsem_offset = data >> 2;
380 nv50_graph_nvsw_vblsem_release_val(struct nouveau_channel *chan,
381 u32 class, u32 mthd, u32 data)
383 chan->nvsw.vblsem_rval = data;
388 nv50_graph_nvsw_vblsem_release(struct nouveau_channel *chan,
389 u32 class, u32 mthd, u32 data)
391 struct drm_device *dev = chan->dev;
392 struct drm_nouveau_private *dev_priv = dev->dev_private;
394 if (!chan->nvsw.vblsem || chan->nvsw.vblsem_offset == ~0 || data > 1)
397 drm_vblank_get(dev, data);
399 chan->nvsw.vblsem_head = data;
400 list_add(&chan->nvsw.vbl_wait, &dev_priv->vbl_waiting);
406 nv50_graph_nvsw_mthd_page_flip(struct nouveau_channel *chan,
407 u32 class, u32 mthd, u32 data)
409 struct nouveau_page_flip_state s;
411 if (!nouveau_finish_page_flip(chan, &s)) {
412 /* XXX - Do something here */
419 nv50_graph_register(struct drm_device *dev)
421 struct drm_nouveau_private *dev_priv = dev->dev_private;
423 if (dev_priv->engine.graph.registered)
426 NVOBJ_CLASS(dev, 0x506e, SW); /* nvsw */
427 NVOBJ_MTHD (dev, 0x506e, 0x018c, nv50_graph_nvsw_dma_vblsem);
428 NVOBJ_MTHD (dev, 0x506e, 0x0400, nv50_graph_nvsw_vblsem_offset);
429 NVOBJ_MTHD (dev, 0x506e, 0x0404, nv50_graph_nvsw_vblsem_release_val);
430 NVOBJ_MTHD (dev, 0x506e, 0x0408, nv50_graph_nvsw_vblsem_release);
431 NVOBJ_MTHD (dev, 0x506e, 0x0500, nv50_graph_nvsw_mthd_page_flip);
433 NVOBJ_CLASS(dev, 0x0030, GR); /* null */
434 NVOBJ_CLASS(dev, 0x5039, GR); /* m2mf */
435 NVOBJ_CLASS(dev, 0x502d, GR); /* 2d */
438 if (dev_priv->chipset == 0x50)
439 NVOBJ_CLASS(dev, 0x5097, GR); /* tesla (nv50) */
441 if (dev_priv->chipset < 0xa0)
442 NVOBJ_CLASS(dev, 0x8297, GR); /* tesla (nv8x/nv9x) */
444 switch (dev_priv->chipset) {
448 NVOBJ_CLASS(dev, 0x8397, GR);
453 NVOBJ_CLASS(dev, 0x8597, GR);
456 NVOBJ_CLASS(dev, 0x8697, GR);
462 NVOBJ_CLASS(dev, 0x50c0, GR);
463 if (dev_priv->chipset > 0xa0 &&
464 dev_priv->chipset != 0xaa &&
465 dev_priv->chipset != 0xac)
466 NVOBJ_CLASS(dev, 0x85c0, GR);
468 dev_priv->engine.graph.registered = true;
473 nv50_graph_tlb_flush(struct drm_device *dev)
475 nv50_vm_flush_engine(dev, 0);
479 nv86_graph_tlb_flush(struct drm_device *dev)
481 struct drm_nouveau_private *dev_priv = dev->dev_private;
482 struct nouveau_timer_engine *ptimer = &dev_priv->engine.timer;
483 bool idle, timeout = false;
488 spin_lock_irqsave(&dev_priv->context_switch_lock, flags);
489 nv_mask(dev, 0x400500, 0x00000001, 0x00000000);
491 start = ptimer->read(dev);
495 for (tmp = nv_rd32(dev, 0x400380); tmp && idle; tmp >>= 3) {
500 for (tmp = nv_rd32(dev, 0x400384); tmp && idle; tmp >>= 3) {
505 for (tmp = nv_rd32(dev, 0x400388); tmp && idle; tmp >>= 3) {
509 } while (!idle && !(timeout = ptimer->read(dev) - start > 2000000000));
512 NV_ERROR(dev, "PGRAPH TLB flush idle timeout fail: "
513 "0x%08x 0x%08x 0x%08x 0x%08x\n",
514 nv_rd32(dev, 0x400700), nv_rd32(dev, 0x400380),
515 nv_rd32(dev, 0x400384), nv_rd32(dev, 0x400388));
518 nv50_vm_flush_engine(dev, 0);
520 nv_mask(dev, 0x400500, 0x00000001, 0x00000001);
521 spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags);
524 static struct nouveau_enum nv50_mp_exec_error_names[] =
526 { 3, "STACK_UNDERFLOW" },
527 { 4, "QUADON_ACTIVE" },
529 { 0x10, "INVALID_OPCODE" },
530 { 0x40, "BREAKPOINT" },
534 static struct nouveau_bitfield nv50_graph_trap_m2mf[] = {
535 { 0x00000001, "NOTIFY" },
536 { 0x00000002, "IN" },
537 { 0x00000004, "OUT" },
541 static struct nouveau_bitfield nv50_graph_trap_vfetch[] = {
542 { 0x00000001, "FAULT" },
546 static struct nouveau_bitfield nv50_graph_trap_strmout[] = {
547 { 0x00000001, "FAULT" },
551 static struct nouveau_bitfield nv50_graph_trap_ccache[] = {
552 { 0x00000001, "FAULT" },
556 /* There must be a *lot* of these. Will take some time to gather them up. */
557 struct nouveau_enum nv50_data_error_names[] = {
558 { 0x00000003, "INVALID_QUERY_OR_TEXTURE" },
559 { 0x00000004, "INVALID_VALUE" },
560 { 0x00000005, "INVALID_ENUM" },
561 { 0x00000008, "INVALID_OBJECT" },
562 { 0x00000009, "READ_ONLY_OBJECT" },
563 { 0x0000000a, "SUPERVISOR_OBJECT" },
564 { 0x0000000b, "INVALID_ADDRESS_ALIGNMENT" },
565 { 0x0000000c, "INVALID_BITFIELD" },
566 { 0x0000000d, "BEGIN_END_ACTIVE" },
567 { 0x0000000e, "SEMANTIC_COLOR_BACK_OVER_LIMIT" },
568 { 0x0000000f, "VIEWPORT_ID_NEEDS_GP" },
569 { 0x00000010, "RT_DOUBLE_BIND" },
570 { 0x00000011, "RT_TYPES_MISMATCH" },
571 { 0x00000012, "RT_LINEAR_WITH_ZETA" },
572 { 0x00000015, "FP_TOO_FEW_REGS" },
573 { 0x00000016, "ZETA_FORMAT_CSAA_MISMATCH" },
574 { 0x00000017, "RT_LINEAR_WITH_MSAA" },
575 { 0x00000018, "FP_INTERPOLANT_START_OVER_LIMIT" },
576 { 0x00000019, "SEMANTIC_LAYER_OVER_LIMIT" },
577 { 0x0000001a, "RT_INVALID_ALIGNMENT" },
578 { 0x0000001b, "SAMPLER_OVER_LIMIT" },
579 { 0x0000001c, "TEXTURE_OVER_LIMIT" },
580 { 0x0000001e, "GP_TOO_MANY_OUTPUTS" },
581 { 0x0000001f, "RT_BPP128_WITH_MS8" },
582 { 0x00000021, "Z_OUT_OF_BOUNDS" },
583 { 0x00000023, "XY_OUT_OF_BOUNDS" },
584 { 0x00000027, "CP_MORE_PARAMS_THAN_SHARED" },
585 { 0x00000028, "CP_NO_REG_SPACE_STRIPED" },
586 { 0x00000029, "CP_NO_REG_SPACE_PACKED" },
587 { 0x0000002a, "CP_NOT_ENOUGH_WARPS" },
588 { 0x0000002b, "CP_BLOCK_SIZE_MISMATCH" },
589 { 0x0000002c, "CP_NOT_ENOUGH_LOCAL_WARPS" },
590 { 0x0000002d, "CP_NOT_ENOUGH_STACK_WARPS" },
591 { 0x0000002e, "CP_NO_BLOCKDIM_LATCH" },
592 { 0x00000031, "ENG2D_FORMAT_MISMATCH" },
593 { 0x0000003f, "PRIMITIVE_ID_NEEDS_GP" },
594 { 0x00000044, "SEMANTIC_VIEWPORT_OVER_LIMIT" },
595 { 0x00000045, "SEMANTIC_COLOR_FRONT_OVER_LIMIT" },
596 { 0x00000046, "LAYER_ID_NEEDS_GP" },
597 { 0x00000047, "SEMANTIC_CLIP_OVER_LIMIT" },
598 { 0x00000048, "SEMANTIC_PTSZ_OVER_LIMIT" },
602 static struct nouveau_bitfield nv50_graph_intr[] = {
603 { 0x00000001, "NOTIFY" },
604 { 0x00000002, "COMPUTE_QUERY" },
605 { 0x00000010, "ILLEGAL_MTHD" },
606 { 0x00000020, "ILLEGAL_CLASS" },
607 { 0x00000040, "DOUBLE_NOTIFY" },
608 { 0x00001000, "CONTEXT_SWITCH" },
609 { 0x00010000, "BUFFER_NOTIFY" },
610 { 0x00100000, "DATA_ERROR" },
611 { 0x00200000, "TRAP" },
612 { 0x01000000, "SINGLE_STEP" },
617 nv50_pgraph_mp_trap(struct drm_device *dev, int tpid, int display)
619 struct drm_nouveau_private *dev_priv = dev->dev_private;
620 uint32_t units = nv_rd32(dev, 0x1540);
621 uint32_t addr, mp10, status, pc, oplow, ophigh;
624 for (i = 0; i < 4; i++) {
625 if (!(units & 1 << (i+24)))
627 if (dev_priv->chipset < 0xa0)
628 addr = 0x408200 + (tpid << 12) + (i << 7);
630 addr = 0x408100 + (tpid << 11) + (i << 7);
631 mp10 = nv_rd32(dev, addr + 0x10);
632 status = nv_rd32(dev, addr + 0x14);
636 nv_rd32(dev, addr + 0x20);
637 pc = nv_rd32(dev, addr + 0x24);
638 oplow = nv_rd32(dev, addr + 0x70);
639 ophigh= nv_rd32(dev, addr + 0x74);
640 NV_INFO(dev, "PGRAPH_TRAP_MP_EXEC - "
641 "TP %d MP %d: ", tpid, i);
642 nouveau_enum_print(nv50_mp_exec_error_names, status);
643 printk(" at %06x warp %d, opcode %08x %08x\n",
644 pc&0xffffff, pc >> 24,
647 nv_wr32(dev, addr + 0x10, mp10);
648 nv_wr32(dev, addr + 0x14, 0);
652 NV_INFO(dev, "PGRAPH_TRAP_MP_EXEC - TP %d: "
653 "No MPs claiming errors?\n", tpid);
657 nv50_pgraph_tp_trap(struct drm_device *dev, int type, uint32_t ustatus_old,
658 uint32_t ustatus_new, int display, const char *name)
660 struct drm_nouveau_private *dev_priv = dev->dev_private;
662 uint32_t units = nv_rd32(dev, 0x1540);
664 uint32_t ustatus_addr, ustatus;
665 for (i = 0; i < 16; i++) {
666 if (!(units & (1 << i)))
668 if (dev_priv->chipset < 0xa0)
669 ustatus_addr = ustatus_old + (i << 12);
671 ustatus_addr = ustatus_new + (i << 11);
672 ustatus = nv_rd32(dev, ustatus_addr) & 0x7fffffff;
677 case 6: /* texture error... unknown for now */
678 nv50_fb_vm_trap(dev, display, name);
680 NV_ERROR(dev, "magic set %d:\n", i);
681 for (r = ustatus_addr + 4; r <= ustatus_addr + 0x10; r += 4)
682 NV_ERROR(dev, "\t0x%08x: 0x%08x\n", r,
686 case 7: /* MP error */
687 if (ustatus & 0x00010000) {
688 nv50_pgraph_mp_trap(dev, i, display);
689 ustatus &= ~0x00010000;
692 case 8: /* TPDMA error */
694 uint32_t e0c = nv_rd32(dev, ustatus_addr + 4);
695 uint32_t e10 = nv_rd32(dev, ustatus_addr + 8);
696 uint32_t e14 = nv_rd32(dev, ustatus_addr + 0xc);
697 uint32_t e18 = nv_rd32(dev, ustatus_addr + 0x10);
698 uint32_t e1c = nv_rd32(dev, ustatus_addr + 0x14);
699 uint32_t e20 = nv_rd32(dev, ustatus_addr + 0x18);
700 uint32_t e24 = nv_rd32(dev, ustatus_addr + 0x1c);
701 nv50_fb_vm_trap(dev, display, name);
702 /* 2d engine destination */
703 if (ustatus & 0x00000010) {
705 NV_INFO(dev, "PGRAPH_TRAP_TPDMA_2D - TP %d - Unknown fault at address %02x%08x\n",
707 NV_INFO(dev, "PGRAPH_TRAP_TPDMA_2D - TP %d - e0c: %08x, e18: %08x, e1c: %08x, e20: %08x, e24: %08x\n",
708 i, e0c, e18, e1c, e20, e24);
710 ustatus &= ~0x00000010;
713 if (ustatus & 0x00000040) {
715 NV_INFO(dev, "PGRAPH_TRAP_TPDMA_RT - TP %d - Unknown fault at address %02x%08x\n",
717 NV_INFO(dev, "PGRAPH_TRAP_TPDMA_RT - TP %d - e0c: %08x, e18: %08x, e1c: %08x, e20: %08x, e24: %08x\n",
718 i, e0c, e18, e1c, e20, e24);
720 ustatus &= ~0x00000040;
722 /* CUDA memory: l[], g[] or stack. */
723 if (ustatus & 0x00000080) {
725 if (e18 & 0x80000000) {
726 /* g[] read fault? */
727 NV_INFO(dev, "PGRAPH_TRAP_TPDMA - TP %d - Global read fault at address %02x%08x\n",
728 i, e14, e10 | ((e18 >> 24) & 0x1f));
730 } else if (e18 & 0xc) {
731 /* g[] write fault? */
732 NV_INFO(dev, "PGRAPH_TRAP_TPDMA - TP %d - Global write fault at address %02x%08x\n",
733 i, e14, e10 | ((e18 >> 7) & 0x1f));
736 NV_INFO(dev, "PGRAPH_TRAP_TPDMA - TP %d - Unknown CUDA fault at address %02x%08x\n",
739 NV_INFO(dev, "PGRAPH_TRAP_TPDMA - TP %d - e0c: %08x, e18: %08x, e1c: %08x, e20: %08x, e24: %08x\n",
740 i, e0c, e18, e1c, e20, e24);
742 ustatus &= ~0x00000080;
749 NV_INFO(dev, "%s - TP%d: Unhandled ustatus 0x%08x\n", name, i, ustatus);
751 nv_wr32(dev, ustatus_addr, 0xc0000000);
755 NV_INFO(dev, "%s - No TPs claiming errors?\n", name);
759 nv50_pgraph_trap_handler(struct drm_device *dev, u32 display, u64 inst, u32 chid)
761 u32 status = nv_rd32(dev, 0x400108);
764 if (!status && display) {
765 NV_INFO(dev, "PGRAPH - TRAP: no units reporting traps?\n");
769 /* DISPATCH: Relays commands to other units and handles NOTIFY,
770 * COND, QUERY. If you get a trap from it, the command is still stuck
771 * in DISPATCH and you need to do something about it. */
772 if (status & 0x001) {
773 ustatus = nv_rd32(dev, 0x400804) & 0x7fffffff;
774 if (!ustatus && display) {
775 NV_INFO(dev, "PGRAPH_TRAP_DISPATCH - no ustatus?\n");
778 nv_wr32(dev, 0x400500, 0x00000000);
780 /* Known to be triggered by screwed up NOTIFY and COND... */
781 if (ustatus & 0x00000001) {
782 u32 addr = nv_rd32(dev, 0x400808);
783 u32 subc = (addr & 0x00070000) >> 16;
784 u32 mthd = (addr & 0x00001ffc);
785 u32 datal = nv_rd32(dev, 0x40080c);
786 u32 datah = nv_rd32(dev, 0x400810);
787 u32 class = nv_rd32(dev, 0x400814);
788 u32 r848 = nv_rd32(dev, 0x400848);
790 NV_INFO(dev, "PGRAPH - TRAP DISPATCH_FAULT\n");
791 if (display && (addr & 0x80000000)) {
792 NV_INFO(dev, "PGRAPH - ch %d (0x%010llx) "
793 "subc %d class 0x%04x mthd 0x%04x "
795 "400808 0x%08x 400848 0x%08x\n",
796 chid, inst, subc, class, mthd, datah,
800 NV_INFO(dev, "PGRAPH - no stuck command?\n");
803 nv_wr32(dev, 0x400808, 0);
804 nv_wr32(dev, 0x4008e8, nv_rd32(dev, 0x4008e8) & 3);
805 nv_wr32(dev, 0x400848, 0);
806 ustatus &= ~0x00000001;
809 if (ustatus & 0x00000002) {
810 u32 addr = nv_rd32(dev, 0x40084c);
811 u32 subc = (addr & 0x00070000) >> 16;
812 u32 mthd = (addr & 0x00001ffc);
813 u32 data = nv_rd32(dev, 0x40085c);
814 u32 class = nv_rd32(dev, 0x400814);
816 NV_INFO(dev, "PGRAPH - TRAP DISPATCH_QUERY\n");
817 if (display && (addr & 0x80000000)) {
818 NV_INFO(dev, "PGRAPH - ch %d (0x%010llx) "
819 "subc %d class 0x%04x mthd 0x%04x "
820 "data 0x%08x 40084c 0x%08x\n",
821 chid, inst, subc, class, mthd,
825 NV_INFO(dev, "PGRAPH - no stuck command?\n");
828 nv_wr32(dev, 0x40084c, 0);
829 ustatus &= ~0x00000002;
832 if (ustatus && display) {
833 NV_INFO(dev, "PGRAPH - TRAP_DISPATCH (unknown "
834 "0x%08x)\n", ustatus);
837 nv_wr32(dev, 0x400804, 0xc0000000);
838 nv_wr32(dev, 0x400108, 0x001);
844 /* M2MF: Memory to memory copy engine. */
845 if (status & 0x002) {
846 u32 ustatus = nv_rd32(dev, 0x406800) & 0x7fffffff;
848 NV_INFO(dev, "PGRAPH - TRAP_M2MF");
849 nouveau_bitfield_print(nv50_graph_trap_m2mf, ustatus);
851 NV_INFO(dev, "PGRAPH - TRAP_M2MF %08x %08x %08x %08x\n",
852 nv_rd32(dev, 0x406804), nv_rd32(dev, 0x406808),
853 nv_rd32(dev, 0x40680c), nv_rd32(dev, 0x406810));
857 /* No sane way found yet -- just reset the bugger. */
858 nv_wr32(dev, 0x400040, 2);
859 nv_wr32(dev, 0x400040, 0);
860 nv_wr32(dev, 0x406800, 0xc0000000);
861 nv_wr32(dev, 0x400108, 0x002);
865 /* VFETCH: Fetches data from vertex buffers. */
866 if (status & 0x004) {
867 u32 ustatus = nv_rd32(dev, 0x400c04) & 0x7fffffff;
869 NV_INFO(dev, "PGRAPH - TRAP_VFETCH");
870 nouveau_bitfield_print(nv50_graph_trap_vfetch, ustatus);
872 NV_INFO(dev, "PGRAPH - TRAP_VFETCH %08x %08x %08x %08x\n",
873 nv_rd32(dev, 0x400c00), nv_rd32(dev, 0x400c08),
874 nv_rd32(dev, 0x400c0c), nv_rd32(dev, 0x400c10));
877 nv_wr32(dev, 0x400c04, 0xc0000000);
878 nv_wr32(dev, 0x400108, 0x004);
882 /* STRMOUT: DirectX streamout / OpenGL transform feedback. */
883 if (status & 0x008) {
884 ustatus = nv_rd32(dev, 0x401800) & 0x7fffffff;
886 NV_INFO(dev, "PGRAPH - TRAP_STRMOUT");
887 nouveau_bitfield_print(nv50_graph_trap_strmout, ustatus);
889 NV_INFO(dev, "PGRAPH - TRAP_STRMOUT %08x %08x %08x %08x\n",
890 nv_rd32(dev, 0x401804), nv_rd32(dev, 0x401808),
891 nv_rd32(dev, 0x40180c), nv_rd32(dev, 0x401810));
895 /* No sane way found yet -- just reset the bugger. */
896 nv_wr32(dev, 0x400040, 0x80);
897 nv_wr32(dev, 0x400040, 0);
898 nv_wr32(dev, 0x401800, 0xc0000000);
899 nv_wr32(dev, 0x400108, 0x008);
903 /* CCACHE: Handles code and c[] caches and fills them. */
904 if (status & 0x010) {
905 ustatus = nv_rd32(dev, 0x405018) & 0x7fffffff;
907 NV_INFO(dev, "PGRAPH - TRAP_CCACHE");
908 nouveau_bitfield_print(nv50_graph_trap_ccache, ustatus);
910 NV_INFO(dev, "PGRAPH - TRAP_CCACHE %08x %08x %08x %08x"
912 nv_rd32(dev, 0x405800), nv_rd32(dev, 0x405804),
913 nv_rd32(dev, 0x405808), nv_rd32(dev, 0x40580c),
914 nv_rd32(dev, 0x405810), nv_rd32(dev, 0x405814),
915 nv_rd32(dev, 0x40581c));
919 nv_wr32(dev, 0x405018, 0xc0000000);
920 nv_wr32(dev, 0x400108, 0x010);
924 /* Unknown, not seen yet... 0x402000 is the only trap status reg
925 * remaining, so try to handle it anyway. Perhaps related to that
926 * unknown DMA slot on tesla? */
928 ustatus = nv_rd32(dev, 0x402000) & 0x7fffffff;
930 NV_INFO(dev, "PGRAPH - TRAP_UNKC04 0x%08x\n", ustatus);
931 nv_wr32(dev, 0x402000, 0xc0000000);
932 /* no status modifiction on purpose */
935 /* TEXTURE: CUDA texturing units */
936 if (status & 0x040) {
937 nv50_pgraph_tp_trap(dev, 6, 0x408900, 0x408600, display,
938 "PGRAPH - TRAP_TEXTURE");
939 nv_wr32(dev, 0x400108, 0x040);
943 /* MP: CUDA execution engines. */
944 if (status & 0x080) {
945 nv50_pgraph_tp_trap(dev, 7, 0x408314, 0x40831c, display,
947 nv_wr32(dev, 0x400108, 0x080);
951 /* TPDMA: Handles TP-initiated uncached memory accesses:
952 * l[], g[], stack, 2d surfaces, render targets. */
953 if (status & 0x100) {
954 nv50_pgraph_tp_trap(dev, 8, 0x408e08, 0x408708, display,
955 "PGRAPH - TRAP_TPDMA");
956 nv_wr32(dev, 0x400108, 0x100);
962 NV_INFO(dev, "PGRAPH - TRAP: unknown 0x%08x\n", status);
963 nv_wr32(dev, 0x400108, status);
970 nv50_graph_isr_chid(struct drm_device *dev, u64 inst)
972 struct drm_nouveau_private *dev_priv = dev->dev_private;
973 struct nouveau_channel *chan;
977 spin_lock_irqsave(&dev_priv->channels.lock, flags);
978 for (i = 0; i < dev_priv->engine.fifo.channels; i++) {
979 chan = dev_priv->channels.ptr[i];
980 if (!chan || !chan->ramin)
983 if (inst == chan->ramin->vinst)
986 spin_unlock_irqrestore(&dev_priv->channels.lock, flags);
991 nv50_graph_isr(struct drm_device *dev)
995 while ((stat = nv_rd32(dev, 0x400100))) {
996 u64 inst = (u64)(nv_rd32(dev, 0x40032c) & 0x0fffffff) << 12;
997 u32 chid = nv50_graph_isr_chid(dev, inst);
998 u32 addr = nv_rd32(dev, NV04_PGRAPH_TRAPPED_ADDR);
999 u32 subc = (addr & 0x00070000) >> 16;
1000 u32 mthd = (addr & 0x00001ffc);
1001 u32 data = nv_rd32(dev, NV04_PGRAPH_TRAPPED_DATA);
1002 u32 class = nv_rd32(dev, 0x400814);
1005 if (stat & 0x00000010) {
1006 if (!nouveau_gpuobj_mthd_call2(dev, chid, class,
1008 show &= ~0x00000010;
1011 if (stat & 0x00001000) {
1012 nv_wr32(dev, 0x400500, 0x00000000);
1013 nv_wr32(dev, 0x400100, 0x00001000);
1014 nv_mask(dev, 0x40013c, 0x00001000, 0x00000000);
1015 nv50_graph_context_switch(dev);
1016 stat &= ~0x00001000;
1017 show &= ~0x00001000;
1020 show = (show && nouveau_ratelimit()) ? show : 0;
1022 if (show & 0x00100000) {
1023 u32 ecode = nv_rd32(dev, 0x400110);
1024 NV_INFO(dev, "PGRAPH - DATA_ERROR ");
1025 nouveau_enum_print(nv50_data_error_names, ecode);
1029 if (stat & 0x00200000) {
1030 if (!nv50_pgraph_trap_handler(dev, show, inst, chid))
1031 show &= ~0x00200000;
1034 nv_wr32(dev, 0x400100, stat);
1035 nv_wr32(dev, 0x400500, 0x00010001);
1038 NV_INFO(dev, "PGRAPH -");
1039 nouveau_bitfield_print(nv50_graph_intr, show);
1041 NV_INFO(dev, "PGRAPH - ch %d (0x%010llx) subc %d "
1042 "class 0x%04x mthd 0x%04x data 0x%08x\n",
1043 chid, inst, subc, class, mthd, data);
1047 if (nv_rd32(dev, 0x400824) & (1 << 31))
1048 nv_wr32(dev, 0x400824, nv_rd32(dev, 0x400824) & ~(1 << 31));