2 * Copyright 2009 Marcin KoĆcielnicki
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
23 #define CP_FLAG_CLEAR 0
25 #define CP_FLAG_SWAP_DIRECTION ((0 * 32) + 0)
26 #define CP_FLAG_SWAP_DIRECTION_LOAD 0
27 #define CP_FLAG_SWAP_DIRECTION_SAVE 1
28 #define CP_FLAG_UNK01 ((0 * 32) + 1)
29 #define CP_FLAG_UNK01_CLEAR 0
30 #define CP_FLAG_UNK01_SET 1
31 #define CP_FLAG_UNK03 ((0 * 32) + 3)
32 #define CP_FLAG_UNK03_CLEAR 0
33 #define CP_FLAG_UNK03_SET 1
34 #define CP_FLAG_USER_SAVE ((0 * 32) + 5)
35 #define CP_FLAG_USER_SAVE_NOT_PENDING 0
36 #define CP_FLAG_USER_SAVE_PENDING 1
37 #define CP_FLAG_USER_LOAD ((0 * 32) + 6)
38 #define CP_FLAG_USER_LOAD_NOT_PENDING 0
39 #define CP_FLAG_USER_LOAD_PENDING 1
40 #define CP_FLAG_UNK0B ((0 * 32) + 0xb)
41 #define CP_FLAG_UNK0B_CLEAR 0
42 #define CP_FLAG_UNK0B_SET 1
43 #define CP_FLAG_STATE ((0 * 32) + 0x1c)
44 #define CP_FLAG_STATE_STOPPED 0
45 #define CP_FLAG_STATE_RUNNING 1
46 #define CP_FLAG_UNK1D ((0 * 32) + 0x1d)
47 #define CP_FLAG_UNK1D_CLEAR 0
48 #define CP_FLAG_UNK1D_SET 1
49 #define CP_FLAG_UNK20 ((1 * 32) + 0)
50 #define CP_FLAG_UNK20_CLEAR 0
51 #define CP_FLAG_UNK20_SET 1
52 #define CP_FLAG_STATUS ((2 * 32) + 0)
53 #define CP_FLAG_STATUS_BUSY 0
54 #define CP_FLAG_STATUS_IDLE 1
55 #define CP_FLAG_AUTO_SAVE ((2 * 32) + 4)
56 #define CP_FLAG_AUTO_SAVE_NOT_PENDING 0
57 #define CP_FLAG_AUTO_SAVE_PENDING 1
58 #define CP_FLAG_AUTO_LOAD ((2 * 32) + 5)
59 #define CP_FLAG_AUTO_LOAD_NOT_PENDING 0
60 #define CP_FLAG_AUTO_LOAD_PENDING 1
61 #define CP_FLAG_NEWCTX ((2 * 32) + 10)
62 #define CP_FLAG_NEWCTX_BUSY 0
63 #define CP_FLAG_NEWCTX_DONE 1
64 #define CP_FLAG_XFER ((2 * 32) + 11)
65 #define CP_FLAG_XFER_IDLE 0
66 #define CP_FLAG_XFER_BUSY 1
67 #define CP_FLAG_ALWAYS ((2 * 32) + 13)
68 #define CP_FLAG_ALWAYS_FALSE 0
69 #define CP_FLAG_ALWAYS_TRUE 1
70 #define CP_FLAG_INTR ((2 * 32) + 15)
71 #define CP_FLAG_INTR_NOT_PENDING 0
72 #define CP_FLAG_INTR_PENDING 1
74 #define CP_CTX 0x00100000
75 #define CP_CTX_COUNT 0x000f0000
76 #define CP_CTX_COUNT_SHIFT 16
77 #define CP_CTX_REG 0x00003fff
78 #define CP_LOAD_SR 0x00200000
79 #define CP_LOAD_SR_VALUE 0x000fffff
80 #define CP_BRA 0x00400000
81 #define CP_BRA_IP 0x0001ff00
82 #define CP_BRA_IP_SHIFT 8
83 #define CP_BRA_IF_CLEAR 0x00000080
84 #define CP_BRA_FLAG 0x0000007f
85 #define CP_WAIT 0x00500000
86 #define CP_WAIT_SET 0x00000080
87 #define CP_WAIT_FLAG 0x0000007f
88 #define CP_SET 0x00700000
89 #define CP_SET_1 0x00000080
90 #define CP_SET_FLAG 0x0000007f
91 #define CP_NEWCTX 0x00600004
92 #define CP_NEXT_TO_SWAP 0x00600005
93 #define CP_SET_CONTEXT_POINTER 0x00600006
94 #define CP_SET_XFER_POINTER 0x00600007
95 #define CP_ENABLE 0x00600009
96 #define CP_END 0x0060000c
97 #define CP_NEXT_TO_CURRENT 0x0060000d
98 #define CP_DISABLE1 0x0090ffff
99 #define CP_DISABLE2 0x0091ffff
100 #define CP_XFER_1 0x008000ff
101 #define CP_XFER_2 0x008800ff
102 #define CP_SEEK_1 0x00c000ff
103 #define CP_SEEK_2 0x00c800ff
106 #include "nouveau_drv.h"
107 #include "nouveau_grctx.h"
109 #define IS_NVA3F(x) (((x) > 0xa0 && (x) < 0xaa) || (x) == 0xaf)
110 #define IS_NVAAF(x) ((x) >= 0xaa && (x) <= 0xac)
113 * This code deals with PGRAPH contexts on NV50 family cards. Like NV40, it's
114 * the GPU itself that does context-switching, but it needs a special
115 * microcode to do it. And it's the driver's task to supply this microcode,
116 * further known as ctxprog, as well as the initial context values, known
119 * Without ctxprog, you cannot switch contexts. Not even in software, since
120 * the majority of context [xfer strands] isn't accessible directly. You're
121 * stuck with a single channel, and you also suffer all the problems resulting
122 * from missing ctxvals, since you cannot load them.
124 * Without ctxvals, you're stuck with PGRAPH's default context. It's enough to
125 * run 2d operations, but trying to utilise 3d or CUDA will just lock you up,
126 * since you don't have... some sort of needed setup.
128 * Nouveau will just disable acceleration if not given ctxprog + ctxvals, since
129 * it's too much hassle to handle no-ctxprog as a special case.
135 * The ctxprog is written in its own kind of microcode, with very small and
136 * crappy set of available commands. You upload it to a small [512 insns]
137 * area of memory on PGRAPH, and it'll be run when PFIFO wants PGRAPH to
138 * switch channel. or when the driver explicitely requests it. Stuff visible
139 * to ctxprog consists of: PGRAPH MMIO registers, PGRAPH context strands,
140 * the per-channel context save area in VRAM [known as ctxvals or grctx],
141 * 4 flags registers, a scratch register, two grctx pointers, plus many
142 * random poorly-understood details.
144 * When ctxprog runs, it's supposed to check what operations are asked of it,
145 * save old context if requested, optionally reset PGRAPH and switch to the
146 * new channel, and load the new context. Context consists of three major
147 * parts: subset of MMIO registers and two "xfer areas".
151 * - document unimplemented bits compared to nvidia
152 * - NVAx: make a TP subroutine, use it.
153 * - use 0x4008fc instead of 0x1540?
166 static void nv50_graph_construct_mmio(struct nouveau_grctx *ctx);
167 static void nv50_graph_construct_xfer1(struct nouveau_grctx *ctx);
168 static void nv50_graph_construct_xfer2(struct nouveau_grctx *ctx);
170 /* Main function: construct the ctxprog skeleton, call the other functions. */
173 nv50_grctx_init(struct nouveau_grctx *ctx)
175 struct drm_nouveau_private *dev_priv = ctx->dev->dev_private;
177 switch (dev_priv->chipset) {
194 NV_ERROR(ctx->dev, "I don't know how to make a ctxprog for "
195 "your NV%x card.\n", dev_priv->chipset);
196 NV_ERROR(ctx->dev, "Disabling acceleration. Please contact "
201 cp_set (ctx, STATE, RUNNING);
202 /* decide whether we're loading/unloading the context */
203 cp_bra (ctx, AUTO_SAVE, PENDING, cp_setup_save);
204 cp_bra (ctx, USER_SAVE, PENDING, cp_setup_save);
206 cp_name(ctx, cp_check_load);
207 cp_bra (ctx, AUTO_LOAD, PENDING, cp_setup_auto_load);
208 cp_bra (ctx, USER_LOAD, PENDING, cp_setup_load);
209 cp_bra (ctx, ALWAYS, TRUE, cp_exit);
211 /* setup for context load */
212 cp_name(ctx, cp_setup_auto_load);
213 cp_out (ctx, CP_DISABLE1);
214 cp_out (ctx, CP_DISABLE2);
215 cp_out (ctx, CP_ENABLE);
216 cp_out (ctx, CP_NEXT_TO_SWAP);
217 cp_set (ctx, UNK01, SET);
218 cp_name(ctx, cp_setup_load);
219 cp_out (ctx, CP_NEWCTX);
220 cp_wait(ctx, NEWCTX, BUSY);
221 cp_set (ctx, UNK1D, CLEAR);
222 cp_set (ctx, SWAP_DIRECTION, LOAD);
223 cp_bra (ctx, UNK0B, SET, cp_prepare_exit);
224 cp_bra (ctx, ALWAYS, TRUE, cp_swap_state);
226 /* setup for context save */
227 cp_name(ctx, cp_setup_save);
228 cp_set (ctx, UNK1D, SET);
229 cp_wait(ctx, STATUS, BUSY);
230 cp_wait(ctx, INTR, PENDING);
231 cp_bra (ctx, STATUS, BUSY, cp_setup_save);
232 cp_set (ctx, UNK01, SET);
233 cp_set (ctx, SWAP_DIRECTION, SAVE);
235 /* general PGRAPH state */
236 cp_name(ctx, cp_swap_state);
237 cp_set (ctx, UNK03, SET);
238 cp_pos (ctx, 0x00004/4);
239 cp_ctx (ctx, 0x400828, 1); /* needed. otherwise, flickering happens. */
240 cp_pos (ctx, 0x00100/4);
241 nv50_graph_construct_mmio(ctx);
242 nv50_graph_construct_xfer1(ctx);
243 nv50_graph_construct_xfer2(ctx);
245 cp_bra (ctx, SWAP_DIRECTION, SAVE, cp_check_load);
247 cp_set (ctx, UNK20, SET);
248 cp_set (ctx, SWAP_DIRECTION, SAVE); /* no idea why this is needed, but fixes at least one lockup. */
249 cp_lsr (ctx, ctx->ctxvals_base);
250 cp_out (ctx, CP_SET_XFER_POINTER);
252 cp_out (ctx, CP_SEEK_1);
253 cp_out (ctx, CP_XFER_1);
254 cp_wait(ctx, XFER, BUSY);
256 /* pre-exit state updates */
257 cp_name(ctx, cp_prepare_exit);
258 cp_set (ctx, UNK01, CLEAR);
259 cp_set (ctx, UNK03, CLEAR);
260 cp_set (ctx, UNK1D, CLEAR);
262 cp_bra (ctx, USER_SAVE, PENDING, cp_exit);
263 cp_out (ctx, CP_NEXT_TO_CURRENT);
265 cp_name(ctx, cp_exit);
266 cp_set (ctx, USER_SAVE, NOT_PENDING);
267 cp_set (ctx, USER_LOAD, NOT_PENDING);
268 cp_set (ctx, STATE, STOPPED);
269 cp_out (ctx, CP_END);
270 ctx->ctxvals_pos += 0x400; /* padding... no idea why you need it */
276 * Constructs MMIO part of ctxprog and ctxvals. Just a matter of knowing which
277 * registers to save/restore and the default values for them.
281 nv50_graph_construct_mmio_ddata(struct nouveau_grctx *ctx);
284 nv50_graph_construct_mmio(struct nouveau_grctx *ctx)
286 struct drm_nouveau_private *dev_priv = ctx->dev->dev_private;
289 uint32_t units = nv_rd32 (ctx->dev, 0x1540);
292 cp_ctx(ctx, 0x400808, 7);
293 gr_def(ctx, 0x400814, 0x00000030);
294 cp_ctx(ctx, 0x400834, 0x32);
295 if (dev_priv->chipset == 0x50) {
296 gr_def(ctx, 0x400834, 0xff400040);
297 gr_def(ctx, 0x400838, 0xfff00080);
298 gr_def(ctx, 0x40083c, 0xfff70090);
299 gr_def(ctx, 0x400840, 0xffe806a8);
301 gr_def(ctx, 0x400844, 0x00000002);
302 if (IS_NVA3F(dev_priv->chipset))
303 gr_def(ctx, 0x400894, 0x00001000);
304 gr_def(ctx, 0x4008e8, 0x00000003);
305 gr_def(ctx, 0x4008ec, 0x00001000);
306 if (dev_priv->chipset == 0x50)
307 cp_ctx(ctx, 0x400908, 0xb);
308 else if (dev_priv->chipset < 0xa0)
309 cp_ctx(ctx, 0x400908, 0xc);
311 cp_ctx(ctx, 0x400908, 0xe);
313 if (dev_priv->chipset >= 0xa0)
314 cp_ctx(ctx, 0x400b00, 0x1);
315 if (IS_NVA3F(dev_priv->chipset)) {
316 cp_ctx(ctx, 0x400b10, 0x1);
317 gr_def(ctx, 0x400b10, 0x0001629d);
318 cp_ctx(ctx, 0x400b20, 0x1);
319 gr_def(ctx, 0x400b20, 0x0001629d);
322 nv50_graph_construct_mmio_ddata(ctx);
325 cp_ctx(ctx, 0x400c08, 0x2);
326 gr_def(ctx, 0x400c08, 0x0000fe0c);
329 if (dev_priv->chipset < 0xa0) {
330 cp_ctx(ctx, 0x401008, 0x4);
331 gr_def(ctx, 0x401014, 0x00001000);
332 } else if (!IS_NVA3F(dev_priv->chipset)) {
333 cp_ctx(ctx, 0x401008, 0x5);
334 gr_def(ctx, 0x401018, 0x00001000);
336 cp_ctx(ctx, 0x401008, 0x5);
337 gr_def(ctx, 0x401018, 0x00004000);
341 cp_ctx(ctx, 0x401400, 0x8);
342 cp_ctx(ctx, 0x401424, 0x3);
343 if (dev_priv->chipset == 0x50)
344 gr_def(ctx, 0x40142c, 0x0001fd87);
346 gr_def(ctx, 0x40142c, 0x00000187);
347 cp_ctx(ctx, 0x401540, 0x5);
348 gr_def(ctx, 0x401550, 0x00001018);
350 /* 1800: STREAMOUT */
351 cp_ctx(ctx, 0x401814, 0x1);
352 gr_def(ctx, 0x401814, 0x000000ff);
353 if (dev_priv->chipset == 0x50) {
354 cp_ctx(ctx, 0x40181c, 0xe);
355 gr_def(ctx, 0x401850, 0x00000004);
356 } else if (dev_priv->chipset < 0xa0) {
357 cp_ctx(ctx, 0x40181c, 0xf);
358 gr_def(ctx, 0x401854, 0x00000004);
360 cp_ctx(ctx, 0x40181c, 0x13);
361 gr_def(ctx, 0x401864, 0x00000004);
365 cp_ctx(ctx, 0x401c00, 0x1);
366 switch (dev_priv->chipset) {
368 gr_def(ctx, 0x401c00, 0x0001005f);
373 gr_def(ctx, 0x401c00, 0x044d00df);
381 gr_def(ctx, 0x401c00, 0x042500df);
387 gr_def(ctx, 0x401c00, 0x142500df);
394 cp_ctx(ctx, 0x402400, 0x1);
395 if (dev_priv->chipset == 0x50)
396 cp_ctx(ctx, 0x402408, 0x1);
398 cp_ctx(ctx, 0x402408, 0x2);
399 gr_def(ctx, 0x402408, 0x00000600);
402 cp_ctx(ctx, 0x402800, 0x1);
403 if (dev_priv->chipset == 0x50)
404 gr_def(ctx, 0x402800, 0x00000006);
407 cp_ctx(ctx, 0x402c08, 0x6);
408 if (dev_priv->chipset != 0x50)
409 gr_def(ctx, 0x402c14, 0x01000000);
410 gr_def(ctx, 0x402c18, 0x000000ff);
411 if (dev_priv->chipset == 0x50)
412 cp_ctx(ctx, 0x402ca0, 0x1);
414 cp_ctx(ctx, 0x402ca0, 0x2);
415 if (dev_priv->chipset < 0xa0)
416 gr_def(ctx, 0x402ca0, 0x00000400);
417 else if (!IS_NVA3F(dev_priv->chipset))
418 gr_def(ctx, 0x402ca0, 0x00000800);
420 gr_def(ctx, 0x402ca0, 0x00000400);
421 cp_ctx(ctx, 0x402cac, 0x4);
424 cp_ctx(ctx, 0x403004, 0x1);
425 gr_def(ctx, 0x403004, 0x00000001);
428 if (dev_priv->chipset >= 0xa0) {
429 cp_ctx(ctx, 0x403404, 0x1);
430 gr_def(ctx, 0x403404, 0x00000001);
434 cp_ctx(ctx, 0x405000, 0x1);
435 switch (dev_priv->chipset) {
437 gr_def(ctx, 0x405000, 0x00300080);
447 gr_def(ctx, 0x405000, 0x000e0080);
454 gr_def(ctx, 0x405000, 0x00000080);
457 cp_ctx(ctx, 0x405014, 0x1);
458 gr_def(ctx, 0x405014, 0x00000004);
459 cp_ctx(ctx, 0x40501c, 0x1);
460 cp_ctx(ctx, 0x405024, 0x1);
461 cp_ctx(ctx, 0x40502c, 0x1);
464 if (dev_priv->chipset == 0x50)
465 cp_ctx(ctx, 0x4063e0, 0x1);
468 if (dev_priv->chipset < 0x90) {
469 cp_ctx(ctx, 0x406814, 0x2b);
470 gr_def(ctx, 0x406818, 0x00000f80);
471 gr_def(ctx, 0x406860, 0x007f0080);
472 gr_def(ctx, 0x40689c, 0x007f0080);
474 cp_ctx(ctx, 0x406814, 0x4);
475 if (dev_priv->chipset == 0x98)
476 gr_def(ctx, 0x406818, 0x00000f80);
478 gr_def(ctx, 0x406818, 0x00001f80);
479 if (IS_NVA3F(dev_priv->chipset))
480 gr_def(ctx, 0x40681c, 0x00000030);
481 cp_ctx(ctx, 0x406830, 0x3);
484 /* 7000: per-ROP group state */
485 for (i = 0; i < 8; i++) {
486 if (units & (1<<(i+16))) {
487 cp_ctx(ctx, 0x407000 + (i<<8), 3);
488 if (dev_priv->chipset == 0x50)
489 gr_def(ctx, 0x407000 + (i<<8), 0x1b74f820);
490 else if (dev_priv->chipset != 0xa5)
491 gr_def(ctx, 0x407000 + (i<<8), 0x3b74f821);
493 gr_def(ctx, 0x407000 + (i<<8), 0x7b74f821);
494 gr_def(ctx, 0x407004 + (i<<8), 0x89058001);
496 if (dev_priv->chipset == 0x50) {
497 cp_ctx(ctx, 0x407010 + (i<<8), 1);
498 } else if (dev_priv->chipset < 0xa0) {
499 cp_ctx(ctx, 0x407010 + (i<<8), 2);
500 gr_def(ctx, 0x407010 + (i<<8), 0x00001000);
501 gr_def(ctx, 0x407014 + (i<<8), 0x0000001f);
503 cp_ctx(ctx, 0x407010 + (i<<8), 3);
504 gr_def(ctx, 0x407010 + (i<<8), 0x00001000);
505 if (dev_priv->chipset != 0xa5)
506 gr_def(ctx, 0x407014 + (i<<8), 0x000000ff);
508 gr_def(ctx, 0x407014 + (i<<8), 0x000001ff);
511 cp_ctx(ctx, 0x407080 + (i<<8), 4);
512 if (dev_priv->chipset != 0xa5)
513 gr_def(ctx, 0x407080 + (i<<8), 0x027c10fa);
515 gr_def(ctx, 0x407080 + (i<<8), 0x827c10fa);
516 if (dev_priv->chipset == 0x50)
517 gr_def(ctx, 0x407084 + (i<<8), 0x000000c0);
519 gr_def(ctx, 0x407084 + (i<<8), 0x400000c0);
520 gr_def(ctx, 0x407088 + (i<<8), 0xb7892080);
522 if (dev_priv->chipset < 0xa0)
523 cp_ctx(ctx, 0x407094 + (i<<8), 1);
524 else if (!IS_NVA3F(dev_priv->chipset))
525 cp_ctx(ctx, 0x407094 + (i<<8), 3);
527 cp_ctx(ctx, 0x407094 + (i<<8), 4);
528 gr_def(ctx, 0x4070a0 + (i<<8), 1);
533 cp_ctx(ctx, 0x407c00, 0x3);
534 if (dev_priv->chipset < 0x90)
535 gr_def(ctx, 0x407c00, 0x00010040);
536 else if (dev_priv->chipset < 0xa0)
537 gr_def(ctx, 0x407c00, 0x00390040);
539 gr_def(ctx, 0x407c00, 0x003d0040);
540 gr_def(ctx, 0x407c08, 0x00000022);
541 if (dev_priv->chipset >= 0xa0) {
542 cp_ctx(ctx, 0x407c10, 0x3);
543 cp_ctx(ctx, 0x407c20, 0x1);
544 cp_ctx(ctx, 0x407c2c, 0x1);
547 if (dev_priv->chipset < 0xa0) {
548 cp_ctx(ctx, 0x407d00, 0x9);
550 cp_ctx(ctx, 0x407d00, 0x15);
552 if (dev_priv->chipset == 0x98)
553 gr_def(ctx, 0x407d08, 0x00380040);
555 if (dev_priv->chipset < 0x90)
556 gr_def(ctx, 0x407d08, 0x00010040);
557 else if (dev_priv->chipset < 0xa0)
558 gr_def(ctx, 0x407d08, 0x00390040);
560 gr_def(ctx, 0x407d08, 0x003d0040);
561 gr_def(ctx, 0x407d0c, 0x00000022);
564 /* 8000+: per-TP state */
565 for (i = 0; i < 10; i++) {
566 if (units & (1<<i)) {
567 if (dev_priv->chipset < 0xa0)
568 base = 0x408000 + (i<<12);
570 base = 0x408000 + (i<<11);
571 if (dev_priv->chipset < 0xa0)
572 offset = base + 0xc00;
574 offset = base + 0x80;
575 cp_ctx(ctx, offset + 0x00, 1);
576 gr_def(ctx, offset + 0x00, 0x0000ff0a);
577 cp_ctx(ctx, offset + 0x08, 1);
580 for (j = 0; j < (dev_priv->chipset < 0xa0 ? 2 : 4); j++) {
581 if (!(units & (1 << (j+24)))) continue;
582 if (dev_priv->chipset < 0xa0)
583 offset = base + 0x200 + (j<<7);
585 offset = base + 0x100 + (j<<7);
586 cp_ctx(ctx, offset, 0x20);
587 gr_def(ctx, offset + 0x00, 0x01800000);
588 gr_def(ctx, offset + 0x04, 0x00160000);
589 gr_def(ctx, offset + 0x08, 0x01800000);
590 gr_def(ctx, offset + 0x18, 0x0003ffff);
591 switch (dev_priv->chipset) {
593 gr_def(ctx, offset + 0x1c, 0x00080000);
596 gr_def(ctx, offset + 0x1c, 0x00880000);
599 gr_def(ctx, offset + 0x1c, 0x008c0000);
604 gr_def(ctx, offset + 0x1c, 0x118c0000);
607 gr_def(ctx, offset + 0x1c, 0x10880000);
611 gr_def(ctx, offset + 0x1c, 0x310c0000);
618 gr_def(ctx, offset + 0x1c, 0x300c0000);
621 gr_def(ctx, offset + 0x40, 0x00010401);
622 if (dev_priv->chipset == 0x50)
623 gr_def(ctx, offset + 0x48, 0x00000040);
625 gr_def(ctx, offset + 0x48, 0x00000078);
626 gr_def(ctx, offset + 0x50, 0x000000bf);
627 gr_def(ctx, offset + 0x58, 0x00001210);
628 if (dev_priv->chipset == 0x50)
629 gr_def(ctx, offset + 0x5c, 0x00000080);
631 gr_def(ctx, offset + 0x5c, 0x08000080);
632 if (dev_priv->chipset >= 0xa0)
633 gr_def(ctx, offset + 0x68, 0x0000003e);
636 if (dev_priv->chipset < 0xa0)
637 cp_ctx(ctx, base + 0x300, 0x4);
639 cp_ctx(ctx, base + 0x300, 0x5);
640 if (dev_priv->chipset == 0x50)
641 gr_def(ctx, base + 0x304, 0x00007070);
642 else if (dev_priv->chipset < 0xa0)
643 gr_def(ctx, base + 0x304, 0x00027070);
644 else if (!IS_NVA3F(dev_priv->chipset))
645 gr_def(ctx, base + 0x304, 0x01127070);
647 gr_def(ctx, base + 0x304, 0x05127070);
649 if (dev_priv->chipset < 0xa0)
650 cp_ctx(ctx, base + 0x318, 1);
652 cp_ctx(ctx, base + 0x320, 1);
653 if (dev_priv->chipset == 0x50)
654 gr_def(ctx, base + 0x318, 0x0003ffff);
655 else if (dev_priv->chipset < 0xa0)
656 gr_def(ctx, base + 0x318, 0x03ffffff);
658 gr_def(ctx, base + 0x320, 0x07ffffff);
660 if (dev_priv->chipset < 0xa0)
661 cp_ctx(ctx, base + 0x324, 5);
663 cp_ctx(ctx, base + 0x328, 4);
665 if (dev_priv->chipset < 0xa0) {
666 cp_ctx(ctx, base + 0x340, 9);
667 offset = base + 0x340;
668 } else if (!IS_NVA3F(dev_priv->chipset)) {
669 cp_ctx(ctx, base + 0x33c, 0xb);
670 offset = base + 0x344;
672 cp_ctx(ctx, base + 0x33c, 0xd);
673 offset = base + 0x344;
675 gr_def(ctx, offset + 0x0, 0x00120407);
676 gr_def(ctx, offset + 0x4, 0x05091507);
677 if (dev_priv->chipset == 0x84)
678 gr_def(ctx, offset + 0x8, 0x05100202);
680 gr_def(ctx, offset + 0x8, 0x05010202);
681 gr_def(ctx, offset + 0xc, 0x00030201);
682 if (dev_priv->chipset == 0xa3)
683 cp_ctx(ctx, base + 0x36c, 1);
685 cp_ctx(ctx, base + 0x400, 2);
686 gr_def(ctx, base + 0x404, 0x00000040);
687 cp_ctx(ctx, base + 0x40c, 2);
688 gr_def(ctx, base + 0x40c, 0x0d0c0b0a);
689 gr_def(ctx, base + 0x410, 0x00141210);
691 if (dev_priv->chipset < 0xa0)
692 offset = base + 0x800;
694 offset = base + 0x500;
695 cp_ctx(ctx, offset, 6);
696 gr_def(ctx, offset + 0x0, 0x000001f0);
697 gr_def(ctx, offset + 0x4, 0x00000001);
698 gr_def(ctx, offset + 0x8, 0x00000003);
699 if (dev_priv->chipset == 0x50 || IS_NVAAF(dev_priv->chipset))
700 gr_def(ctx, offset + 0xc, 0x00008000);
701 gr_def(ctx, offset + 0x14, 0x00039e00);
702 cp_ctx(ctx, offset + 0x1c, 2);
703 if (dev_priv->chipset == 0x50)
704 gr_def(ctx, offset + 0x1c, 0x00000040);
706 gr_def(ctx, offset + 0x1c, 0x00000100);
707 gr_def(ctx, offset + 0x20, 0x00003800);
709 if (dev_priv->chipset >= 0xa0) {
710 cp_ctx(ctx, base + 0x54c, 2);
711 if (!IS_NVA3F(dev_priv->chipset))
712 gr_def(ctx, base + 0x54c, 0x003fe006);
714 gr_def(ctx, base + 0x54c, 0x003fe007);
715 gr_def(ctx, base + 0x550, 0x003fe000);
718 if (dev_priv->chipset < 0xa0)
719 offset = base + 0xa00;
721 offset = base + 0x680;
722 cp_ctx(ctx, offset, 1);
723 gr_def(ctx, offset, 0x00404040);
725 if (dev_priv->chipset < 0xa0)
726 offset = base + 0xe00;
728 offset = base + 0x700;
729 cp_ctx(ctx, offset, 2);
730 if (dev_priv->chipset < 0xa0)
731 gr_def(ctx, offset, 0x0077f005);
732 else if (dev_priv->chipset == 0xa5)
733 gr_def(ctx, offset, 0x6cf7f007);
734 else if (dev_priv->chipset == 0xa8)
735 gr_def(ctx, offset, 0x6cfff007);
736 else if (dev_priv->chipset == 0xac)
737 gr_def(ctx, offset, 0x0cfff007);
739 gr_def(ctx, offset, 0x0cf7f007);
740 if (dev_priv->chipset == 0x50)
741 gr_def(ctx, offset + 0x4, 0x00007fff);
742 else if (dev_priv->chipset < 0xa0)
743 gr_def(ctx, offset + 0x4, 0x003f7fff);
745 gr_def(ctx, offset + 0x4, 0x02bf7fff);
746 cp_ctx(ctx, offset + 0x2c, 1);
747 if (dev_priv->chipset == 0x50) {
748 cp_ctx(ctx, offset + 0x50, 9);
749 gr_def(ctx, offset + 0x54, 0x000003ff);
750 gr_def(ctx, offset + 0x58, 0x00000003);
751 gr_def(ctx, offset + 0x5c, 0x00000003);
752 gr_def(ctx, offset + 0x60, 0x000001ff);
753 gr_def(ctx, offset + 0x64, 0x0000001f);
754 gr_def(ctx, offset + 0x68, 0x0000000f);
755 gr_def(ctx, offset + 0x6c, 0x0000000f);
756 } else if (dev_priv->chipset < 0xa0) {
757 cp_ctx(ctx, offset + 0x50, 1);
758 cp_ctx(ctx, offset + 0x70, 1);
760 cp_ctx(ctx, offset + 0x50, 1);
761 cp_ctx(ctx, offset + 0x60, 5);
768 dd_emit(struct nouveau_grctx *ctx, int num, uint32_t val) {
770 if (val && ctx->mode == NOUVEAU_GRCTX_VALS)
771 for (i = 0; i < num; i++)
772 nv_wo32(ctx->data, 4 * (ctx->ctxvals_pos + i), val);
773 ctx->ctxvals_pos += num;
777 nv50_graph_construct_mmio_ddata(struct nouveau_grctx *ctx)
779 struct drm_nouveau_private *dev_priv = ctx->dev->dev_private;
781 base = ctx->ctxvals_pos;
784 dd_emit(ctx, 1, 0); /* 00000001 UNK0F90 */
785 dd_emit(ctx, 1, 0); /* 00000001 UNK135C */
788 dd_emit(ctx, 1, 0); /* 00000007 SRC_TILE_MODE_Z */
789 dd_emit(ctx, 1, 2); /* 00000007 SRC_TILE_MODE_Y */
790 dd_emit(ctx, 1, 1); /* 00000001 SRC_LINEAR #1 */
791 dd_emit(ctx, 1, 0); /* 000000ff SRC_ADDRESS_HIGH */
792 dd_emit(ctx, 1, 0); /* 00000001 SRC_SRGB */
793 if (dev_priv->chipset >= 0x94)
794 dd_emit(ctx, 1, 0); /* 00000003 eng2d UNK0258 */
795 dd_emit(ctx, 1, 1); /* 00000fff SRC_DEPTH */
796 dd_emit(ctx, 1, 0x100); /* 0000ffff SRC_HEIGHT */
799 dd_emit(ctx, 1, 0); /* 0000000f TEXTURES_LOG2 */
800 dd_emit(ctx, 1, 0); /* 0000000f SAMPLERS_LOG2 */
801 dd_emit(ctx, 1, 0); /* 000000ff CB_DEF_ADDRESS_HIGH */
802 dd_emit(ctx, 1, 0); /* ffffffff CB_DEF_ADDRESS_LOW */
803 dd_emit(ctx, 1, 0); /* ffffffff SHARED_SIZE */
804 dd_emit(ctx, 1, 2); /* ffffffff REG_MODE */
805 dd_emit(ctx, 1, 1); /* 0000ffff BLOCK_ALLOC_THREADS */
806 dd_emit(ctx, 1, 1); /* 00000001 LANES32 */
807 dd_emit(ctx, 1, 0); /* 000000ff UNK370 */
808 dd_emit(ctx, 1, 0); /* 000000ff USER_PARAM_UNK */
809 dd_emit(ctx, 1, 0); /* 000000ff USER_PARAM_COUNT */
810 dd_emit(ctx, 1, 1); /* 000000ff UNK384 bits 8-15 */
811 dd_emit(ctx, 1, 0x3fffff); /* 003fffff TIC_LIMIT */
812 dd_emit(ctx, 1, 0x1fff); /* 000fffff TSC_LIMIT */
813 dd_emit(ctx, 1, 0); /* 0000ffff CB_ADDR_INDEX */
814 dd_emit(ctx, 1, 1); /* 000007ff BLOCKDIM_X */
815 dd_emit(ctx, 1, 1); /* 000007ff BLOCKDIM_XMY */
816 dd_emit(ctx, 1, 0); /* 00000001 BLOCKDIM_XMY_OVERFLOW */
817 dd_emit(ctx, 1, 1); /* 0003ffff BLOCKDIM_XMYMZ */
818 dd_emit(ctx, 1, 1); /* 000007ff BLOCKDIM_Y */
819 dd_emit(ctx, 1, 1); /* 0000007f BLOCKDIM_Z */
820 dd_emit(ctx, 1, 4); /* 000000ff CP_REG_ALLOC_TEMP */
821 dd_emit(ctx, 1, 1); /* 00000001 BLOCKDIM_DIRTY */
822 if (IS_NVA3F(dev_priv->chipset))
823 dd_emit(ctx, 1, 0); /* 00000003 UNK03E8 */
824 dd_emit(ctx, 1, 1); /* 0000007f BLOCK_ALLOC_HALFWARPS */
825 dd_emit(ctx, 1, 1); /* 00000007 LOCAL_WARPS_NO_CLAMP */
826 dd_emit(ctx, 1, 7); /* 00000007 LOCAL_WARPS_LOG_ALLOC */
827 dd_emit(ctx, 1, 1); /* 00000007 STACK_WARPS_NO_CLAMP */
828 dd_emit(ctx, 1, 7); /* 00000007 STACK_WARPS_LOG_ALLOC */
829 dd_emit(ctx, 1, 1); /* 00001fff BLOCK_ALLOC_REGSLOTS_PACKED */
830 dd_emit(ctx, 1, 1); /* 00001fff BLOCK_ALLOC_REGSLOTS_STRIDED */
831 dd_emit(ctx, 1, 1); /* 000007ff BLOCK_ALLOC_THREADS */
833 /* compat 2d state */
834 if (dev_priv->chipset == 0x50) {
835 dd_emit(ctx, 4, 0); /* 0000ffff clip X, Y, W, H */
837 dd_emit(ctx, 1, 1); /* ffffffff chroma COLOR_FORMAT */
839 dd_emit(ctx, 1, 1); /* ffffffff pattern COLOR_FORMAT */
840 dd_emit(ctx, 1, 0); /* ffffffff pattern SHAPE */
841 dd_emit(ctx, 1, 1); /* ffffffff pattern PATTERN_SELECT */
843 dd_emit(ctx, 1, 0xa); /* ffffffff surf2d SRC_FORMAT */
844 dd_emit(ctx, 1, 0); /* ffffffff surf2d DMA_SRC */
845 dd_emit(ctx, 1, 0); /* 000000ff surf2d SRC_ADDRESS_HIGH */
846 dd_emit(ctx, 1, 0); /* ffffffff surf2d SRC_ADDRESS_LOW */
847 dd_emit(ctx, 1, 0x40); /* 0000ffff surf2d SRC_PITCH */
848 dd_emit(ctx, 1, 0); /* 0000000f surf2d SRC_TILE_MODE_Z */
849 dd_emit(ctx, 1, 2); /* 0000000f surf2d SRC_TILE_MODE_Y */
850 dd_emit(ctx, 1, 0x100); /* ffffffff surf2d SRC_HEIGHT */
851 dd_emit(ctx, 1, 1); /* 00000001 surf2d SRC_LINEAR */
852 dd_emit(ctx, 1, 0x100); /* ffffffff surf2d SRC_WIDTH */
854 dd_emit(ctx, 1, 0); /* 0000ffff gdirect CLIP_B_X */
855 dd_emit(ctx, 1, 0); /* 0000ffff gdirect CLIP_B_Y */
856 dd_emit(ctx, 1, 0); /* 0000ffff gdirect CLIP_C_X */
857 dd_emit(ctx, 1, 0); /* 0000ffff gdirect CLIP_C_Y */
858 dd_emit(ctx, 1, 0); /* 0000ffff gdirect CLIP_D_X */
859 dd_emit(ctx, 1, 0); /* 0000ffff gdirect CLIP_D_Y */
860 dd_emit(ctx, 1, 1); /* ffffffff gdirect COLOR_FORMAT */
861 dd_emit(ctx, 1, 0); /* ffffffff gdirect OPERATION */
862 dd_emit(ctx, 1, 0); /* 0000ffff gdirect POINT_X */
863 dd_emit(ctx, 1, 0); /* 0000ffff gdirect POINT_Y */
865 dd_emit(ctx, 1, 0); /* 0000ffff blit SRC_Y */
866 dd_emit(ctx, 1, 0); /* ffffffff blit OPERATION */
868 dd_emit(ctx, 1, 0); /* ffffffff ifc OPERATION */
870 dd_emit(ctx, 1, 0); /* ffffffff iifc INDEX_FORMAT */
871 dd_emit(ctx, 1, 0); /* ffffffff iifc LUT_OFFSET */
872 dd_emit(ctx, 1, 4); /* ffffffff iifc COLOR_FORMAT */
873 dd_emit(ctx, 1, 0); /* ffffffff iifc OPERATION */
877 dd_emit(ctx, 1, 0); /* ffffffff m2mf LINE_COUNT */
878 dd_emit(ctx, 1, 0); /* ffffffff m2mf LINE_LENGTH_IN */
879 dd_emit(ctx, 2, 0); /* ffffffff m2mf OFFSET_IN, OFFSET_OUT */
880 dd_emit(ctx, 1, 1); /* ffffffff m2mf TILING_DEPTH_OUT */
881 dd_emit(ctx, 1, 0x100); /* ffffffff m2mf TILING_HEIGHT_OUT */
882 dd_emit(ctx, 1, 0); /* ffffffff m2mf TILING_POSITION_OUT_Z */
883 dd_emit(ctx, 1, 1); /* 00000001 m2mf LINEAR_OUT */
884 dd_emit(ctx, 2, 0); /* 0000ffff m2mf TILING_POSITION_OUT_X, Y */
885 dd_emit(ctx, 1, 0x100); /* ffffffff m2mf TILING_PITCH_OUT */
886 dd_emit(ctx, 1, 1); /* ffffffff m2mf TILING_DEPTH_IN */
887 dd_emit(ctx, 1, 0x100); /* ffffffff m2mf TILING_HEIGHT_IN */
888 dd_emit(ctx, 1, 0); /* ffffffff m2mf TILING_POSITION_IN_Z */
889 dd_emit(ctx, 1, 1); /* 00000001 m2mf LINEAR_IN */
890 dd_emit(ctx, 2, 0); /* 0000ffff m2mf TILING_POSITION_IN_X, Y */
891 dd_emit(ctx, 1, 0x100); /* ffffffff m2mf TILING_PITCH_IN */
893 /* more compat 2d state */
894 if (dev_priv->chipset == 0x50) {
895 dd_emit(ctx, 1, 1); /* ffffffff line COLOR_FORMAT */
896 dd_emit(ctx, 1, 0); /* ffffffff line OPERATION */
898 dd_emit(ctx, 1, 1); /* ffffffff triangle COLOR_FORMAT */
899 dd_emit(ctx, 1, 0); /* ffffffff triangle OPERATION */
901 dd_emit(ctx, 1, 0); /* 0000000f sifm TILE_MODE_Z */
902 dd_emit(ctx, 1, 2); /* 0000000f sifm TILE_MODE_Y */
903 dd_emit(ctx, 1, 0); /* 000000ff sifm FORMAT_FILTER */
904 dd_emit(ctx, 1, 1); /* 000000ff sifm FORMAT_ORIGIN */
905 dd_emit(ctx, 1, 0); /* 0000ffff sifm SRC_PITCH */
906 dd_emit(ctx, 1, 1); /* 00000001 sifm SRC_LINEAR */
907 dd_emit(ctx, 1, 0); /* 000000ff sifm SRC_OFFSET_HIGH */
908 dd_emit(ctx, 1, 0); /* ffffffff sifm SRC_OFFSET */
909 dd_emit(ctx, 1, 0); /* 0000ffff sifm SRC_HEIGHT */
910 dd_emit(ctx, 1, 0); /* 0000ffff sifm SRC_WIDTH */
911 dd_emit(ctx, 1, 3); /* ffffffff sifm COLOR_FORMAT */
912 dd_emit(ctx, 1, 0); /* ffffffff sifm OPERATION */
914 dd_emit(ctx, 1, 0); /* ffffffff sifc OPERATION */
918 dd_emit(ctx, 1, 0); /* 0000000f GP_TEXTURES_LOG2 */
919 dd_emit(ctx, 1, 0); /* 0000000f GP_SAMPLERS_LOG2 */
920 dd_emit(ctx, 1, 0); /* 000000ff */
921 dd_emit(ctx, 1, 0); /* ffffffff */
922 dd_emit(ctx, 1, 4); /* 000000ff UNK12B0_0 */
923 dd_emit(ctx, 1, 0x70); /* 000000ff UNK12B0_1 */
924 dd_emit(ctx, 1, 0x80); /* 000000ff UNK12B0_3 */
925 dd_emit(ctx, 1, 0); /* 000000ff UNK12B0_2 */
926 dd_emit(ctx, 1, 0); /* 0000000f FP_TEXTURES_LOG2 */
927 dd_emit(ctx, 1, 0); /* 0000000f FP_SAMPLERS_LOG2 */
928 if (IS_NVA3F(dev_priv->chipset)) {
929 dd_emit(ctx, 1, 0); /* ffffffff */
930 dd_emit(ctx, 1, 0); /* 0000007f MULTISAMPLE_SAMPLES_LOG2 */
932 dd_emit(ctx, 1, 0); /* 0000000f MULTISAMPLE_SAMPLES_LOG2 */
934 dd_emit(ctx, 1, 0xc); /* 000000ff SEMANTIC_COLOR.BFC0_ID */
935 if (dev_priv->chipset != 0x50)
936 dd_emit(ctx, 1, 0); /* 00000001 SEMANTIC_COLOR.CLMP_EN */
937 dd_emit(ctx, 1, 8); /* 000000ff SEMANTIC_COLOR.COLR_NR */
938 dd_emit(ctx, 1, 0x14); /* 000000ff SEMANTIC_COLOR.FFC0_ID */
939 if (dev_priv->chipset == 0x50) {
940 dd_emit(ctx, 1, 0); /* 000000ff SEMANTIC_LAYER */
941 dd_emit(ctx, 1, 0); /* 00000001 */
943 dd_emit(ctx, 1, 0); /* 00000001 SEMANTIC_PTSZ.ENABLE */
944 dd_emit(ctx, 1, 0x29); /* 000000ff SEMANTIC_PTSZ.PTSZ_ID */
945 dd_emit(ctx, 1, 0x27); /* 000000ff SEMANTIC_PRIM */
946 dd_emit(ctx, 1, 0x26); /* 000000ff SEMANTIC_LAYER */
947 dd_emit(ctx, 1, 8); /* 0000000f SMENATIC_CLIP.CLIP_HIGH */
948 dd_emit(ctx, 1, 4); /* 000000ff SEMANTIC_CLIP.CLIP_LO */
949 dd_emit(ctx, 1, 0x27); /* 000000ff UNK0FD4 */
950 dd_emit(ctx, 1, 0); /* 00000001 UNK1900 */
952 dd_emit(ctx, 1, 0); /* 00000007 RT_CONTROL_MAP0 */
953 dd_emit(ctx, 1, 1); /* 00000007 RT_CONTROL_MAP1 */
954 dd_emit(ctx, 1, 2); /* 00000007 RT_CONTROL_MAP2 */
955 dd_emit(ctx, 1, 3); /* 00000007 RT_CONTROL_MAP3 */
956 dd_emit(ctx, 1, 4); /* 00000007 RT_CONTROL_MAP4 */
957 dd_emit(ctx, 1, 5); /* 00000007 RT_CONTROL_MAP5 */
958 dd_emit(ctx, 1, 6); /* 00000007 RT_CONTROL_MAP6 */
959 dd_emit(ctx, 1, 7); /* 00000007 RT_CONTROL_MAP7 */
960 dd_emit(ctx, 1, 1); /* 0000000f RT_CONTROL_COUNT */
961 dd_emit(ctx, 8, 0); /* 00000001 RT_HORIZ_UNK */
962 dd_emit(ctx, 8, 0); /* ffffffff RT_ADDRESS_LOW */
963 dd_emit(ctx, 1, 0xcf); /* 000000ff RT_FORMAT */
964 dd_emit(ctx, 7, 0); /* 000000ff RT_FORMAT */
965 if (dev_priv->chipset != 0x50)
966 dd_emit(ctx, 3, 0); /* 1, 1, 1 */
968 dd_emit(ctx, 2, 0); /* 1, 1 */
969 dd_emit(ctx, 1, 0); /* ffffffff GP_ENABLE */
970 dd_emit(ctx, 1, 0x80); /* 0000ffff GP_VERTEX_OUTPUT_COUNT*/
971 dd_emit(ctx, 1, 4); /* 000000ff GP_REG_ALLOC_RESULT */
972 dd_emit(ctx, 1, 4); /* 000000ff GP_RESULT_MAP_SIZE */
973 if (IS_NVA3F(dev_priv->chipset)) {
974 dd_emit(ctx, 1, 3); /* 00000003 */
975 dd_emit(ctx, 1, 0); /* 00000001 UNK1418. Alone. */
977 if (dev_priv->chipset != 0x50)
978 dd_emit(ctx, 1, 3); /* 00000003 UNK15AC */
979 dd_emit(ctx, 1, 1); /* ffffffff RASTERIZE_ENABLE */
980 dd_emit(ctx, 1, 0); /* 00000001 FP_CONTROL.EXPORTS_Z */
981 if (dev_priv->chipset != 0x50)
982 dd_emit(ctx, 1, 0); /* 00000001 FP_CONTROL.MULTIPLE_RESULTS */
983 dd_emit(ctx, 1, 0x12); /* 000000ff FP_INTERPOLANT_CTRL.COUNT */
984 dd_emit(ctx, 1, 0x10); /* 000000ff FP_INTERPOLANT_CTRL.COUNT_NONFLAT */
985 dd_emit(ctx, 1, 0xc); /* 000000ff FP_INTERPOLANT_CTRL.OFFSET */
986 dd_emit(ctx, 1, 1); /* 00000001 FP_INTERPOLANT_CTRL.UMASK.W */
987 dd_emit(ctx, 1, 0); /* 00000001 FP_INTERPOLANT_CTRL.UMASK.X */
988 dd_emit(ctx, 1, 0); /* 00000001 FP_INTERPOLANT_CTRL.UMASK.Y */
989 dd_emit(ctx, 1, 0); /* 00000001 FP_INTERPOLANT_CTRL.UMASK.Z */
990 dd_emit(ctx, 1, 4); /* 000000ff FP_RESULT_COUNT */
991 dd_emit(ctx, 1, 2); /* ffffffff REG_MODE */
992 dd_emit(ctx, 1, 4); /* 000000ff FP_REG_ALLOC_TEMP */
993 if (dev_priv->chipset >= 0xa0)
994 dd_emit(ctx, 1, 0); /* ffffffff */
995 dd_emit(ctx, 1, 0); /* 00000001 GP_BUILTIN_RESULT_EN.LAYER_IDX */
996 dd_emit(ctx, 1, 0); /* ffffffff STRMOUT_ENABLE */
997 dd_emit(ctx, 1, 0x3fffff); /* 003fffff TIC_LIMIT */
998 dd_emit(ctx, 1, 0x1fff); /* 000fffff TSC_LIMIT */
999 dd_emit(ctx, 1, 0); /* 00000001 VERTEX_TWO_SIDE_ENABLE*/
1000 if (dev_priv->chipset != 0x50)
1001 dd_emit(ctx, 8, 0); /* 00000001 */
1002 if (dev_priv->chipset >= 0xa0) {
1003 dd_emit(ctx, 1, 1); /* 00000007 VTX_ATTR_DEFINE.COMP */
1004 dd_emit(ctx, 1, 1); /* 00000007 VTX_ATTR_DEFINE.SIZE */
1005 dd_emit(ctx, 1, 2); /* 00000007 VTX_ATTR_DEFINE.TYPE */
1006 dd_emit(ctx, 1, 0); /* 000000ff VTX_ATTR_DEFINE.ATTR */
1008 dd_emit(ctx, 1, 4); /* 0000007f VP_RESULT_MAP_SIZE */
1009 dd_emit(ctx, 1, 0x14); /* 0000001f ZETA_FORMAT */
1010 dd_emit(ctx, 1, 1); /* 00000001 ZETA_ENABLE */
1011 dd_emit(ctx, 1, 0); /* 0000000f VP_TEXTURES_LOG2 */
1012 dd_emit(ctx, 1, 0); /* 0000000f VP_SAMPLERS_LOG2 */
1013 if (IS_NVA3F(dev_priv->chipset))
1014 dd_emit(ctx, 1, 0); /* 00000001 */
1015 dd_emit(ctx, 1, 2); /* 00000003 POLYGON_MODE_BACK */
1016 if (dev_priv->chipset >= 0xa0)
1017 dd_emit(ctx, 1, 0); /* 00000003 VTX_ATTR_DEFINE.SIZE - 1 */
1018 dd_emit(ctx, 1, 0); /* 0000ffff CB_ADDR_INDEX */
1019 if (dev_priv->chipset >= 0xa0)
1020 dd_emit(ctx, 1, 0); /* 00000003 */
1021 dd_emit(ctx, 1, 0); /* 00000001 CULL_FACE_ENABLE */
1022 dd_emit(ctx, 1, 1); /* 00000003 CULL_FACE */
1023 dd_emit(ctx, 1, 0); /* 00000001 FRONT_FACE */
1024 dd_emit(ctx, 1, 2); /* 00000003 POLYGON_MODE_FRONT */
1025 dd_emit(ctx, 1, 0x1000); /* 00007fff UNK141C */
1026 if (dev_priv->chipset != 0x50) {
1027 dd_emit(ctx, 1, 0xe00); /* 7fff */
1028 dd_emit(ctx, 1, 0x1000); /* 7fff */
1029 dd_emit(ctx, 1, 0x1e00); /* 7fff */
1031 dd_emit(ctx, 1, 0); /* 00000001 BEGIN_END_ACTIVE */
1032 dd_emit(ctx, 1, 1); /* 00000001 POLYGON_MODE_??? */
1033 dd_emit(ctx, 1, 1); /* 000000ff GP_REG_ALLOC_TEMP / 4 rounded up */
1034 dd_emit(ctx, 1, 1); /* 000000ff FP_REG_ALLOC_TEMP... without /4? */
1035 dd_emit(ctx, 1, 1); /* 000000ff VP_REG_ALLOC_TEMP / 4 rounded up */
1036 dd_emit(ctx, 1, 1); /* 00000001 */
1037 dd_emit(ctx, 1, 0); /* 00000001 */
1038 dd_emit(ctx, 1, 0); /* 00000001 VTX_ATTR_MASK_UNK0 nonempty */
1039 dd_emit(ctx, 1, 0); /* 00000001 VTX_ATTR_MASK_UNK1 nonempty */
1040 dd_emit(ctx, 1, 0x200); /* 0003ffff GP_VERTEX_OUTPUT_COUNT*GP_REG_ALLOC_RESULT */
1041 if (IS_NVA3F(dev_priv->chipset))
1042 dd_emit(ctx, 1, 0x200);
1043 dd_emit(ctx, 1, 0); /* 00000001 */
1044 if (dev_priv->chipset < 0xa0) {
1045 dd_emit(ctx, 1, 1); /* 00000001 */
1046 dd_emit(ctx, 1, 0x70); /* 000000ff */
1047 dd_emit(ctx, 1, 0x80); /* 000000ff */
1048 dd_emit(ctx, 1, 0); /* 000000ff */
1049 dd_emit(ctx, 1, 0); /* 00000001 */
1050 dd_emit(ctx, 1, 1); /* 00000001 */
1051 dd_emit(ctx, 1, 0x70); /* 000000ff */
1052 dd_emit(ctx, 1, 0x80); /* 000000ff */
1053 dd_emit(ctx, 1, 0); /* 000000ff */
1055 dd_emit(ctx, 1, 1); /* 00000001 */
1056 dd_emit(ctx, 1, 0xf0); /* 000000ff */
1057 dd_emit(ctx, 1, 0xff); /* 000000ff */
1058 dd_emit(ctx, 1, 0); /* 000000ff */
1059 dd_emit(ctx, 1, 0); /* 00000001 */
1060 dd_emit(ctx, 1, 1); /* 00000001 */
1061 dd_emit(ctx, 1, 0xf0); /* 000000ff */
1062 dd_emit(ctx, 1, 0xff); /* 000000ff */
1063 dd_emit(ctx, 1, 0); /* 000000ff */
1064 dd_emit(ctx, 1, 9); /* 0000003f UNK114C.COMP,SIZE */
1068 dd_emit(ctx, 1, 0); /* 00000001 eng2d COLOR_KEY_ENABLE */
1069 dd_emit(ctx, 1, 0); /* 00000007 eng2d COLOR_KEY_FORMAT */
1070 dd_emit(ctx, 1, 1); /* ffffffff eng2d DST_DEPTH */
1071 dd_emit(ctx, 1, 0xcf); /* 000000ff eng2d DST_FORMAT */
1072 dd_emit(ctx, 1, 0); /* ffffffff eng2d DST_LAYER */
1073 dd_emit(ctx, 1, 1); /* 00000001 eng2d DST_LINEAR */
1074 dd_emit(ctx, 1, 0); /* 00000007 eng2d PATTERN_COLOR_FORMAT */
1075 dd_emit(ctx, 1, 0); /* 00000007 eng2d OPERATION */
1076 dd_emit(ctx, 1, 0); /* 00000003 eng2d PATTERN_SELECT */
1077 dd_emit(ctx, 1, 0xcf); /* 000000ff eng2d SIFC_FORMAT */
1078 dd_emit(ctx, 1, 0); /* 00000001 eng2d SIFC_BITMAP_ENABLE */
1079 dd_emit(ctx, 1, 2); /* 00000003 eng2d SIFC_BITMAP_UNK808 */
1080 dd_emit(ctx, 1, 0); /* ffffffff eng2d BLIT_DU_DX_FRACT */
1081 dd_emit(ctx, 1, 1); /* ffffffff eng2d BLIT_DU_DX_INT */
1082 dd_emit(ctx, 1, 0); /* ffffffff eng2d BLIT_DV_DY_FRACT */
1083 dd_emit(ctx, 1, 1); /* ffffffff eng2d BLIT_DV_DY_INT */
1084 dd_emit(ctx, 1, 0); /* 00000001 eng2d BLIT_CONTROL_FILTER */
1085 dd_emit(ctx, 1, 0xcf); /* 000000ff eng2d DRAW_COLOR_FORMAT */
1086 dd_emit(ctx, 1, 0xcf); /* 000000ff eng2d SRC_FORMAT */
1087 dd_emit(ctx, 1, 1); /* 00000001 eng2d SRC_LINEAR #2 */
1089 num = ctx->ctxvals_pos - base;
1090 ctx->ctxvals_pos = base;
1091 if (IS_NVA3F(dev_priv->chipset))
1092 cp_ctx(ctx, 0x404800, num);
1094 cp_ctx(ctx, 0x405400, num);
1098 * xfer areas. These are a pain.
1100 * There are 2 xfer areas: the first one is big and contains all sorts of
1101 * stuff, the second is small and contains some per-TP context.
1103 * Each area is split into 8 "strands". The areas, when saved to grctx,
1104 * are made of 8-word blocks. Each block contains a single word from
1105 * each strand. The strands are independent of each other, their
1106 * addresses are unrelated to each other, and data in them is closely
1107 * packed together. The strand layout varies a bit between cards: here
1108 * and there, a single word is thrown out in the middle and the whole
1109 * strand is offset by a bit from corresponding one on another chipset.
1110 * For this reason, addresses of stuff in strands are almost useless.
1111 * Knowing sequence of stuff and size of gaps between them is much more
1112 * useful, and that's how we build the strands in our generator.
1114 * NVA0 takes this mess to a whole new level by cutting the old strands
1115 * into a few dozen pieces [known as genes], rearranging them randomly,
1116 * and putting them back together to make new strands. Hopefully these
1117 * genes correspond more or less directly to the same PGRAPH subunits
1118 * as in 400040 register.
1120 * The most common value in default context is 0, and when the genes
1121 * are separated by 0's, gene bounduaries are quite speculative...
1122 * some of them can be clearly deduced, others can be guessed, and yet
1123 * others won't be resolved without figuring out the real meaning of
1124 * given ctxval. For the same reason, ending point of each strand
1125 * is unknown. Except for strand 0, which is the longest strand and
1126 * its end corresponds to end of the whole xfer.
1128 * An unsolved mystery is the seek instruction: it takes an argument
1129 * in bits 8-18, and that argument is clearly the place in strands to
1130 * seek to... but the offsets don't seem to correspond to offsets as
1131 * seen in grctx. Perhaps there's another, real, not randomly-changing
1132 * addressing in strands, and the xfer insn just happens to skip over
1133 * the unused bits? NV10-NV30 PIPE comes to mind...
1135 * As far as I know, there's no way to access the xfer areas directly
1136 * without the help of ctxprog.
1140 xf_emit(struct nouveau_grctx *ctx, int num, uint32_t val) {
1142 if (val && ctx->mode == NOUVEAU_GRCTX_VALS)
1143 for (i = 0; i < num; i++)
1144 nv_wo32(ctx->data, 4 * (ctx->ctxvals_pos + (i << 3)), val);
1145 ctx->ctxvals_pos += num << 3;
1148 /* Gene declarations... */
1150 static void nv50_graph_construct_gene_dispatch(struct nouveau_grctx *ctx);
1151 static void nv50_graph_construct_gene_m2mf(struct nouveau_grctx *ctx);
1152 static void nv50_graph_construct_gene_ccache(struct nouveau_grctx *ctx);
1153 static void nv50_graph_construct_gene_unk10xx(struct nouveau_grctx *ctx);
1154 static void nv50_graph_construct_gene_unk14xx(struct nouveau_grctx *ctx);
1155 static void nv50_graph_construct_gene_zcull(struct nouveau_grctx *ctx);
1156 static void nv50_graph_construct_gene_clipid(struct nouveau_grctx *ctx);
1157 static void nv50_graph_construct_gene_unk24xx(struct nouveau_grctx *ctx);
1158 static void nv50_graph_construct_gene_vfetch(struct nouveau_grctx *ctx);
1159 static void nv50_graph_construct_gene_eng2d(struct nouveau_grctx *ctx);
1160 static void nv50_graph_construct_gene_csched(struct nouveau_grctx *ctx);
1161 static void nv50_graph_construct_gene_unk1cxx(struct nouveau_grctx *ctx);
1162 static void nv50_graph_construct_gene_strmout(struct nouveau_grctx *ctx);
1163 static void nv50_graph_construct_gene_unk34xx(struct nouveau_grctx *ctx);
1164 static void nv50_graph_construct_gene_ropm1(struct nouveau_grctx *ctx);
1165 static void nv50_graph_construct_gene_ropm2(struct nouveau_grctx *ctx);
1166 static void nv50_graph_construct_gene_ropc(struct nouveau_grctx *ctx);
1167 static void nv50_graph_construct_xfer_tp(struct nouveau_grctx *ctx);
1170 nv50_graph_construct_xfer1(struct nouveau_grctx *ctx)
1172 struct drm_nouveau_private *dev_priv = ctx->dev->dev_private;
1176 uint32_t units = nv_rd32 (ctx->dev, 0x1540);
1178 offset = (ctx->ctxvals_pos+0x3f)&~0x3f;
1179 ctx->ctxvals_base = offset;
1181 if (dev_priv->chipset < 0xa0) {
1183 ctx->ctxvals_pos = offset;
1184 nv50_graph_construct_gene_dispatch(ctx);
1185 nv50_graph_construct_gene_m2mf(ctx);
1186 nv50_graph_construct_gene_unk24xx(ctx);
1187 nv50_graph_construct_gene_clipid(ctx);
1188 nv50_graph_construct_gene_zcull(ctx);
1189 if ((ctx->ctxvals_pos-offset)/8 > size)
1190 size = (ctx->ctxvals_pos-offset)/8;
1193 ctx->ctxvals_pos = offset + 0x1;
1194 nv50_graph_construct_gene_vfetch(ctx);
1195 nv50_graph_construct_gene_eng2d(ctx);
1196 nv50_graph_construct_gene_csched(ctx);
1197 nv50_graph_construct_gene_ropm1(ctx);
1198 nv50_graph_construct_gene_ropm2(ctx);
1199 if ((ctx->ctxvals_pos-offset)/8 > size)
1200 size = (ctx->ctxvals_pos-offset)/8;
1203 ctx->ctxvals_pos = offset + 0x2;
1204 nv50_graph_construct_gene_ccache(ctx);
1205 nv50_graph_construct_gene_unk1cxx(ctx);
1206 nv50_graph_construct_gene_strmout(ctx);
1207 nv50_graph_construct_gene_unk14xx(ctx);
1208 nv50_graph_construct_gene_unk10xx(ctx);
1209 nv50_graph_construct_gene_unk34xx(ctx);
1210 if ((ctx->ctxvals_pos-offset)/8 > size)
1211 size = (ctx->ctxvals_pos-offset)/8;
1213 /* Strand 3: per-ROP group state */
1214 ctx->ctxvals_pos = offset + 3;
1215 for (i = 0; i < 6; i++)
1216 if (units & (1 << (i + 16)))
1217 nv50_graph_construct_gene_ropc(ctx);
1218 if ((ctx->ctxvals_pos-offset)/8 > size)
1219 size = (ctx->ctxvals_pos-offset)/8;
1221 /* Strands 4-7: per-TP state */
1222 for (i = 0; i < 4; i++) {
1223 ctx->ctxvals_pos = offset + 4 + i;
1224 if (units & (1 << (2 * i)))
1225 nv50_graph_construct_xfer_tp(ctx);
1226 if (units & (1 << (2 * i + 1)))
1227 nv50_graph_construct_xfer_tp(ctx);
1228 if ((ctx->ctxvals_pos-offset)/8 > size)
1229 size = (ctx->ctxvals_pos-offset)/8;
1233 ctx->ctxvals_pos = offset;
1234 nv50_graph_construct_gene_dispatch(ctx);
1235 nv50_graph_construct_gene_m2mf(ctx);
1236 nv50_graph_construct_gene_unk34xx(ctx);
1237 nv50_graph_construct_gene_csched(ctx);
1238 nv50_graph_construct_gene_unk1cxx(ctx);
1239 nv50_graph_construct_gene_strmout(ctx);
1240 if ((ctx->ctxvals_pos-offset)/8 > size)
1241 size = (ctx->ctxvals_pos-offset)/8;
1244 ctx->ctxvals_pos = offset + 1;
1245 nv50_graph_construct_gene_unk10xx(ctx);
1246 if ((ctx->ctxvals_pos-offset)/8 > size)
1247 size = (ctx->ctxvals_pos-offset)/8;
1250 ctx->ctxvals_pos = offset + 2;
1251 if (dev_priv->chipset == 0xa0)
1252 nv50_graph_construct_gene_unk14xx(ctx);
1253 nv50_graph_construct_gene_unk24xx(ctx);
1254 if ((ctx->ctxvals_pos-offset)/8 > size)
1255 size = (ctx->ctxvals_pos-offset)/8;
1258 ctx->ctxvals_pos = offset + 3;
1259 nv50_graph_construct_gene_vfetch(ctx);
1260 if ((ctx->ctxvals_pos-offset)/8 > size)
1261 size = (ctx->ctxvals_pos-offset)/8;
1264 ctx->ctxvals_pos = offset + 4;
1265 nv50_graph_construct_gene_ccache(ctx);
1266 if ((ctx->ctxvals_pos-offset)/8 > size)
1267 size = (ctx->ctxvals_pos-offset)/8;
1270 ctx->ctxvals_pos = offset + 5;
1271 nv50_graph_construct_gene_ropm2(ctx);
1272 nv50_graph_construct_gene_ropm1(ctx);
1273 /* per-ROP context */
1274 for (i = 0; i < 8; i++)
1275 if (units & (1<<(i+16)))
1276 nv50_graph_construct_gene_ropc(ctx);
1277 if ((ctx->ctxvals_pos-offset)/8 > size)
1278 size = (ctx->ctxvals_pos-offset)/8;
1281 ctx->ctxvals_pos = offset + 6;
1282 nv50_graph_construct_gene_zcull(ctx);
1283 nv50_graph_construct_gene_clipid(ctx);
1284 nv50_graph_construct_gene_eng2d(ctx);
1285 if (units & (1 << 0))
1286 nv50_graph_construct_xfer_tp(ctx);
1287 if (units & (1 << 1))
1288 nv50_graph_construct_xfer_tp(ctx);
1289 if (units & (1 << 2))
1290 nv50_graph_construct_xfer_tp(ctx);
1291 if (units & (1 << 3))
1292 nv50_graph_construct_xfer_tp(ctx);
1293 if ((ctx->ctxvals_pos-offset)/8 > size)
1294 size = (ctx->ctxvals_pos-offset)/8;
1297 ctx->ctxvals_pos = offset + 7;
1298 if (dev_priv->chipset == 0xa0) {
1299 if (units & (1 << 4))
1300 nv50_graph_construct_xfer_tp(ctx);
1301 if (units & (1 << 5))
1302 nv50_graph_construct_xfer_tp(ctx);
1303 if (units & (1 << 6))
1304 nv50_graph_construct_xfer_tp(ctx);
1305 if (units & (1 << 7))
1306 nv50_graph_construct_xfer_tp(ctx);
1307 if (units & (1 << 8))
1308 nv50_graph_construct_xfer_tp(ctx);
1309 if (units & (1 << 9))
1310 nv50_graph_construct_xfer_tp(ctx);
1312 nv50_graph_construct_gene_unk14xx(ctx);
1314 if ((ctx->ctxvals_pos-offset)/8 > size)
1315 size = (ctx->ctxvals_pos-offset)/8;
1318 ctx->ctxvals_pos = offset + size * 8;
1319 ctx->ctxvals_pos = (ctx->ctxvals_pos+0x3f)&~0x3f;
1320 cp_lsr (ctx, offset);
1321 cp_out (ctx, CP_SET_XFER_POINTER);
1323 cp_out (ctx, CP_SEEK_1);
1324 cp_out (ctx, CP_XFER_1);
1325 cp_wait(ctx, XFER, BUSY);
1329 * non-trivial demagiced parts of ctx init go here
1333 nv50_graph_construct_gene_dispatch(struct nouveau_grctx *ctx)
1335 /* start of strand 0 */
1336 struct drm_nouveau_private *dev_priv = ctx->dev->dev_private;
1338 if (dev_priv->chipset == 0x50)
1340 else if (!IS_NVA3F(dev_priv->chipset))
1345 /* the PGRAPH's internal FIFO */
1346 if (dev_priv->chipset == 0x50)
1347 xf_emit(ctx, 8*3, 0);
1349 xf_emit(ctx, 0x100*3, 0);
1350 /* and another bonus slot?!? */
1352 /* and YET ANOTHER bonus slot? */
1353 if (IS_NVA3F(dev_priv->chipset))
1356 /* CTX_SWITCH: caches of gr objects bound to subchannels. 8 values, last used index */
1365 if (dev_priv->chipset < 0x90)
1370 xf_emit(ctx, 6*2, 0);
1375 xf_emit(ctx, 6*2, 0);
1378 if (dev_priv->chipset == 0x50)
1379 xf_emit(ctx, 0x1c, 0);
1380 else if (dev_priv->chipset < 0xa0)
1381 xf_emit(ctx, 0x1e, 0);
1383 xf_emit(ctx, 0x22, 0);
1385 xf_emit(ctx, 0x15, 0);
1389 nv50_graph_construct_gene_m2mf(struct nouveau_grctx *ctx)
1391 /* Strand 0, right after dispatch */
1392 struct drm_nouveau_private *dev_priv = ctx->dev->dev_private;
1394 if (dev_priv->chipset < 0x92 || dev_priv->chipset == 0x98)
1397 xf_emit (ctx, 1, 0); /* DMA_NOTIFY instance >> 4 */
1398 xf_emit (ctx, 1, 0); /* DMA_BUFFER_IN instance >> 4 */
1399 xf_emit (ctx, 1, 0); /* DMA_BUFFER_OUT instance >> 4 */
1400 xf_emit (ctx, 1, 0); /* OFFSET_IN */
1401 xf_emit (ctx, 1, 0); /* OFFSET_OUT */
1402 xf_emit (ctx, 1, 0); /* PITCH_IN */
1403 xf_emit (ctx, 1, 0); /* PITCH_OUT */
1404 xf_emit (ctx, 1, 0); /* LINE_LENGTH */
1405 xf_emit (ctx, 1, 0); /* LINE_COUNT */
1406 xf_emit (ctx, 1, 0x21); /* FORMAT: bits 0-4 INPUT_INC, bits 5-9 OUTPUT_INC */
1407 xf_emit (ctx, 1, 1); /* LINEAR_IN */
1408 xf_emit (ctx, 1, 0x2); /* TILING_MODE_IN: bits 0-2 y tiling, bits 3-5 z tiling */
1409 xf_emit (ctx, 1, 0x100); /* TILING_PITCH_IN */
1410 xf_emit (ctx, 1, 0x100); /* TILING_HEIGHT_IN */
1411 xf_emit (ctx, 1, 1); /* TILING_DEPTH_IN */
1412 xf_emit (ctx, 1, 0); /* TILING_POSITION_IN_Z */
1413 xf_emit (ctx, 1, 0); /* TILING_POSITION_IN */
1414 xf_emit (ctx, 1, 1); /* LINEAR_OUT */
1415 xf_emit (ctx, 1, 0x2); /* TILING_MODE_OUT: bits 0-2 y tiling, bits 3-5 z tiling */
1416 xf_emit (ctx, 1, 0x100); /* TILING_PITCH_OUT */
1417 xf_emit (ctx, 1, 0x100); /* TILING_HEIGHT_OUT */
1418 xf_emit (ctx, 1, 1); /* TILING_DEPTH_OUT */
1419 xf_emit (ctx, 1, 0); /* TILING_POSITION_OUT_Z */
1420 xf_emit (ctx, 1, 0); /* TILING_POSITION_OUT */
1421 xf_emit (ctx, 1, 0); /* OFFSET_IN_HIGH */
1422 xf_emit (ctx, 1, 0); /* OFFSET_OUT_HIGH */
1425 xf_emit(ctx, 0x40, 0); /* 20 * ffffffff, 3ffff */
1427 xf_emit(ctx, 0x100, 0); /* 80 * ffffffff, 3ffff */
1428 xf_emit(ctx, 4, 0); /* 1f/7f, 0, 1f/7f, 0 [1f for smallm2mf, 7f otherwise] */
1431 xf_emit(ctx, 0x400, 0); /* ffffffff */
1433 xf_emit(ctx, 0x800, 0); /* ffffffff */
1434 xf_emit(ctx, 4, 0); /* ff/1ff, 0, 0, 0 [ff for smallm2mf, 1ff otherwise] */
1436 xf_emit(ctx, 0x40, 0); /* 20 * bits ffffffff, 3ffff */
1437 xf_emit(ctx, 0x6, 0); /* 1f, 0, 1f, 0, 1f, 0 */
1441 nv50_graph_construct_gene_ccache(struct nouveau_grctx *ctx)
1443 struct drm_nouveau_private *dev_priv = ctx->dev->dev_private;
1444 xf_emit(ctx, 2, 0); /* RO */
1445 xf_emit(ctx, 0x800, 0); /* ffffffff */
1446 switch (dev_priv->chipset) {
1450 xf_emit(ctx, 0x2b, 0);
1453 xf_emit(ctx, 0x29, 0);
1458 xf_emit(ctx, 0x27, 0);
1467 xf_emit(ctx, 0x25, 0);
1470 /* CB bindings, 0x80 of them. first word is address >> 8, second is
1471 * size >> 4 | valid << 24 */
1472 xf_emit(ctx, 0x100, 0); /* ffffffff CB_DEF */
1473 xf_emit(ctx, 1, 0); /* 0000007f CB_ADDR_BUFFER */
1474 xf_emit(ctx, 1, 0); /* 0 */
1475 xf_emit(ctx, 0x30, 0); /* ff SET_PROGRAM_CB */
1476 xf_emit(ctx, 1, 0); /* 3f last SET_PROGRAM_CB */
1477 xf_emit(ctx, 4, 0); /* RO */
1478 xf_emit(ctx, 0x100, 0); /* ffffffff */
1479 xf_emit(ctx, 8, 0); /* 1f, 0, 0, ... */
1480 xf_emit(ctx, 8, 0); /* ffffffff */
1481 xf_emit(ctx, 4, 0); /* ffffffff */
1482 xf_emit(ctx, 1, 0); /* 3 */
1483 xf_emit(ctx, 1, 0); /* ffffffff */
1484 xf_emit(ctx, 1, 0); /* 0000ffff DMA_CODE_CB */
1485 xf_emit(ctx, 1, 0); /* 0000ffff DMA_TIC */
1486 xf_emit(ctx, 1, 0); /* 0000ffff DMA_TSC */
1487 xf_emit(ctx, 1, 0); /* 00000001 LINKED_TSC */
1488 xf_emit(ctx, 1, 0); /* 000000ff TIC_ADDRESS_HIGH */
1489 xf_emit(ctx, 1, 0); /* ffffffff TIC_ADDRESS_LOW */
1490 xf_emit(ctx, 1, 0x3fffff); /* 003fffff TIC_LIMIT */
1491 xf_emit(ctx, 1, 0); /* 000000ff TSC_ADDRESS_HIGH */
1492 xf_emit(ctx, 1, 0); /* ffffffff TSC_ADDRESS_LOW */
1493 xf_emit(ctx, 1, 0x1fff); /* 000fffff TSC_LIMIT */
1494 xf_emit(ctx, 1, 0); /* 000000ff VP_ADDRESS_HIGH */
1495 xf_emit(ctx, 1, 0); /* ffffffff VP_ADDRESS_LOW */
1496 xf_emit(ctx, 1, 0); /* 00ffffff VP_START_ID */
1497 xf_emit(ctx, 1, 0); /* 000000ff CB_DEF_ADDRESS_HIGH */
1498 xf_emit(ctx, 1, 0); /* ffffffff CB_DEF_ADDRESS_LOW */
1499 xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */
1500 xf_emit(ctx, 1, 0); /* 000000ff GP_ADDRESS_HIGH */
1501 xf_emit(ctx, 1, 0); /* ffffffff GP_ADDRESS_LOW */
1502 xf_emit(ctx, 1, 0); /* 00ffffff GP_START_ID */
1503 xf_emit(ctx, 1, 0); /* 000000ff FP_ADDRESS_HIGH */
1504 xf_emit(ctx, 1, 0); /* ffffffff FP_ADDRESS_LOW */
1505 xf_emit(ctx, 1, 0); /* 00ffffff FP_START_ID */
1509 nv50_graph_construct_gene_unk10xx(struct nouveau_grctx *ctx)
1511 struct drm_nouveau_private *dev_priv = ctx->dev->dev_private;
1513 /* end of area 2 on pre-NVA0, area 1 on NVAx */
1514 xf_emit(ctx, 1, 4); /* 000000ff GP_RESULT_MAP_SIZE */
1515 xf_emit(ctx, 1, 4); /* 0000007f VP_RESULT_MAP_SIZE */
1516 xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */
1517 xf_emit(ctx, 1, 0x80); /* 0000ffff GP_VERTEX_OUTPUT_COUNT */
1518 xf_emit(ctx, 1, 4); /* 000000ff GP_REG_ALLOC_RESULT */
1519 xf_emit(ctx, 1, 0x80c14); /* 01ffffff SEMANTIC_COLOR */
1520 xf_emit(ctx, 1, 0); /* 00000001 VERTEX_TWO_SIDE_ENABLE */
1521 if (dev_priv->chipset == 0x50)
1522 xf_emit(ctx, 1, 0x3ff);
1524 xf_emit(ctx, 1, 0x7ff); /* 000007ff */
1525 xf_emit(ctx, 1, 0); /* 111/113 */
1526 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A30 */
1527 for (i = 0; i < 8; i++) {
1528 switch (dev_priv->chipset) {
1534 xf_emit(ctx, 0xa0, 0); /* ffffffff */
1540 xf_emit(ctx, 0x120, 0);
1544 xf_emit(ctx, 0x100, 0); /* ffffffff */
1549 xf_emit(ctx, 0x400, 0); /* ffffffff */
1552 xf_emit(ctx, 4, 0); /* 3f, 0, 0, 0 */
1553 xf_emit(ctx, 4, 0); /* ffffffff */
1555 xf_emit(ctx, 1, 4); /* 000000ff GP_RESULT_MAP_SIZE */
1556 xf_emit(ctx, 1, 4); /* 0000007f VP_RESULT_MAP_SIZE */
1557 xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */
1558 xf_emit(ctx, 1, 0x80); /* 0000ffff GP_VERTEX_OUTPUT_COUNT */
1559 xf_emit(ctx, 1, 4); /* 000000ff GP_REG_ALLOC_TEMP */
1560 xf_emit(ctx, 1, 1); /* 00000001 RASTERIZE_ENABLE */
1561 xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1900 */
1562 xf_emit(ctx, 1, 0x27); /* 000000ff UNK0FD4 */
1563 xf_emit(ctx, 1, 0); /* 0001ffff GP_BUILTIN_RESULT_EN */
1564 xf_emit(ctx, 1, 0x26); /* 000000ff SEMANTIC_LAYER */
1565 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A30 */
1569 nv50_graph_construct_gene_unk34xx(struct nouveau_grctx *ctx)
1571 struct drm_nouveau_private *dev_priv = ctx->dev->dev_private;
1572 /* end of area 2 on pre-NVA0, area 1 on NVAx */
1573 xf_emit(ctx, 1, 0); /* 00000001 VIEWPORT_CLIP_RECTS_EN */
1574 xf_emit(ctx, 1, 0); /* 00000003 VIEWPORT_CLIP_MODE */
1575 xf_emit(ctx, 0x10, 0x04000000); /* 07ffffff VIEWPORT_CLIP_HORIZ*8, VIEWPORT_CLIP_VERT*8 */
1576 xf_emit(ctx, 1, 0); /* 00000001 POLYGON_STIPPLE_ENABLE */
1577 xf_emit(ctx, 0x20, 0); /* ffffffff POLYGON_STIPPLE */
1578 xf_emit(ctx, 2, 0); /* 00007fff WINDOW_OFFSET_XY */
1579 xf_emit(ctx, 1, 0); /* ffff0ff3 */
1580 xf_emit(ctx, 1, 0x04e3bfdf); /* ffffffff UNK0D64 */
1581 xf_emit(ctx, 1, 0x04e3bfdf); /* ffffffff UNK0DF4 */
1582 xf_emit(ctx, 1, 0); /* 00000003 WINDOW_ORIGIN */
1583 xf_emit(ctx, 1, 0); /* 00000007 */
1584 xf_emit(ctx, 1, 0x1fe21); /* 0001ffff tesla UNK0FAC */
1585 if (dev_priv->chipset >= 0xa0)
1586 xf_emit(ctx, 1, 0x0fac6881);
1587 if (IS_NVA3F(dev_priv->chipset)) {
1594 nv50_graph_construct_gene_unk14xx(struct nouveau_grctx *ctx)
1596 struct drm_nouveau_private *dev_priv = ctx->dev->dev_private;
1597 /* middle of area 2 on pre-NVA0, beginning of area 2 on NVA0, area 7 on >NVA0 */
1598 if (dev_priv->chipset != 0x50) {
1599 xf_emit(ctx, 5, 0); /* ffffffff */
1600 xf_emit(ctx, 1, 0x80c14); /* 01ffffff SEMANTIC_COLOR */
1601 xf_emit(ctx, 1, 0); /* 00000001 */
1602 xf_emit(ctx, 1, 0); /* 000003ff */
1603 xf_emit(ctx, 1, 0x804); /* 00000fff SEMANTIC_CLIP */
1604 xf_emit(ctx, 1, 0); /* 00000001 */
1605 xf_emit(ctx, 2, 4); /* 7f, ff */
1606 xf_emit(ctx, 1, 0x8100c12); /* 1fffffff FP_INTERPOLANT_CTRL */
1608 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A30 */
1609 xf_emit(ctx, 1, 4); /* 0000007f VP_RESULT_MAP_SIZE */
1610 xf_emit(ctx, 1, 4); /* 000000ff GP_RESULT_MAP_SIZE */
1611 xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */
1612 xf_emit(ctx, 1, 0x10); /* 7f/ff VIEW_VOLUME_CLIP_CTRL */
1613 xf_emit(ctx, 1, 0); /* 000000ff VP_CLIP_DISTANCE_ENABLE */
1614 if (dev_priv->chipset != 0x50)
1615 xf_emit(ctx, 1, 0); /* 3ff */
1616 xf_emit(ctx, 1, 0); /* 000000ff tesla UNK1940 */
1617 xf_emit(ctx, 1, 0); /* 00000001 tesla UNK0D7C */
1618 xf_emit(ctx, 1, 0x804); /* 00000fff SEMANTIC_CLIP */
1619 xf_emit(ctx, 1, 1); /* 00000001 VIEWPORT_TRANSFORM_EN */
1620 xf_emit(ctx, 1, 0x1a); /* 0000001f POLYGON_MODE */
1621 if (dev_priv->chipset != 0x50)
1622 xf_emit(ctx, 1, 0x7f); /* 000000ff tesla UNK0FFC */
1623 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A30 */
1624 xf_emit(ctx, 1, 1); /* 00000001 SHADE_MODEL */
1625 xf_emit(ctx, 1, 0x80c14); /* 01ffffff SEMANTIC_COLOR */
1626 xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1900 */
1627 xf_emit(ctx, 1, 0x8100c12); /* 1fffffff FP_INTERPOLANT_CTRL */
1628 xf_emit(ctx, 1, 4); /* 0000007f VP_RESULT_MAP_SIZE */
1629 xf_emit(ctx, 1, 4); /* 000000ff GP_RESULT_MAP_SIZE */
1630 xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */
1631 xf_emit(ctx, 1, 0x10); /* 7f/ff VIEW_VOLUME_CLIP_CTRL */
1632 xf_emit(ctx, 1, 0); /* 00000001 tesla UNK0D7C */
1633 xf_emit(ctx, 1, 0); /* 00000001 tesla UNK0F8C */
1634 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A30 */
1635 xf_emit(ctx, 1, 1); /* 00000001 VIEWPORT_TRANSFORM_EN */
1636 xf_emit(ctx, 1, 0x8100c12); /* 1fffffff FP_INTERPOLANT_CTRL */
1637 xf_emit(ctx, 4, 0); /* ffffffff NOPERSPECTIVE_BITMAP */
1638 xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1900 */
1639 xf_emit(ctx, 1, 0); /* 0000000f */
1640 if (dev_priv->chipset == 0x50)
1641 xf_emit(ctx, 1, 0x3ff); /* 000003ff tesla UNK0D68 */
1643 xf_emit(ctx, 1, 0x7ff); /* 000007ff tesla UNK0D68 */
1644 xf_emit(ctx, 1, 0x80c14); /* 01ffffff SEMANTIC_COLOR */
1645 xf_emit(ctx, 1, 0); /* 00000001 VERTEX_TWO_SIDE_ENABLE */
1646 xf_emit(ctx, 0x30, 0); /* ffffffff VIEWPORT_SCALE: X0, Y0, Z0, X1, Y1, ... */
1647 xf_emit(ctx, 3, 0); /* f, 0, 0 */
1648 xf_emit(ctx, 3, 0); /* ffffffff last VIEWPORT_SCALE? */
1649 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A30 */
1650 xf_emit(ctx, 1, 1); /* 00000001 VIEWPORT_TRANSFORM_EN */
1651 xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1900 */
1652 xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1924 */
1653 xf_emit(ctx, 1, 0x10); /* 000000ff VIEW_VOLUME_CLIP_CTRL */
1654 xf_emit(ctx, 1, 0); /* 00000001 */
1655 xf_emit(ctx, 0x30, 0); /* ffffffff VIEWPORT_TRANSLATE */
1656 xf_emit(ctx, 3, 0); /* f, 0, 0 */
1657 xf_emit(ctx, 3, 0); /* ffffffff */
1658 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A30 */
1659 xf_emit(ctx, 2, 0x88); /* 000001ff tesla UNK19D8 */
1660 xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1924 */
1661 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A30 */
1662 xf_emit(ctx, 1, 4); /* 0000000f CULL_MODE */
1663 xf_emit(ctx, 2, 0); /* 07ffffff SCREEN_SCISSOR */
1664 xf_emit(ctx, 2, 0); /* 00007fff WINDOW_OFFSET_XY */
1665 xf_emit(ctx, 1, 0); /* 00000003 WINDOW_ORIGIN */
1666 xf_emit(ctx, 0x10, 0); /* 00000001 SCISSOR_ENABLE */
1667 xf_emit(ctx, 1, 0); /* 0001ffff GP_BUILTIN_RESULT_EN */
1668 xf_emit(ctx, 1, 0x26); /* 000000ff SEMANTIC_LAYER */
1669 xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1900 */
1670 xf_emit(ctx, 1, 0); /* 0000000f */
1671 xf_emit(ctx, 1, 0x3f800000); /* ffffffff LINE_WIDTH */
1672 xf_emit(ctx, 1, 0); /* 00000001 LINE_STIPPLE_ENABLE */
1673 xf_emit(ctx, 1, 0); /* 00000001 LINE_SMOOTH_ENABLE */
1674 xf_emit(ctx, 1, 0); /* 00000007 MULTISAMPLE_SAMPLES_LOG2 */
1675 if (IS_NVA3F(dev_priv->chipset))
1676 xf_emit(ctx, 1, 0); /* 00000001 */
1677 xf_emit(ctx, 1, 0x1a); /* 0000001f POLYGON_MODE */
1678 xf_emit(ctx, 1, 0x10); /* 000000ff VIEW_VOLUME_CLIP_CTRL */
1679 if (dev_priv->chipset != 0x50) {
1680 xf_emit(ctx, 1, 0); /* ffffffff */
1681 xf_emit(ctx, 1, 0); /* 00000001 */
1682 xf_emit(ctx, 1, 0); /* 000003ff */
1684 xf_emit(ctx, 0x20, 0); /* 10xbits ffffffff, 3fffff. SCISSOR_* */
1685 xf_emit(ctx, 1, 0); /* f */
1686 xf_emit(ctx, 1, 0); /* 0? */
1687 xf_emit(ctx, 1, 0); /* ffffffff */
1688 xf_emit(ctx, 1, 0); /* 003fffff */
1689 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A30 */
1690 xf_emit(ctx, 1, 0x52); /* 000001ff SEMANTIC_PTSZ */
1691 xf_emit(ctx, 1, 0); /* 0001ffff GP_BUILTIN_RESULT_EN */
1692 xf_emit(ctx, 1, 0x26); /* 000000ff SEMANTIC_LAYER */
1693 xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1900 */
1694 xf_emit(ctx, 1, 4); /* 0000007f VP_RESULT_MAP_SIZE */
1695 xf_emit(ctx, 1, 4); /* 000000ff GP_RESULT_MAP_SIZE */
1696 xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */
1697 xf_emit(ctx, 1, 0x1a); /* 0000001f POLYGON_MODE */
1698 xf_emit(ctx, 1, 0); /* 00000001 LINE_SMOOTH_ENABLE */
1699 xf_emit(ctx, 1, 0); /* 00000001 LINE_STIPPLE_ENABLE */
1700 xf_emit(ctx, 1, 0x00ffff00); /* 00ffffff LINE_STIPPLE_PATTERN */
1701 xf_emit(ctx, 1, 0); /* 0000000f */
1705 nv50_graph_construct_gene_zcull(struct nouveau_grctx *ctx)
1707 struct drm_nouveau_private *dev_priv = ctx->dev->dev_private;
1708 /* end of strand 0 on pre-NVA0, beginning of strand 6 on NVAx */
1710 xf_emit(ctx, 1, 0x3f); /* 0000003f UNK1590 */
1711 xf_emit(ctx, 1, 0); /* 00000001 ALPHA_TEST_ENABLE */
1712 xf_emit(ctx, 1, 0); /* 00000007 MULTISAMPLE_SAMPLES_LOG2 */
1713 xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1534 */
1714 xf_emit(ctx, 1, 0); /* 00000007 STENCIL_BACK_FUNC_FUNC */
1715 xf_emit(ctx, 1, 0); /* 000000ff STENCIL_BACK_FUNC_MASK */
1716 xf_emit(ctx, 1, 0); /* 000000ff STENCIL_BACK_FUNC_REF */
1717 xf_emit(ctx, 1, 0); /* 000000ff STENCIL_BACK_MASK */
1718 xf_emit(ctx, 3, 0); /* 00000007 STENCIL_BACK_OP_FAIL, ZFAIL, ZPASS */
1719 xf_emit(ctx, 1, 2); /* 00000003 tesla UNK143C */
1720 xf_emit(ctx, 2, 0x04000000); /* 07ffffff tesla UNK0D6C */
1721 xf_emit(ctx, 1, 0); /* ffff0ff3 */
1722 xf_emit(ctx, 1, 0); /* 00000001 CLIPID_ENABLE */
1723 xf_emit(ctx, 2, 0); /* ffffffff DEPTH_BOUNDS */
1724 xf_emit(ctx, 1, 0); /* 00000001 */
1725 xf_emit(ctx, 1, 0); /* 00000007 DEPTH_TEST_FUNC */
1726 xf_emit(ctx, 1, 0); /* 00000001 DEPTH_TEST_ENABLE */
1727 xf_emit(ctx, 1, 0); /* 00000001 DEPTH_WRITE_ENABLE */
1728 xf_emit(ctx, 1, 4); /* 0000000f CULL_MODE */
1729 xf_emit(ctx, 1, 0); /* 0000ffff */
1730 xf_emit(ctx, 1, 0); /* 00000001 UNK0FB0 */
1731 xf_emit(ctx, 1, 0); /* 00000001 POLYGON_STIPPLE_ENABLE */
1732 xf_emit(ctx, 1, 4); /* 00000007 FP_CONTROL */
1733 xf_emit(ctx, 1, 0); /* ffffffff */
1734 xf_emit(ctx, 1, 0); /* 0001ffff GP_BUILTIN_RESULT_EN */
1735 xf_emit(ctx, 1, 0); /* 000000ff CLEAR_STENCIL */
1736 xf_emit(ctx, 1, 0); /* 00000007 STENCIL_FRONT_FUNC_FUNC */
1737 xf_emit(ctx, 1, 0); /* 000000ff STENCIL_FRONT_FUNC_MASK */
1738 xf_emit(ctx, 1, 0); /* 000000ff STENCIL_FRONT_FUNC_REF */
1739 xf_emit(ctx, 1, 0); /* 000000ff STENCIL_FRONT_MASK */
1740 xf_emit(ctx, 3, 0); /* 00000007 STENCIL_FRONT_OP_FAIL, ZFAIL, ZPASS */
1741 xf_emit(ctx, 1, 0); /* 00000001 STENCIL_FRONT_ENABLE */
1742 xf_emit(ctx, 1, 0); /* 00000001 STENCIL_BACK_ENABLE */
1743 xf_emit(ctx, 1, 0); /* ffffffff CLEAR_DEPTH */
1744 xf_emit(ctx, 1, 0); /* 00000007 */
1745 if (dev_priv->chipset != 0x50)
1746 xf_emit(ctx, 1, 0); /* 00000003 tesla UNK1108 */
1747 xf_emit(ctx, 1, 0); /* 00000001 SAMPLECNT_ENABLE */
1748 xf_emit(ctx, 1, 0); /* 0000000f ZETA_FORMAT */
1749 xf_emit(ctx, 1, 1); /* 00000001 ZETA_ENABLE */
1750 xf_emit(ctx, 1, 0x1001); /* 00001fff ZETA_ARRAY_MODE */
1752 xf_emit(ctx, 4, 0xffff); /* 0000ffff MSAA_MASK */
1753 xf_emit(ctx, 0x10, 0); /* 00000001 SCISSOR_ENABLE */
1754 xf_emit(ctx, 0x10, 0); /* ffffffff DEPTH_RANGE_NEAR */
1755 xf_emit(ctx, 0x10, 0x3f800000); /* ffffffff DEPTH_RANGE_FAR */
1756 xf_emit(ctx, 1, 0x10); /* 7f/ff/3ff VIEW_VOLUME_CLIP_CTRL */
1757 xf_emit(ctx, 1, 0); /* 00000001 VIEWPORT_CLIP_RECTS_EN */
1758 xf_emit(ctx, 1, 3); /* 00000003 FP_CTRL_UNK196C */
1759 xf_emit(ctx, 1, 0); /* 00000003 tesla UNK1968 */
1760 if (dev_priv->chipset != 0x50)
1761 xf_emit(ctx, 1, 0); /* 0fffffff tesla UNK1104 */
1762 xf_emit(ctx, 1, 0); /* 00000001 tesla UNK151C */
1766 nv50_graph_construct_gene_clipid(struct nouveau_grctx *ctx)
1768 /* middle of strand 0 on pre-NVA0 [after 24xx], middle of area 6 on NVAx */
1770 xf_emit(ctx, 1, 0); /* 00000007 UNK0FB4 */
1772 xf_emit(ctx, 4, 0); /* 07ffffff CLIPID_REGION_HORIZ */
1773 xf_emit(ctx, 4, 0); /* 07ffffff CLIPID_REGION_VERT */
1774 xf_emit(ctx, 2, 0); /* 07ffffff SCREEN_SCISSOR */
1775 xf_emit(ctx, 2, 0x04000000); /* 07ffffff UNK1508 */
1776 xf_emit(ctx, 1, 0); /* 00000001 CLIPID_ENABLE */
1777 xf_emit(ctx, 1, 0x80); /* 00003fff CLIPID_WIDTH */
1778 xf_emit(ctx, 1, 0); /* 000000ff CLIPID_ID */
1779 xf_emit(ctx, 1, 0); /* 000000ff CLIPID_ADDRESS_HIGH */
1780 xf_emit(ctx, 1, 0); /* ffffffff CLIPID_ADDRESS_LOW */
1781 xf_emit(ctx, 1, 0x80); /* 00003fff CLIPID_HEIGHT */
1782 xf_emit(ctx, 1, 0); /* 0000ffff DMA_CLIPID */
1786 nv50_graph_construct_gene_unk24xx(struct nouveau_grctx *ctx)
1788 struct drm_nouveau_private *dev_priv = ctx->dev->dev_private;
1790 /* middle of strand 0 on pre-NVA0 [after m2mf], end of strand 2 on NVAx */
1792 xf_emit(ctx, 0x33, 0);
1796 xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */
1797 xf_emit(ctx, 1, 4); /* 0000007f VP_RESULT_MAP_SIZE */
1798 xf_emit(ctx, 1, 4); /* 000000ff GP_RESULT_MAP_SIZE */
1800 if (IS_NVA3F(dev_priv->chipset)) {
1801 xf_emit(ctx, 4, 0); /* RO */
1802 xf_emit(ctx, 0xe10, 0); /* 190 * 9: 8*ffffffff, 7ff */
1803 xf_emit(ctx, 1, 0); /* 1ff */
1804 xf_emit(ctx, 8, 0); /* 0? */
1805 xf_emit(ctx, 9, 0); /* ffffffff, 7ff */
1807 xf_emit(ctx, 4, 0); /* RO */
1808 xf_emit(ctx, 0xe10, 0); /* 190 * 9: 8*ffffffff, 7ff */
1809 xf_emit(ctx, 1, 0); /* 1ff */
1810 xf_emit(ctx, 8, 0); /* 0? */
1811 xf_emit(ctx, 9, 0); /* ffffffff, 7ff */
1813 xf_emit(ctx, 0xc, 0); /* RO */
1815 xf_emit(ctx, 0xe10, 0); /* 190 * 9: 8*ffffffff, 7ff */
1816 xf_emit(ctx, 1, 0); /* 1ff */
1817 xf_emit(ctx, 8, 0); /* 0? */
1820 xf_emit(ctx, 0xc, 0); /* RO */
1822 xf_emit(ctx, 0xe10, 0); /* 190 * 9: 8*ffffffff, 7ff */
1823 xf_emit(ctx, 1, 0); /* 1ff */
1824 xf_emit(ctx, 8, 0); /* 0? */
1827 xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */
1828 xf_emit(ctx, 1, 4); /* 000000ff GP_RESULT_MAP_SIZE */
1829 xf_emit(ctx, 1, 4); /* 0000007f VP_RESULT_MAP_SIZE */
1830 xf_emit(ctx, 1, 0x8100c12); /* 1fffffff FP_INTERPOLANT_CTRL */
1831 if (dev_priv->chipset != 0x50)
1832 xf_emit(ctx, 1, 3); /* 00000003 tesla UNK1100 */
1834 xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */
1835 xf_emit(ctx, 1, 0x8100c12); /* 1fffffff FP_INTERPOLANT_CTRL */
1836 xf_emit(ctx, 1, 0); /* 0000000f VP_GP_BUILTIN_ATTR_EN */
1837 xf_emit(ctx, 1, 0x80c14); /* 01ffffff SEMANTIC_COLOR */
1838 xf_emit(ctx, 1, 1); /* 00000001 */
1840 if (dev_priv->chipset >= 0xa0)
1841 xf_emit(ctx, 2, 4); /* 000000ff */
1842 xf_emit(ctx, 1, 0x80c14); /* 01ffffff SEMANTIC_COLOR */
1843 xf_emit(ctx, 1, 0); /* 00000001 VERTEX_TWO_SIDE_ENABLE */
1844 xf_emit(ctx, 1, 0); /* 00000001 POINT_SPRITE_ENABLE */
1845 xf_emit(ctx, 1, 0x8100c12); /* 1fffffff FP_INTERPOLANT_CTRL */
1846 xf_emit(ctx, 1, 0x27); /* 000000ff SEMANTIC_PRIM_ID */
1847 xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */
1848 xf_emit(ctx, 1, 0); /* 0000000f */
1849 xf_emit(ctx, 1, 1); /* 00000001 */
1850 for (i = 0; i < 10; i++) {
1852 xf_emit(ctx, 0x40, 0); /* ffffffff */
1853 xf_emit(ctx, 0x10, 0); /* 3, 0, 0.... */
1854 xf_emit(ctx, 0x10, 0); /* ffffffff */
1857 xf_emit(ctx, 1, 0); /* 00000001 POINT_SPRITE_CTRL */
1858 xf_emit(ctx, 1, 1); /* 00000001 */
1859 xf_emit(ctx, 1, 0); /* ffffffff */
1860 xf_emit(ctx, 4, 0); /* ffffffff NOPERSPECTIVE_BITMAP */
1861 xf_emit(ctx, 0x10, 0); /* 00ffffff POINT_COORD_REPLACE_MAP */
1862 xf_emit(ctx, 1, 0); /* 00000003 WINDOW_ORIGIN */
1863 xf_emit(ctx, 1, 0x8100c12); /* 1fffffff FP_INTERPOLANT_CTRL */
1864 if (dev_priv->chipset != 0x50)
1865 xf_emit(ctx, 1, 0); /* 000003ff */
1869 nv50_graph_construct_gene_vfetch(struct nouveau_grctx *ctx)
1871 struct drm_nouveau_private *dev_priv = ctx->dev->dev_private;
1872 int acnt = 0x10, rep, i;
1873 /* beginning of strand 1 on pre-NVA0, strand 3 on NVAx */
1874 if (IS_NVA3F(dev_priv->chipset))
1877 if (dev_priv->chipset >= 0xa0) {
1878 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK13A4 */
1879 xf_emit(ctx, 1, 1); /* 00000fff tesla UNK1318 */
1881 xf_emit(ctx, 1, 0); /* ffffffff VERTEX_BUFFER_FIRST */
1882 xf_emit(ctx, 1, 0); /* 00000001 PRIMITIVE_RESTART_ENABLE */
1883 xf_emit(ctx, 1, 0); /* 00000001 UNK0DE8 */
1884 xf_emit(ctx, 1, 0); /* ffffffff PRIMITIVE_RESTART_INDEX */
1885 xf_emit(ctx, 1, 0xf); /* ffffffff VP_ATTR_EN */
1886 xf_emit(ctx, (acnt/8)-1, 0); /* ffffffff VP_ATTR_EN */
1887 xf_emit(ctx, acnt/8, 0); /* ffffffff VTX_ATR_MASK_UNK0DD0 */
1888 xf_emit(ctx, 1, 0); /* 0000000f VP_GP_BUILTIN_ATTR_EN */
1889 xf_emit(ctx, 1, 0x20); /* 0000ffff tesla UNK129C */
1890 xf_emit(ctx, 1, 0); /* 000000ff turing UNK370??? */
1891 xf_emit(ctx, 1, 0); /* 0000ffff turing USER_PARAM_COUNT */
1892 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A30 */
1894 if (IS_NVA3F(dev_priv->chipset))
1895 xf_emit(ctx, 0xb, 0); /* RO */
1896 else if (dev_priv->chipset >= 0xa0)
1897 xf_emit(ctx, 0x9, 0); /* RO */
1899 xf_emit(ctx, 0x8, 0); /* RO */
1901 xf_emit(ctx, 1, 0); /* 00000001 EDGE_FLAG */
1902 xf_emit(ctx, 1, 0); /* 00000001 PROVOKING_VERTEX_LAST */
1903 xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */
1904 xf_emit(ctx, 1, 0x1a); /* 0000001f POLYGON_MODE */
1906 xf_emit(ctx, 0xc, 0); /* RO */
1908 xf_emit(ctx, 1, 0); /* 7f/ff */
1909 xf_emit(ctx, 1, 4); /* 7f/ff VP_REG_ALLOC_RESULT */
1910 xf_emit(ctx, 1, 4); /* 7f/ff VP_RESULT_MAP_SIZE */
1911 xf_emit(ctx, 1, 0); /* 0000000f VP_GP_BUILTIN_ATTR_EN */
1912 xf_emit(ctx, 1, 4); /* 000001ff UNK1A28 */
1913 xf_emit(ctx, 1, 8); /* 000001ff UNK0DF0 */
1914 xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */
1915 if (dev_priv->chipset == 0x50)
1916 xf_emit(ctx, 1, 0x3ff); /* 3ff tesla UNK0D68 */
1918 xf_emit(ctx, 1, 0x7ff); /* 7ff tesla UNK0D68 */
1919 if (dev_priv->chipset == 0xa8)
1920 xf_emit(ctx, 1, 0x1e00); /* 7fff */
1922 xf_emit(ctx, 0xc, 0); /* RO or close */
1924 xf_emit(ctx, 1, 0xf); /* ffffffff VP_ATTR_EN */
1925 xf_emit(ctx, (acnt/8)-1, 0); /* ffffffff VP_ATTR_EN */
1926 xf_emit(ctx, 1, 0); /* 0000000f VP_GP_BUILTIN_ATTR_EN */
1927 if (dev_priv->chipset > 0x50 && dev_priv->chipset < 0xa0)
1928 xf_emit(ctx, 2, 0); /* ffffffff */
1930 xf_emit(ctx, 1, 0); /* ffffffff */
1931 xf_emit(ctx, 1, 0); /* 00000003 tesla UNK0FD8 */
1933 if (IS_NVA3F(dev_priv->chipset)) {
1934 xf_emit(ctx, 0x10, 0); /* 0? */
1935 xf_emit(ctx, 2, 0); /* weird... */
1936 xf_emit(ctx, 2, 0); /* RO */
1938 xf_emit(ctx, 8, 0); /* 0? */
1939 xf_emit(ctx, 1, 0); /* weird... */
1940 xf_emit(ctx, 2, 0); /* RO */
1943 xf_emit(ctx, 1, 0); /* ffffffff VB_ELEMENT_BASE */
1944 xf_emit(ctx, 1, 0); /* ffffffff UNK1438 */
1945 xf_emit(ctx, acnt, 0); /* 1 tesla UNK1000 */
1946 if (dev_priv->chipset >= 0xa0)
1947 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1118? */
1949 xf_emit(ctx, acnt, 0); /* ffffffff VERTEX_ARRAY_UNK90C */
1950 xf_emit(ctx, 1, 0); /* f/1f */
1952 xf_emit(ctx, acnt, 0); /* ffffffff VERTEX_ARRAY_UNK90C */
1953 xf_emit(ctx, 1, 0); /* f/1f */
1955 xf_emit(ctx, acnt, 0); /* RO */
1956 xf_emit(ctx, 2, 0); /* RO */
1958 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK111C? */
1959 xf_emit(ctx, 1, 0); /* RO */
1961 xf_emit(ctx, 1, 0); /* 000000ff UNK15F4_ADDRESS_HIGH */
1962 xf_emit(ctx, 1, 0); /* ffffffff UNK15F4_ADDRESS_LOW */
1963 xf_emit(ctx, 1, 0); /* 000000ff UNK0F84_ADDRESS_HIGH */
1964 xf_emit(ctx, 1, 0); /* ffffffff UNK0F84_ADDRESS_LOW */
1966 xf_emit(ctx, acnt, 0); /* 00003fff VERTEX_ARRAY_ATTRIB_OFFSET */
1967 xf_emit(ctx, 3, 0); /* f/1f */
1969 xf_emit(ctx, acnt, 0); /* 00000fff VERTEX_ARRAY_STRIDE */
1970 xf_emit(ctx, 3, 0); /* f/1f */
1972 xf_emit(ctx, acnt, 0); /* ffffffff VERTEX_ARRAY_LOW */
1973 xf_emit(ctx, 3, 0); /* f/1f */
1975 xf_emit(ctx, acnt, 0); /* 000000ff VERTEX_ARRAY_HIGH */
1976 xf_emit(ctx, 3, 0); /* f/1f */
1978 xf_emit(ctx, acnt, 0); /* ffffffff VERTEX_LIMIT_LOW */
1979 xf_emit(ctx, 3, 0); /* f/1f */
1981 xf_emit(ctx, acnt, 0); /* 000000ff VERTEX_LIMIT_HIGH */
1982 xf_emit(ctx, 3, 0); /* f/1f */
1984 if (IS_NVA3F(dev_priv->chipset)) {
1985 xf_emit(ctx, acnt, 0); /* f */
1986 xf_emit(ctx, 3, 0); /* f/1f */
1989 if (IS_NVA3F(dev_priv->chipset))
1990 xf_emit(ctx, 2, 0); /* RO */
1992 xf_emit(ctx, 5, 0); /* RO */
1994 xf_emit(ctx, 1, 0); /* ffff DMA_VTXBUF */
1996 if (dev_priv->chipset < 0xa0) {
1997 xf_emit(ctx, 0x41, 0); /* RO */
1999 xf_emit(ctx, 0x11, 0); /* RO */
2000 } else if (!IS_NVA3F(dev_priv->chipset))
2001 xf_emit(ctx, 0x50, 0); /* RO */
2003 xf_emit(ctx, 0x58, 0); /* RO */
2005 xf_emit(ctx, 1, 0xf); /* ffffffff VP_ATTR_EN */
2006 xf_emit(ctx, (acnt/8)-1, 0); /* ffffffff VP_ATTR_EN */
2007 xf_emit(ctx, 1, 1); /* 1 UNK0DEC */
2009 xf_emit(ctx, acnt*4, 0); /* ffffffff VTX_ATTR */
2010 xf_emit(ctx, 4, 0); /* f/1f, 0, 0, 0 */
2012 if (IS_NVA3F(dev_priv->chipset))
2013 xf_emit(ctx, 0x1d, 0); /* RO */
2015 xf_emit(ctx, 0x16, 0); /* RO */
2017 xf_emit(ctx, 1, 0xf); /* ffffffff VP_ATTR_EN */
2018 xf_emit(ctx, (acnt/8)-1, 0); /* ffffffff VP_ATTR_EN */
2020 if (dev_priv->chipset < 0xa0)
2021 xf_emit(ctx, 8, 0); /* RO */
2022 else if (IS_NVA3F(dev_priv->chipset))
2023 xf_emit(ctx, 0xc, 0); /* RO */
2025 xf_emit(ctx, 7, 0); /* RO */
2027 xf_emit(ctx, 0xa, 0); /* RO */
2028 if (dev_priv->chipset == 0xa0)
2032 for (i = 0; i < rep; i++) {
2034 if (IS_NVA3F(dev_priv->chipset))
2035 xf_emit(ctx, 0x20, 0); /* ffffffff */
2036 xf_emit(ctx, 0x200, 0); /* ffffffff */
2037 xf_emit(ctx, 4, 0); /* 7f/ff, 0, 0, 0 */
2038 xf_emit(ctx, 4, 0); /* ffffffff */
2041 xf_emit(ctx, 1, 0); /* 113/111 */
2042 xf_emit(ctx, 1, 0xf); /* ffffffff VP_ATTR_EN */
2043 xf_emit(ctx, (acnt/8)-1, 0); /* ffffffff VP_ATTR_EN */
2044 xf_emit(ctx, acnt/8, 0); /* ffffffff VTX_ATTR_MASK_UNK0DD0 */
2045 xf_emit(ctx, 1, 0); /* 0000000f VP_GP_BUILTIN_ATTR_EN */
2046 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A30 */
2048 if (IS_NVA3F(dev_priv->chipset))
2049 xf_emit(ctx, 7, 0); /* weird... */
2051 xf_emit(ctx, 5, 0); /* weird... */
2055 nv50_graph_construct_gene_eng2d(struct nouveau_grctx *ctx)
2057 struct drm_nouveau_private *dev_priv = ctx->dev->dev_private;
2058 /* middle of strand 1 on pre-NVA0 [after vfetch], middle of strand 6 on NVAx */
2060 xf_emit(ctx, 2, 0); /* 0001ffff CLIP_X, CLIP_Y */
2061 xf_emit(ctx, 2, 0); /* 0000ffff CLIP_W, CLIP_H */
2062 xf_emit(ctx, 1, 0); /* 00000001 CLIP_ENABLE */
2063 if (dev_priv->chipset < 0xa0) {
2064 /* this is useless on everything but the original NV50,
2065 * guess they forgot to nuke it. Or just didn't bother. */
2066 xf_emit(ctx, 2, 0); /* 0000ffff IFC_CLIP_X, Y */
2067 xf_emit(ctx, 2, 1); /* 0000ffff IFC_CLIP_W, H */
2068 xf_emit(ctx, 1, 0); /* 00000001 IFC_CLIP_ENABLE */
2070 xf_emit(ctx, 1, 1); /* 00000001 DST_LINEAR */
2071 xf_emit(ctx, 1, 0x100); /* 0001ffff DST_WIDTH */
2072 xf_emit(ctx, 1, 0x100); /* 0001ffff DST_HEIGHT */
2073 xf_emit(ctx, 1, 0x11); /* 3f[NV50]/7f[NV84+] DST_FORMAT */
2074 xf_emit(ctx, 1, 0); /* 0001ffff DRAW_POINT_X */
2075 xf_emit(ctx, 1, 8); /* 0000000f DRAW_UNK58C */
2076 xf_emit(ctx, 1, 0); /* 000fffff SIFC_DST_X_FRACT */
2077 xf_emit(ctx, 1, 0); /* 0001ffff SIFC_DST_X_INT */
2078 xf_emit(ctx, 1, 0); /* 000fffff SIFC_DST_Y_FRACT */
2079 xf_emit(ctx, 1, 0); /* 0001ffff SIFC_DST_Y_INT */
2080 xf_emit(ctx, 1, 0); /* 000fffff SIFC_DX_DU_FRACT */
2081 xf_emit(ctx, 1, 1); /* 0001ffff SIFC_DX_DU_INT */
2082 xf_emit(ctx, 1, 0); /* 000fffff SIFC_DY_DV_FRACT */
2083 xf_emit(ctx, 1, 1); /* 0001ffff SIFC_DY_DV_INT */
2084 xf_emit(ctx, 1, 1); /* 0000ffff SIFC_WIDTH */
2085 xf_emit(ctx, 1, 1); /* 0000ffff SIFC_HEIGHT */
2086 xf_emit(ctx, 1, 0xcf); /* 000000ff SIFC_FORMAT */
2087 xf_emit(ctx, 1, 2); /* 00000003 SIFC_BITMAP_UNK808 */
2088 xf_emit(ctx, 1, 0); /* 00000003 SIFC_BITMAP_LINE_PACK_MODE */
2089 xf_emit(ctx, 1, 0); /* 00000001 SIFC_BITMAP_LSB_FIRST */
2090 xf_emit(ctx, 1, 0); /* 00000001 SIFC_BITMAP_ENABLE */
2091 xf_emit(ctx, 1, 0); /* 0000ffff BLIT_DST_X */
2092 xf_emit(ctx, 1, 0); /* 0000ffff BLIT_DST_Y */
2093 xf_emit(ctx, 1, 0); /* 000fffff BLIT_DU_DX_FRACT */
2094 xf_emit(ctx, 1, 1); /* 0001ffff BLIT_DU_DX_INT */
2095 xf_emit(ctx, 1, 0); /* 000fffff BLIT_DV_DY_FRACT */
2096 xf_emit(ctx, 1, 1); /* 0001ffff BLIT_DV_DY_INT */
2097 xf_emit(ctx, 1, 1); /* 0000ffff BLIT_DST_W */
2098 xf_emit(ctx, 1, 1); /* 0000ffff BLIT_DST_H */
2099 xf_emit(ctx, 1, 0); /* 000fffff BLIT_SRC_X_FRACT */
2100 xf_emit(ctx, 1, 0); /* 0001ffff BLIT_SRC_X_INT */
2101 xf_emit(ctx, 1, 0); /* 000fffff BLIT_SRC_Y_FRACT */
2102 xf_emit(ctx, 1, 0); /* 00000001 UNK888 */
2103 xf_emit(ctx, 1, 4); /* 0000003f UNK884 */
2104 xf_emit(ctx, 1, 0); /* 00000007 UNK880 */
2105 xf_emit(ctx, 1, 1); /* 0000001f tesla UNK0FB8 */
2106 xf_emit(ctx, 1, 0x15); /* 000000ff tesla UNK128C */
2107 xf_emit(ctx, 2, 0); /* 00000007, ffff0ff3 */
2108 xf_emit(ctx, 1, 0); /* 00000001 UNK260 */
2109 xf_emit(ctx, 1, 0x4444480); /* 1fffffff UNK870 */
2111 xf_emit(ctx, 0x10, 0);
2113 xf_emit(ctx, 0x27, 0);
2117 nv50_graph_construct_gene_csched(struct nouveau_grctx *ctx)
2119 struct drm_nouveau_private *dev_priv = ctx->dev->dev_private;
2120 /* middle of strand 1 on pre-NVA0 [after eng2d], middle of strand 0 on NVAx */
2122 xf_emit(ctx, 2, 0); /* 00007fff WINDOW_OFFSET_XY... what is it doing here??? */
2123 xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1924 */
2124 xf_emit(ctx, 1, 0); /* 00000003 WINDOW_ORIGIN */
2125 xf_emit(ctx, 1, 0x8100c12); /* 1fffffff FP_INTERPOLANT_CTRL */
2126 xf_emit(ctx, 1, 0); /* 000003ff */
2128 xf_emit(ctx, 1, 0); /* ffffffff turing UNK364 */
2129 xf_emit(ctx, 1, 0); /* 0000000f turing UNK36C */
2130 xf_emit(ctx, 1, 0); /* 0000ffff USER_PARAM_COUNT */
2131 xf_emit(ctx, 1, 0x100); /* 00ffffff turing UNK384 */
2132 xf_emit(ctx, 1, 0); /* 0000000f turing UNK2A0 */
2133 xf_emit(ctx, 1, 0); /* 0000ffff GRIDID */
2134 xf_emit(ctx, 1, 0x10001); /* ffffffff GRIDDIM_XY */
2135 xf_emit(ctx, 1, 0); /* ffffffff */
2136 xf_emit(ctx, 1, 0x10001); /* ffffffff BLOCKDIM_XY */
2137 xf_emit(ctx, 1, 1); /* 0000ffff BLOCKDIM_Z */
2138 xf_emit(ctx, 1, 0x10001); /* 00ffffff BLOCK_ALLOC */
2139 xf_emit(ctx, 1, 1); /* 00000001 LANES32 */
2140 xf_emit(ctx, 1, 4); /* 000000ff FP_REG_ALLOC_TEMP */
2141 xf_emit(ctx, 1, 2); /* 00000003 REG_MODE */
2143 xf_emit(ctx, 0x40, 0); /* ffffffff USER_PARAM */
2144 switch (dev_priv->chipset) {
2147 xf_emit(ctx, 8, 0); /* 7, 0, 0, 0, ... */
2148 xf_emit(ctx, 0x80, 0); /* fff */
2149 xf_emit(ctx, 2, 0); /* ff, fff */
2150 xf_emit(ctx, 0x10*2, 0); /* ffffffff, 1f */
2153 xf_emit(ctx, 8, 0); /* 7, 0, 0, 0, ... */
2154 xf_emit(ctx, 0x60, 0); /* fff */
2155 xf_emit(ctx, 2, 0); /* ff, fff */
2156 xf_emit(ctx, 0xc*2, 0); /* ffffffff, 1f */
2160 xf_emit(ctx, 8, 0); /* 7, 0, 0, 0, ... */
2161 xf_emit(ctx, 0x40, 0); /* fff */
2162 xf_emit(ctx, 2, 0); /* ff, fff */
2163 xf_emit(ctx, 8*2, 0); /* ffffffff, 1f */
2167 xf_emit(ctx, 4, 0); /* f, 0, 0, 0 */
2168 xf_emit(ctx, 0x10, 0); /* fff */
2169 xf_emit(ctx, 2, 0); /* ff, fff */
2170 xf_emit(ctx, 2*2, 0); /* ffffffff, 1f */
2173 xf_emit(ctx, 8, 0); /* 7, 0, 0, 0, ... */
2174 xf_emit(ctx, 0xf0, 0); /* fff */
2175 xf_emit(ctx, 2, 0); /* ff, fff */
2176 xf_emit(ctx, 0x1e*2, 0); /* ffffffff, 1f */
2179 xf_emit(ctx, 8, 0); /* 7, 0, 0, 0, ... */
2180 xf_emit(ctx, 0x60, 0); /* fff */
2181 xf_emit(ctx, 2, 0); /* ff, fff */
2182 xf_emit(ctx, 0xc*2, 0); /* ffffffff, 1f */
2186 xf_emit(ctx, 8, 0); /* 7, 0, 0, 0, ... */
2187 xf_emit(ctx, 0x30, 0); /* fff */
2188 xf_emit(ctx, 2, 0); /* ff, fff */
2189 xf_emit(ctx, 6*2, 0); /* ffffffff, 1f */
2192 xf_emit(ctx, 0x12, 0);
2196 xf_emit(ctx, 4, 0); /* f, 0, 0, 0 */
2197 xf_emit(ctx, 0x10, 0); /* fff */
2198 xf_emit(ctx, 2, 0); /* ff, fff */
2199 xf_emit(ctx, 2*2, 0); /* ffffffff, 1f */
2202 xf_emit(ctx, 1, 0); /* 0000000f */
2203 xf_emit(ctx, 1, 0); /* 00000000 */
2204 xf_emit(ctx, 1, 0); /* ffffffff */
2205 xf_emit(ctx, 1, 0); /* 0000001f */
2206 xf_emit(ctx, 4, 0); /* ffffffff */
2207 xf_emit(ctx, 1, 0); /* 00000003 turing UNK35C */
2208 xf_emit(ctx, 1, 0); /* ffffffff */
2209 xf_emit(ctx, 4, 0); /* ffffffff */
2210 xf_emit(ctx, 1, 0); /* 00000003 turing UNK35C */
2211 xf_emit(ctx, 1, 0); /* ffffffff */
2212 xf_emit(ctx, 1, 0); /* 000000ff */
2216 nv50_graph_construct_gene_unk1cxx(struct nouveau_grctx *ctx)
2218 struct drm_nouveau_private *dev_priv = ctx->dev->dev_private;
2219 xf_emit(ctx, 2, 0); /* 00007fff WINDOW_OFFSET_XY */
2220 xf_emit(ctx, 1, 0x3f800000); /* ffffffff LINE_WIDTH */
2221 xf_emit(ctx, 1, 0); /* 00000001 LINE_SMOOTH_ENABLE */
2222 xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1658 */
2223 xf_emit(ctx, 1, 0); /* 00000001 POLYGON_SMOOTH_ENABLE */
2224 xf_emit(ctx, 3, 0); /* 00000001 POLYGON_OFFSET_*_ENABLE */
2225 xf_emit(ctx, 1, 4); /* 0000000f CULL_MODE */
2226 xf_emit(ctx, 1, 0x1a); /* 0000001f POLYGON_MODE */
2227 xf_emit(ctx, 1, 0); /* 0000000f ZETA_FORMAT */
2228 xf_emit(ctx, 1, 0); /* 00000001 POINT_SPRITE_ENABLE */
2229 xf_emit(ctx, 1, 1); /* 00000001 tesla UNK165C */
2230 xf_emit(ctx, 0x10, 0); /* 00000001 SCISSOR_ENABLE */
2231 xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1534 */
2232 xf_emit(ctx, 1, 0); /* 00000001 LINE_STIPPLE_ENABLE */
2233 xf_emit(ctx, 1, 0x00ffff00); /* 00ffffff LINE_STIPPLE_PATTERN */
2234 xf_emit(ctx, 1, 0); /* ffffffff POLYGON_OFFSET_UNITS */
2235 xf_emit(ctx, 1, 0); /* ffffffff POLYGON_OFFSET_FACTOR */
2236 xf_emit(ctx, 1, 0); /* 00000003 tesla UNK1668 */
2237 xf_emit(ctx, 2, 0); /* 07ffffff SCREEN_SCISSOR */
2238 xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1900 */
2239 xf_emit(ctx, 1, 0xf); /* 0000000f COLOR_MASK */
2240 xf_emit(ctx, 7, 0); /* 0000000f COLOR_MASK */
2241 xf_emit(ctx, 1, 0x0fac6881); /* 0fffffff RT_CONTROL */
2242 xf_emit(ctx, 1, 0x11); /* 0000007f RT_FORMAT */
2243 xf_emit(ctx, 7, 0); /* 0000007f RT_FORMAT */
2244 xf_emit(ctx, 8, 0); /* 00000001 RT_HORIZ_LINEAR */
2245 xf_emit(ctx, 1, 4); /* 00000007 FP_CONTROL */
2246 xf_emit(ctx, 1, 0); /* 00000001 ALPHA_TEST_ENABLE */
2247 xf_emit(ctx, 1, 0); /* 00000007 ALPHA_TEST_FUNC */
2248 if (IS_NVA3F(dev_priv->chipset))
2249 xf_emit(ctx, 1, 3); /* 00000003 UNK16B4 */
2250 else if (dev_priv->chipset >= 0xa0)
2251 xf_emit(ctx, 1, 1); /* 00000001 UNK16B4 */
2252 xf_emit(ctx, 1, 0); /* 00000003 MULTISAMPLE_CTRL */
2253 xf_emit(ctx, 1, 0); /* 00000003 tesla UNK0F90 */
2254 xf_emit(ctx, 1, 2); /* 00000003 tesla UNK143C */
2255 xf_emit(ctx, 2, 0x04000000); /* 07ffffff tesla UNK0D6C */
2256 xf_emit(ctx, 1, 0); /* 000000ff STENCIL_FRONT_MASK */
2257 xf_emit(ctx, 1, 0); /* 00000001 DEPTH_WRITE_ENABLE */
2258 xf_emit(ctx, 1, 0); /* 00000001 SAMPLECNT_ENABLE */
2259 xf_emit(ctx, 1, 5); /* 0000000f UNK1408 */
2260 xf_emit(ctx, 1, 0x52); /* 000001ff SEMANTIC_PTSZ */
2261 xf_emit(ctx, 1, 0); /* ffffffff POINT_SIZE */
2262 xf_emit(ctx, 1, 0); /* 00000001 */
2263 xf_emit(ctx, 1, 0); /* 00000007 tesla UNK0FB4 */
2264 if (dev_priv->chipset != 0x50) {
2265 xf_emit(ctx, 1, 0); /* 3ff */
2266 xf_emit(ctx, 1, 1); /* 00000001 tesla UNK1110 */
2268 if (IS_NVA3F(dev_priv->chipset))
2269 xf_emit(ctx, 1, 0); /* 00000003 tesla UNK1928 */
2270 xf_emit(ctx, 0x10, 0); /* ffffffff DEPTH_RANGE_NEAR */
2271 xf_emit(ctx, 0x10, 0x3f800000); /* ffffffff DEPTH_RANGE_FAR */
2272 xf_emit(ctx, 1, 0x10); /* 000000ff VIEW_VOLUME_CLIP_CTRL */
2273 xf_emit(ctx, 0x20, 0); /* 07ffffff VIEWPORT_HORIZ, then VIEWPORT_VERT. (W&0x3fff)<<13 | (X&0x1fff). */
2274 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK187C */
2275 xf_emit(ctx, 1, 0); /* 00000003 WINDOW_ORIGIN */
2276 xf_emit(ctx, 1, 0); /* 00000001 STENCIL_FRONT_ENABLE */
2277 xf_emit(ctx, 1, 0); /* 00000001 DEPTH_TEST_ENABLE */
2278 xf_emit(ctx, 1, 0); /* 00000001 STENCIL_BACK_ENABLE */
2279 xf_emit(ctx, 1, 0); /* 000000ff STENCIL_BACK_MASK */
2280 xf_emit(ctx, 1, 0x8100c12); /* 1fffffff FP_INTERPOLANT_CTRL */
2281 xf_emit(ctx, 1, 5); /* 0000000f tesla UNK1220 */
2282 xf_emit(ctx, 1, 0); /* 00000007 MULTISAMPLE_SAMPLES_LOG2 */
2283 xf_emit(ctx, 1, 0); /* 000000ff tesla UNK1A20 */
2284 xf_emit(ctx, 1, 1); /* 00000001 ZETA_ENABLE */
2285 xf_emit(ctx, 1, 0); /* 00000001 VERTEX_TWO_SIDE_ENABLE */
2286 xf_emit(ctx, 4, 0xffff); /* 0000ffff MSAA_MASK */
2287 if (dev_priv->chipset != 0x50)
2288 xf_emit(ctx, 1, 3); /* 00000003 tesla UNK1100 */
2289 if (dev_priv->chipset < 0xa0)
2290 xf_emit(ctx, 0x1c, 0); /* RO */
2291 else if (IS_NVA3F(dev_priv->chipset))
2292 xf_emit(ctx, 0x9, 0);
2293 xf_emit(ctx, 1, 0); /* 00000001 UNK1534 */
2294 xf_emit(ctx, 1, 0); /* 00000001 LINE_SMOOTH_ENABLE */
2295 xf_emit(ctx, 1, 0); /* 00000001 LINE_STIPPLE_ENABLE */
2296 xf_emit(ctx, 1, 0x00ffff00); /* 00ffffff LINE_STIPPLE_PATTERN */
2297 xf_emit(ctx, 1, 0x1a); /* 0000001f POLYGON_MODE */
2298 xf_emit(ctx, 1, 0); /* 00000003 WINDOW_ORIGIN */
2299 if (dev_priv->chipset != 0x50) {
2300 xf_emit(ctx, 1, 3); /* 00000003 tesla UNK1100 */
2301 xf_emit(ctx, 1, 0); /* 3ff */
2303 /* XXX: the following block could belong either to unk1cxx, or
2304 * to STRMOUT. Rather hard to tell. */
2305 if (dev_priv->chipset < 0xa0)
2306 xf_emit(ctx, 0x25, 0);
2308 xf_emit(ctx, 0x3b, 0);
2312 nv50_graph_construct_gene_strmout(struct nouveau_grctx *ctx)
2314 struct drm_nouveau_private *dev_priv = ctx->dev->dev_private;
2315 xf_emit(ctx, 1, 0x102); /* 0000ffff STRMOUT_BUFFER_CTRL */
2316 xf_emit(ctx, 1, 0); /* ffffffff STRMOUT_PRIMITIVE_COUNT */
2317 xf_emit(ctx, 4, 4); /* 000000ff STRMOUT_NUM_ATTRIBS */
2318 if (dev_priv->chipset >= 0xa0) {
2319 xf_emit(ctx, 4, 0); /* ffffffff UNK1A8C */
2320 xf_emit(ctx, 4, 0); /* ffffffff UNK1780 */
2322 xf_emit(ctx, 1, 4); /* 000000ff GP_RESULT_MAP_SIZE */
2323 xf_emit(ctx, 1, 4); /* 0000007f VP_RESULT_MAP_SIZE */
2324 xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */
2325 if (dev_priv->chipset == 0x50)
2326 xf_emit(ctx, 1, 0x3ff); /* 000003ff tesla UNK0D68 */
2328 xf_emit(ctx, 1, 0x7ff); /* 000007ff tesla UNK0D68 */
2329 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A30 */
2331 xf_emit(ctx, 1, 0x102); /* 0000ffff STRMOUT_BUFFER_CTRL */
2332 xf_emit(ctx, 1, 0); /* ffffffff STRMOUT_PRIMITIVE_COUNT */
2333 xf_emit(ctx, 4, 0); /* 000000ff STRMOUT_ADDRESS_HIGH */
2334 xf_emit(ctx, 4, 0); /* ffffffff STRMOUT_ADDRESS_LOW */
2335 xf_emit(ctx, 4, 4); /* 000000ff STRMOUT_NUM_ATTRIBS */
2336 if (dev_priv->chipset >= 0xa0) {
2337 xf_emit(ctx, 4, 0); /* ffffffff UNK1A8C */
2338 xf_emit(ctx, 4, 0); /* ffffffff UNK1780 */
2340 xf_emit(ctx, 1, 0); /* 0000ffff DMA_STRMOUT */
2341 xf_emit(ctx, 1, 0); /* 0000ffff DMA_QUERY */
2342 xf_emit(ctx, 1, 0); /* 000000ff QUERY_ADDRESS_HIGH */
2343 xf_emit(ctx, 2, 0); /* ffffffff QUERY_ADDRESS_LOW QUERY_COUNTER */
2344 xf_emit(ctx, 2, 0); /* ffffffff */
2345 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A30 */
2347 xf_emit(ctx, 0x20, 0); /* ffffffff STRMOUT_MAP */
2348 xf_emit(ctx, 1, 0); /* 0000000f */
2349 xf_emit(ctx, 1, 0); /* 00000000? */
2350 xf_emit(ctx, 2, 0); /* ffffffff */
2354 nv50_graph_construct_gene_ropm1(struct nouveau_grctx *ctx)
2356 struct drm_nouveau_private *dev_priv = ctx->dev->dev_private;
2357 xf_emit(ctx, 1, 0x4e3bfdf); /* ffffffff UNK0D64 */
2358 xf_emit(ctx, 1, 0x4e3bfdf); /* ffffffff UNK0DF4 */
2359 xf_emit(ctx, 1, 0); /* 00000007 */
2360 xf_emit(ctx, 1, 0); /* 000003ff */
2361 if (IS_NVA3F(dev_priv->chipset))
2362 xf_emit(ctx, 1, 0x11); /* 000000ff tesla UNK1968 */
2363 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A3C */
2367 nv50_graph_construct_gene_ropm2(struct nouveau_grctx *ctx)
2369 struct drm_nouveau_private *dev_priv = ctx->dev->dev_private;
2371 xf_emit(ctx, 1, 0); /* 0000ffff DMA_QUERY */
2372 xf_emit(ctx, 1, 0x0fac6881); /* 0fffffff RT_CONTROL */
2373 xf_emit(ctx, 2, 0); /* ffffffff */
2374 xf_emit(ctx, 1, 0); /* 000000ff QUERY_ADDRESS_HIGH */
2375 xf_emit(ctx, 2, 0); /* ffffffff QUERY_ADDRESS_LOW, COUNTER */
2376 xf_emit(ctx, 1, 0); /* 00000001 SAMPLECNT_ENABLE */
2377 xf_emit(ctx, 1, 0); /* 7 */
2379 xf_emit(ctx, 1, 0); /* 0000ffff DMA_QUERY */
2380 xf_emit(ctx, 1, 0); /* 000000ff QUERY_ADDRESS_HIGH */
2381 xf_emit(ctx, 2, 0); /* ffffffff QUERY_ADDRESS_LOW, COUNTER */
2382 xf_emit(ctx, 1, 0x4e3bfdf); /* ffffffff UNK0D64 */
2383 xf_emit(ctx, 1, 0x4e3bfdf); /* ffffffff UNK0DF4 */
2384 xf_emit(ctx, 1, 0); /* 00000001 eng2d UNK260 */
2385 xf_emit(ctx, 1, 0); /* ff/3ff */
2386 xf_emit(ctx, 1, 0); /* 00000007 */
2387 if (IS_NVA3F(dev_priv->chipset))
2388 xf_emit(ctx, 1, 0x11); /* 000000ff tesla UNK1968 */
2389 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A3C */
2393 nv50_graph_construct_gene_ropc(struct nouveau_grctx *ctx)
2395 struct drm_nouveau_private *dev_priv = ctx->dev->dev_private;
2397 if (dev_priv->chipset == 0x50) {
2398 magic2 = 0x00003e60;
2399 } else if (!IS_NVA3F(dev_priv->chipset)) {
2400 magic2 = 0x001ffe67;
2402 magic2 = 0x00087e67;
2404 xf_emit(ctx, 1, 0); /* f/7 MUTISAMPLE_SAMPLES_LOG2 */
2405 xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1534 */
2406 xf_emit(ctx, 1, 0); /* 00000007 STENCIL_BACK_FUNC_FUNC */
2407 xf_emit(ctx, 1, 0); /* 000000ff STENCIL_BACK_FUNC_MASK */
2408 xf_emit(ctx, 1, 0); /* 000000ff STENCIL_BACK_MASK */
2409 xf_emit(ctx, 3, 0); /* 00000007 STENCIL_BACK_OP_FAIL, ZFAIL, ZPASS */
2410 xf_emit(ctx, 1, 2); /* 00000003 tesla UNK143C */
2411 xf_emit(ctx, 1, 0); /* ffff0ff3 */
2412 xf_emit(ctx, 1, magic2); /* 001fffff tesla UNK0F78 */
2413 xf_emit(ctx, 1, 0); /* 00000001 DEPTH_BOUNDS_EN */
2414 xf_emit(ctx, 1, 0); /* 00000007 DEPTH_TEST_FUNC */
2415 xf_emit(ctx, 1, 0); /* 00000001 DEPTH_TEST_ENABLE */
2416 xf_emit(ctx, 1, 0); /* 00000001 DEPTH_WRITE_ENABLE */
2417 if (IS_NVA3F(dev_priv->chipset))
2418 xf_emit(ctx, 1, 1); /* 0000001f tesla UNK169C */
2419 xf_emit(ctx, 1, 0); /* 00000007 STENCIL_FRONT_FUNC_FUNC */
2420 xf_emit(ctx, 1, 0); /* 000000ff STENCIL_FRONT_FUNC_MASK */
2421 xf_emit(ctx, 1, 0); /* 000000ff STENCIL_FRONT_MASK */
2422 xf_emit(ctx, 3, 0); /* 00000007 STENCIL_FRONT_OP_FAIL, ZFAIL, ZPASS */
2423 xf_emit(ctx, 1, 0); /* 00000001 STENCIL_FRONT_ENABLE */
2424 if (dev_priv->chipset >= 0xa0 && !IS_NVAAF(dev_priv->chipset))
2425 xf_emit(ctx, 1, 0x15); /* 000000ff */
2426 xf_emit(ctx, 1, 0); /* 00000001 STENCIL_BACK_ENABLE */
2427 xf_emit(ctx, 1, 1); /* 00000001 tesla UNK15B4 */
2428 xf_emit(ctx, 1, 0x10); /* 3ff/ff VIEW_VOLUME_CLIP_CTRL */
2429 xf_emit(ctx, 1, 0); /* ffffffff CLEAR_DEPTH */
2430 xf_emit(ctx, 1, 0); /* 0000000f ZETA_FORMAT */
2431 xf_emit(ctx, 1, 1); /* 00000001 ZETA_ENABLE */
2432 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A3C */
2433 if (dev_priv->chipset == 0x86 || dev_priv->chipset == 0x92 || dev_priv->chipset == 0x98 || dev_priv->chipset >= 0xa0) {
2434 xf_emit(ctx, 3, 0); /* ff, ffffffff, ffffffff */
2435 xf_emit(ctx, 1, 4); /* 7 */
2436 xf_emit(ctx, 1, 0x400); /* fffffff */
2437 xf_emit(ctx, 1, 0x300); /* ffff */
2438 xf_emit(ctx, 1, 0x1001); /* 1fff */
2439 if (dev_priv->chipset != 0xa0) {
2440 if (IS_NVA3F(dev_priv->chipset))
2441 xf_emit(ctx, 1, 0); /* 0000000f UNK15C8 */
2443 xf_emit(ctx, 1, 0x15); /* ff */
2446 xf_emit(ctx, 1, 0); /* 00000007 MULTISAMPLE_SAMPLES_LOG2 */
2447 xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1534 */
2448 xf_emit(ctx, 1, 0); /* 00000007 STENCIL_BACK_FUNC_FUNC */
2449 xf_emit(ctx, 1, 0); /* 000000ff STENCIL_BACK_FUNC_MASK */
2450 xf_emit(ctx, 1, 0); /* ffff0ff3 */
2451 xf_emit(ctx, 1, 2); /* 00000003 tesla UNK143C */
2452 xf_emit(ctx, 1, 0); /* 00000001 DEPTH_BOUNDS_EN */
2453 xf_emit(ctx, 1, 0); /* 00000007 DEPTH_TEST_FUNC */
2454 xf_emit(ctx, 1, 0); /* 00000001 DEPTH_TEST_ENABLE */
2455 xf_emit(ctx, 1, 0); /* 00000001 DEPTH_WRITE_ENABLE */
2456 xf_emit(ctx, 1, 0); /* 00000007 STENCIL_FRONT_FUNC_FUNC */
2457 xf_emit(ctx, 1, 0); /* 000000ff STENCIL_FRONT_FUNC_MASK */
2458 xf_emit(ctx, 1, 0); /* 00000001 STENCIL_FRONT_ENABLE */
2459 xf_emit(ctx, 1, 0); /* 00000001 STENCIL_BACK_ENABLE */
2460 xf_emit(ctx, 1, 1); /* 00000001 tesla UNK15B4 */
2461 xf_emit(ctx, 1, 0x10); /* 7f/ff VIEW_VOLUME_CLIP_CTRL */
2462 xf_emit(ctx, 1, 0); /* 0000000f ZETA_FORMAT */
2463 xf_emit(ctx, 1, 1); /* 00000001 ZETA_ENABLE */
2464 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A3C */
2465 xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1534 */
2466 xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1900 */
2467 xf_emit(ctx, 1, 0); /* 00000007 STENCIL_BACK_FUNC_FUNC */
2468 xf_emit(ctx, 1, 0); /* 000000ff STENCIL_BACK_FUNC_MASK */
2469 xf_emit(ctx, 1, 0); /* 000000ff STENCIL_BACK_FUNC_REF */
2470 xf_emit(ctx, 2, 0); /* ffffffff DEPTH_BOUNDS */
2471 xf_emit(ctx, 1, 0); /* 00000001 DEPTH_BOUNDS_EN */
2472 xf_emit(ctx, 1, 0); /* 00000007 DEPTH_TEST_FUNC */
2473 xf_emit(ctx, 1, 0); /* 00000001 DEPTH_TEST_ENABLE */
2474 xf_emit(ctx, 1, 0); /* 00000001 DEPTH_WRITE_ENABLE */
2475 xf_emit(ctx, 1, 0); /* 0000000f */
2476 xf_emit(ctx, 1, 0); /* 00000001 tesla UNK0FB0 */
2477 xf_emit(ctx, 1, 0); /* 00000007 STENCIL_FRONT_FUNC_FUNC */
2478 xf_emit(ctx, 1, 0); /* 000000ff STENCIL_FRONT_FUNC_MASK */
2479 xf_emit(ctx, 1, 0); /* 000000ff STENCIL_FRONT_FUNC_REF */
2480 xf_emit(ctx, 1, 0); /* 00000001 STENCIL_FRONT_ENABLE */
2481 xf_emit(ctx, 1, 0); /* 00000001 STENCIL_BACK_ENABLE */
2482 xf_emit(ctx, 1, 0x10); /* 7f/ff VIEW_VOLUME_CLIP_CTRL */
2483 xf_emit(ctx, 0x10, 0); /* ffffffff DEPTH_RANGE_NEAR */
2484 xf_emit(ctx, 0x10, 0x3f800000); /* ffffffff DEPTH_RANGE_FAR */
2485 xf_emit(ctx, 1, 0); /* 0000000f ZETA_FORMAT */
2486 xf_emit(ctx, 1, 0); /* 00000007 MULTISAMPLE_SAMPLES_LOG2 */
2487 xf_emit(ctx, 1, 0); /* 00000007 STENCIL_BACK_FUNC_FUNC */
2488 xf_emit(ctx, 1, 0); /* 000000ff STENCIL_BACK_FUNC_MASK */
2489 xf_emit(ctx, 1, 0); /* 000000ff STENCIL_BACK_FUNC_REF */
2490 xf_emit(ctx, 1, 0); /* 000000ff STENCIL_BACK_MASK */
2491 xf_emit(ctx, 3, 0); /* 00000007 STENCIL_BACK_OP_FAIL, ZFAIL, ZPASS */
2492 xf_emit(ctx, 2, 0); /* ffffffff DEPTH_BOUNDS */
2493 xf_emit(ctx, 1, 0); /* 00000001 DEPTH_BOUNDS_EN */
2494 xf_emit(ctx, 1, 0); /* 00000007 DEPTH_TEST_FUNC */
2495 xf_emit(ctx, 1, 0); /* 00000001 DEPTH_TEST_ENABLE */
2496 xf_emit(ctx, 1, 0); /* 00000001 DEPTH_WRITE_ENABLE */
2497 xf_emit(ctx, 1, 0); /* 000000ff CLEAR_STENCIL */
2498 xf_emit(ctx, 1, 0); /* 00000007 STENCIL_FRONT_FUNC_FUNC */
2499 xf_emit(ctx, 1, 0); /* 000000ff STENCIL_FRONT_FUNC_MASK */
2500 xf_emit(ctx, 1, 0); /* 000000ff STENCIL_FRONT_FUNC_REF */
2501 xf_emit(ctx, 1, 0); /* 000000ff STENCIL_FRONT_MASK */
2502 xf_emit(ctx, 3, 0); /* 00000007 STENCIL_FRONT_OP_FAIL, ZFAIL, ZPASS */
2503 xf_emit(ctx, 1, 0); /* 00000001 STENCIL_FRONT_ENABLE */
2504 xf_emit(ctx, 1, 0); /* 00000001 STENCIL_BACK_ENABLE */
2505 xf_emit(ctx, 1, 0x10); /* 7f/ff VIEW_VOLUME_CLIP_CTRL */
2506 xf_emit(ctx, 1, 0); /* 0000000f ZETA_FORMAT */
2507 xf_emit(ctx, 1, 0x3f); /* 0000003f UNK1590 */
2508 xf_emit(ctx, 1, 0); /* 00000007 MULTISAMPLE_SAMPLES_LOG2 */
2509 xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1534 */
2510 xf_emit(ctx, 2, 0); /* ffff0ff3, ffff */
2511 xf_emit(ctx, 1, 0); /* 00000001 tesla UNK0FB0 */
2512 xf_emit(ctx, 1, 0); /* 0001ffff GP_BUILTIN_RESULT_EN */
2513 xf_emit(ctx, 1, 1); /* 00000001 tesla UNK15B4 */
2514 xf_emit(ctx, 1, 0); /* 0000000f ZETA_FORMAT */
2515 xf_emit(ctx, 1, 1); /* 00000001 ZETA_ENABLE */
2516 xf_emit(ctx, 1, 0); /* ffffffff CLEAR_DEPTH */
2517 xf_emit(ctx, 1, 1); /* 00000001 tesla UNK19CC */
2518 if (dev_priv->chipset >= 0xa0) {
2520 xf_emit(ctx, 1, 0x1001);
2521 xf_emit(ctx, 0xb, 0);
2523 xf_emit(ctx, 1, 0); /* 00000007 */
2524 xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1534 */
2525 xf_emit(ctx, 1, 0); /* 00000007 MULTISAMPLE_SAMPLES_LOG2 */
2526 xf_emit(ctx, 8, 0); /* 00000001 BLEND_ENABLE */
2527 xf_emit(ctx, 1, 0); /* ffff0ff3 */
2529 xf_emit(ctx, 1, 0x11); /* 3f/7f RT_FORMAT */
2530 xf_emit(ctx, 7, 0); /* 3f/7f RT_FORMAT */
2531 xf_emit(ctx, 1, 0xf); /* 0000000f COLOR_MASK */
2532 xf_emit(ctx, 7, 0); /* 0000000f COLOR_MASK */
2533 xf_emit(ctx, 1, 0x11); /* 3f/7f */
2534 xf_emit(ctx, 1, 0); /* 00000001 LOGIC_OP_ENABLE */
2535 if (dev_priv->chipset != 0x50) {
2536 xf_emit(ctx, 1, 0); /* 0000000f LOGIC_OP */
2537 xf_emit(ctx, 1, 0); /* 000000ff */
2539 xf_emit(ctx, 1, 0); /* 00000007 OPERATION */
2540 xf_emit(ctx, 1, 0); /* ff/3ff */
2541 xf_emit(ctx, 1, 0); /* 00000003 UNK0F90 */
2542 xf_emit(ctx, 2, 1); /* 00000007 BLEND_EQUATION_RGB, ALPHA */
2543 xf_emit(ctx, 1, 1); /* 00000001 UNK133C */
2544 xf_emit(ctx, 1, 2); /* 0000001f BLEND_FUNC_SRC_RGB */
2545 xf_emit(ctx, 1, 1); /* 0000001f BLEND_FUNC_DST_RGB */
2546 xf_emit(ctx, 1, 2); /* 0000001f BLEND_FUNC_SRC_ALPHA */
2547 xf_emit(ctx, 1, 1); /* 0000001f BLEND_FUNC_DST_ALPHA */
2548 xf_emit(ctx, 1, 0); /* 00000001 */
2549 xf_emit(ctx, 1, magic2); /* 001fffff tesla UNK0F78 */
2550 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A3C */
2551 xf_emit(ctx, 1, 0x0fac6881); /* 0fffffff RT_CONTROL */
2552 if (IS_NVA3F(dev_priv->chipset)) {
2553 xf_emit(ctx, 1, 0); /* 00000001 tesla UNK12E4 */
2554 xf_emit(ctx, 8, 1); /* 00000007 IBLEND_EQUATION_RGB */
2555 xf_emit(ctx, 8, 1); /* 00000007 IBLEND_EQUATION_ALPHA */
2556 xf_emit(ctx, 8, 1); /* 00000001 IBLEND_UNK00 */
2557 xf_emit(ctx, 8, 2); /* 0000001f IBLEND_FUNC_SRC_RGB */
2558 xf_emit(ctx, 8, 1); /* 0000001f IBLEND_FUNC_DST_RGB */
2559 xf_emit(ctx, 8, 2); /* 0000001f IBLEND_FUNC_SRC_ALPHA */
2560 xf_emit(ctx, 8, 1); /* 0000001f IBLEND_FUNC_DST_ALPHA */
2561 xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1140 */
2562 xf_emit(ctx, 2, 0); /* 00000001 */
2563 xf_emit(ctx, 1, 1); /* 0000001f tesla UNK169C */
2564 xf_emit(ctx, 1, 0); /* 0000000f */
2565 xf_emit(ctx, 1, 0); /* 00000003 */
2566 xf_emit(ctx, 1, 0); /* ffffffff */
2567 xf_emit(ctx, 2, 0); /* 00000001 */
2568 xf_emit(ctx, 1, 1); /* 0000001f tesla UNK169C */
2569 xf_emit(ctx, 1, 0); /* 00000001 */
2570 xf_emit(ctx, 1, 0); /* 000003ff */
2571 } else if (dev_priv->chipset >= 0xa0) {
2572 xf_emit(ctx, 2, 0); /* 00000001 */
2573 xf_emit(ctx, 1, 0); /* 00000007 */
2574 xf_emit(ctx, 1, 0); /* 00000003 */
2575 xf_emit(ctx, 1, 0); /* ffffffff */
2576 xf_emit(ctx, 2, 0); /* 00000001 */
2578 xf_emit(ctx, 1, 0); /* 00000007 MULTISAMPLE_SAMPLES_LOG2 */
2579 xf_emit(ctx, 1, 0); /* 00000003 tesla UNK1430 */
2580 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A3C */
2582 xf_emit(ctx, 4, 0); /* ffffffff CLEAR_COLOR */
2583 xf_emit(ctx, 4, 0); /* ffffffff BLEND_COLOR A R G B */
2584 xf_emit(ctx, 1, 0); /* 00000fff eng2d UNK2B0 */
2585 if (dev_priv->chipset >= 0xa0)
2586 xf_emit(ctx, 2, 0); /* 00000001 */
2587 xf_emit(ctx, 1, 0); /* 000003ff */
2588 xf_emit(ctx, 8, 0); /* 00000001 BLEND_ENABLE */
2589 xf_emit(ctx, 1, 1); /* 00000001 UNK133C */
2590 xf_emit(ctx, 1, 2); /* 0000001f BLEND_FUNC_SRC_RGB */
2591 xf_emit(ctx, 1, 1); /* 0000001f BLEND_FUNC_DST_RGB */
2592 xf_emit(ctx, 1, 1); /* 00000007 BLEND_EQUATION_RGB */
2593 xf_emit(ctx, 1, 2); /* 0000001f BLEND_FUNC_SRC_ALPHA */
2594 xf_emit(ctx, 1, 1); /* 0000001f BLEND_FUNC_DST_ALPHA */
2595 xf_emit(ctx, 1, 1); /* 00000007 BLEND_EQUATION_ALPHA */
2596 xf_emit(ctx, 1, 0); /* 00000001 UNK19C0 */
2597 xf_emit(ctx, 1, 0); /* 00000001 LOGIC_OP_ENABLE */
2598 xf_emit(ctx, 1, 0); /* 0000000f LOGIC_OP */
2599 if (dev_priv->chipset >= 0xa0)
2600 xf_emit(ctx, 1, 0); /* 00000001 UNK12E4? NVA3+ only? */
2601 if (IS_NVA3F(dev_priv->chipset)) {
2602 xf_emit(ctx, 8, 1); /* 00000001 IBLEND_UNK00 */
2603 xf_emit(ctx, 8, 1); /* 00000007 IBLEND_EQUATION_RGB */
2604 xf_emit(ctx, 8, 2); /* 0000001f IBLEND_FUNC_SRC_RGB */
2605 xf_emit(ctx, 8, 1); /* 0000001f IBLEND_FUNC_DST_RGB */
2606 xf_emit(ctx, 8, 1); /* 00000007 IBLEND_EQUATION_ALPHA */
2607 xf_emit(ctx, 8, 2); /* 0000001f IBLEND_FUNC_SRC_ALPHA */
2608 xf_emit(ctx, 8, 1); /* 0000001f IBLEND_FUNC_DST_ALPHA */
2609 xf_emit(ctx, 1, 0); /* 00000001 tesla UNK15C4 */
2610 xf_emit(ctx, 1, 0); /* 00000001 */
2611 xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1140 */
2613 xf_emit(ctx, 1, 0x11); /* 3f/7f DST_FORMAT */
2614 xf_emit(ctx, 1, 1); /* 00000001 DST_LINEAR */
2615 xf_emit(ctx, 1, 0); /* 00000007 PATTERN_COLOR_FORMAT */
2616 xf_emit(ctx, 2, 0); /* ffffffff PATTERN_MONO_COLOR */
2617 xf_emit(ctx, 1, 0); /* 00000001 PATTERN_MONO_FORMAT */
2618 xf_emit(ctx, 2, 0); /* ffffffff PATTERN_MONO_BITMAP */
2619 xf_emit(ctx, 1, 0); /* 00000003 PATTERN_SELECT */
2620 xf_emit(ctx, 1, 0); /* 000000ff ROP */
2621 xf_emit(ctx, 1, 0); /* ffffffff BETA1 */
2622 xf_emit(ctx, 1, 0); /* ffffffff BETA4 */
2623 xf_emit(ctx, 1, 0); /* 00000007 OPERATION */
2624 xf_emit(ctx, 0x50, 0); /* 10x ffffff, ffffff, ffffff, ffffff, 3 PATTERN */
2628 nv50_graph_construct_xfer_unk84xx(struct nouveau_grctx *ctx)
2630 struct drm_nouveau_private *dev_priv = ctx->dev->dev_private;
2632 switch (dev_priv->chipset) {
2647 xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */
2648 xf_emit(ctx, 1, 4); /* 7f/ff[NVA0+] VP_REG_ALLOC_RESULT */
2649 xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */
2650 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A30 */
2651 xf_emit(ctx, 1, 0); /* 111/113[NVA0+] */
2652 if (IS_NVA3F(dev_priv->chipset))
2653 xf_emit(ctx, 0x1f, 0); /* ffffffff */
2654 else if (dev_priv->chipset >= 0xa0)
2655 xf_emit(ctx, 0x0f, 0); /* ffffffff */
2657 xf_emit(ctx, 0x10, 0); /* fffffff VP_RESULT_MAP_1 up */
2658 xf_emit(ctx, 2, 0); /* f/1f[NVA3], fffffff/ffffffff[NVA0+] */
2659 xf_emit(ctx, 1, 4); /* 7f/ff VP_REG_ALLOC_RESULT */
2660 xf_emit(ctx, 1, 4); /* 7f/ff VP_RESULT_MAP_SIZE */
2661 if (dev_priv->chipset >= 0xa0)
2662 xf_emit(ctx, 1, 0x03020100); /* ffffffff */
2664 xf_emit(ctx, 1, 0x00608080); /* fffffff VP_RESULT_MAP_0 */
2665 xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */
2666 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A30 */
2667 xf_emit(ctx, 2, 0); /* 111/113, 7f/ff */
2668 xf_emit(ctx, 1, 4); /* 7f/ff VP_RESULT_MAP_SIZE */
2669 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A30 */
2670 xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */
2671 xf_emit(ctx, 1, 4); /* 000000ff GP_REG_ALLOC_RESULT */
2672 xf_emit(ctx, 1, 4); /* 000000ff GP_RESULT_MAP_SIZE */
2673 xf_emit(ctx, 1, 0x80); /* 0000ffff GP_VERTEX_OUTPUT_COUNT */
2675 xf_emit(ctx, 1, magic3); /* 00007fff tesla UNK141C */
2676 xf_emit(ctx, 1, 4); /* 7f/ff VP_RESULT_MAP_SIZE */
2677 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A30 */
2678 xf_emit(ctx, 1, 0); /* 111/113 */
2679 xf_emit(ctx, 0x1f, 0); /* ffffffff GP_RESULT_MAP_1 up */
2680 xf_emit(ctx, 1, 0); /* 0000001f */
2681 xf_emit(ctx, 1, 0); /* ffffffff */
2682 xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */
2683 xf_emit(ctx, 1, 4); /* 000000ff GP_REG_ALLOC_RESULT */
2684 xf_emit(ctx, 1, 0x80); /* 0000ffff GP_VERTEX_OUTPUT_COUNT */
2685 xf_emit(ctx, 1, 4); /* 000000ff GP_RESULT_MAP_SIZE */
2686 xf_emit(ctx, 1, 0x03020100); /* ffffffff GP_RESULT_MAP_0 */
2687 xf_emit(ctx, 1, 3); /* 00000003 GP_OUTPUT_PRIMITIVE_TYPE */
2689 xf_emit(ctx, 1, magic3); /* 7fff tesla UNK141C */
2690 xf_emit(ctx, 1, 4); /* 7f/ff VP_RESULT_MAP_SIZE */
2691 xf_emit(ctx, 1, 0); /* 00000001 PROVOKING_VERTEX_LAST */
2692 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A30 */
2693 xf_emit(ctx, 1, 0); /* 111/113 */
2694 xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */
2695 xf_emit(ctx, 1, 4); /* 000000ff GP_RESULT_MAP_SIZE */
2696 xf_emit(ctx, 1, 3); /* 00000003 GP_OUTPUT_PRIMITIVE_TYPE */
2697 xf_emit(ctx, 1, 0); /* 00000001 PROVOKING_VERTEX_LAST */
2698 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A30 */
2699 xf_emit(ctx, 1, 0); /* 00000003 tesla UNK13A0 */
2700 xf_emit(ctx, 1, 4); /* 7f/ff VP_REG_ALLOC_RESULT */
2701 xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */
2702 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A30 */
2703 xf_emit(ctx, 1, 0); /* 111/113 */
2704 if (dev_priv->chipset == 0x94 || dev_priv->chipset == 0x96)
2705 xf_emit(ctx, 0x1020, 0); /* 4 x (0x400 x 0xffffffff, ff, 0, 0, 0, 4 x ffffffff) */
2706 else if (dev_priv->chipset < 0xa0)
2707 xf_emit(ctx, 0xa20, 0); /* 4 x (0x280 x 0xffffffff, ff, 0, 0, 0, 4 x ffffffff) */
2708 else if (!IS_NVA3F(dev_priv->chipset))
2709 xf_emit(ctx, 0x210, 0); /* ffffffff */
2711 xf_emit(ctx, 0x410, 0); /* ffffffff */
2712 xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */
2713 xf_emit(ctx, 1, 4); /* 000000ff GP_RESULT_MAP_SIZE */
2714 xf_emit(ctx, 1, 3); /* 00000003 GP_OUTPUT_PRIMITIVE_TYPE */
2715 xf_emit(ctx, 1, 0); /* 00000001 PROVOKING_VERTEX_LAST */
2716 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A30 */
2720 nv50_graph_construct_xfer_tprop(struct nouveau_grctx *ctx)
2722 struct drm_nouveau_private *dev_priv = ctx->dev->dev_private;
2724 if (dev_priv->chipset == 0x50) {
2726 magic2 = 0x00003e60;
2727 } else if (!IS_NVA3F(dev_priv->chipset)) {
2729 magic2 = 0x001ffe67;
2732 magic2 = 0x00087e67;
2734 xf_emit(ctx, 1, 0); /* 00000007 ALPHA_TEST_FUNC */
2735 xf_emit(ctx, 1, 0); /* ffffffff ALPHA_TEST_REF */
2736 xf_emit(ctx, 1, 0); /* 00000001 ALPHA_TEST_ENABLE */
2737 if (IS_NVA3F(dev_priv->chipset))
2738 xf_emit(ctx, 1, 1); /* 0000000f UNK16A0 */
2739 xf_emit(ctx, 1, 0); /* 7/f MULTISAMPLE_SAMPLES_LOG2 */
2740 xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1534 */
2741 xf_emit(ctx, 1, 0); /* 000000ff STENCIL_BACK_MASK */
2742 xf_emit(ctx, 3, 0); /* 00000007 STENCIL_BACK_OP_FAIL, ZFAIL, ZPASS */
2743 xf_emit(ctx, 4, 0); /* ffffffff BLEND_COLOR */
2744 xf_emit(ctx, 1, 0); /* 00000001 UNK19C0 */
2745 xf_emit(ctx, 1, 0); /* 00000001 UNK0FDC */
2746 xf_emit(ctx, 1, 0xf); /* 0000000f COLOR_MASK */
2747 xf_emit(ctx, 7, 0); /* 0000000f COLOR_MASK */
2748 xf_emit(ctx, 1, 0); /* 00000001 DEPTH_TEST_ENABLE */
2749 xf_emit(ctx, 1, 0); /* 00000001 DEPTH_WRITE_ENABLE */
2750 xf_emit(ctx, 1, 0); /* 00000001 LOGIC_OP_ENABLE */
2751 xf_emit(ctx, 1, 0); /* ff[NV50]/3ff[NV84+] */
2752 xf_emit(ctx, 1, 4); /* 00000007 FP_CONTROL */
2753 xf_emit(ctx, 4, 0xffff); /* 0000ffff MSAA_MASK */
2754 xf_emit(ctx, 1, 0); /* 000000ff STENCIL_FRONT_MASK */
2755 xf_emit(ctx, 3, 0); /* 00000007 STENCIL_FRONT_OP_FAIL, ZFAIL, ZPASS */
2756 xf_emit(ctx, 1, 0); /* 00000001 STENCIL_FRONT_ENABLE */
2757 xf_emit(ctx, 1, 0); /* 00000001 STENCIL_BACK_ENABLE */
2758 xf_emit(ctx, 2, 0); /* 00007fff WINDOW_OFFSET_XY */
2759 xf_emit(ctx, 1, 1); /* 00000001 tesla UNK19CC */
2760 xf_emit(ctx, 1, 0); /* 7 */
2761 xf_emit(ctx, 1, 0); /* 00000001 SAMPLECNT_ENABLE */
2762 xf_emit(ctx, 1, 0); /* 0000000f ZETA_FORMAT */
2763 xf_emit(ctx, 1, 1); /* 00000001 ZETA_ENABLE */
2764 xf_emit(ctx, 1, 0); /* ffffffff COLOR_KEY */
2765 xf_emit(ctx, 1, 0); /* 00000001 COLOR_KEY_ENABLE */
2766 xf_emit(ctx, 1, 0); /* 00000007 COLOR_KEY_FORMAT */
2767 xf_emit(ctx, 2, 0); /* ffffffff SIFC_BITMAP_COLOR */
2768 xf_emit(ctx, 1, 1); /* 00000001 SIFC_BITMAP_WRITE_BIT0_ENABLE */
2769 xf_emit(ctx, 1, 0); /* 00000007 ALPHA_TEST_FUNC */
2770 xf_emit(ctx, 1, 0); /* 00000001 ALPHA_TEST_ENABLE */
2771 if (IS_NVA3F(dev_priv->chipset)) {
2772 xf_emit(ctx, 1, 3); /* 00000003 tesla UNK16B4 */
2773 xf_emit(ctx, 1, 0); /* 00000003 */
2774 xf_emit(ctx, 1, 0); /* 00000003 tesla UNK1298 */
2775 } else if (dev_priv->chipset >= 0xa0) {
2776 xf_emit(ctx, 1, 1); /* 00000001 tesla UNK16B4 */
2777 xf_emit(ctx, 1, 0); /* 00000003 */
2779 xf_emit(ctx, 1, 0); /* 00000003 MULTISAMPLE_CTRL */
2781 xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1534 */
2782 xf_emit(ctx, 8, 0); /* 00000001 BLEND_ENABLE */
2783 xf_emit(ctx, 1, 1); /* 0000001f BLEND_FUNC_DST_ALPHA */
2784 xf_emit(ctx, 1, 1); /* 00000007 BLEND_EQUATION_ALPHA */
2785 xf_emit(ctx, 1, 2); /* 0000001f BLEND_FUNC_SRC_ALPHA */
2786 xf_emit(ctx, 1, 1); /* 0000001f BLEND_FUNC_DST_RGB */
2787 xf_emit(ctx, 1, 1); /* 00000007 BLEND_EQUATION_RGB */
2788 xf_emit(ctx, 1, 2); /* 0000001f BLEND_FUNC_SRC_RGB */
2789 if (IS_NVA3F(dev_priv->chipset)) {
2790 xf_emit(ctx, 1, 0); /* 00000001 UNK12E4 */
2791 xf_emit(ctx, 8, 1); /* 00000007 IBLEND_EQUATION_RGB */
2792 xf_emit(ctx, 8, 1); /* 00000007 IBLEND_EQUATION_ALPHA */
2793 xf_emit(ctx, 8, 1); /* 00000001 IBLEND_UNK00 */
2794 xf_emit(ctx, 8, 2); /* 0000001f IBLEND_SRC_RGB */
2795 xf_emit(ctx, 8, 1); /* 0000001f IBLEND_DST_RGB */
2796 xf_emit(ctx, 8, 2); /* 0000001f IBLEND_SRC_ALPHA */
2797 xf_emit(ctx, 8, 1); /* 0000001f IBLEND_DST_ALPHA */
2798 xf_emit(ctx, 1, 0); /* 00000001 UNK1140 */
2800 xf_emit(ctx, 1, 1); /* 00000001 UNK133C */
2801 xf_emit(ctx, 1, 0); /* ffff0ff3 */
2802 xf_emit(ctx, 1, 0x11); /* 3f/7f RT_FORMAT */
2803 xf_emit(ctx, 7, 0); /* 3f/7f RT_FORMAT */
2804 xf_emit(ctx, 1, 0x0fac6881); /* 0fffffff RT_CONTROL */
2805 xf_emit(ctx, 1, 0); /* 00000001 LOGIC_OP_ENABLE */
2806 xf_emit(ctx, 1, 0); /* ff/3ff */
2807 xf_emit(ctx, 1, 4); /* 00000007 FP_CONTROL */
2808 xf_emit(ctx, 1, 0); /* 00000003 UNK0F90 */
2809 xf_emit(ctx, 1, 0); /* 00000001 FRAMEBUFFER_SRGB */
2810 xf_emit(ctx, 1, 0); /* 7 */
2811 xf_emit(ctx, 1, 0x11); /* 3f/7f DST_FORMAT */
2812 xf_emit(ctx, 1, 1); /* 00000001 DST_LINEAR */
2813 xf_emit(ctx, 1, 0); /* 00000007 OPERATION */
2814 xf_emit(ctx, 1, 0xcf); /* 000000ff SIFC_FORMAT */
2815 xf_emit(ctx, 1, 0xcf); /* 000000ff DRAW_COLOR_FORMAT */
2816 xf_emit(ctx, 1, 0xcf); /* 000000ff SRC_FORMAT */
2817 if (IS_NVA3F(dev_priv->chipset))
2818 xf_emit(ctx, 1, 1); /* 0000001f tesla UNK169C */
2819 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A3C */
2820 xf_emit(ctx, 1, 0); /* 7/f[NVA3] MULTISAMPLE_SAMPLES_LOG2 */
2821 xf_emit(ctx, 8, 0); /* 00000001 BLEND_ENABLE */
2822 xf_emit(ctx, 1, 1); /* 0000001f BLEND_FUNC_DST_ALPHA */
2823 xf_emit(ctx, 1, 1); /* 00000007 BLEND_EQUATION_ALPHA */
2824 xf_emit(ctx, 1, 2); /* 0000001f BLEND_FUNC_SRC_ALPHA */
2825 xf_emit(ctx, 1, 1); /* 0000001f BLEND_FUNC_DST_RGB */
2826 xf_emit(ctx, 1, 1); /* 00000007 BLEND_EQUATION_RGB */
2827 xf_emit(ctx, 1, 2); /* 0000001f BLEND_FUNC_SRC_RGB */
2828 xf_emit(ctx, 1, 1); /* 00000001 UNK133C */
2829 xf_emit(ctx, 1, 0); /* ffff0ff3 */
2830 xf_emit(ctx, 8, 1); /* 00000001 UNK19E0 */
2831 xf_emit(ctx, 1, 0x11); /* 3f/7f RT_FORMAT */
2832 xf_emit(ctx, 7, 0); /* 3f/7f RT_FORMAT */
2833 xf_emit(ctx, 1, 0x0fac6881); /* 0fffffff RT_CONTROL */
2834 xf_emit(ctx, 1, 0xf); /* 0000000f COLOR_MASK */
2835 xf_emit(ctx, 7, 0); /* 0000000f COLOR_MASK */
2836 xf_emit(ctx, 1, magic2); /* 001fffff tesla UNK0F78 */
2837 xf_emit(ctx, 1, 0); /* 00000001 DEPTH_BOUNDS_EN */
2838 xf_emit(ctx, 1, 0); /* 00000001 DEPTH_TEST_ENABLE */
2839 xf_emit(ctx, 1, 0x11); /* 3f/7f DST_FORMAT */
2840 xf_emit(ctx, 1, 1); /* 00000001 DST_LINEAR */
2841 if (IS_NVA3F(dev_priv->chipset))
2842 xf_emit(ctx, 1, 1); /* 0000001f tesla UNK169C */
2843 if (dev_priv->chipset == 0x50)
2844 xf_emit(ctx, 1, 0); /* ff */
2846 xf_emit(ctx, 3, 0); /* 1, 7, 3ff */
2847 xf_emit(ctx, 1, 4); /* 00000007 FP_CONTROL */
2848 xf_emit(ctx, 1, 0); /* 00000003 UNK0F90 */
2849 xf_emit(ctx, 1, 0); /* 00000001 STENCIL_FRONT_ENABLE */
2850 xf_emit(ctx, 1, 0); /* 00000007 */
2851 xf_emit(ctx, 1, 0); /* 00000001 SAMPLECNT_ENABLE */
2852 xf_emit(ctx, 1, 0); /* 0000000f ZETA_FORMAT */
2853 xf_emit(ctx, 1, 1); /* 00000001 ZETA_ENABLE */
2854 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A3C */
2855 xf_emit(ctx, 1, 0); /* 7/f MULTISAMPLE_SAMPLES_LOG2 */
2856 xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1534 */
2857 xf_emit(ctx, 1, 0); /* ffff0ff3 */
2858 xf_emit(ctx, 1, 0x11); /* 3f/7f RT_FORMAT */
2859 xf_emit(ctx, 7, 0); /* 3f/7f RT_FORMAT */
2860 xf_emit(ctx, 1, 0x0fac6881); /* 0fffffff RT_CONTROL */
2861 xf_emit(ctx, 1, 0); /* 00000001 DEPTH_BOUNDS_EN */
2862 xf_emit(ctx, 1, 0); /* 00000001 DEPTH_TEST_ENABLE */
2863 xf_emit(ctx, 1, 0); /* 00000001 DEPTH_WRITE_ENABLE */
2864 xf_emit(ctx, 1, 0x11); /* 3f/7f DST_FORMAT */
2865 xf_emit(ctx, 1, 1); /* 00000001 DST_LINEAR */
2866 xf_emit(ctx, 1, 0); /* 000fffff BLIT_DU_DX_FRACT */
2867 xf_emit(ctx, 1, 1); /* 0001ffff BLIT_DU_DX_INT */
2868 xf_emit(ctx, 1, 0); /* 000fffff BLIT_DV_DY_FRACT */
2869 xf_emit(ctx, 1, 1); /* 0001ffff BLIT_DV_DY_INT */
2870 xf_emit(ctx, 1, 0); /* ff/3ff */
2871 xf_emit(ctx, 1, magic1); /* 3ff/7ff tesla UNK0D68 */
2872 xf_emit(ctx, 1, 0); /* 00000001 STENCIL_FRONT_ENABLE */
2873 xf_emit(ctx, 1, 1); /* 00000001 tesla UNK15B4 */
2874 xf_emit(ctx, 1, 0); /* 0000000f ZETA_FORMAT */
2875 xf_emit(ctx, 1, 1); /* 00000001 ZETA_ENABLE */
2876 xf_emit(ctx, 1, 0); /* 00000007 */
2877 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A3C */
2878 if (IS_NVA3F(dev_priv->chipset))
2879 xf_emit(ctx, 1, 1); /* 0000001f tesla UNK169C */
2880 xf_emit(ctx, 8, 0); /* 0000ffff DMA_COLOR */
2881 xf_emit(ctx, 1, 0); /* 0000ffff DMA_GLOBAL */
2882 xf_emit(ctx, 1, 0); /* 0000ffff DMA_LOCAL */
2883 xf_emit(ctx, 1, 0); /* 0000ffff DMA_STACK */
2884 xf_emit(ctx, 1, 0); /* ff/3ff */
2885 xf_emit(ctx, 1, 0); /* 0000ffff DMA_DST */
2886 xf_emit(ctx, 1, 0); /* 7 */
2887 xf_emit(ctx, 1, 0); /* 7/f MULTISAMPLE_SAMPLES_LOG2 */
2888 xf_emit(ctx, 1, 0); /* ffff0ff3 */
2889 xf_emit(ctx, 8, 0); /* 000000ff RT_ADDRESS_HIGH */
2890 xf_emit(ctx, 8, 0); /* ffffffff RT_LAYER_STRIDE */
2891 xf_emit(ctx, 8, 0); /* ffffffff RT_ADDRESS_LOW */
2892 xf_emit(ctx, 8, 8); /* 0000007f RT_TILE_MODE */
2893 xf_emit(ctx, 1, 0x11); /* 3f/7f RT_FORMAT */
2894 xf_emit(ctx, 7, 0); /* 3f/7f RT_FORMAT */
2895 xf_emit(ctx, 1, 0x0fac6881); /* 0fffffff RT_CONTROL */
2896 xf_emit(ctx, 8, 0x400); /* 0fffffff RT_HORIZ */
2897 xf_emit(ctx, 8, 0x300); /* 0000ffff RT_VERT */
2898 xf_emit(ctx, 1, 1); /* 00001fff RT_ARRAY_MODE */
2899 xf_emit(ctx, 1, 0xf); /* 0000000f COLOR_MASK */
2900 xf_emit(ctx, 7, 0); /* 0000000f COLOR_MASK */
2901 xf_emit(ctx, 1, 0x20); /* 00000fff DST_TILE_MODE */
2902 xf_emit(ctx, 1, 0x11); /* 3f/7f DST_FORMAT */
2903 xf_emit(ctx, 1, 0x100); /* 0001ffff DST_HEIGHT */
2904 xf_emit(ctx, 1, 0); /* 000007ff DST_LAYER */
2905 xf_emit(ctx, 1, 1); /* 00000001 DST_LINEAR */
2906 xf_emit(ctx, 1, 0); /* ffffffff DST_ADDRESS_LOW */
2907 xf_emit(ctx, 1, 0); /* 000000ff DST_ADDRESS_HIGH */
2908 xf_emit(ctx, 1, 0x40); /* 0007ffff DST_PITCH */
2909 xf_emit(ctx, 1, 0x100); /* 0001ffff DST_WIDTH */
2910 xf_emit(ctx, 1, 0); /* 0000ffff */
2911 xf_emit(ctx, 1, 3); /* 00000003 tesla UNK15AC */
2912 xf_emit(ctx, 1, 0); /* ff/3ff */
2913 xf_emit(ctx, 1, 0); /* 0001ffff GP_BUILTIN_RESULT_EN */
2914 xf_emit(ctx, 1, 0); /* 00000003 UNK0F90 */
2915 xf_emit(ctx, 1, 0); /* 00000007 */
2916 if (IS_NVA3F(dev_priv->chipset))
2917 xf_emit(ctx, 1, 1); /* 0000001f tesla UNK169C */
2918 xf_emit(ctx, 1, magic2); /* 001fffff tesla UNK0F78 */
2919 xf_emit(ctx, 1, 0); /* 7/f MULTISAMPLE_SAMPLES_LOG2 */
2920 xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1534 */
2921 xf_emit(ctx, 1, 0); /* ffff0ff3 */
2922 xf_emit(ctx, 1, 2); /* 00000003 tesla UNK143C */
2923 xf_emit(ctx, 1, 0x0fac6881); /* 0fffffff RT_CONTROL */
2924 xf_emit(ctx, 1, 0); /* 0000ffff DMA_ZETA */
2925 xf_emit(ctx, 1, 0); /* 00000001 DEPTH_BOUNDS_EN */
2926 xf_emit(ctx, 1, 0); /* 00000001 DEPTH_TEST_ENABLE */
2927 xf_emit(ctx, 1, 0); /* 00000001 DEPTH_WRITE_ENABLE */
2928 xf_emit(ctx, 2, 0); /* ffff, ff/3ff */
2929 xf_emit(ctx, 1, 0); /* 0001ffff GP_BUILTIN_RESULT_EN */
2930 xf_emit(ctx, 1, 0); /* 00000001 STENCIL_FRONT_ENABLE */
2931 xf_emit(ctx, 1, 0); /* 000000ff STENCIL_FRONT_MASK */
2932 xf_emit(ctx, 1, 1); /* 00000001 tesla UNK15B4 */
2933 xf_emit(ctx, 1, 0); /* 00000007 */
2934 xf_emit(ctx, 1, 0); /* ffffffff ZETA_LAYER_STRIDE */
2935 xf_emit(ctx, 1, 0); /* 000000ff ZETA_ADDRESS_HIGH */
2936 xf_emit(ctx, 1, 0); /* ffffffff ZETA_ADDRESS_LOW */
2937 xf_emit(ctx, 1, 4); /* 00000007 ZETA_TILE_MODE */
2938 xf_emit(ctx, 1, 0); /* 0000000f ZETA_FORMAT */
2939 xf_emit(ctx, 1, 1); /* 00000001 ZETA_ENABLE */
2940 xf_emit(ctx, 1, 0x400); /* 0fffffff ZETA_HORIZ */
2941 xf_emit(ctx, 1, 0x300); /* 0000ffff ZETA_VERT */
2942 xf_emit(ctx, 1, 0x1001); /* 00001fff ZETA_ARRAY_MODE */
2943 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A3C */
2944 xf_emit(ctx, 1, 0); /* 7/f MULTISAMPLE_SAMPLES_LOG2 */
2945 if (IS_NVA3F(dev_priv->chipset))
2946 xf_emit(ctx, 1, 0); /* 00000001 */
2947 xf_emit(ctx, 1, 0); /* ffff0ff3 */
2948 xf_emit(ctx, 1, 0x11); /* 3f/7f RT_FORMAT */
2949 xf_emit(ctx, 7, 0); /* 3f/7f RT_FORMAT */
2950 xf_emit(ctx, 1, 0x0fac6881); /* 0fffffff RT_CONTROL */
2951 xf_emit(ctx, 1, 0xf); /* 0000000f COLOR_MASK */
2952 xf_emit(ctx, 7, 0); /* 0000000f COLOR_MASK */
2953 xf_emit(ctx, 1, 0); /* ff/3ff */
2954 xf_emit(ctx, 8, 0); /* 00000001 BLEND_ENABLE */
2955 xf_emit(ctx, 1, 0); /* 00000003 UNK0F90 */
2956 xf_emit(ctx, 1, 0); /* 00000001 FRAMEBUFFER_SRGB */
2957 xf_emit(ctx, 1, 0); /* 7 */
2958 xf_emit(ctx, 1, 0); /* 00000001 LOGIC_OP_ENABLE */
2959 if (IS_NVA3F(dev_priv->chipset)) {
2960 xf_emit(ctx, 1, 0); /* 00000001 UNK1140 */
2961 xf_emit(ctx, 1, 1); /* 0000001f tesla UNK169C */
2963 xf_emit(ctx, 1, 0); /* 7/f MULTISAMPLE_SAMPLES_LOG2 */
2964 xf_emit(ctx, 1, 0); /* 00000001 UNK1534 */
2965 xf_emit(ctx, 1, 0); /* ffff0ff3 */
2966 if (dev_priv->chipset >= 0xa0)
2967 xf_emit(ctx, 1, 0x0fac6881); /* fffffff */
2968 xf_emit(ctx, 1, magic2); /* 001fffff tesla UNK0F78 */
2969 xf_emit(ctx, 1, 0); /* 00000001 DEPTH_BOUNDS_EN */
2970 xf_emit(ctx, 1, 0); /* 00000001 DEPTH_TEST_ENABLE */
2971 xf_emit(ctx, 1, 0); /* 00000001 DEPTH_WRITE_ENABLE */
2972 xf_emit(ctx, 1, 0x11); /* 3f/7f DST_FORMAT */
2973 xf_emit(ctx, 1, 0); /* 00000001 tesla UNK0FB0 */
2974 xf_emit(ctx, 1, 0); /* ff/3ff */
2975 xf_emit(ctx, 1, 4); /* 00000007 FP_CONTROL */
2976 xf_emit(ctx, 1, 0); /* 00000001 STENCIL_FRONT_ENABLE */
2977 xf_emit(ctx, 1, 1); /* 00000001 tesla UNK15B4 */
2978 xf_emit(ctx, 1, 1); /* 00000001 tesla UNK19CC */
2979 xf_emit(ctx, 1, 0); /* 00000007 */
2980 xf_emit(ctx, 1, 0); /* 00000001 SAMPLECNT_ENABLE */
2981 xf_emit(ctx, 1, 0); /* 0000000f ZETA_FORMAT */
2982 xf_emit(ctx, 1, 1); /* 00000001 ZETA_ENABLE */
2983 if (IS_NVA3F(dev_priv->chipset)) {
2984 xf_emit(ctx, 1, 1); /* 0000001f tesla UNK169C */
2985 xf_emit(ctx, 1, 0); /* 0000000f tesla UNK15C8 */
2987 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A3C */
2988 if (dev_priv->chipset >= 0xa0) {
2989 xf_emit(ctx, 3, 0); /* 7/f, 1, ffff0ff3 */
2990 xf_emit(ctx, 1, 0xfac6881); /* fffffff */
2991 xf_emit(ctx, 4, 0); /* 1, 1, 1, 3ff */
2992 xf_emit(ctx, 1, 4); /* 7 */
2993 xf_emit(ctx, 1, 0); /* 1 */
2994 xf_emit(ctx, 2, 1); /* 1 */
2995 xf_emit(ctx, 2, 0); /* 7, f */
2996 xf_emit(ctx, 1, 1); /* 1 */
2997 xf_emit(ctx, 1, 0); /* 7/f */
2998 if (IS_NVA3F(dev_priv->chipset))
2999 xf_emit(ctx, 0x9, 0); /* 1 */
3001 xf_emit(ctx, 0x8, 0); /* 1 */
3002 xf_emit(ctx, 1, 0); /* ffff0ff3 */
3003 xf_emit(ctx, 8, 1); /* 1 */
3004 xf_emit(ctx, 1, 0x11); /* 7f */
3005 xf_emit(ctx, 7, 0); /* 7f */
3006 xf_emit(ctx, 1, 0xfac6881); /* fffffff */
3007 xf_emit(ctx, 1, 0xf); /* f */
3008 xf_emit(ctx, 7, 0); /* f */
3009 xf_emit(ctx, 1, 0x11); /* 7f */
3010 xf_emit(ctx, 1, 1); /* 1 */
3011 xf_emit(ctx, 5, 0); /* 1, 7, 3ff, 3, 7 */
3012 if (IS_NVA3F(dev_priv->chipset)) {
3013 xf_emit(ctx, 1, 0); /* 00000001 UNK1140 */
3014 xf_emit(ctx, 1, 1); /* 0000001f tesla UNK169C */
3020 nv50_graph_construct_xfer_tex(struct nouveau_grctx *ctx)
3022 struct drm_nouveau_private *dev_priv = ctx->dev->dev_private;
3023 xf_emit(ctx, 2, 0); /* 1 LINKED_TSC. yes, 2. */
3024 if (dev_priv->chipset != 0x50)
3025 xf_emit(ctx, 1, 0); /* 3 */
3026 xf_emit(ctx, 1, 1); /* 1ffff BLIT_DU_DX_INT */
3027 xf_emit(ctx, 1, 0); /* fffff BLIT_DU_DX_FRACT */
3028 xf_emit(ctx, 1, 1); /* 1ffff BLIT_DV_DY_INT */
3029 xf_emit(ctx, 1, 0); /* fffff BLIT_DV_DY_FRACT */
3030 if (dev_priv->chipset == 0x50)
3031 xf_emit(ctx, 1, 0); /* 3 BLIT_CONTROL */
3033 xf_emit(ctx, 2, 0); /* 3ff, 1 */
3034 xf_emit(ctx, 1, 0x2a712488); /* ffffffff SRC_TIC_0 */
3035 xf_emit(ctx, 1, 0); /* ffffffff SRC_TIC_1 */
3036 xf_emit(ctx, 1, 0x4085c000); /* ffffffff SRC_TIC_2 */
3037 xf_emit(ctx, 1, 0x40); /* ffffffff SRC_TIC_3 */
3038 xf_emit(ctx, 1, 0x100); /* ffffffff SRC_TIC_4 */
3039 xf_emit(ctx, 1, 0x10100); /* ffffffff SRC_TIC_5 */
3040 xf_emit(ctx, 1, 0x02800000); /* ffffffff SRC_TIC_6 */
3041 xf_emit(ctx, 1, 0); /* ffffffff SRC_TIC_7 */
3042 if (dev_priv->chipset == 0x50) {
3043 xf_emit(ctx, 1, 0); /* 00000001 turing UNK358 */
3044 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A34? */
3045 xf_emit(ctx, 1, 0); /* 00000003 turing UNK37C tesla UNK1690 */
3046 xf_emit(ctx, 1, 0); /* 00000003 BLIT_CONTROL */
3047 xf_emit(ctx, 1, 0); /* 00000001 turing UNK32C tesla UNK0F94 */
3048 } else if (!IS_NVAAF(dev_priv->chipset)) {
3049 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A34? */
3050 xf_emit(ctx, 1, 0); /* 00000003 */
3051 xf_emit(ctx, 1, 0); /* 000003ff */
3052 xf_emit(ctx, 1, 0); /* 00000003 */
3053 xf_emit(ctx, 1, 0); /* 000003ff */
3054 xf_emit(ctx, 1, 0); /* 00000003 tesla UNK1664 / turing UNK03E8 */
3055 xf_emit(ctx, 1, 0); /* 00000003 */
3056 xf_emit(ctx, 1, 0); /* 000003ff */
3058 xf_emit(ctx, 0x6, 0);
3060 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A34 */
3061 xf_emit(ctx, 1, 0); /* 0000ffff DMA_TEXTURE */
3062 xf_emit(ctx, 1, 0); /* 0000ffff DMA_SRC */
3066 nv50_graph_construct_xfer_unk8cxx(struct nouveau_grctx *ctx)
3068 struct drm_nouveau_private *dev_priv = ctx->dev->dev_private;
3069 xf_emit(ctx, 1, 0); /* 00000001 UNK1534 */
3070 xf_emit(ctx, 1, 0); /* 7/f MULTISAMPLE_SAMPLES_LOG2 */
3071 xf_emit(ctx, 2, 0); /* 7, ffff0ff3 */
3072 xf_emit(ctx, 1, 0); /* 00000001 DEPTH_TEST_ENABLE */
3073 xf_emit(ctx, 1, 0); /* 00000001 DEPTH_WRITE */
3074 xf_emit(ctx, 1, 0x04e3bfdf); /* ffffffff UNK0D64 */
3075 xf_emit(ctx, 1, 0x04e3bfdf); /* ffffffff UNK0DF4 */
3076 xf_emit(ctx, 1, 1); /* 00000001 UNK15B4 */
3077 xf_emit(ctx, 1, 0); /* 00000001 LINE_STIPPLE_ENABLE */
3078 xf_emit(ctx, 1, 0x00ffff00); /* 00ffffff LINE_STIPPLE_PATTERN */
3079 xf_emit(ctx, 1, 1); /* 00000001 tesla UNK0F98 */
3080 if (IS_NVA3F(dev_priv->chipset))
3081 xf_emit(ctx, 1, 1); /* 0000001f tesla UNK169C */
3082 xf_emit(ctx, 1, 0); /* 00000003 tesla UNK1668 */
3083 xf_emit(ctx, 1, 0); /* 00000001 LINE_STIPPLE_ENABLE */
3084 xf_emit(ctx, 1, 0x00ffff00); /* 00ffffff LINE_STIPPLE_PATTERN */
3085 xf_emit(ctx, 1, 0); /* 00000001 POLYGON_SMOOTH_ENABLE */
3086 xf_emit(ctx, 1, 0); /* 00000001 UNK1534 */
3087 xf_emit(ctx, 1, 0); /* 7/f MULTISAMPLE_SAMPLES_LOG2 */
3088 xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1658 */
3089 xf_emit(ctx, 1, 0); /* 00000001 LINE_SMOOTH_ENABLE */
3090 xf_emit(ctx, 1, 0); /* ffff0ff3 */
3091 xf_emit(ctx, 1, 0); /* 00000001 DEPTH_TEST_ENABLE */
3092 xf_emit(ctx, 1, 0); /* 00000001 DEPTH_WRITE */
3093 xf_emit(ctx, 1, 1); /* 00000001 UNK15B4 */
3094 xf_emit(ctx, 1, 0); /* 00000001 POINT_SPRITE_ENABLE */
3095 xf_emit(ctx, 1, 1); /* 00000001 tesla UNK165C */
3096 xf_emit(ctx, 1, 0x30201000); /* ffffffff tesla UNK1670 */
3097 xf_emit(ctx, 1, 0x70605040); /* ffffffff tesla UNK1670 */
3098 xf_emit(ctx, 1, 0xb8a89888); /* ffffffff tesla UNK1670 */
3099 xf_emit(ctx, 1, 0xf8e8d8c8); /* ffffffff tesla UNK1670 */
3100 xf_emit(ctx, 1, 0); /* 00000001 VERTEX_TWO_SIDE_ENABLE */
3101 xf_emit(ctx, 1, 0x1a); /* 0000001f POLYGON_MODE */
3105 nv50_graph_construct_xfer_tp(struct nouveau_grctx *ctx)
3107 struct drm_nouveau_private *dev_priv = ctx->dev->dev_private;
3108 if (dev_priv->chipset < 0xa0) {
3109 nv50_graph_construct_xfer_unk84xx(ctx);
3110 nv50_graph_construct_xfer_tprop(ctx);
3111 nv50_graph_construct_xfer_tex(ctx);
3112 nv50_graph_construct_xfer_unk8cxx(ctx);
3114 nv50_graph_construct_xfer_tex(ctx);
3115 nv50_graph_construct_xfer_tprop(ctx);
3116 nv50_graph_construct_xfer_unk8cxx(ctx);
3117 nv50_graph_construct_xfer_unk84xx(ctx);
3122 nv50_graph_construct_xfer_mpc(struct nouveau_grctx *ctx)
3124 struct drm_nouveau_private *dev_priv = ctx->dev->dev_private;
3126 switch (dev_priv->chipset) {
3148 for (i = 0; i < mpcnt; i++) {
3149 xf_emit(ctx, 1, 0); /* ff */
3150 xf_emit(ctx, 1, 0x80); /* ffffffff tesla UNK1404 */
3151 xf_emit(ctx, 1, 0x80007004); /* ffffffff tesla UNK12B0 */
3152 xf_emit(ctx, 1, 0x04000400); /* ffffffff */
3153 if (dev_priv->chipset >= 0xa0)
3154 xf_emit(ctx, 1, 0xc0); /* 00007fff tesla UNK152C */
3155 xf_emit(ctx, 1, 0x1000); /* 0000ffff tesla UNK0D60 */
3156 xf_emit(ctx, 1, 0); /* ff/3ff */
3157 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A30 */
3158 if (dev_priv->chipset == 0x86 || dev_priv->chipset == 0x98 || dev_priv->chipset == 0xa8 || IS_NVAAF(dev_priv->chipset)) {
3159 xf_emit(ctx, 1, 0xe00); /* 7fff */
3160 xf_emit(ctx, 1, 0x1e00); /* 7fff */
3162 xf_emit(ctx, 1, 1); /* 000000ff VP_REG_ALLOC_TEMP */
3163 xf_emit(ctx, 1, 0); /* 00000001 LINKED_TSC */
3164 xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */
3165 if (dev_priv->chipset == 0x50)
3166 xf_emit(ctx, 2, 0x1000); /* 7fff tesla UNK141C */
3167 xf_emit(ctx, 1, 1); /* 000000ff GP_REG_ALLOC_TEMP */
3168 xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */
3169 xf_emit(ctx, 1, 4); /* 000000ff FP_REG_ALLOC_TEMP */
3170 xf_emit(ctx, 1, 2); /* 00000003 REG_MODE */
3171 if (IS_NVAAF(dev_priv->chipset))
3172 xf_emit(ctx, 0xb, 0); /* RO */
3173 else if (dev_priv->chipset >= 0xa0)
3174 xf_emit(ctx, 0xc, 0); /* RO */
3176 xf_emit(ctx, 0xa, 0); /* RO */
3178 xf_emit(ctx, 1, 0x08100c12); /* 1fffffff FP_INTERPOLANT_CTRL */
3179 xf_emit(ctx, 1, 0); /* ff/3ff */
3180 if (dev_priv->chipset >= 0xa0) {
3181 xf_emit(ctx, 1, 0x1fe21); /* 0003ffff tesla UNK0FAC */
3183 xf_emit(ctx, 3, 0); /* 7fff, 0, 0 */
3184 xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1534 */
3185 xf_emit(ctx, 1, 0); /* 7/f MULTISAMPLE_SAMPLES_LOG2 */
3186 xf_emit(ctx, 4, 0xffff); /* 0000ffff MSAA_MASK */
3187 xf_emit(ctx, 1, 1); /* 00000001 LANES32 */
3188 xf_emit(ctx, 1, 0x10001); /* 00ffffff BLOCK_ALLOC */
3189 xf_emit(ctx, 1, 0x10001); /* ffffffff BLOCKDIM_XY */
3190 xf_emit(ctx, 1, 1); /* 0000ffff BLOCKDIM_Z */
3191 xf_emit(ctx, 1, 0); /* ffffffff SHARED_SIZE */
3192 xf_emit(ctx, 1, 0x1fe21); /* 1ffff/3ffff[NVA0+] tesla UNk0FAC */
3193 xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A34 */
3194 if (IS_NVA3F(dev_priv->chipset))
3195 xf_emit(ctx, 1, 1); /* 0000001f tesla UNK169C */
3196 xf_emit(ctx, 1, 0); /* ff/3ff */
3197 xf_emit(ctx, 1, 0); /* 1 LINKED_TSC */
3198 xf_emit(ctx, 1, 0); /* ff FP_ADDRESS_HIGH */
3199 xf_emit(ctx, 1, 0); /* ffffffff FP_ADDRESS_LOW */
3200 xf_emit(ctx, 1, 0x08100c12); /* 1fffffff FP_INTERPOLANT_CTRL */
3201 xf_emit(ctx, 1, 4); /* 00000007 FP_CONTROL */
3202 xf_emit(ctx, 1, 0); /* 000000ff FRAG_COLOR_CLAMP_EN */
3203 xf_emit(ctx, 1, 2); /* 00000003 REG_MODE */
3204 xf_emit(ctx, 1, 0x11); /* 0000007f RT_FORMAT */
3205 xf_emit(ctx, 7, 0); /* 0000007f RT_FORMAT */
3206 xf_emit(ctx, 1, 0); /* 00000007 */
3207 xf_emit(ctx, 1, 0xfac6881); /* 0fffffff RT_CONTROL */
3208 xf_emit(ctx, 1, 0); /* 00000003 MULTISAMPLE_CTRL */
3209 if (IS_NVA3F(dev_priv->chipset))
3210 xf_emit(ctx, 1, 3); /* 00000003 tesla UNK16B4 */
3211 xf_emit(ctx, 1, 0); /* 00000001 ALPHA_TEST_ENABLE */
3212 xf_emit(ctx, 1, 0); /* 00000007 ALPHA_TEST_FUNC */
3213 xf_emit(ctx, 1, 0); /* 00000001 FRAMEBUFFER_SRGB */
3214 xf_emit(ctx, 1, 4); /* ffffffff tesla UNK1400 */
3215 xf_emit(ctx, 8, 0); /* 00000001 BLEND_ENABLE */
3216 xf_emit(ctx, 1, 0); /* 00000001 LOGIC_OP_ENABLE */
3217 xf_emit(ctx, 1, 2); /* 0000001f BLEND_FUNC_SRC_RGB */
3218 xf_emit(ctx, 1, 1); /* 0000001f BLEND_FUNC_DST_RGB */
3219 xf_emit(ctx, 1, 1); /* 00000007 BLEND_EQUATION_RGB */
3220 xf_emit(ctx, 1, 2); /* 0000001f BLEND_FUNC_SRC_ALPHA */
3221 xf_emit(ctx, 1, 1); /* 0000001f BLEND_FUNC_DST_ALPHA */
3222 xf_emit(ctx, 1, 1); /* 00000007 BLEND_EQUATION_ALPHA */
3223 xf_emit(ctx, 1, 1); /* 00000001 UNK133C */
3224 if (IS_NVA3F(dev_priv->chipset)) {
3225 xf_emit(ctx, 1, 0); /* 00000001 UNK12E4 */
3226 xf_emit(ctx, 8, 2); /* 0000001f IBLEND_FUNC_SRC_RGB */
3227 xf_emit(ctx, 8, 1); /* 0000001f IBLEND_FUNC_DST_RGB */
3228 xf_emit(ctx, 8, 1); /* 00000007 IBLEND_EQUATION_RGB */
3229 xf_emit(ctx, 8, 2); /* 0000001f IBLEND_FUNC_SRC_ALPHA */
3230 xf_emit(ctx, 8, 1); /* 0000001f IBLEND_FUNC_DST_ALPHA */
3231 xf_emit(ctx, 8, 1); /* 00000007 IBLEND_EQUATION_ALPHA */
3232 xf_emit(ctx, 8, 1); /* 00000001 IBLEND_UNK00 */
3233 xf_emit(ctx, 1, 0); /* 00000003 tesla UNK1928 */
3234 xf_emit(ctx, 1, 0); /* 00000001 UNK1140 */
3236 xf_emit(ctx, 1, 0); /* 00000003 tesla UNK0F90 */
3237 xf_emit(ctx, 1, 4); /* 000000ff FP_RESULT_COUNT */
3238 /* XXX: demagic this part some day */
3239 if (dev_priv->chipset == 0x50)
3240 xf_emit(ctx, 0x3a0, 0);
3241 else if (dev_priv->chipset < 0x94)
3242 xf_emit(ctx, 0x3a2, 0);
3243 else if (dev_priv->chipset == 0x98 || dev_priv->chipset == 0xaa)
3244 xf_emit(ctx, 0x39f, 0);
3246 xf_emit(ctx, 0x3a3, 0);
3247 xf_emit(ctx, 1, 0x11); /* 3f/7f DST_FORMAT */
3248 xf_emit(ctx, 1, 0); /* 7 OPERATION */
3249 xf_emit(ctx, 1, 1); /* 1 DST_LINEAR */
3250 xf_emit(ctx, 0x2d, 0);
3254 nv50_graph_construct_xfer2(struct nouveau_grctx *ctx)
3256 struct drm_nouveau_private *dev_priv = ctx->dev->dev_private;
3259 uint32_t units = nv_rd32 (ctx->dev, 0x1540);
3262 offset = (ctx->ctxvals_pos+0x3f)&~0x3f;
3264 if (dev_priv->chipset < 0xa0) {
3265 for (i = 0; i < 8; i++) {
3266 ctx->ctxvals_pos = offset + i;
3267 /* that little bugger belongs to csched. No idea
3268 * what it's doing here. */
3270 xf_emit(ctx, 1, 0x08100c12); /* FP_INTERPOLANT_CTRL */
3271 if (units & (1 << i))
3272 nv50_graph_construct_xfer_mpc(ctx);
3273 if ((ctx->ctxvals_pos-offset)/8 > size)
3274 size = (ctx->ctxvals_pos-offset)/8;
3277 /* Strand 0: TPs 0, 1 */
3278 ctx->ctxvals_pos = offset;
3279 /* that little bugger belongs to csched. No idea
3280 * what it's doing here. */
3281 xf_emit(ctx, 1, 0x08100c12); /* FP_INTERPOLANT_CTRL */
3282 if (units & (1 << 0))
3283 nv50_graph_construct_xfer_mpc(ctx);
3284 if (units & (1 << 1))
3285 nv50_graph_construct_xfer_mpc(ctx);
3286 if ((ctx->ctxvals_pos-offset)/8 > size)
3287 size = (ctx->ctxvals_pos-offset)/8;
3289 /* Strand 1: TPs 2, 3 */
3290 ctx->ctxvals_pos = offset + 1;
3291 if (units & (1 << 2))
3292 nv50_graph_construct_xfer_mpc(ctx);
3293 if (units & (1 << 3))
3294 nv50_graph_construct_xfer_mpc(ctx);
3295 if ((ctx->ctxvals_pos-offset)/8 > size)
3296 size = (ctx->ctxvals_pos-offset)/8;
3298 /* Strand 2: TPs 4, 5, 6 */
3299 ctx->ctxvals_pos = offset + 2;
3300 if (units & (1 << 4))
3301 nv50_graph_construct_xfer_mpc(ctx);
3302 if (units & (1 << 5))
3303 nv50_graph_construct_xfer_mpc(ctx);
3304 if (units & (1 << 6))
3305 nv50_graph_construct_xfer_mpc(ctx);
3306 if ((ctx->ctxvals_pos-offset)/8 > size)
3307 size = (ctx->ctxvals_pos-offset)/8;
3309 /* Strand 3: TPs 7, 8, 9 */
3310 ctx->ctxvals_pos = offset + 3;
3311 if (units & (1 << 7))
3312 nv50_graph_construct_xfer_mpc(ctx);
3313 if (units & (1 << 8))
3314 nv50_graph_construct_xfer_mpc(ctx);
3315 if (units & (1 << 9))
3316 nv50_graph_construct_xfer_mpc(ctx);
3317 if ((ctx->ctxvals_pos-offset)/8 > size)
3318 size = (ctx->ctxvals_pos-offset)/8;
3320 ctx->ctxvals_pos = offset + size * 8;
3321 ctx->ctxvals_pos = (ctx->ctxvals_pos+0x3f)&~0x3f;
3322 cp_lsr (ctx, offset);
3323 cp_out (ctx, CP_SET_XFER_POINTER);
3325 cp_out (ctx, CP_SEEK_2);
3326 cp_out (ctx, CP_XFER_2);
3327 cp_wait(ctx, XFER, BUSY);