2 * Copyright (C) 2007 Ben Skeggs.
6 * Permission is hereby granted, free of charge, to any person obtaining
7 * a copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sublicense, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial
16 * portions of the Software.
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
30 #include "nouveau_drv.h"
32 struct nv50_instmem_priv {
33 uint32_t save1700[5]; /* 0x1700->0x1710 */
35 struct nouveau_gpuobj_ref *pramin_pt;
36 struct nouveau_gpuobj_ref *pramin_bar;
37 struct nouveau_gpuobj_ref *fb_bar;
42 #define NV50_INSTMEM_PAGE_SHIFT 12
43 #define NV50_INSTMEM_PAGE_SIZE (1 << NV50_INSTMEM_PAGE_SHIFT)
44 #define NV50_INSTMEM_PT_SIZE(a) (((a) >> 12) << 3)
46 /*NOTE: - Assumes 0x1700 already covers the correct MiB of PRAMIN
48 #define BAR0_WI32(g, o, v) do { \
50 if ((g)->im_backing) { \
51 offset = (g)->im_backing_start; \
53 offset = chan->ramin->gpuobj->im_backing_start; \
54 offset += (g)->im_pramin->start; \
57 nv_wr32(dev, NV_RAMIN + (offset & 0xfffff), (v)); \
61 nv50_instmem_init(struct drm_device *dev)
63 struct drm_nouveau_private *dev_priv = dev->dev_private;
64 struct nouveau_channel *chan;
65 uint32_t c_offset, c_size, c_ramfc, c_vmpd, c_base, pt_size;
66 struct nv50_instmem_priv *priv;
68 uint32_t v, save_nv001700;
70 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
73 dev_priv->engine.instmem.priv = priv;
75 /* Save state, will restore at takedown. */
76 for (i = 0x1700; i <= 0x1710; i += 4)
77 priv->save1700[(i-0x1700)/4] = nv_rd32(dev, i);
79 /* Reserve the last MiB of VRAM, we should probably try to avoid
80 * setting up the below tables over the top of the VBIOS image at
83 dev_priv->ramin_rsvd_vram = 1 << 20;
84 c_offset = nouveau_mem_fb_amount(dev) - dev_priv->ramin_rsvd_vram;
86 c_vmpd = ((dev_priv->chipset & 0xf0) == 0x50) ? 0x1400 : 0x200;
87 c_ramfc = ((dev_priv->chipset & 0xf0) == 0x50) ? 0x0 : 0x20;
88 c_base = c_vmpd + 0x4000;
89 pt_size = NV50_INSTMEM_PT_SIZE(dev_priv->ramin_size);
91 NV_DEBUG(dev, " Rsvd VRAM base: 0x%08x\n", c_offset);
92 NV_DEBUG(dev, " VBIOS image: 0x%08x\n",
93 (nv_rd32(dev, 0x619f04) & ~0xff) << 8);
94 NV_DEBUG(dev, " Aperture size: %d MiB\n", dev_priv->ramin_size >> 20);
95 NV_DEBUG(dev, " PT size: %d KiB\n", pt_size >> 10);
97 /* Determine VM layout, we need to do this first to make sure
98 * we allocate enough memory for all the page tables.
100 dev_priv->vm_gart_base = roundup(NV50_VM_BLOCK, NV50_VM_BLOCK);
101 dev_priv->vm_gart_size = NV50_VM_BLOCK;
103 dev_priv->vm_vram_base = dev_priv->vm_gart_base + dev_priv->vm_gart_size;
104 dev_priv->vm_vram_size = nouveau_mem_fb_amount(dev);
105 if (dev_priv->vm_vram_size > NV50_VM_MAX_VRAM)
106 dev_priv->vm_vram_size = NV50_VM_MAX_VRAM;
107 dev_priv->vm_vram_size = roundup(dev_priv->vm_vram_size, NV50_VM_BLOCK);
108 dev_priv->vm_vram_pt_nr = dev_priv->vm_vram_size / NV50_VM_BLOCK;
110 dev_priv->vm_end = dev_priv->vm_vram_base + dev_priv->vm_vram_size;
112 NV_DEBUG(dev, "NV50VM: GART 0x%016llx-0x%016llx\n",
113 dev_priv->vm_gart_base,
114 dev_priv->vm_gart_base + dev_priv->vm_gart_size - 1);
115 NV_DEBUG(dev, "NV50VM: VRAM 0x%016llx-0x%016llx\n",
116 dev_priv->vm_vram_base,
117 dev_priv->vm_vram_base + dev_priv->vm_vram_size - 1);
119 c_size += dev_priv->vm_vram_pt_nr * (NV50_VM_BLOCK / 65536 * 8);
121 /* Map BAR0 PRAMIN aperture over the memory we want to use */
122 save_nv001700 = nv_rd32(dev, NV50_PUNK_BAR0_PRAMIN);
123 nv_wr32(dev, NV50_PUNK_BAR0_PRAMIN, (c_offset >> 16));
125 /* Create a fake channel, and use it as our "dummy" channels 0/127.
126 * The main reason for creating a channel is so we can use the gpuobj
127 * code. However, it's probably worth noting that NVIDIA also setup
128 * their channels 0/127 with the same values they configure here.
129 * So, there may be some other reason for doing this.
131 * Have to create the entire channel manually, as the real channel
132 * creation code assumes we have PRAMIN access, and we don't until
135 chan = kzalloc(sizeof(*chan), GFP_KERNEL);
140 chan->file_priv = (struct drm_file *)-2;
141 dev_priv->fifos[0] = dev_priv->fifos[127] = chan;
143 /* Channel's PRAMIN object + heap */
144 ret = nouveau_gpuobj_new_fake(dev, 0, c_offset, c_size, 0,
149 if (nouveau_mem_init_heap(&chan->ramin_heap, c_base, c_size - c_base))
152 /* RAMFC + zero channel's PRAMIN up to start of VM pagedir */
153 ret = nouveau_gpuobj_new_fake(dev, c_ramfc, c_offset + c_ramfc,
154 0x4000, 0, NULL, &chan->ramfc);
158 for (i = 0; i < c_vmpd; i += 4)
159 BAR0_WI32(chan->ramin->gpuobj, i, 0);
161 /* VM page directory */
162 ret = nouveau_gpuobj_new_fake(dev, c_vmpd, c_offset + c_vmpd,
163 0x4000, 0, &chan->vm_pd, NULL);
166 for (i = 0; i < 0x4000; i += 8) {
167 BAR0_WI32(chan->vm_pd, i + 0x00, 0x00000000);
168 BAR0_WI32(chan->vm_pd, i + 0x04, 0x00000000);
171 /* PRAMIN page table, cheat and map into VM at 0x0000000000.
172 * We map the entire fake channel into the start of the PRAMIN BAR
174 ret = nouveau_gpuobj_new_ref(dev, chan, NULL, 0, pt_size, 0x1000,
175 0, &priv->pramin_pt);
179 for (i = 0, v = c_offset; i < pt_size; i += 8, v += 0x1000) {
180 if (v < (c_offset + c_size))
181 BAR0_WI32(priv->pramin_pt->gpuobj, i + 0, v | 1);
183 BAR0_WI32(priv->pramin_pt->gpuobj, i + 0, 0x00000009);
184 BAR0_WI32(priv->pramin_pt->gpuobj, i + 4, 0x00000000);
187 BAR0_WI32(chan->vm_pd, 0x00, priv->pramin_pt->instance | 0x63);
188 BAR0_WI32(chan->vm_pd, 0x04, 0x00000000);
190 /* VRAM page table(s), mapped into VM at +1GiB */
191 for (i = 0; i < dev_priv->vm_vram_pt_nr; i++) {
192 ret = nouveau_gpuobj_new_ref(dev, chan, NULL, 0,
193 NV50_VM_BLOCK/65536*8, 0, 0,
194 &chan->vm_vram_pt[i]);
196 NV_ERROR(dev, "Error creating VRAM page tables: %d\n",
198 dev_priv->vm_vram_pt_nr = i;
201 dev_priv->vm_vram_pt[i] = chan->vm_vram_pt[i]->gpuobj;
203 for (v = 0; v < dev_priv->vm_vram_pt[i]->im_pramin->size;
205 BAR0_WI32(dev_priv->vm_vram_pt[i], v, 0);
207 BAR0_WI32(chan->vm_pd, 0x10 + (i*8),
208 chan->vm_vram_pt[i]->instance | 0x61);
209 BAR0_WI32(chan->vm_pd, 0x14 + (i*8), 0);
212 /* DMA object for PRAMIN BAR */
213 ret = nouveau_gpuobj_new_ref(dev, chan, chan, 0, 6*4, 16, 0,
217 BAR0_WI32(priv->pramin_bar->gpuobj, 0x00, 0x7fc00000);
218 BAR0_WI32(priv->pramin_bar->gpuobj, 0x04, dev_priv->ramin_size - 1);
219 BAR0_WI32(priv->pramin_bar->gpuobj, 0x08, 0x00000000);
220 BAR0_WI32(priv->pramin_bar->gpuobj, 0x0c, 0x00000000);
221 BAR0_WI32(priv->pramin_bar->gpuobj, 0x10, 0x00000000);
222 BAR0_WI32(priv->pramin_bar->gpuobj, 0x14, 0x00000000);
224 /* DMA object for FB BAR */
225 ret = nouveau_gpuobj_new_ref(dev, chan, chan, 0, 6*4, 16, 0,
229 BAR0_WI32(priv->fb_bar->gpuobj, 0x00, 0x7fc00000);
230 BAR0_WI32(priv->fb_bar->gpuobj, 0x04, 0x40000000 +
231 drm_get_resource_len(dev, 1) - 1);
232 BAR0_WI32(priv->fb_bar->gpuobj, 0x08, 0x40000000);
233 BAR0_WI32(priv->fb_bar->gpuobj, 0x0c, 0x00000000);
234 BAR0_WI32(priv->fb_bar->gpuobj, 0x10, 0x00000000);
235 BAR0_WI32(priv->fb_bar->gpuobj, 0x14, 0x00000000);
237 /* Poke the relevant regs, and pray it works :) */
238 nv_wr32(dev, NV50_PUNK_BAR_CFG_BASE, (chan->ramin->instance >> 12));
239 nv_wr32(dev, NV50_PUNK_UNK1710, 0);
240 nv_wr32(dev, NV50_PUNK_BAR_CFG_BASE, (chan->ramin->instance >> 12) |
241 NV50_PUNK_BAR_CFG_BASE_VALID);
242 nv_wr32(dev, NV50_PUNK_BAR1_CTXDMA, (priv->fb_bar->instance >> 4) |
243 NV50_PUNK_BAR1_CTXDMA_VALID);
244 nv_wr32(dev, NV50_PUNK_BAR3_CTXDMA, (priv->pramin_bar->instance >> 4) |
245 NV50_PUNK_BAR3_CTXDMA_VALID);
247 for (i = 0; i < 8; i++)
248 nv_wr32(dev, 0x1900 + (i*4), 0);
250 /* Assume that praying isn't enough, check that we can re-read the
251 * entire fake channel back from the PRAMIN BAR */
252 dev_priv->engine.instmem.prepare_access(dev, false);
253 for (i = 0; i < c_size; i += 4) {
254 if (nv_rd32(dev, NV_RAMIN + i) != nv_ri32(dev, i)) {
255 NV_ERROR(dev, "Error reading back PRAMIN at 0x%08x\n",
257 dev_priv->engine.instmem.finish_access(dev);
261 dev_priv->engine.instmem.finish_access(dev);
263 nv_wr32(dev, NV50_PUNK_BAR0_PRAMIN, save_nv001700);
265 /* Global PRAMIN heap */
266 if (nouveau_mem_init_heap(&dev_priv->ramin_heap,
267 c_size, dev_priv->ramin_size - c_size)) {
268 dev_priv->ramin_heap = NULL;
269 NV_ERROR(dev, "Failed to init RAMIN heap\n");
272 /*XXX: incorrect, but needed to make hash func "work" */
273 dev_priv->ramht_offset = 0x10000;
274 dev_priv->ramht_bits = 9;
275 dev_priv->ramht_size = (1 << dev_priv->ramht_bits);
280 nv50_instmem_takedown(struct drm_device *dev)
282 struct drm_nouveau_private *dev_priv = dev->dev_private;
283 struct nv50_instmem_priv *priv = dev_priv->engine.instmem.priv;
284 struct nouveau_channel *chan = dev_priv->fifos[0];
292 /* Restore state from before init */
293 for (i = 0x1700; i <= 0x1710; i += 4)
294 nv_wr32(dev, i, priv->save1700[(i - 0x1700) / 4]);
296 nouveau_gpuobj_ref_del(dev, &priv->fb_bar);
297 nouveau_gpuobj_ref_del(dev, &priv->pramin_bar);
298 nouveau_gpuobj_ref_del(dev, &priv->pramin_pt);
300 /* Destroy dummy channel */
302 for (i = 0; i < dev_priv->vm_vram_pt_nr; i++) {
303 nouveau_gpuobj_ref_del(dev, &chan->vm_vram_pt[i]);
304 dev_priv->vm_vram_pt[i] = NULL;
306 dev_priv->vm_vram_pt_nr = 0;
308 nouveau_gpuobj_del(dev, &chan->vm_pd);
309 nouveau_gpuobj_ref_del(dev, &chan->ramfc);
310 nouveau_gpuobj_ref_del(dev, &chan->ramin);
311 nouveau_mem_takedown(&chan->ramin_heap);
313 dev_priv->fifos[0] = dev_priv->fifos[127] = NULL;
317 dev_priv->engine.instmem.priv = NULL;
322 nv50_instmem_suspend(struct drm_device *dev)
324 struct drm_nouveau_private *dev_priv = dev->dev_private;
325 struct nouveau_channel *chan = dev_priv->fifos[0];
326 struct nouveau_gpuobj *ramin = chan->ramin->gpuobj;
329 ramin->im_backing_suspend = vmalloc(ramin->im_pramin->size);
330 if (!ramin->im_backing_suspend)
333 for (i = 0; i < ramin->im_pramin->size; i += 4)
334 ramin->im_backing_suspend[i/4] = nv_ri32(dev, i);
339 nv50_instmem_resume(struct drm_device *dev)
341 struct drm_nouveau_private *dev_priv = dev->dev_private;
342 struct nv50_instmem_priv *priv = dev_priv->engine.instmem.priv;
343 struct nouveau_channel *chan = dev_priv->fifos[0];
344 struct nouveau_gpuobj *ramin = chan->ramin->gpuobj;
347 nv_wr32(dev, NV50_PUNK_BAR0_PRAMIN, (ramin->im_backing_start >> 16));
348 for (i = 0; i < ramin->im_pramin->size; i += 4)
349 BAR0_WI32(ramin, i, ramin->im_backing_suspend[i/4]);
350 vfree(ramin->im_backing_suspend);
351 ramin->im_backing_suspend = NULL;
353 /* Poke the relevant regs, and pray it works :) */
354 nv_wr32(dev, NV50_PUNK_BAR_CFG_BASE, (chan->ramin->instance >> 12));
355 nv_wr32(dev, NV50_PUNK_UNK1710, 0);
356 nv_wr32(dev, NV50_PUNK_BAR_CFG_BASE, (chan->ramin->instance >> 12) |
357 NV50_PUNK_BAR_CFG_BASE_VALID);
358 nv_wr32(dev, NV50_PUNK_BAR1_CTXDMA, (priv->fb_bar->instance >> 4) |
359 NV50_PUNK_BAR1_CTXDMA_VALID);
360 nv_wr32(dev, NV50_PUNK_BAR3_CTXDMA, (priv->pramin_bar->instance >> 4) |
361 NV50_PUNK_BAR3_CTXDMA_VALID);
363 for (i = 0; i < 8; i++)
364 nv_wr32(dev, 0x1900 + (i*4), 0);
368 nv50_instmem_populate(struct drm_device *dev, struct nouveau_gpuobj *gpuobj,
373 if (gpuobj->im_backing)
376 *sz = (*sz + (NV50_INSTMEM_PAGE_SIZE-1)) & ~(NV50_INSTMEM_PAGE_SIZE-1);
380 ret = nouveau_bo_new(dev, NULL, *sz, 0, TTM_PL_FLAG_VRAM, 0, 0x0000,
381 true, false, &gpuobj->im_backing);
383 NV_ERROR(dev, "error getting PRAMIN backing pages: %d\n", ret);
387 ret = nouveau_bo_pin(gpuobj->im_backing, TTM_PL_FLAG_VRAM);
389 NV_ERROR(dev, "error pinning PRAMIN backing VRAM: %d\n", ret);
390 nouveau_bo_ref(NULL, &gpuobj->im_backing);
394 gpuobj->im_backing_start = gpuobj->im_backing->bo.mem.mm_node->start;
395 gpuobj->im_backing_start <<= PAGE_SHIFT;
401 nv50_instmem_clear(struct drm_device *dev, struct nouveau_gpuobj *gpuobj)
403 struct drm_nouveau_private *dev_priv = dev->dev_private;
405 if (gpuobj && gpuobj->im_backing) {
406 if (gpuobj->im_bound)
407 dev_priv->engine.instmem.unbind(dev, gpuobj);
408 nouveau_bo_unpin(gpuobj->im_backing);
409 nouveau_bo_ref(NULL, &gpuobj->im_backing);
410 gpuobj->im_backing = NULL;
415 nv50_instmem_bind(struct drm_device *dev, struct nouveau_gpuobj *gpuobj)
417 struct drm_nouveau_private *dev_priv = dev->dev_private;
418 struct nv50_instmem_priv *priv = dev_priv->engine.instmem.priv;
419 uint32_t pte, pte_end, vram;
421 if (!gpuobj->im_backing || !gpuobj->im_pramin || gpuobj->im_bound)
424 NV_DEBUG(dev, "st=0x%0llx sz=0x%0llx\n",
425 gpuobj->im_pramin->start, gpuobj->im_pramin->size);
427 pte = (gpuobj->im_pramin->start >> 12) << 3;
428 pte_end = ((gpuobj->im_pramin->size >> 12) << 3) + pte;
429 vram = gpuobj->im_backing_start;
431 NV_DEBUG(dev, "pramin=0x%llx, pte=%d, pte_end=%d\n",
432 gpuobj->im_pramin->start, pte, pte_end);
433 NV_DEBUG(dev, "first vram page: 0x%08x\n", gpuobj->im_backing_start);
435 dev_priv->engine.instmem.prepare_access(dev, true);
436 while (pte < pte_end) {
437 nv_wo32(dev, priv->pramin_pt->gpuobj, (pte + 0)/4, vram | 1);
438 nv_wo32(dev, priv->pramin_pt->gpuobj, (pte + 4)/4, 0x00000000);
441 vram += NV50_INSTMEM_PAGE_SIZE;
443 dev_priv->engine.instmem.finish_access(dev);
445 nv_wr32(dev, 0x100c80, 0x00040001);
446 if (!nv_wait(0x100c80, 0x00000001, 0x00000000)) {
447 NV_ERROR(dev, "timeout: (0x100c80 & 1) == 0 (1)\n");
448 NV_ERROR(dev, "0x100c80 = 0x%08x\n", nv_rd32(dev, 0x100c80));
452 nv_wr32(dev, 0x100c80, 0x00060001);
453 if (!nv_wait(0x100c80, 0x00000001, 0x00000000)) {
454 NV_ERROR(dev, "timeout: (0x100c80 & 1) == 0 (2)\n");
455 NV_ERROR(dev, "0x100c80 = 0x%08x\n", nv_rd32(dev, 0x100c80));
459 gpuobj->im_bound = 1;
464 nv50_instmem_unbind(struct drm_device *dev, struct nouveau_gpuobj *gpuobj)
466 struct drm_nouveau_private *dev_priv = dev->dev_private;
467 struct nv50_instmem_priv *priv = dev_priv->engine.instmem.priv;
468 uint32_t pte, pte_end;
470 if (gpuobj->im_bound == 0)
473 pte = (gpuobj->im_pramin->start >> 12) << 3;
474 pte_end = ((gpuobj->im_pramin->size >> 12) << 3) + pte;
476 dev_priv->engine.instmem.prepare_access(dev, true);
477 while (pte < pte_end) {
478 nv_wo32(dev, priv->pramin_pt->gpuobj, (pte + 0)/4, 0x00000009);
479 nv_wo32(dev, priv->pramin_pt->gpuobj, (pte + 4)/4, 0x00000000);
482 dev_priv->engine.instmem.finish_access(dev);
484 gpuobj->im_bound = 0;
489 nv50_instmem_prepare_access(struct drm_device *dev, bool write)
491 struct drm_nouveau_private *dev_priv = dev->dev_private;
492 struct nv50_instmem_priv *priv = dev_priv->engine.instmem.priv;
494 priv->last_access_wr = write;
498 nv50_instmem_finish_access(struct drm_device *dev)
500 struct drm_nouveau_private *dev_priv = dev->dev_private;
501 struct nv50_instmem_priv *priv = dev_priv->engine.instmem.priv;
503 if (priv->last_access_wr) {
504 nv_wr32(dev, 0x070000, 0x00000001);
505 if (!nv_wait(0x070000, 0x00000001, 0x00000000))
506 NV_ERROR(dev, "PRAMIN flush timeout\n");