drivers/gpu/drm/nouveau/nv50_instmem.c

   1 /*
   2  * Copyright (C) 2007 Ben Skeggs.
   3  *
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining
   7  * a copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sublicense, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial
  16  * portions of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  */
  27
  28 #include "drmP.h"
  29 #include "drm.h"
  30
  31 #include "nouveau_drv.h"
  32 #include "nouveau_vm.h"
  33
  34 #define BAR1_VM_BASE 0x0020000000ULL
  35 #define BAR1_VM_SIZE pci_resource_len(dev->pdev, 1)
  36 #define BAR3_VM_BASE 0x0000000000ULL
  37 #define BAR3_VM_SIZE pci_resource_len(dev->pdev, 3)
  38
  39 struct nv50_instmem_priv {
  40         uint32_t save1700[5]; /* 0x1700->0x1710 */
  41
  42         struct nouveau_gpuobj *bar1_dmaobj;
  43         struct nouveau_gpuobj *bar3_dmaobj;
  44 };
  45
  46 static void
  47 nv50_channel_del(struct nouveau_channel **pchan)
  48 {
  49         struct nouveau_channel *chan;
  50
  51         chan = *pchan;
  52         *pchan = NULL;
  53         if (!chan)
  54                 return;
  55
  56         nouveau_gpuobj_ref(NULL, &chan->ramfc);
  57         nouveau_vm_ref(NULL, &chan->vm, chan->vm_pd);
  58         nouveau_gpuobj_ref(NULL, &chan->vm_pd);
  59         if (chan->ramin_heap.free_stack.next)
  60                 drm_mm_takedown(&chan->ramin_heap);
  61         nouveau_gpuobj_ref(NULL, &chan->ramin);
  62         kfree(chan);
  63 }
  64
  65 static int
  66 nv50_channel_new(struct drm_device *dev, u32 size, struct nouveau_vm *vm,
  67                  struct nouveau_channel **pchan)
  68 {
  69         struct drm_nouveau_private *dev_priv = dev->dev_private;
  70         u32 pgd = (dev_priv->chipset == 0x50) ? 0x1400 : 0x0200;
  71         u32  fc = (dev_priv->chipset == 0x50) ? 0x0000 : 0x4200;
  72         struct nouveau_channel *chan;
  73         int ret, i;
  74
  75         chan = kzalloc(sizeof(*chan), GFP_KERNEL);
  76         if (!chan)
  77                 return -ENOMEM;
  78         chan->dev = dev;
  79
  80         ret = nouveau_gpuobj_new(dev, NULL, size, 0x1000, 0, &chan->ramin);
  81         if (ret) {
  82                 nv50_channel_del(&chan);
  83                 return ret;
  84         }
  85
  86         ret = drm_mm_init(&chan->ramin_heap, 0x6000, chan->ramin->size);
  87         if (ret) {
  88                 nv50_channel_del(&chan);
  89                 return ret;
  90         }
  91
  92         ret = nouveau_gpuobj_new_fake(dev, chan->ramin->pinst == ~0 ? ~0 :
  93                                       chan->ramin->pinst + pgd,
  94                                       chan->ramin->vinst + pgd,
  95                                       0x4000, NVOBJ_FLAG_ZERO_ALLOC,
  96                                       &chan->vm_pd);
  97         if (ret) {
  98                 nv50_channel_del(&chan);
  99                 return ret;
 100         }
 101
 102         for (i = 0; i < 0x4000; i += 8) {
 103                 nv_wo32(chan->vm_pd, i + 0, 0x00000000);
 104                 nv_wo32(chan->vm_pd, i + 4, 0xdeadcafe);
 105         }
 106
 107         ret = nouveau_vm_ref(vm, &chan->vm, chan->vm_pd);
 108         if (ret) {
 109                 nv50_channel_del(&chan);
 110                 return ret;
 111         }
 112
 113         ret = nouveau_gpuobj_new_fake(dev, chan->ramin->pinst == ~0 ? ~0 :
 114                                       chan->ramin->pinst + fc,
 115                                       chan->ramin->vinst + fc, 0x100,
 116                                       NVOBJ_FLAG_ZERO_ALLOC, &chan->ramfc);
 117         if (ret) {
 118                 nv50_channel_del(&chan);
 119                 return ret;
 120         }
 121
 122         *pchan = chan;
 123         return 0;
 124 }
 125
 126 int
 127 nv50_instmem_init(struct drm_device *dev)
 128 {
 129         struct drm_nouveau_private *dev_priv = dev->dev_private;
 130         struct nv50_instmem_priv *priv;
 131         struct nouveau_channel *chan;
 132         struct nouveau_vm *vm;
 133         int ret, i;
 134         u32 tmp;
 135
 136         priv = kzalloc(sizeof(*priv), GFP_KERNEL);
 137         if (!priv)
 138                 return -ENOMEM;
 139         dev_priv->engine.instmem.priv = priv;
 140
 141         /* Save state, will restore at takedown. */
 142         for (i = 0x1700; i <= 0x1710; i += 4)
 143                 priv->save1700[(i-0x1700)/4] = nv_rd32(dev, i);
 144
 145         /* Global PRAMIN heap */
 146         ret = drm_mm_init(&dev_priv->ramin_heap, 0, dev_priv->ramin_size);
 147         if (ret) {
 148                 NV_ERROR(dev, "Failed to init RAMIN heap\n");
 149                 goto error;
 150         }
 151
 152         /* BAR3 */
 153         ret = nouveau_vm_new(dev, BAR3_VM_BASE, BAR3_VM_SIZE, BAR3_VM_BASE,
 154                              29, 12, 16, &dev_priv->bar3_vm);
 155         if (ret)
 156                 goto error;
 157
 158         ret = nouveau_gpuobj_new(dev, NULL, (BAR3_VM_SIZE >> 12) * 8,
 159                                  0x1000, NVOBJ_FLAG_DONT_MAP |
 160                                  NVOBJ_FLAG_ZERO_ALLOC,
 161                                  &dev_priv->bar3_vm->pgt[0].obj);
 162         if (ret)
 163                 goto error;
 164         dev_priv->bar3_vm->pgt[0].page_shift = 12;
 165         dev_priv->bar3_vm->pgt[0].refcount = 1;
 166
 167         nv50_instmem_map(dev_priv->bar3_vm->pgt[0].obj);
 168
 169         ret = nv50_channel_new(dev, 128 * 1024, dev_priv->bar3_vm, &chan);
 170         if (ret)
 171                 goto error;
 172         dev_priv->channels.ptr[0] = dev_priv->channels.ptr[127] = chan;
 173
 174         ret = nv50_gpuobj_dma_new(chan, 0x0000, BAR3_VM_BASE, BAR3_VM_SIZE,
 175                                   NV_MEM_TARGET_VM, NV_MEM_ACCESS_VM,
 176                                   NV_MEM_TYPE_VM, NV_MEM_COMP_VM,
 177                                   &priv->bar3_dmaobj);
 178         if (ret)
 179                 goto error;
 180
 181         nv_wr32(dev, 0x001704, 0x00000000 | (chan->ramin->vinst >> 12));
 182         nv_wr32(dev, 0x001704, 0x40000000 | (chan->ramin->vinst >> 12));
 183         nv_wr32(dev, 0x00170c, 0x80000000 | (priv->bar3_dmaobj->cinst >> 4));
 184
 185         dev_priv->engine.instmem.flush(dev);
 186         dev_priv->ramin_available = true;
 187
 188         tmp = nv_ro32(chan->ramin, 0);
 189         nv_wo32(chan->ramin, 0, ~tmp);
 190         if (nv_ro32(chan->ramin, 0) != ~tmp) {
 191                 NV_ERROR(dev, "PRAMIN readback failed\n");
 192                 ret = -EIO;
 193                 goto error;
 194         }
 195         nv_wo32(chan->ramin, 0, tmp);
 196
 197         /* BAR1 */
 198         ret = nouveau_vm_new(dev, BAR1_VM_BASE, BAR1_VM_SIZE, BAR1_VM_BASE,
 199                              29, 12, 16, &vm);
 200         if (ret)
 201                 goto error;
 202
 203         ret = nouveau_vm_ref(vm, &dev_priv->bar1_vm, chan->vm_pd);
 204         if (ret)
 205                 goto error;
 206         nouveau_vm_ref(NULL, &vm, NULL);
 207
 208         ret = nv50_gpuobj_dma_new(chan, 0x0000, BAR1_VM_BASE, BAR1_VM_SIZE,
 209                                   NV_MEM_TARGET_VM, NV_MEM_ACCESS_VM,
 210                                   NV_MEM_TYPE_VM, NV_MEM_COMP_VM,
 211                                   &priv->bar1_dmaobj);
 212         if (ret)
 213                 goto error;
 214
 215         nv_wr32(dev, 0x001708, 0x80000000 | (priv->bar1_dmaobj->cinst >> 4));
 216         for (i = 0; i < 8; i++)
 217                 nv_wr32(dev, 0x1900 + (i*4), 0);
 218
 219         /* Create shared channel VM, space is reserved at the beginning
 220          * to catch "NULL pointer" references
 221          */
 222         ret = nouveau_vm_new(dev, 0, (1ULL << 40), 0x0020000000ULL,
 223                              29, 12, 16, &dev_priv->chan_vm);
 224         if (ret)
 225                 return ret;
 226
 227         return 0;
 228
 229 error:
 230         nv50_instmem_takedown(dev);
 231         return ret;
 232 }
 233
 234 void
 235 nv50_instmem_takedown(struct drm_device *dev)
 236 {
 237         struct drm_nouveau_private *dev_priv = dev->dev_private;
 238         struct nv50_instmem_priv *priv = dev_priv->engine.instmem.priv;
 239         struct nouveau_channel *chan = dev_priv->channels.ptr[0];
 240         int i;
 241
 242         NV_DEBUG(dev, "\n");
 243
 244         if (!priv)
 245                 return;
 246
 247         dev_priv->ramin_available = false;
 248
 249         nouveau_vm_ref(NULL, &dev_priv->chan_vm, NULL);
 250
 251         for (i = 0x1700; i <= 0x1710; i += 4)
 252                 nv_wr32(dev, i, priv->save1700[(i - 0x1700) / 4]);
 253
 254         nouveau_gpuobj_ref(NULL, &priv->bar3_dmaobj);
 255         nouveau_gpuobj_ref(NULL, &priv->bar1_dmaobj);
 256
 257         nouveau_vm_ref(NULL, &dev_priv->bar1_vm, chan->vm_pd);
 258         dev_priv->channels.ptr[127] = 0;
 259         nv50_channel_del(&dev_priv->channels.ptr[0]);
 260
 261         nouveau_gpuobj_ref(NULL, &dev_priv->bar3_vm->pgt[0].obj);
 262         nouveau_vm_ref(NULL, &dev_priv->bar3_vm, NULL);
 263
 264         if (dev_priv->ramin_heap.free_stack.next)
 265                 drm_mm_takedown(&dev_priv->ramin_heap);
 266
 267         dev_priv->engine.instmem.priv = NULL;
 268         kfree(priv);
 269 }
 270
 271 int
 272 nv50_instmem_suspend(struct drm_device *dev)
 273 {
 274         struct drm_nouveau_private *dev_priv = dev->dev_private;
 275
 276         dev_priv->ramin_available = false;
 277         return 0;
 278 }
 279
 280 void
 281 nv50_instmem_resume(struct drm_device *dev)
 282 {
 283         struct drm_nouveau_private *dev_priv = dev->dev_private;
 284         struct nv50_instmem_priv *priv = dev_priv->engine.instmem.priv;
 285         struct nouveau_channel *chan = dev_priv->channels.ptr[0];
 286         int i;
 287
 288         /* Poke the relevant regs, and pray it works :) */
 289         nv_wr32(dev, NV50_PUNK_BAR_CFG_BASE, (chan->ramin->vinst >> 12));
 290         nv_wr32(dev, NV50_PUNK_UNK1710, 0);
 291         nv_wr32(dev, NV50_PUNK_BAR_CFG_BASE, (chan->ramin->vinst >> 12) |
 292                                          NV50_PUNK_BAR_CFG_BASE_VALID);
 293         nv_wr32(dev, NV50_PUNK_BAR1_CTXDMA, (priv->bar1_dmaobj->cinst >> 4) |
 294                                         NV50_PUNK_BAR1_CTXDMA_VALID);
 295         nv_wr32(dev, NV50_PUNK_BAR3_CTXDMA, (priv->bar3_dmaobj->cinst >> 4) |
 296                                         NV50_PUNK_BAR3_CTXDMA_VALID);
 297
 298         for (i = 0; i < 8; i++)
 299                 nv_wr32(dev, 0x1900 + (i*4), 0);
 300
 301         dev_priv->ramin_available = true;
 302 }
 303
 304 struct nv50_gpuobj_node {
 305         struct nouveau_vram *vram;
 306         struct nouveau_vma chan_vma;
 307         u32 align;
 308 };
 309
 310
 311 int
 312 nv50_instmem_get(struct nouveau_gpuobj *gpuobj, u32 size, u32 align)
 313 {
 314         struct drm_device *dev = gpuobj->dev;
 315         struct drm_nouveau_private *dev_priv = dev->dev_private;
 316         struct nouveau_vram_engine *vram = &dev_priv->engine.vram;
 317         struct nv50_gpuobj_node *node = NULL;
 318         int ret;
 319
 320         node = kzalloc(sizeof(*node), GFP_KERNEL);
 321         if (!node)
 322                 return -ENOMEM;
 323         node->align = align;
 324
 325         size  = (size + 4095) & ~4095;
 326         align = max(align, (u32)4096);
 327
 328         ret = vram->get(dev, size, align, 0, 0, &node->vram);
 329         if (ret) {
 330                 kfree(node);
 331                 return ret;
 332         }
 333
 334         gpuobj->vinst = node->vram->offset;
 335
 336         if (gpuobj->flags & NVOBJ_FLAG_VM) {
 337                 ret = nouveau_vm_get(dev_priv->chan_vm, size, 12,
 338                                      NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS,
 339                                      &node->chan_vma);
 340                 if (ret) {
 341                         vram->put(dev, &node->vram);
 342                         kfree(node);
 343                         return ret;
 344                 }
 345
 346                 nouveau_vm_map(&node->chan_vma, node->vram);
 347                 gpuobj->vinst = node->chan_vma.offset;
 348         }
 349
 350         gpuobj->size = size;
 351         gpuobj->node = node;
 352         return 0;
 353 }
 354
 355 void
 356 nv50_instmem_put(struct nouveau_gpuobj *gpuobj)
 357 {
 358         struct drm_device *dev = gpuobj->dev;
 359         struct drm_nouveau_private *dev_priv = dev->dev_private;
 360         struct nouveau_vram_engine *vram = &dev_priv->engine.vram;
 361         struct nv50_gpuobj_node *node;
 362
 363         node = gpuobj->node;
 364         gpuobj->node = NULL;
 365
 366         if (node->chan_vma.node) {
 367                 nouveau_vm_unmap(&node->chan_vma);
 368                 nouveau_vm_put(&node->chan_vma);
 369         }
 370         vram->put(dev, &node->vram);
 371         kfree(node);
 372 }
 373
 374 int
 375 nv50_instmem_map(struct nouveau_gpuobj *gpuobj)
 376 {
 377         struct drm_nouveau_private *dev_priv = gpuobj->dev->dev_private;
 378         struct nv50_gpuobj_node *node = gpuobj->node;
 379         int ret;
 380
 381         ret = nouveau_vm_get(dev_priv->bar3_vm, gpuobj->size, 12,
 382                              NV_MEM_ACCESS_RW, &node->vram->bar_vma);
 383         if (ret)
 384                 return ret;
 385
 386         nouveau_vm_map(&node->vram->bar_vma, node->vram);
 387         gpuobj->pinst = node->vram->bar_vma.offset;
 388         return 0;
 389 }
 390
 391 void
 392 nv50_instmem_unmap(struct nouveau_gpuobj *gpuobj)
 393 {
 394         struct nv50_gpuobj_node *node = gpuobj->node;
 395
 396         if (node->vram->bar_vma.node) {
 397                 nouveau_vm_unmap(&node->vram->bar_vma);
 398                 nouveau_vm_put(&node->vram->bar_vma);
 399         }
 400 }
 401
 402 void
 403 nv50_instmem_flush(struct drm_device *dev)
 404 {
 405         nv_wr32(dev, 0x00330c, 0x00000001);
 406         if (!nv_wait(dev, 0x00330c, 0x00000002, 0x00000000))
 407                 NV_ERROR(dev, "PRAMIN flush timeout\n");
 408 }
 409
 410 void
 411 nv84_instmem_flush(struct drm_device *dev)
 412 {
 413         nv_wr32(dev, 0x070000, 0x00000001);
 414         if (!nv_wait(dev, 0x070000, 0x00000002, 0x00000000))
 415                 NV_ERROR(dev, "PRAMIN flush timeout\n");
 416 }
 417