2 * Copyright 2012 Red Hat Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
27 #include "nouveau_drv.h"
28 #include "nouveau_ramht.h"
29 #include "nouveau_software.h"
31 #include "nv50_display.h"
33 struct nv50_software_priv {
34 struct nouveau_software_priv base;
37 struct nv50_software_chan {
38 struct nouveau_software_chan base;
40 struct nouveau_gpuobj *object;
45 mthd_dma_vblsem(struct nouveau_channel *chan, u32 class, u32 mthd, u32 data)
47 struct nv50_software_chan *pch = chan->engctx[NVOBJ_ENGINE_SW];
48 struct nouveau_gpuobj *gpuobj;
50 gpuobj = nouveau_ramht_find(chan, data);
54 if (nouveau_notifier_offset(gpuobj, NULL))
57 pch->vblank.object = gpuobj;
58 pch->base.vblank.offset = ~0;
63 mthd_vblsem_offset(struct nouveau_channel *chan, u32 class, u32 mthd, u32 data)
65 struct nv50_software_chan *pch = chan->engctx[NVOBJ_ENGINE_SW];
67 if (nouveau_notifier_offset(pch->vblank.object, &data))
70 pch->base.vblank.offset = data >> 2;
75 mthd_vblsem_value(struct nouveau_channel *chan, u32 class, u32 mthd, u32 data)
77 struct nv50_software_chan *pch = chan->engctx[NVOBJ_ENGINE_SW];
78 pch->base.vblank.value = data;
83 mthd_vblsem_release(struct nouveau_channel *chan, u32 class, u32 mthd, u32 data)
85 struct nv50_software_priv *psw = nv_engine(chan->dev, NVOBJ_ENGINE_SW);
86 struct nv50_software_chan *pch = chan->engctx[NVOBJ_ENGINE_SW];
87 struct drm_device *dev = chan->dev;
89 if (!pch->vblank.object || pch->base.vblank.offset == ~0 || data > 1)
92 drm_vblank_get(dev, data);
94 pch->base.vblank.head = data;
95 list_add(&pch->base.vblank.list, &psw->base.vblank);
100 mthd_flip(struct nouveau_channel *chan, u32 class, u32 mthd, u32 data)
102 nouveau_finish_page_flip(chan, NULL);
107 nv50_software_context_new(struct nouveau_channel *chan, int engine)
109 struct nv50_software_priv *psw = nv_engine(chan->dev, NVOBJ_ENGINE_SW);
110 struct nv50_display *pdisp = nv50_display(chan->dev);
111 struct nv50_software_chan *pch;
114 pch = kzalloc(sizeof(*pch), GFP_KERNEL);
118 nouveau_software_context_new(&pch->base);
119 pch->base.vblank.bo = chan->notifier_bo;
120 chan->engctx[engine] = pch;
122 /* dma objects for display sync channel semaphore blocks */
123 for (i = 0; i < chan->dev->mode_config.num_crtc; i++) {
124 struct nv50_display_crtc *dispc = &pdisp->crtc[i];
125 struct nouveau_gpuobj *obj = NULL;
127 ret = nouveau_gpuobj_dma_new(chan, NV_CLASS_DMA_IN_MEMORY,
128 dispc->sem.bo->bo.offset, 0x1000,
130 NV_MEM_TARGET_VRAM, &obj);
134 ret = nouveau_ramht_insert(chan, NvEvoSema0 + i, obj);
135 nouveau_gpuobj_ref(NULL, &obj);
139 psw->base.base.context_del(chan, engine);
144 nv50_software_context_del(struct nouveau_channel *chan, int engine)
146 struct nv50_software_chan *pch = chan->engctx[engine];
147 chan->engctx[engine] = NULL;
152 nv50_software_object_new(struct nouveau_channel *chan, int engine,
153 u32 handle, u16 class)
155 struct drm_device *dev = chan->dev;
156 struct nouveau_gpuobj *obj = NULL;
159 ret = nouveau_gpuobj_new(dev, chan, 16, 16, 0, &obj);
165 ret = nouveau_ramht_insert(chan, handle, obj);
166 nouveau_gpuobj_ref(NULL, &obj);
171 nv50_software_init(struct drm_device *dev, int engine)
177 nv50_software_fini(struct drm_device *dev, int engine, bool suspend)
183 nv50_software_destroy(struct drm_device *dev, int engine)
185 struct nv50_software_priv *psw = nv_engine(dev, engine);
187 NVOBJ_ENGINE_DEL(dev, SW);
192 nv50_software_create(struct drm_device *dev)
194 struct nv50_software_priv *psw = kzalloc(sizeof(*psw), GFP_KERNEL);
198 psw->base.base.destroy = nv50_software_destroy;
199 psw->base.base.init = nv50_software_init;
200 psw->base.base.fini = nv50_software_fini;
201 psw->base.base.context_new = nv50_software_context_new;
202 psw->base.base.context_del = nv50_software_context_del;
203 psw->base.base.object_new = nv50_software_object_new;
204 nouveau_software_create(&psw->base);
206 NVOBJ_ENGINE_ADD(dev, SW, &psw->base.base);
207 NVOBJ_CLASS(dev, 0x506e, SW);
208 NVOBJ_MTHD (dev, 0x506e, 0x018c, mthd_dma_vblsem);
209 NVOBJ_MTHD (dev, 0x506e, 0x0400, mthd_vblsem_offset);
210 NVOBJ_MTHD (dev, 0x506e, 0x0404, mthd_vblsem_value);
211 NVOBJ_MTHD (dev, 0x506e, 0x0408, mthd_vblsem_release);
212 NVOBJ_MTHD (dev, 0x506e, 0x0500, mthd_flip);