2 * Copyright 2010 Red Hat Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
26 #include "nouveau_drv.h"
27 #include "nouveau_util.h"
29 static void nv84_crypt_isr(struct drm_device *);
32 nv84_crypt_create_context(struct nouveau_channel *chan)
34 struct drm_device *dev = chan->dev;
35 struct drm_nouveau_private *dev_priv = dev->dev_private;
36 struct nouveau_gpuobj *ramin = chan->ramin;
39 NV_DEBUG(dev, "ch%d\n", chan->id);
41 ret = nouveau_gpuobj_new(dev, chan, 256, 0,
42 NVOBJ_FLAG_ZERO_ALLOC | NVOBJ_FLAG_ZERO_FREE,
47 nv_wo32(ramin, 0xa0, 0x00190000);
48 nv_wo32(ramin, 0xa4, chan->crypt_ctx->vinst + 0xff);
49 nv_wo32(ramin, 0xa8, chan->crypt_ctx->vinst);
50 nv_wo32(ramin, 0xac, 0);
51 nv_wo32(ramin, 0xb0, 0);
52 nv_wo32(ramin, 0xb4, 0);
54 dev_priv->engine.instmem.flush(dev);
59 nv84_crypt_destroy_context(struct nouveau_channel *chan)
61 struct drm_device *dev = chan->dev;
67 inst = (chan->ramin->vinst >> 12);
70 /* mark context as invalid if still on the hardware, not
71 * doing this causes issues the next time PCRYPT is used,
74 nv_wr32(dev, 0x10200c, 0x00000000);
75 if (nv_rd32(dev, 0x102188) == inst)
76 nv_mask(dev, 0x102188, 0x80000000, 0x00000000);
77 if (nv_rd32(dev, 0x10218c) == inst)
78 nv_mask(dev, 0x10218c, 0x80000000, 0x00000000);
79 nv_wr32(dev, 0x10200c, 0x00000010);
81 nouveau_gpuobj_ref(NULL, &chan->crypt_ctx);
85 nv84_crypt_tlb_flush(struct drm_device *dev)
87 nv50_vm_flush(dev, 0x0a);
91 nv84_crypt_init(struct drm_device *dev)
93 struct drm_nouveau_private *dev_priv = dev->dev_private;
94 struct nouveau_crypt_engine *pcrypt = &dev_priv->engine.crypt;
96 if (!pcrypt->registered) {
97 NVOBJ_CLASS(dev, 0x74c1, CRYPT);
98 pcrypt->registered = true;
101 nv_mask(dev, 0x000200, 0x00004000, 0x00000000);
102 nv_mask(dev, 0x000200, 0x00004000, 0x00004000);
104 nouveau_irq_register(dev, 14, nv84_crypt_isr);
105 nv_wr32(dev, 0x102130, 0xffffffff);
106 nv_wr32(dev, 0x102140, 0xffffffbf);
108 nv_wr32(dev, 0x10200c, 0x00000010);
113 nv84_crypt_fini(struct drm_device *dev)
115 nv_wr32(dev, 0x102140, 0x00000000);
116 nouveau_irq_unregister(dev, 14);
120 nv84_crypt_isr(struct drm_device *dev)
122 u32 stat = nv_rd32(dev, 0x102130);
123 u32 mthd = nv_rd32(dev, 0x102190);
124 u32 data = nv_rd32(dev, 0x102194);
125 u32 inst = nv_rd32(dev, 0x102188) & 0x7fffffff;
126 int show = nouveau_ratelimit();
129 NV_INFO(dev, "PCRYPT_INTR: 0x%08x 0x%08x 0x%08x 0x%08x\n",
130 stat, mthd, data, inst);
133 nv_wr32(dev, 0x102130, stat);
134 nv_wr32(dev, 0x10200c, 0x10);
136 nv50_fb_vm_trap(dev, show, "PCRYPT");