2 * Copyright 2010 Red Hat Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
26 #include "nouveau_drv.h"
29 nv84_crypt_create_context(struct nouveau_channel *chan)
31 struct drm_device *dev = chan->dev;
32 struct drm_nouveau_private *dev_priv = dev->dev_private;
33 struct nouveau_gpuobj *ramin = chan->ramin;
36 NV_DEBUG(dev, "ch%d\n", chan->id);
38 ret = nouveau_gpuobj_new(dev, chan, 256, 0,
39 NVOBJ_FLAG_ZERO_ALLOC | NVOBJ_FLAG_ZERO_FREE,
44 nv_wo32(ramin, 0xa0, 0x00190000);
45 nv_wo32(ramin, 0xa4, chan->crypt_ctx->vinst + 0xff);
46 nv_wo32(ramin, 0xa8, chan->crypt_ctx->vinst);
47 nv_wo32(ramin, 0xac, 0);
48 nv_wo32(ramin, 0xb0, 0);
49 nv_wo32(ramin, 0xb4, 0);
51 dev_priv->engine.instmem.flush(dev);
56 nv84_crypt_destroy_context(struct nouveau_channel *chan)
58 struct drm_device *dev = chan->dev;
64 inst = (chan->ramin->vinst >> 12);
67 /* mark context as invalid if still on the hardware, not
68 * doing this causes issues the next time PCRYPT is used,
71 nv_wr32(dev, 0x10200c, 0x00000000);
72 if (nv_rd32(dev, 0x102188) == inst)
73 nv_mask(dev, 0x102188, 0x80000000, 0x00000000);
74 if (nv_rd32(dev, 0x10218c) == inst)
75 nv_mask(dev, 0x10218c, 0x80000000, 0x00000000);
76 nv_wr32(dev, 0x10200c, 0x00000010);
78 nouveau_gpuobj_ref(NULL, &chan->crypt_ctx);
82 nv84_crypt_tlb_flush(struct drm_device *dev)
84 nv50_vm_flush(dev, 0x0a);
88 nv84_crypt_init(struct drm_device *dev)
90 struct drm_nouveau_private *dev_priv = dev->dev_private;
91 struct nouveau_crypt_engine *pcrypt = &dev_priv->engine.crypt;
93 if (!pcrypt->registered) {
94 NVOBJ_CLASS(dev, 0x74c1, CRYPT);
95 pcrypt->registered = true;
98 nv_mask(dev, 0x000200, 0x00004000, 0x00000000);
99 nv_mask(dev, 0x000200, 0x00004000, 0x00004000);
100 nv_wr32(dev, 0x102130, 0xffffffff);
101 nv_wr32(dev, 0x102140, 0xffffffbf);
102 nv_wr32(dev, 0x10200c, 0x00000010);
107 nv84_crypt_fini(struct drm_device *dev)
109 nv_wr32(dev, 0x102140, 0x00000000);