2 * Copyright 2012 Red Hat Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
25 #include <core/object.h>
26 #include <core/class.h>
28 #include <engine/fifo.h>
30 #include "nouveau_drm.h"
31 #include "nouveau_dma.h"
32 #include "nouveau_fence.h"
34 #include "nv50_display.h"
36 struct nv84_fence_chan {
37 struct nouveau_fence_chan base;
40 struct nv84_fence_priv {
41 struct nouveau_fence_priv base;
42 struct nouveau_gpuobj *mem;
46 nv84_fence_emit(struct nouveau_fence *fence)
48 struct nouveau_channel *chan = fence->channel;
49 struct nouveau_fifo_chan *fifo = (void *)chan->object;
50 int ret = RING_SPACE(chan, 7);
52 BEGIN_NV04(chan, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 1);
53 OUT_RING (chan, NvSema);
54 BEGIN_NV04(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4);
55 OUT_RING (chan, upper_32_bits(fifo->chid * 16));
56 OUT_RING (chan, lower_32_bits(fifo->chid * 16));
57 OUT_RING (chan, fence->sequence);
58 OUT_RING (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_WRITE_LONG);
66 nv84_fence_sync(struct nouveau_fence *fence,
67 struct nouveau_channel *prev, struct nouveau_channel *chan)
69 struct nouveau_fifo_chan *fifo = (void *)prev->object;
70 int ret = RING_SPACE(chan, 7);
72 BEGIN_NV04(chan, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 1);
73 OUT_RING (chan, NvSema);
74 BEGIN_NV04(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4);
75 OUT_RING (chan, upper_32_bits(fifo->chid * 16));
76 OUT_RING (chan, lower_32_bits(fifo->chid * 16));
77 OUT_RING (chan, fence->sequence);
78 OUT_RING (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_GEQUAL);
85 nv84_fence_read(struct nouveau_channel *chan)
87 struct nouveau_fifo_chan *fifo = (void *)chan->object;
88 struct nv84_fence_priv *priv = chan->drm->fence;
89 return nv_ro32(priv->mem, fifo->chid * 16);
93 nv84_fence_context_del(struct nouveau_channel *chan)
95 struct nv84_fence_chan *fctx = chan->fence;
96 nouveau_fence_context_del(&fctx->base);
102 nv84_fence_context_new(struct nouveau_channel *chan)
104 struct drm_device *dev = chan->drm->dev;
105 struct nouveau_fifo_chan *fifo = (void *)chan->object;
106 struct nv84_fence_priv *priv = chan->drm->fence;
107 struct nv84_fence_chan *fctx;
108 struct nouveau_object *object;
111 fctx = chan->fence = kzalloc(sizeof(*fctx), GFP_KERNEL);
115 nouveau_fence_context_new(&fctx->base);
117 ret = nouveau_object_new(nv_object(chan->cli), chan->handle,
119 &(struct nv_dma_class) {
120 .flags = NV_DMA_TARGET_VRAM |
122 .start = priv->mem->addr,
123 .limit = priv->mem->addr +
125 }, sizeof(struct nv_dma_class),
128 /* dma objects for display sync channel semaphore blocks */
129 for (i = 0; !ret && i < dev->mode_config.num_crtc; i++) {
130 struct nouveau_bo *bo = nv50_display_crtc_sema(dev, i);
132 ret = nouveau_object_new(nv_object(chan->cli), chan->handle,
133 NvEvoSema0 + i, 0x003d,
134 &(struct nv_dma_class) {
135 .flags = NV_DMA_TARGET_VRAM |
137 .start = bo->bo.offset,
138 .limit = bo->bo.offset + 0xfff,
139 }, sizeof(struct nv_dma_class),
144 nv84_fence_context_del(chan);
145 nv_wo32(priv->mem, fifo->chid * 16, 0x00000000);
150 nv84_fence_destroy(struct nouveau_drm *drm)
152 struct nv84_fence_priv *priv = drm->fence;
153 nouveau_gpuobj_ref(NULL, &priv->mem);
159 nv84_fence_create(struct nouveau_drm *drm)
161 struct nouveau_fifo *pfifo = nouveau_fifo(drm->device);
162 struct nv84_fence_priv *priv;
163 u32 chan = pfifo->max + 1;
166 priv = drm->fence = kzalloc(sizeof(*priv), GFP_KERNEL);
170 priv->base.dtor = nv84_fence_destroy;
171 priv->base.context_new = nv84_fence_context_new;
172 priv->base.context_del = nv84_fence_context_del;
173 priv->base.emit = nv84_fence_emit;
174 priv->base.sync = nv84_fence_sync;
175 priv->base.read = nv84_fence_read;
177 ret = nouveau_gpuobj_new(drm->device, NULL, chan * 16, 0x1000, 0,
180 nv84_fence_destroy(drm);