drivers/gpu/drm/nouveau/nv84_fence.c

   1 /*
   2  * Copyright 2012 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24
  25 #include "drmP.h"
  26 #include "nouveau_drv.h"
  27 #include "nouveau_dma.h"
  28 #include "nouveau_ramht.h"
  29 #include "nouveau_fence.h"
  30
  31 struct nv84_fence_chan {
  32         struct nouveau_fence_chan base;
  33 };
  34
  35 struct nv84_fence_priv {
  36         struct nouveau_fence_priv base;
  37         struct nouveau_gpuobj *mem;
  38 };
  39
  40 static int
  41 nv84_fence_emit(struct nouveau_fence *fence)
  42 {
  43         struct nouveau_channel *chan = fence->channel;
  44         int ret = RING_SPACE(chan, 7);
  45         if (ret == 0) {
  46                 BEGIN_NV04(chan, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 1);
  47                 OUT_RING  (chan, NvSema);
  48                 BEGIN_NV04(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4);
  49                 OUT_RING  (chan, upper_32_bits(chan->id * 16));
  50                 OUT_RING  (chan, lower_32_bits(chan->id * 16));
  51                 OUT_RING  (chan, fence->sequence);
  52                 OUT_RING  (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_WRITE_LONG);
  53                 FIRE_RING (chan);
  54         }
  55         return ret;
  56 }
  57
  58 static int
  59 nv84_fence_sync(struct nouveau_fence *fence, struct nouveau_channel *chan)
  60 {
  61         int ret = RING_SPACE(chan, 7);
  62         if (ret == 0) {
  63                 BEGIN_NV04(chan, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 1);
  64                 OUT_RING  (chan, NvSema);
  65                 BEGIN_NV04(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4);
  66                 OUT_RING  (chan, upper_32_bits(fence->channel->id * 16));
  67                 OUT_RING  (chan, lower_32_bits(fence->channel->id * 16));
  68                 OUT_RING  (chan, fence->sequence);
  69                 OUT_RING  (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_GEQUAL);
  70                 FIRE_RING (chan);
  71         }
  72         return ret;
  73 }
  74
  75 static u32
  76 nv84_fence_read(struct nouveau_channel *chan)
  77 {
  78         struct nv84_fence_priv *priv = nv_engine(chan->dev, NVOBJ_ENGINE_FENCE);
  79         return nv_ro32(priv->mem, chan->id * 16);
  80 }
  81
  82 static void
  83 nv84_fence_context_del(struct nouveau_channel *chan, int engine)
  84 {
  85         struct nv84_fence_chan *fctx = chan->engctx[engine];
  86         nouveau_fence_context_del(&fctx->base);
  87         chan->engctx[engine] = NULL;
  88         kfree(fctx);
  89 }
  90
  91 static int
  92 nv84_fence_context_new(struct nouveau_channel *chan, int engine)
  93 {
  94         struct nv84_fence_priv *priv = nv_engine(chan->dev, engine);
  95         struct nv84_fence_chan *fctx;
  96         struct nouveau_gpuobj *obj;
  97         int ret;
  98
  99         fctx = chan->engctx[engine] = kzalloc(sizeof(*fctx), GFP_KERNEL);
 100         if (!fctx)
 101                 return -ENOMEM;
 102
 103         nouveau_fence_context_new(&fctx->base);
 104
 105         ret = nouveau_gpuobj_dma_new(chan, NV_CLASS_DMA_FROM_MEMORY,
 106                                      priv->mem->vinst, priv->mem->size,
 107                                      NV_MEM_ACCESS_RW,
 108                                      NV_MEM_TARGET_VRAM, &obj);
 109         if (ret == 0) {
 110                 ret = nouveau_ramht_insert(chan, NvSema, obj);
 111                 nouveau_gpuobj_ref(NULL, &obj);
 112                 nv_wo32(priv->mem, chan->id * 16, 0x00000000);
 113         }
 114
 115         if (ret)
 116                 nv84_fence_context_del(chan, engine);
 117         return ret;
 118 }
 119
 120 static int
 121 nv84_fence_fini(struct drm_device *dev, int engine, bool suspend)
 122 {
 123         return 0;
 124 }
 125
 126 static int
 127 nv84_fence_init(struct drm_device *dev, int engine)
 128 {
 129         return 0;
 130 }
 131
 132 static void
 133 nv84_fence_destroy(struct drm_device *dev, int engine)
 134 {
 135         struct drm_nouveau_private *dev_priv = dev->dev_private;
 136         struct nv84_fence_priv *priv = nv_engine(dev, engine);
 137
 138         nouveau_gpuobj_ref(NULL, &priv->mem);
 139         dev_priv->eng[engine] = NULL;
 140         kfree(priv);
 141 }
 142
 143 int
 144 nv84_fence_create(struct drm_device *dev)
 145 {
 146         struct drm_nouveau_private *dev_priv = dev->dev_private;
 147         struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
 148         struct nv84_fence_priv *priv;
 149         int ret;
 150
 151         priv = kzalloc(sizeof(*priv), GFP_KERNEL);
 152         if (!priv)
 153                 return -ENOMEM;
 154
 155         priv->base.engine.destroy = nv84_fence_destroy;
 156         priv->base.engine.init = nv84_fence_init;
 157         priv->base.engine.fini = nv84_fence_fini;
 158         priv->base.engine.context_new = nv84_fence_context_new;
 159         priv->base.engine.context_del = nv84_fence_context_del;
 160         priv->base.emit = nv84_fence_emit;
 161         priv->base.sync = nv84_fence_sync;
 162         priv->base.read = nv84_fence_read;
 163         dev_priv->eng[NVOBJ_ENGINE_FENCE] = &priv->base.engine;
 164
 165         ret = nouveau_gpuobj_new(dev, NULL, 16 * pfifo->channels,
 166                                  0x1000, 0, &priv->mem);
 167         if (ret)
 168                 goto out;
 169
 170 out:
 171         if (ret)
 172                 nv84_fence_destroy(dev, NVOBJ_ENGINE_FENCE);
 173         return ret;
 174 }