2 * Copyright 2010 Red Hat Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
26 #include "nouveau_drv.h"
27 #include <nouveau_bios.h>
28 #include "nouveau_pm.h"
30 static u32 read_clk(struct drm_device *, int, bool);
31 static u32 read_pll(struct drm_device *, int, u32);
34 read_vco(struct drm_device *dev, int clk)
36 u32 sctl = nv_rd32(dev, 0x4120 + (clk * 4));
37 if ((sctl & 0x00000030) != 0x00000030)
38 return read_pll(dev, 0x41, 0x00e820);
39 return read_pll(dev, 0x42, 0x00e8a0);
43 read_clk(struct drm_device *dev, int clk, bool ignore_en)
45 struct drm_nouveau_private *dev_priv = dev->dev_private;
48 /* refclk for the 0xe8xx plls is a fixed frequency */
50 if (dev_priv->chipset == 0xaf) {
51 /* no joke.. seriously.. sigh.. */
52 return nv_rd32(dev, 0x00471c) * 1000;
55 return dev_priv->crystal;
58 sctl = nv_rd32(dev, 0x4120 + (clk * 4));
59 if (!ignore_en && !(sctl & 0x00000100))
62 switch (sctl & 0x00003000) {
64 return dev_priv->crystal;
66 if (sctl & 0x00000040)
70 sclk = read_vco(dev, clk);
71 sdiv = ((sctl & 0x003f0000) >> 16) + 2;
72 return (sclk * 2) / sdiv;
79 read_pll(struct drm_device *dev, int clk, u32 pll)
81 u32 ctrl = nv_rd32(dev, pll + 0);
82 u32 sclk = 0, P = 1, N = 1, M = 1;
84 if (!(ctrl & 0x00000008)) {
85 if (ctrl & 0x00000001) {
86 u32 coef = nv_rd32(dev, pll + 4);
87 M = (coef & 0x000000ff) >> 0;
88 N = (coef & 0x0000ff00) >> 8;
89 P = (coef & 0x003f0000) >> 16;
91 /* no post-divider on these.. */
92 if ((pll & 0x00ff00) == 0x00e800)
95 sclk = read_clk(dev, 0x00 + clk, false);
98 sclk = read_clk(dev, 0x10 + clk, false);
102 return sclk * N / (M * P);
112 calc_clk(struct drm_device *dev, int clk, u32 pll, u32 khz, struct creg *reg)
114 struct nvbios_pll limits;
115 u32 oclk, sclk, sdiv;
122 NV_DEBUG(dev, "no clock for 0x%04x/0x%02x\n", pll, clk);
128 reg->clk = 0x00000100;
131 reg->clk = 0x00002100;
134 reg->clk = 0x00002140;
137 sclk = read_vco(dev, clk);
138 sdiv = min((sclk * 2) / (khz - 2999), (u32)65);
139 /* if the clock has a PLL attached, and we can get a within
140 * [-2, 3) MHz of a divider, we'll disable the PLL and use
141 * the divider instead.
143 * divider can go as low as 2, limited here because NVIDIA
144 * and the VBIOS on my NVA8 seem to prefer using the PLL
145 * for 810MHz - is there a good reason?
148 oclk = (sclk * 2) / sdiv;
150 if (!pll || (diff >= -2000 && diff < 3000)) {
151 reg->clk = (((sdiv - 2) << 16) | 0x00003100);
157 NV_ERROR(dev, "bad freq %02x: %d %d\n", clk, khz, sclk);
164 ret = get_pll_limits(dev, pll, &limits);
168 limits.refclk = read_clk(dev, clk - 0x10, true);
172 ret = nva3_calc_pll(dev, &limits, khz, &N, NULL, &M, &P);
174 reg->clk = nv_rd32(dev, 0x4120 + (clk * 4));
175 reg->pll = (P << 16) | (N << 8) | M;
181 prog_pll(struct drm_device *dev, int clk, u32 pll, struct creg *reg)
183 const u32 src0 = 0x004120 + (clk * 4);
184 const u32 src1 = 0x004160 + (clk * 4);
185 const u32 ctrl = pll + 0;
186 const u32 coef = pll + 4;
188 if (!reg->clk && !reg->pll) {
189 NV_DEBUG(dev, "no clock for %02x\n", clk);
194 nv_mask(dev, src0, 0x00000101, 0x00000101);
195 nv_wr32(dev, coef, reg->pll);
196 nv_mask(dev, ctrl, 0x00000015, 0x00000015);
197 nv_mask(dev, ctrl, 0x00000010, 0x00000000);
198 nv_wait(dev, ctrl, 0x00020000, 0x00020000);
199 nv_mask(dev, ctrl, 0x00000010, 0x00000010);
200 nv_mask(dev, ctrl, 0x00000008, 0x00000000);
201 nv_mask(dev, src1, 0x00000100, 0x00000000);
202 nv_mask(dev, src1, 0x00000001, 0x00000000);
204 nv_mask(dev, src1, 0x003f3141, 0x00000101 | reg->clk);
205 nv_mask(dev, ctrl, 0x00000018, 0x00000018);
207 nv_mask(dev, ctrl, 0x00000001, 0x00000000);
208 nv_mask(dev, src0, 0x00000100, 0x00000000);
209 nv_mask(dev, src0, 0x00000001, 0x00000000);
214 prog_clk(struct drm_device *dev, int clk, struct creg *reg)
217 NV_DEBUG(dev, "no clock for %02x\n", clk);
221 nv_mask(dev, 0x004120 + (clk * 4), 0x003f3141, 0x00000101 | reg->clk);
225 nva3_pm_clocks_get(struct drm_device *dev, struct nouveau_pm_level *perflvl)
227 perflvl->core = read_pll(dev, 0x00, 0x4200);
228 perflvl->shader = read_pll(dev, 0x01, 0x4220);
229 perflvl->memory = read_pll(dev, 0x02, 0x4000);
230 perflvl->unka0 = read_clk(dev, 0x20, false);
231 perflvl->vdec = read_clk(dev, 0x21, false);
232 perflvl->daemon = read_clk(dev, 0x25, false);
233 perflvl->copy = perflvl->core;
237 struct nva3_pm_state {
238 struct nouveau_pm_level *perflvl;
256 nva3_pm_clocks_pre(struct drm_device *dev, struct nouveau_pm_level *perflvl)
258 struct nva3_pm_state *info;
262 info = kzalloc(sizeof(*info), GFP_KERNEL);
264 return ERR_PTR(-ENOMEM);
266 ret = calc_clk(dev, 0x10, 0x4200, perflvl->core, &info->nclk);
270 ret = calc_clk(dev, 0x11, 0x4220, perflvl->shader, &info->sclk);
274 ret = calc_clk(dev, 0x12, 0x4000, perflvl->memory, &info->mclk);
278 ret = calc_clk(dev, 0x20, 0x0000, perflvl->unka0, &info->unka0);
282 ret = calc_clk(dev, 0x21, 0x0000, perflvl->vdec, &info->vdec);
286 info->rammap = nouveau_perf_rammap(dev, perflvl->memory,
289 &ramcfg_cnt, &info->ramcfg_len);
290 if (info->rammap_ver != 0x10 || info->rammap_len < 5)
293 info->ramcfg = nouveau_perf_ramcfg(dev, perflvl->memory,
296 if (info->rammap_ver != 0x10)
299 info->perflvl = perflvl;
309 nva3_pm_grcp_idle(void *data)
311 struct drm_device *dev = data;
313 if (!(nv_rd32(dev, 0x400304) & 0x00000001))
315 if (nv_rd32(dev, 0x400308) == 0x0050001c)
321 mclk_precharge(struct nouveau_mem_exec_func *exec)
323 nv_wr32(exec->dev, 0x1002d4, 0x00000001);
327 mclk_refresh(struct nouveau_mem_exec_func *exec)
329 nv_wr32(exec->dev, 0x1002d0, 0x00000001);
333 mclk_refresh_auto(struct nouveau_mem_exec_func *exec, bool enable)
335 nv_wr32(exec->dev, 0x100210, enable ? 0x80000000 : 0x00000000);
339 mclk_refresh_self(struct nouveau_mem_exec_func *exec, bool enable)
341 nv_wr32(exec->dev, 0x1002dc, enable ? 0x00000001 : 0x00000000);
345 mclk_wait(struct nouveau_mem_exec_func *exec, u32 nsec)
347 volatile u32 post = nv_rd32(exec->dev, 0); (void)post;
348 udelay((nsec + 500) / 1000);
352 mclk_mrg(struct nouveau_mem_exec_func *exec, int mr)
355 return nv_rd32(exec->dev, 0x1002c0 + ((mr - 0) * 4));
357 return nv_rd32(exec->dev, 0x1002e0 + ((mr - 2) * 4));
362 mclk_mrs(struct nouveau_mem_exec_func *exec, int mr, u32 data)
365 if (nvfb_vram_rank_B(exec->dev))
366 nv_wr32(exec->dev, 0x1002c8 + ((mr - 0) * 4), data);
367 nv_wr32(exec->dev, 0x1002c0 + ((mr - 0) * 4), data);
370 if (nvfb_vram_rank_B(exec->dev))
371 nv_wr32(exec->dev, 0x1002e8 + ((mr - 2) * 4), data);
372 nv_wr32(exec->dev, 0x1002e0 + ((mr - 2) * 4), data);
377 mclk_clock_set(struct nouveau_mem_exec_func *exec)
379 struct drm_device *dev = exec->dev;
380 struct nva3_pm_state *info = exec->priv;
383 ctrl = nv_rd32(dev, 0x004000);
384 if (!(ctrl & 0x00000008) && info->mclk.pll) {
385 nv_wr32(dev, 0x004000, (ctrl |= 0x00000008));
386 nv_mask(dev, 0x1110e0, 0x00088000, 0x00088000);
387 nv_wr32(dev, 0x004018, 0x00001000);
388 nv_wr32(dev, 0x004000, (ctrl &= ~0x00000001));
389 nv_wr32(dev, 0x004004, info->mclk.pll);
390 nv_wr32(dev, 0x004000, (ctrl |= 0x00000001));
392 nv_wr32(dev, 0x004018, 0x00005000 | info->r004018);
395 if (!info->mclk.pll) {
396 nv_mask(dev, 0x004168, 0x003f3040, info->mclk.clk);
397 nv_wr32(dev, 0x004000, (ctrl |= 0x00000008));
398 nv_mask(dev, 0x1110e0, 0x00088000, 0x00088000);
399 nv_wr32(dev, 0x004018, 0x0000d000 | info->r004018);
403 if (info->ramcfg && (info->rammap[4] & 0x08)) {
404 u32 unk5a0 = (ROM16(info->ramcfg[5]) << 8) |
406 u32 unk5a4 = ROM16(info->ramcfg[7]);
407 u32 unk804 = (info->ramcfg[9] & 0xf0) << 16 |
408 (info->ramcfg[3] & 0x0f) << 16 |
409 (info->ramcfg[9] & 0x0f) |
411 nv_wr32(dev, 0x1005a0, unk5a0);
412 nv_wr32(dev, 0x1005a4, unk5a4);
413 nv_wr32(dev, 0x10f804, unk804);
414 nv_mask(dev, 0x10053c, 0x00001000, 0x00000000);
416 nv_mask(dev, 0x10053c, 0x00001000, 0x00001000);
417 nv_mask(dev, 0x10f804, 0x80000000, 0x00000000);
418 nv_mask(dev, 0x100760, 0x22222222, info->r100760);
419 nv_mask(dev, 0x1007a0, 0x22222222, info->r100760);
420 nv_mask(dev, 0x1007e0, 0x22222222, info->r100760);
424 if (info->mclk.pll) {
425 nv_mask(dev, 0x1110e0, 0x00088000, 0x00011000);
426 nv_wr32(dev, 0x004000, (ctrl &= ~0x00000008));
431 mclk_timing_set(struct nouveau_mem_exec_func *exec)
433 struct drm_device *dev = exec->dev;
434 struct nva3_pm_state *info = exec->priv;
435 struct nouveau_pm_level *perflvl = info->perflvl;
438 for (i = 0; i < 9; i++)
439 nv_wr32(dev, 0x100220 + (i * 4), perflvl->timing.reg[i]);
442 u32 data = (info->ramcfg[2] & 0x08) ? 0x00000000 : 0x00001000;
443 nv_mask(dev, 0x100200, 0x00001000, data);
447 u32 unk714 = nv_rd32(dev, 0x100714) & ~0xf0000010;
448 u32 unk718 = nv_rd32(dev, 0x100718) & ~0x00000100;
449 u32 unk71c = nv_rd32(dev, 0x10071c) & ~0x00000100;
450 if ( (info->ramcfg[2] & 0x20))
451 unk714 |= 0xf0000000;
452 if (!(info->ramcfg[2] & 0x04))
453 unk714 |= 0x00000010;
454 nv_wr32(dev, 0x100714, unk714);
456 if (info->ramcfg[2] & 0x01)
457 unk71c |= 0x00000100;
458 nv_wr32(dev, 0x10071c, unk71c);
460 if (info->ramcfg[2] & 0x02)
461 unk718 |= 0x00000100;
462 nv_wr32(dev, 0x100718, unk718);
464 if (info->ramcfg[2] & 0x10)
465 nv_wr32(dev, 0x111100, 0x48000000); /*XXX*/
470 prog_mem(struct drm_device *dev, struct nva3_pm_state *info)
472 struct nouveau_mem_exec_func exec = {
474 .precharge = mclk_precharge,
475 .refresh = mclk_refresh,
476 .refresh_auto = mclk_refresh_auto,
477 .refresh_self = mclk_refresh_self,
481 .clock_set = mclk_clock_set,
482 .timing_set = mclk_timing_set,
487 /* XXX: where the fuck does 750MHz come from? */
488 if (info->perflvl->memory <= 750000) {
489 info->r004018 = 0x10000000;
490 info->r100760 = 0x22222222;
493 ctrl = nv_rd32(dev, 0x004000);
494 if (ctrl & 0x00000008) {
495 if (info->mclk.pll) {
496 nv_mask(dev, 0x004128, 0x00000101, 0x00000101);
497 nv_wr32(dev, 0x004004, info->mclk.pll);
498 nv_wr32(dev, 0x004000, (ctrl |= 0x00000001));
499 nv_wr32(dev, 0x004000, (ctrl &= 0xffffffef));
500 nv_wait(dev, 0x004000, 0x00020000, 0x00020000);
501 nv_wr32(dev, 0x004000, (ctrl |= 0x00000010));
502 nv_wr32(dev, 0x004018, 0x00005000 | info->r004018);
503 nv_wr32(dev, 0x004000, (ctrl |= 0x00000004));
506 u32 ssel = 0x00000101;
508 ssel |= info->mclk.clk;
510 ssel |= 0x00080000; /* 324MHz, shouldn't matter... */
511 nv_mask(dev, 0x004168, 0x003f3141, ctrl);
515 if (info->ramcfg[2] & 0x10) {
516 nv_mask(dev, 0x111104, 0x00000600, 0x00000000);
518 nv_mask(dev, 0x111100, 0x40000000, 0x40000000);
519 nv_mask(dev, 0x111104, 0x00000180, 0x00000000);
522 if (info->rammap && !(info->rammap[4] & 0x02))
523 nv_mask(dev, 0x100200, 0x00000800, 0x00000000);
524 nv_wr32(dev, 0x611200, 0x00003300);
525 if (!(info->ramcfg[2] & 0x10))
526 nv_wr32(dev, 0x111100, 0x4c020000); /*XXX*/
528 nouveau_mem_exec(&exec, info->perflvl);
530 nv_wr32(dev, 0x611200, 0x00003330);
531 if (info->rammap && (info->rammap[4] & 0x02))
532 nv_mask(dev, 0x100200, 0x00000800, 0x00000800);
534 if (info->ramcfg[2] & 0x10) {
535 nv_mask(dev, 0x111104, 0x00000180, 0x00000180);
536 nv_mask(dev, 0x111100, 0x40000000, 0x00000000);
538 nv_mask(dev, 0x111104, 0x00000600, 0x00000600);
542 if (info->mclk.pll) {
543 nv_mask(dev, 0x004168, 0x00000001, 0x00000000);
544 nv_mask(dev, 0x004168, 0x00000100, 0x00000000);
546 nv_mask(dev, 0x004000, 0x00000001, 0x00000000);
547 nv_mask(dev, 0x004128, 0x00000001, 0x00000000);
548 nv_mask(dev, 0x004128, 0x00000100, 0x00000000);
553 nva3_pm_clocks_set(struct drm_device *dev, void *pre_state)
555 struct drm_nouveau_private *dev_priv = dev->dev_private;
556 struct nva3_pm_state *info = pre_state;
560 /* prevent any new grctx switches from starting */
561 spin_lock_irqsave(&dev_priv->context_switch_lock, flags);
562 nv_wr32(dev, 0x400324, 0x00000000);
563 nv_wr32(dev, 0x400328, 0x0050001c); /* wait flag 0x1c */
564 /* wait for any pending grctx switches to complete */
565 if (!nv_wait_cb(dev, nva3_pm_grcp_idle, dev)) {
566 NV_ERROR(dev, "pm: ctxprog didn't go idle\n");
570 nv_mask(dev, 0x002504, 0x00000001, 0x00000001);
571 if (!nv_wait(dev, 0x002504, 0x00000010, 0x00000010)) {
572 NV_ERROR(dev, "pm: fifo didn't go idle\n");
576 prog_pll(dev, 0x00, 0x004200, &info->nclk);
577 prog_pll(dev, 0x01, 0x004220, &info->sclk);
578 prog_clk(dev, 0x20, &info->unka0);
579 prog_clk(dev, 0x21, &info->vdec);
581 if (info->mclk.clk || info->mclk.pll)
588 nv_mask(dev, 0x002504, 0x00000001, 0x00000000);
589 /* restore ctxprog to normal */
590 nv_wr32(dev, 0x400324, 0x00000000);
591 nv_wr32(dev, 0x400328, 0x0070009c); /* set flag 0x1c */
592 /* unblock it if necessary */
593 if (nv_rd32(dev, 0x400308) == 0x0050001c)
594 nv_mask(dev, 0x400824, 0x10000000, 0x10000000);
595 spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags);