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15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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26 #include "nouveau_drv.h"
27 #include "nouveau_bios.h"
28 #include "nouveau_pm.h"
30 static u32 read_clk(struct drm_device *, int, bool);
31 static u32 read_pll(struct drm_device *, u32, int);
34 read_vco(struct drm_device *dev, int clk)
36 u32 sctl = nv_rd32(dev, 0x4120 + (clk * 4));
37 if ((sctl & 0x00000030) != 0x00000030)
38 return read_pll(dev, 0x00e820, 0x41);
39 return read_pll(dev, 0x00e8a0, 0x42);
43 read_clk(struct drm_device *dev, int clk, bool ignore_en)
50 sctl = nv_rd32(dev, 0x4120 + (clk * 4));
51 if (!ignore_en && !(sctl & 0x00000100))
54 switch (sctl & 0x00003000) {
58 if (sctl & 0x00000040)
62 sclk = read_vco(dev, clk);
63 sdiv = ((sctl & 0x003f0000) >> 16) + 2;
64 return (sclk * 2) / sdiv;
71 read_pll(struct drm_device *dev, u32 pll, int clk)
73 u32 ctrl = nv_rd32(dev, pll + 0);
74 u32 sclk, P = 1, N = 1, M = 1;
76 if (!(ctrl & 0x00000008)) {
77 u32 coef = nv_rd32(dev, pll + 4);
78 M = (coef & 0x000000ff) >> 0;
79 N = (coef & 0x0000ff00) >> 8;
80 P = (coef & 0x003f0000) >> 16;
81 if ((pll & 0x00ff00) == 0x00e800)
84 sclk = read_clk(dev, 0x00 + clk, false);
86 sclk = read_clk(dev, 0x10 + clk, false);
89 return sclk * N / (M * P);
98 calc_clk(struct drm_device *dev, u32 pll, int clk, u32 khz, struct creg *reg)
100 struct pll_lims limits;
101 u32 oclk, sclk, sdiv;
110 reg->clk = 0x00000100;
113 reg->clk = 0x00002100;
116 reg->clk = 0x00002140;
119 sclk = read_vco(dev, clk);
120 sdiv = min((sclk * 2) / (khz - 2999), (u32)65);
122 oclk = (sclk * 2) / sdiv;
124 if (!pll || (diff >= -2000 && diff < 3000)) {
125 reg->clk = (((sdiv - 2) << 16) | 0x00003100);
132 ret = get_pll_limits(dev, pll, &limits);
136 limits.refclk = read_clk(dev, clk - 0x10, true);
140 ret = nva3_calc_pll(dev, &limits, khz, &N, NULL, &M, &P);
142 reg->clk = nv_rd32(dev, 0x4120 + (clk * 4));
143 reg->pll = (P << 16) | (N << 8) | M;
149 nva3_pm_clocks_get(struct drm_device *dev, struct nouveau_pm_level *perflvl)
151 perflvl->core = read_pll(dev, 0x4200, 0);
152 perflvl->shader = read_pll(dev, 0x4220, 1);
153 perflvl->memory = read_pll(dev, 0x4000, 2);
154 perflvl->unka0 = read_clk(dev, 0x20, false);
155 perflvl->vdec = read_clk(dev, 0x21, false);
159 struct nva3_pm_state {
168 nva3_pm_clocks_pre(struct drm_device *dev, struct nouveau_pm_level *perflvl)
170 struct nva3_pm_state *info;
173 info = kzalloc(sizeof(*info), GFP_KERNEL);
175 return ERR_PTR(-ENOMEM);
177 ret = calc_clk(dev, 0x4200, 0x10, perflvl->core, &info->nclk);
181 ret = calc_clk(dev, 0x4220, 0x11, perflvl->shader, &info->sclk);
185 ret = calc_clk(dev, 0x4000, 0x12, perflvl->memory, &info->mclk);
189 ret = calc_clk(dev, 0x0000, 0x20, perflvl->unka0, &info->unka0);
193 ret = calc_clk(dev, 0x0000, 0x21, perflvl->vdec, &info->vdec);
206 prog_pll(struct drm_device *dev, u32 pll, int clk, struct creg *reg)
208 const u32 src0 = 0x004120 + (clk * 4);
209 const u32 src1 = 0x004160 + (clk * 4);
210 const u32 ctrl = pll + 0;
211 const u32 coef = pll + 4;
214 cntl = nv_rd32(dev, ctrl) & 0xfffffff2;
216 nv_mask(dev, src0, 0x00000101, 0x00000101);
217 nv_wr32(dev, coef, reg->pll);
218 nv_wr32(dev, ctrl, cntl | 0x00000015);
219 nv_mask(dev, src1, 0x00000100, 0x00000000);
220 nv_mask(dev, src1, 0x00000001, 0x00000000);
222 nv_mask(dev, src1, 0x003f3141, 0x00000101 | reg->clk);
223 nv_wr32(dev, ctrl, cntl | 0x0000001d);
224 nv_mask(dev, ctrl, 0x00000001, 0x00000000);
225 nv_mask(dev, src0, 0x00000100, 0x00000000);
226 nv_mask(dev, src0, 0x00000001, 0x00000000);
231 prog_clk(struct drm_device *dev, int clk, struct creg *reg)
233 nv_mask(dev, 0x004120 + (clk * 4), 0x003f3141, 0x00000101 | reg->clk);
237 nva3_pm_clocks_set(struct drm_device *dev, void *pre_state)
239 struct nva3_pm_state *info = pre_state;
241 prog_pll(dev, 0x004200, 0, &info->nclk);
242 prog_pll(dev, 0x004220, 1, &info->sclk);
243 prog_clk(dev, 0x20, &info->unka0);
244 prog_clk(dev, 0x21, &info->vdec);
246 nv_wr32(dev, 0x100210, 0);
247 nv_wr32(dev, 0x1002dc, 1);
248 nv_wr32(dev, 0x004018, 0x00001000);
249 prog_pll(dev, 0x004000, 2, &info->mclk);
250 if (nv_rd32(dev, 0x4000) & 0x00000008)
251 nv_wr32(dev, 0x004018, 0x1000d000);
253 nv_wr32(dev, 0x004018, 0x10005000);
254 nv_wr32(dev, 0x1002dc, 0);
255 nv_wr32(dev, 0x100210, 0x80000000);