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26 #include "nouveau_drv.h"
27 #include "nouveau_bios.h"
28 #include "nouveau_pm.h"
30 /*XXX: boards using limits 0x40 need fixing, the register layout
31 * is correct here, but, there's some other funny magic
32 * that modifies things, so it's not likely we'll set/read
33 * the correct timings yet.. working on it...
36 struct nva3_pm_state {
42 nva3_pm_clock_get(struct drm_device *dev, u32 id)
48 ret = get_pll_limits(dev, id, &pll);
52 reg = nv_rd32(dev, pll.reg + 4);
53 P = (reg & 0x003f0000) >> 16;
54 N = (reg & 0x0000ff00) >> 8;
55 M = (reg & 0x000000ff);
56 return pll.refclk * N / M / P;
60 nva3_pm_clock_pre(struct drm_device *dev, struct nouveau_pm_level *perflvl,
63 struct nva3_pm_state *state;
66 state = kzalloc(sizeof(*state), GFP_KERNEL);
68 return ERR_PTR(-ENOMEM);
70 ret = get_pll_limits(dev, id, &state->pll);
73 return (ret == -ENOENT) ? NULL : ERR_PTR(ret);
76 ret = nv50_calc_pll2(dev, &state->pll, khz, &state->N, &dummy,
77 &state->M, &state->P);
87 nva3_pm_clock_set(struct drm_device *dev, void *pre_state)
89 struct nva3_pm_state *state = pre_state;
90 u32 reg = state->pll.reg;
92 nv_wr32(dev, reg + 4, (state->P << 16) | (state->N << 8) | state->M);