drivers/gpu/drm/nouveau/nvc0_fence.c

   1 /*
   2  * Copyright 2012 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24
  25 #include "drmP.h"
  26 #include "nouveau_drv.h"
  27 #include "nouveau_dma.h"
  28 #include <engine/fifo.h>
  29 #include <core/ramht.h>
  30 #include "nouveau_fence.h"
  31 #include "nv50_display.h"
  32
  33 struct nvc0_fence_priv {
  34         struct nouveau_fence_priv base;
  35         struct nouveau_bo *bo;
  36         u32 *suspend;
  37 };
  38
  39 struct nvc0_fence_chan {
  40         struct nouveau_fence_chan base;
  41         struct nouveau_vma vma;
  42         struct nouveau_vma dispc_vma[4];
  43 };
  44
  45 u64
  46 nvc0_fence_crtc(struct nouveau_channel *chan, int crtc)
  47 {
  48         struct nvc0_fence_chan *fctx = chan->fence;
  49         return fctx->dispc_vma[crtc].offset;
  50 }
  51
  52 static int
  53 nvc0_fence_emit(struct nouveau_fence *fence)
  54 {
  55         struct nouveau_channel *chan = fence->channel;
  56         struct nvc0_fence_chan *fctx = chan->fence;
  57         u64 addr = fctx->vma.offset + chan->id * 16;
  58         int ret;
  59
  60         ret = RING_SPACE(chan, 5);
  61         if (ret == 0) {
  62                 BEGIN_NVC0(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4);
  63                 OUT_RING  (chan, upper_32_bits(addr));
  64                 OUT_RING  (chan, lower_32_bits(addr));
  65                 OUT_RING  (chan, fence->sequence);
  66                 OUT_RING  (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_WRITE_LONG);
  67                 FIRE_RING (chan);
  68         }
  69
  70         return ret;
  71 }
  72
  73 static int
  74 nvc0_fence_sync(struct nouveau_fence *fence,
  75                 struct nouveau_channel *prev, struct nouveau_channel *chan)
  76 {
  77         struct nvc0_fence_chan *fctx = chan->fence;
  78         u64 addr = fctx->vma.offset + prev->id * 16;
  79         int ret;
  80
  81         ret = RING_SPACE(chan, 5);
  82         if (ret == 0) {
  83                 BEGIN_NVC0(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4);
  84                 OUT_RING  (chan, upper_32_bits(addr));
  85                 OUT_RING  (chan, lower_32_bits(addr));
  86                 OUT_RING  (chan, fence->sequence);
  87                 OUT_RING  (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_GEQUAL |
  88                                  NVC0_SUBCHAN_SEMAPHORE_TRIGGER_YIELD);
  89                 FIRE_RING (chan);
  90         }
  91
  92         return ret;
  93 }
  94
  95 static u32
  96 nvc0_fence_read(struct nouveau_channel *chan)
  97 {
  98         struct drm_nouveau_private *dev_priv = chan->dev->dev_private;
  99         struct nvc0_fence_priv *priv = dev_priv->fence.func;
 100         return nouveau_bo_rd32(priv->bo, chan->id * 16/4);
 101 }
 102
 103 static void
 104 nvc0_fence_context_del(struct nouveau_channel *chan)
 105 {
 106         struct drm_device *dev = chan->dev;
 107         struct drm_nouveau_private *dev_priv = dev->dev_private;
 108         struct nvc0_fence_priv *priv = dev_priv->fence.func;
 109         struct nvc0_fence_chan *fctx = chan->fence;
 110         int i;
 111
 112         if (dev_priv->card_type >= NV_D0) {
 113                 for (i = 0; i < dev->mode_config.num_crtc; i++) {
 114                         struct nouveau_bo *bo = nvd0_display_crtc_sema(dev, i);
 115                         nouveau_bo_vma_del(bo, &fctx->dispc_vma[i]);
 116                 }
 117         } else
 118         if (dev_priv->card_type >= NV_50) {
 119                 struct nv50_display *disp = nv50_display(dev);
 120                 for (i = 0; i < dev->mode_config.num_crtc; i++) {
 121                         struct nv50_display_crtc *dispc = &disp->crtc[i];
 122                         nouveau_bo_vma_del(dispc->sem.bo, &fctx->dispc_vma[i]);
 123                 }
 124         }
 125
 126         nouveau_bo_vma_del(priv->bo, &fctx->vma);
 127         nouveau_fence_context_del(&fctx->base);
 128         chan->fence = NULL;
 129         kfree(fctx);
 130 }
 131
 132 static int
 133 nvc0_fence_context_new(struct nouveau_channel *chan)
 134 {
 135         struct drm_device *dev = chan->dev;
 136         struct drm_nouveau_private *dev_priv = dev->dev_private;
 137         struct nvc0_fence_priv *priv = dev_priv->fence.func;
 138         struct nvc0_fence_chan *fctx;
 139         int ret, i;
 140
 141         fctx = chan->fence = kzalloc(sizeof(*fctx), GFP_KERNEL);
 142         if (!fctx)
 143                 return -ENOMEM;
 144
 145         nouveau_fence_context_new(&fctx->base);
 146
 147         ret = nouveau_bo_vma_add(priv->bo, chan->vm, &fctx->vma);
 148         if (ret)
 149                 nvc0_fence_context_del(chan);
 150
 151         /* map display semaphore buffers into channel's vm */
 152         for (i = 0; !ret && i < dev->mode_config.num_crtc; i++) {
 153                 struct nouveau_bo *bo;
 154                 if (dev_priv->card_type >= NV_D0)
 155                         bo = nvd0_display_crtc_sema(dev, i);
 156                 else
 157                         bo = nv50_display(dev)->crtc[i].sem.bo;
 158
 159                 ret = nouveau_bo_vma_add(bo, chan->vm, &fctx->dispc_vma[i]);
 160         }
 161
 162         nouveau_bo_wr32(priv->bo, chan->id * 16/4, 0x00000000);
 163         return ret;
 164 }
 165
 166 static bool
 167 nvc0_fence_suspend(struct drm_device *dev)
 168 {
 169         struct nouveau_fifo_priv *pfifo = nv_engine(dev, NVOBJ_ENGINE_FIFO);
 170         struct drm_nouveau_private *dev_priv = dev->dev_private;
 171         struct nvc0_fence_priv *priv = dev_priv->fence.func;
 172         int i;
 173
 174         priv->suspend = vmalloc(pfifo->channels * sizeof(u32));
 175         if (priv->suspend) {
 176                 for (i = 0; i < pfifo->channels; i++)
 177                         priv->suspend[i] = nouveau_bo_rd32(priv->bo, i);
 178         }
 179
 180         return priv->suspend != NULL;
 181 }
 182
 183 static void
 184 nvc0_fence_resume(struct drm_device *dev)
 185 {
 186         struct nouveau_fifo_priv *pfifo = nv_engine(dev, NVOBJ_ENGINE_FIFO);
 187         struct drm_nouveau_private *dev_priv = dev->dev_private;
 188         struct nvc0_fence_priv *priv = dev_priv->fence.func;
 189         int i;
 190
 191         if (priv->suspend) {
 192                 for (i = 0; i < pfifo->channels; i++)
 193                         nouveau_bo_wr32(priv->bo, i, priv->suspend[i]);
 194                 vfree(priv->suspend);
 195                 priv->suspend = NULL;
 196         }
 197 }
 198
 199 static void
 200 nvc0_fence_destroy(struct drm_device *dev)
 201 {
 202         struct drm_nouveau_private *dev_priv = dev->dev_private;
 203         struct nvc0_fence_priv *priv = dev_priv->fence.func;
 204
 205         nouveau_bo_unmap(priv->bo);
 206         nouveau_bo_ref(NULL, &priv->bo);
 207         dev_priv->fence.func = NULL;
 208         kfree(priv);
 209 }
 210
 211 int
 212 nvc0_fence_create(struct drm_device *dev)
 213 {
 214         struct nouveau_fifo_priv *pfifo = nv_engine(dev, NVOBJ_ENGINE_FIFO);
 215         struct drm_nouveau_private *dev_priv = dev->dev_private;
 216         struct nvc0_fence_priv *priv;
 217         int ret;
 218
 219         priv = kzalloc(sizeof(*priv), GFP_KERNEL);
 220         if (!priv)
 221                 return -ENOMEM;
 222
 223         priv->base.dtor = nvc0_fence_destroy;
 224         priv->base.suspend = nvc0_fence_suspend;
 225         priv->base.resume = nvc0_fence_resume;
 226         priv->base.context_new = nvc0_fence_context_new;
 227         priv->base.context_del = nvc0_fence_context_del;
 228         priv->base.emit = nvc0_fence_emit;
 229         priv->base.sync = nvc0_fence_sync;
 230         priv->base.read = nvc0_fence_read;
 231         dev_priv->fence.func = priv;
 232
 233         ret = nouveau_bo_new(dev, 16 * pfifo->channels, 0, TTM_PL_FLAG_VRAM,
 234                              0, 0, NULL, &priv->bo);
 235         if (ret == 0) {
 236                 ret = nouveau_bo_pin(priv->bo, TTM_PL_FLAG_VRAM);
 237                 if (ret == 0)
 238                         ret = nouveau_bo_map(priv->bo);
 239                 if (ret)
 240                         nouveau_bo_ref(NULL, &priv->bo);
 241         }
 242
 243         if (ret)
 244                 nvc0_fence_destroy(dev);
 245         return ret;
 246 }