2 * Copyright 2010 Red Hat Inc.
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5 * copy of this software and associated documentation files (the "Software"),
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9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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27 #include "nouveau_drv.h"
30 nvc0_instmem_populate(struct drm_device *dev, struct nouveau_gpuobj *gpuobj,
35 *size = ALIGN(*size, 4096);
39 ret = nouveau_bo_new(dev, NULL, *size, 0, TTM_PL_FLAG_VRAM, 0, 0x0000,
40 true, false, &gpuobj->im_backing);
42 NV_ERROR(dev, "error getting PRAMIN backing pages: %d\n", ret);
46 ret = nouveau_bo_pin(gpuobj->im_backing, TTM_PL_FLAG_VRAM);
48 NV_ERROR(dev, "error pinning PRAMIN backing VRAM: %d\n", ret);
49 nouveau_bo_ref(NULL, &gpuobj->im_backing);
53 gpuobj->im_backing_start = gpuobj->im_backing->bo.mem.mm_node->start;
54 gpuobj->im_backing_start <<= PAGE_SHIFT;
59 nvc0_instmem_clear(struct drm_device *dev, struct nouveau_gpuobj *gpuobj)
61 struct drm_nouveau_private *dev_priv = dev->dev_private;
63 if (gpuobj && gpuobj->im_backing) {
65 dev_priv->engine.instmem.unbind(dev, gpuobj);
66 nouveau_bo_unpin(gpuobj->im_backing);
67 nouveau_bo_ref(NULL, &gpuobj->im_backing);
68 gpuobj->im_backing = NULL;
73 nvc0_instmem_bind(struct drm_device *dev, struct nouveau_gpuobj *gpuobj)
75 struct drm_nouveau_private *dev_priv = dev->dev_private;
76 uint32_t pte, pte_end;
79 if (!gpuobj->im_backing || !gpuobj->im_pramin || gpuobj->im_bound)
82 NV_DEBUG(dev, "st=0x%lx sz=0x%lx\n",
83 gpuobj->im_pramin->start, gpuobj->im_pramin->size);
85 pte = gpuobj->im_pramin->start >> 12;
86 pte_end = (gpuobj->im_pramin->size >> 12) + pte;
87 vram = gpuobj->im_backing_start;
89 NV_DEBUG(dev, "pramin=0x%lx, pte=%d, pte_end=%d\n",
90 gpuobj->im_pramin->start, pte, pte_end);
91 NV_DEBUG(dev, "first vram page: 0x%08x\n", gpuobj->im_backing_start);
93 while (pte < pte_end) {
94 nv_wr32(dev, 0x702000 + (pte * 8), (vram >> 8) | 1);
95 nv_wr32(dev, 0x702004 + (pte * 8), 0);
99 dev_priv->engine.instmem.flush(dev);
102 u32 chan = nv_rd32(dev, 0x1700) << 16;
103 nv_wr32(dev, 0x100cb8, (chan + 0x1000) >> 8);
104 nv_wr32(dev, 0x100cbc, 0x80000005);
107 gpuobj->im_bound = 1;
112 nvc0_instmem_unbind(struct drm_device *dev, struct nouveau_gpuobj *gpuobj)
114 struct drm_nouveau_private *dev_priv = dev->dev_private;
115 uint32_t pte, pte_end;
117 if (gpuobj->im_bound == 0)
120 pte = gpuobj->im_pramin->start >> 12;
121 pte_end = (gpuobj->im_pramin->size >> 12) + pte;
122 while (pte < pte_end) {
123 nv_wr32(dev, 0x702000 + (pte * 8), 0);
124 nv_wr32(dev, 0x702004 + (pte * 8), 0);
127 dev_priv->engine.instmem.flush(dev);
129 gpuobj->im_bound = 0;
134 nvc0_instmem_flush(struct drm_device *dev)
136 nv_wr32(dev, 0x070000, 1);
137 if (!nv_wait(0x070000, 0x00000002, 0x00000000))
138 NV_ERROR(dev, "PRAMIN flush timeout\n");
142 nvc0_instmem_suspend(struct drm_device *dev)
144 struct drm_nouveau_private *dev_priv = dev->dev_private;
148 dev_priv->susres.ramin_copy = vmalloc(65536);
149 if (!dev_priv->susres.ramin_copy)
151 buf = dev_priv->susres.ramin_copy;
153 for (i = 0; i < 65536; i += 4)
154 buf[i/4] = nv_rd32(dev, NV04_PRAMIN + i);
159 nvc0_instmem_resume(struct drm_device *dev)
161 struct drm_nouveau_private *dev_priv = dev->dev_private;
162 u32 *buf = dev_priv->susres.ramin_copy;
166 chan = dev_priv->vram_size - dev_priv->ramin_rsvd_vram;
167 nv_wr32(dev, 0x001700, chan >> 16);
169 for (i = 0; i < 65536; i += 4)
170 nv_wr32(dev, NV04_PRAMIN + i, buf[i/4]);
171 vfree(dev_priv->susres.ramin_copy);
172 dev_priv->susres.ramin_copy = NULL;
174 nv_wr32(dev, 0x001714, 0xc0000000 | (chan >> 12));
178 nvc0_instmem_init(struct drm_device *dev)
180 struct drm_nouveau_private *dev_priv = dev->dev_private;
181 u64 chan, pgt3, imem, lim3 = dev_priv->ramin_size - 1;
184 dev_priv->ramin_rsvd_vram = 1 * 1024 * 1024;
185 chan = dev_priv->vram_size - dev_priv->ramin_rsvd_vram;
186 imem = 4096 + 4096 + 32768;
188 nv_wr32(dev, 0x001700, chan >> 16);
191 nv_wr32(dev, 0x700200, lower_32_bits(chan + 0x1000));
192 nv_wr32(dev, 0x700204, upper_32_bits(chan + 0x1000));
193 nv_wr32(dev, 0x700208, lower_32_bits(lim3));
194 nv_wr32(dev, 0x70020c, upper_32_bits(lim3));
196 /* point pgd -> pgt */
197 nv_wr32(dev, 0x701000, 0);
198 nv_wr32(dev, 0x701004, ((chan + 0x2000) >> 8) | 1);
200 /* point pgt -> physical vram for channel */
202 for (i = 0; i < dev_priv->ramin_rsvd_vram; i += 4096, pgt3 += 8) {
203 nv_wr32(dev, 0x700000 + pgt3, ((chan + i) >> 8) | 1);
204 nv_wr32(dev, 0x700004 + pgt3, 0);
207 /* clear rest of pgt */
208 for (; i < dev_priv->ramin_size; i += 4096, pgt3 += 8) {
209 nv_wr32(dev, 0x700000 + pgt3, 0);
210 nv_wr32(dev, 0x700004 + pgt3, 0);
213 /* point bar3 at the channel */
214 nv_wr32(dev, 0x001714, 0xc0000000 | (chan >> 12));
216 /* Global PRAMIN heap */
217 ret = drm_mm_init(&dev_priv->ramin_heap, imem,
218 dev_priv->ramin_size - imem);
220 NV_ERROR(dev, "Failed to init RAMIN heap\n");
224 /*XXX: incorrect, but needed to make hash func "work" */
225 dev_priv->ramht_offset = 0x10000;
226 dev_priv->ramht_bits = 9;
227 dev_priv->ramht_size = (1 << dev_priv->ramht_bits) * 8;
232 nvc0_instmem_takedown(struct drm_device *dev)