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15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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26 #include "nouveau_drv.h"
27 #include <nouveau_bios.h>
28 #include "nouveau_pm.h"
30 static u32 read_div(struct drm_device *, int, u32, u32);
31 static u32 read_pll(struct drm_device *, u32);
34 read_vco(struct drm_device *dev, u32 dsrc)
36 u32 ssrc = nv_rd32(dev, dsrc);
37 if (!(ssrc & 0x00000100))
38 return read_pll(dev, 0x00e800);
39 return read_pll(dev, 0x00e820);
43 read_pll(struct drm_device *dev, u32 pll)
45 u32 ctrl = nv_rd32(dev, pll + 0);
46 u32 coef = nv_rd32(dev, pll + 4);
47 u32 P = (coef & 0x003f0000) >> 16;
48 u32 N = (coef & 0x0000ff00) >> 8;
49 u32 M = (coef & 0x000000ff) >> 0;
52 if (!(ctrl & 0x00000001))
55 switch (pll & 0xfff000) {
61 doff = (pll - 0x137000) / 0x20;
62 sclk = read_div(dev, doff, 0x137120, 0x137140);
67 sclk = read_pll(dev, 0x132020);
70 sclk = read_div(dev, 0, 0x137320, 0x137330);
80 return sclk * N / M / P;
84 read_div(struct drm_device *dev, int doff, u32 dsrc, u32 dctl)
86 u32 ssrc = nv_rd32(dev, dsrc + (doff * 4));
87 u32 sctl = nv_rd32(dev, dctl + (doff * 4));
89 switch (ssrc & 0x00000003) {
91 if ((ssrc & 0x00030000) != 0x00030000)
97 if (sctl & 0x80000000) {
98 u32 sclk = read_vco(dev, dsrc + (doff * 4));
99 u32 sdiv = (sctl & 0x0000003f) + 2;
100 return (sclk * 2) / sdiv;
103 return read_vco(dev, dsrc + (doff * 4));
110 read_mem(struct drm_device *dev)
112 u32 ssel = nv_rd32(dev, 0x1373f0);
113 if (ssel & 0x00000001)
114 return read_div(dev, 0, 0x137300, 0x137310);
115 return read_pll(dev, 0x132000);
119 read_clk(struct drm_device *dev, int clk)
121 u32 sctl = nv_rd32(dev, 0x137250 + (clk * 4));
122 u32 ssel = nv_rd32(dev, 0x137100);
125 if (ssel & (1 << clk)) {
127 sclk = read_pll(dev, 0x137000 + (clk * 0x20));
129 sclk = read_pll(dev, 0x1370e0);
130 sdiv = ((sctl & 0x00003f00) >> 8) + 2;
132 sclk = read_div(dev, clk, 0x137160, 0x1371d0);
133 sdiv = ((sctl & 0x0000003f) >> 0) + 2;
136 if (sctl & 0x80000000)
137 return (sclk * 2) / sdiv;
142 nvc0_pm_clocks_get(struct drm_device *dev, struct nouveau_pm_level *perflvl)
144 perflvl->shader = read_clk(dev, 0x00);
145 perflvl->core = perflvl->shader / 2;
146 perflvl->memory = read_mem(dev);
147 perflvl->rop = read_clk(dev, 0x01);
148 perflvl->hub07 = read_clk(dev, 0x02);
149 perflvl->hub06 = read_clk(dev, 0x07);
150 perflvl->hub01 = read_clk(dev, 0x08);
151 perflvl->copy = read_clk(dev, 0x09);
152 perflvl->daemon = read_clk(dev, 0x0c);
153 perflvl->vdec = read_clk(dev, 0x0e);
157 struct nvc0_pm_clock {
166 struct nvc0_pm_state {
167 struct nouveau_pm_level *perflvl;
168 struct nvc0_pm_clock eng[16];
169 struct nvc0_pm_clock mem;
173 calc_div(struct drm_device *dev, int clk, u32 ref, u32 freq, u32 *ddiv)
175 u32 div = min((ref * 2) / freq, (u32)65);
180 return (ref * 2) / div;
184 calc_src(struct drm_device *dev, int clk, u32 freq, u32 *dsrc, u32 *ddiv)
188 /* use one of the fixed frequencies if possible */
205 /* otherwise, calculate the closest divider */
206 sclk = read_vco(dev, clk);
208 sclk = calc_div(dev, clk, sclk, freq, ddiv);
213 calc_pll(struct drm_device *dev, int clk, u32 freq, u32 *coef)
215 struct nvbios_pll limits;
218 ret = get_pll_limits(dev, 0x137000 + (clk * 0x20), &limits);
222 limits.refclk = read_div(dev, clk, 0x137120, 0x137140);
226 ret = nva3_calc_pll(dev, &limits, freq, &N, NULL, &M, &P);
230 *coef = (P << 16) | (N << 8) | M;
234 /* A (likely rather simplified and incomplete) view of the clock tree
245 * 137250(D) ---- 137100(F0) ---- 137160(S)/1371d0(D) ------------------- ref
246 * (F1) ---- 1370X0(P) ---- 137120(S)/137140(D) ---- ref
248 * Not all registers exist for all clocks. For example: clocks >= 8 don't
249 * have their own PLL (all tied to clock 7's PLL when in PLL mode), nor do
250 * they have the divider at 1371d0, though the source selection at 137160
251 * still exists. You must use the divider at 137250 for these instead.
255 * TBD, read_mem() above is likely very wrong...
260 calc_clk(struct drm_device *dev, int clk, struct nvc0_pm_clock *info, u32 freq)
262 u32 src0, div0, div1D, div1P = 0;
265 /* invalid clock domain */
269 /* first possible path, using only dividers */
270 clk0 = calc_src(dev, clk, freq, &src0, &div0);
271 clk0 = calc_div(dev, clk, clk0, freq, &div1D);
273 /* see if we can get any closer using PLLs */
274 if (clk0 != freq && (0x00004387 & (1 << clk))) {
276 clk1 = calc_pll(dev, clk, freq, &info->coef);
278 clk1 = read_pll(dev, 0x1370e0);
279 clk1 = calc_div(dev, clk, clk1, freq, &div1P);
282 /* select the method which gets closest to target freq */
283 if (abs((int)freq - clk0) <= abs((int)freq - clk1)) {
286 info->ddiv |= 0x80000000;
287 info->ddiv |= div0 << 8;
291 info->mdiv |= 0x80000000;
298 info->mdiv |= 0x80000000;
299 info->mdiv |= div1P << 8;
301 info->ssel = (1 << clk);
309 calc_mem(struct drm_device *dev, struct nvc0_pm_clock *info, u32 freq)
311 struct nvbios_pll pll;
315 /* mclk pll input freq comes from another pll, make sure it's on */
316 ctrl = nv_rd32(dev, 0x132020);
317 if (!(ctrl & 0x00000001)) {
318 /* if not, program it to 567MHz. nfi where this value comes
319 * from - it looks like it's in the pll limits table for
320 * 132000 but the binary driver ignores all my attempts to
323 nv_wr32(dev, 0x137320, 0x00000103);
324 nv_wr32(dev, 0x137330, 0x81200606);
325 nv_wait(dev, 0x132020, 0x00010000, 0x00010000);
326 nv_wr32(dev, 0x132024, 0x0001150f);
327 nv_mask(dev, 0x132020, 0x00000001, 0x00000001);
328 nv_wait(dev, 0x137390, 0x00020000, 0x00020000);
329 nv_mask(dev, 0x132020, 0x00000004, 0x00000004);
332 /* for the moment, until the clock tree is better understood, use
333 * pll mode for all clock frequencies
335 ret = get_pll_limits(dev, 0x132000, &pll);
337 pll.refclk = read_pll(dev, 0x132020);
339 ret = nva3_calc_pll(dev, &pll, freq, &N, NULL, &M, &P);
341 info->coef = (P << 16) | (N << 8) | M;
351 nvc0_pm_clocks_pre(struct drm_device *dev, struct nouveau_pm_level *perflvl)
353 struct drm_nouveau_private *dev_priv = dev->dev_private;
354 struct nvc0_pm_state *info;
357 info = kzalloc(sizeof(*info), GFP_KERNEL);
359 return ERR_PTR(-ENOMEM);
361 /* NFI why this is still in the performance table, the ROPCs appear
362 * to get their clock from clock 2 ("hub07", actually hub05 on this
363 * chip, but, anyway...) as well. nvatiming confirms hub05 and ROP
364 * are always the same freq with the binary driver even when the
365 * performance table says they should differ.
367 if (dev_priv->chipset == 0xd9)
370 if ((ret = calc_clk(dev, 0x00, &info->eng[0x00], perflvl->shader)) ||
371 (ret = calc_clk(dev, 0x01, &info->eng[0x01], perflvl->rop)) ||
372 (ret = calc_clk(dev, 0x02, &info->eng[0x02], perflvl->hub07)) ||
373 (ret = calc_clk(dev, 0x07, &info->eng[0x07], perflvl->hub06)) ||
374 (ret = calc_clk(dev, 0x08, &info->eng[0x08], perflvl->hub01)) ||
375 (ret = calc_clk(dev, 0x09, &info->eng[0x09], perflvl->copy)) ||
376 (ret = calc_clk(dev, 0x0c, &info->eng[0x0c], perflvl->daemon)) ||
377 (ret = calc_clk(dev, 0x0e, &info->eng[0x0e], perflvl->vdec))) {
382 if (perflvl->memory) {
383 ret = calc_mem(dev, &info->mem, perflvl->memory);
390 info->perflvl = perflvl;
395 prog_clk(struct drm_device *dev, int clk, struct nvc0_pm_clock *info)
397 /* program dividers at 137160/1371d0 first */
398 if (clk < 7 && !info->ssel) {
399 nv_mask(dev, 0x1371d0 + (clk * 0x04), 0x80003f3f, info->ddiv);
400 nv_wr32(dev, 0x137160 + (clk * 0x04), info->dsrc);
403 /* switch clock to non-pll mode */
404 nv_mask(dev, 0x137100, (1 << clk), 0x00000000);
405 nv_wait(dev, 0x137100, (1 << clk), 0x00000000);
409 /* make sure it's disabled first... */
410 u32 base = 0x137000 + (clk * 0x20);
411 u32 ctrl = nv_rd32(dev, base + 0x00);
412 if (ctrl & 0x00000001) {
413 nv_mask(dev, base + 0x00, 0x00000004, 0x00000000);
414 nv_mask(dev, base + 0x00, 0x00000001, 0x00000000);
416 /* program it to new values, if necessary */
418 nv_wr32(dev, base + 0x04, info->coef);
419 nv_mask(dev, base + 0x00, 0x00000001, 0x00000001);
420 nv_wait(dev, base + 0x00, 0x00020000, 0x00020000);
421 nv_mask(dev, base + 0x00, 0x00020004, 0x00000004);
425 /* select pll/non-pll mode, and program final clock divider */
426 nv_mask(dev, 0x137100, (1 << clk), info->ssel);
427 nv_wait(dev, 0x137100, (1 << clk), info->ssel);
428 nv_mask(dev, 0x137250 + (clk * 0x04), 0x00003f3f, info->mdiv);
432 mclk_precharge(struct nouveau_mem_exec_func *exec)
437 mclk_refresh(struct nouveau_mem_exec_func *exec)
442 mclk_refresh_auto(struct nouveau_mem_exec_func *exec, bool enable)
444 nv_wr32(exec->dev, 0x10f210, enable ? 0x80000000 : 0x00000000);
448 mclk_refresh_self(struct nouveau_mem_exec_func *exec, bool enable)
453 mclk_wait(struct nouveau_mem_exec_func *exec, u32 nsec)
455 udelay((nsec + 500) / 1000);
459 mclk_mrg(struct nouveau_mem_exec_func *exec, int mr)
461 struct drm_device *dev = exec->dev;
462 if (nvfb_vram_type(dev) != NV_MEM_TYPE_GDDR5) {
464 return nv_rd32(dev, 0x10f300 + ((mr - 0) * 4));
465 return nv_rd32(dev, 0x10f320 + ((mr - 2) * 4));
468 return nv_rd32(dev, 0x10f300 + (mr * 4));
471 return nv_rd32(dev, 0x10f32c + (mr * 4));
472 return nv_rd32(dev, 0x10f34c);
477 mclk_mrs(struct nouveau_mem_exec_func *exec, int mr, u32 data)
479 struct drm_device *dev = exec->dev;
480 if (nvfb_vram_type(dev) != NV_MEM_TYPE_GDDR5) {
482 nv_wr32(dev, 0x10f300 + ((mr - 0) * 4), data);
483 if (nvfb_vram_rank_B(dev))
484 nv_wr32(dev, 0x10f308 + ((mr - 0) * 4), data);
487 nv_wr32(dev, 0x10f320 + ((mr - 2) * 4), data);
488 if (nvfb_vram_rank_B(dev))
489 nv_wr32(dev, 0x10f328 + ((mr - 2) * 4), data);
492 if (mr == 0) nv_wr32(dev, 0x10f300 + (mr * 4), data);
493 else if (mr <= 7) nv_wr32(dev, 0x10f32c + (mr * 4), data);
494 else if (mr == 15) nv_wr32(dev, 0x10f34c, data);
499 mclk_clock_set(struct nouveau_mem_exec_func *exec)
501 struct nvc0_pm_state *info = exec->priv;
502 struct drm_device *dev = exec->dev;
503 u32 ctrl = nv_rd32(dev, 0x132000);
505 nv_wr32(dev, 0x137360, 0x00000001);
506 nv_wr32(dev, 0x137370, 0x00000000);
507 nv_wr32(dev, 0x137380, 0x00000000);
508 if (ctrl & 0x00000001)
509 nv_wr32(dev, 0x132000, (ctrl &= ~0x00000001));
511 nv_wr32(dev, 0x132004, info->mem.coef);
512 nv_wr32(dev, 0x132000, (ctrl |= 0x00000001));
513 nv_wait(dev, 0x137390, 0x00000002, 0x00000002);
514 nv_wr32(dev, 0x132018, 0x00005000);
516 nv_wr32(dev, 0x137370, 0x00000001);
517 nv_wr32(dev, 0x137380, 0x00000001);
518 nv_wr32(dev, 0x137360, 0x00000000);
522 mclk_timing_set(struct nouveau_mem_exec_func *exec)
524 struct nvc0_pm_state *info = exec->priv;
525 struct nouveau_pm_level *perflvl = info->perflvl;
528 for (i = 0; i < 5; i++)
529 nv_wr32(exec->dev, 0x10f290 + (i * 4), perflvl->timing.reg[i]);
533 prog_mem(struct drm_device *dev, struct nvc0_pm_state *info)
535 struct drm_nouveau_private *dev_priv = dev->dev_private;
536 struct nouveau_mem_exec_func exec = {
538 .precharge = mclk_precharge,
539 .refresh = mclk_refresh,
540 .refresh_auto = mclk_refresh_auto,
541 .refresh_self = mclk_refresh_self,
545 .clock_set = mclk_clock_set,
546 .timing_set = mclk_timing_set,
550 if (dev_priv->chipset < 0xd0)
551 nv_wr32(dev, 0x611200, 0x00003300);
553 nv_wr32(dev, 0x62c000, 0x03030000);
555 nouveau_mem_exec(&exec, info->perflvl);
557 if (dev_priv->chipset < 0xd0)
558 nv_wr32(dev, 0x611200, 0x00003330);
560 nv_wr32(dev, 0x62c000, 0x03030300);
563 nvc0_pm_clocks_set(struct drm_device *dev, void *data)
565 struct nvc0_pm_state *info = data;
571 for (i = 0; i < 16; i++) {
572 if (!info->eng[i].freq)
574 prog_clk(dev, i, &info->eng[i]);