drivers/gpu/drm/nouveau/nve0_fifo.c

   1 /*
   2  * Copyright 2010 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24
  25 #include "drmP.h"
  26
  27 #include "nouveau_drv.h"
  28 #include "nouveau_mm.h"
  29
  30 #define NVE0_FIFO_ENGINE_NUM 32
  31
  32 static void nve0_fifo_isr(struct drm_device *);
  33
  34 struct nve0_fifo_engine {
  35         struct nouveau_gpuobj *playlist[2];
  36         int cur_playlist;
  37 };
  38
  39 struct nve0_fifo_priv {
  40         struct nve0_fifo_engine engine[NVE0_FIFO_ENGINE_NUM];
  41         struct {
  42                 struct nouveau_gpuobj *mem;
  43                 struct nouveau_vma bar;
  44         } user;
  45         int spoon_nr;
  46 };
  47
  48 struct nve0_fifo_chan {
  49         struct nouveau_gpuobj *ramfc;
  50         u32 engine;
  51 };
  52
  53 static void
  54 nve0_fifo_playlist_update(struct drm_device *dev, u32 engine)
  55 {
  56         struct drm_nouveau_private *dev_priv = dev->dev_private;
  57         struct nouveau_instmem_engine *pinstmem = &dev_priv->engine.instmem;
  58         struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
  59         struct nve0_fifo_priv *priv = pfifo->priv;
  60         struct nve0_fifo_engine *peng = &priv->engine[engine];
  61         struct nouveau_gpuobj *cur;
  62         u32 match = (engine << 16) | 0x00000001;
  63         int ret, i, p;
  64
  65         cur = peng->playlist[peng->cur_playlist];
  66         if (unlikely(cur == NULL)) {
  67                 ret = nouveau_gpuobj_new(dev, NULL, 0x8000, 0x1000, 0, &cur);
  68                 if (ret) {
  69                         NV_ERROR(dev, "PFIFO: playlist alloc failed\n");
  70                         return;
  71                 }
  72
  73                 peng->playlist[peng->cur_playlist] = cur;
  74         }
  75
  76         peng->cur_playlist = !peng->cur_playlist;
  77
  78         for (i = 0, p = 0; i < pfifo->channels; i++) {
  79                 u32 ctrl = nv_rd32(dev, 0x800004 + (i * 8)) & 0x001f0001;
  80                 if (ctrl != match)
  81                         continue;
  82                 nv_wo32(cur, p + 0, i);
  83                 nv_wo32(cur, p + 4, 0x00000000);
  84                 p += 8;
  85         }
  86         pinstmem->flush(dev);
  87
  88         nv_wr32(dev, 0x002270, cur->vinst >> 12);
  89         nv_wr32(dev, 0x002274, (engine << 20) | (p >> 3));
  90         if (!nv_wait(dev, 0x002284 + (engine * 4), 0x00100000, 0x00000000))
  91                 NV_ERROR(dev, "PFIFO: playlist %d update timeout\n", engine);
  92 }
  93
  94 int
  95 nve0_fifo_channel_id(struct drm_device *dev)
  96 {
  97         return 4095;
  98 }
  99
 100 int
 101 nve0_fifo_create_context(struct nouveau_channel *chan)
 102 {
 103         struct drm_device *dev = chan->dev;
 104         struct drm_nouveau_private *dev_priv = dev->dev_private;
 105         struct nouveau_instmem_engine *pinstmem = &dev_priv->engine.instmem;
 106         struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
 107         struct nve0_fifo_priv *priv = pfifo->priv;
 108         struct nve0_fifo_chan *fifoch;
 109         u64 usermem = priv->user.mem->vinst + chan->id * 512;
 110         u64 ib_virt = chan->pushbuf_base + chan->dma.ib_base * 4;
 111         int ret;
 112
 113         chan->fifo_priv = kzalloc(sizeof(*fifoch), GFP_KERNEL);
 114         if (!chan->fifo_priv)
 115                 return -ENOMEM;
 116         fifoch = chan->fifo_priv;
 117         fifoch->engine = 0; /* PGRAPH */
 118
 119         /* allocate vram for control regs, map into polling area */
 120         chan->user = ioremap_wc(pci_resource_start(dev->pdev, 1) +
 121                                 priv->user.bar.offset + (chan->id * 512), 512);
 122         if (!chan->user) {
 123                 ret = -ENOMEM;
 124                 goto error;
 125         }
 126
 127         /* ramfc */
 128         ret = nouveau_gpuobj_new_fake(dev, chan->ramin->pinst,
 129                                       chan->ramin->vinst, 0x100,
 130                                       NVOBJ_FLAG_ZERO_ALLOC, &fifoch->ramfc);
 131         if (ret)
 132                 goto error;
 133
 134         nv_wo32(fifoch->ramfc, 0x08, lower_32_bits(usermem));
 135         nv_wo32(fifoch->ramfc, 0x0c, upper_32_bits(usermem));
 136         nv_wo32(fifoch->ramfc, 0x10, 0x0000face);
 137         nv_wo32(fifoch->ramfc, 0x30, 0xfffff902);
 138         nv_wo32(fifoch->ramfc, 0x48, lower_32_bits(ib_virt));
 139         nv_wo32(fifoch->ramfc, 0x4c, drm_order(chan->dma.ib_max + 1) << 16 |
 140                                      upper_32_bits(ib_virt));
 141         nv_wo32(fifoch->ramfc, 0x84, 0x20400000);
 142         nv_wo32(fifoch->ramfc, 0x94, 0x30000001);
 143         nv_wo32(fifoch->ramfc, 0x9c, 0x00000100);
 144         nv_wo32(fifoch->ramfc, 0xac, 0x0000001f);
 145         nv_wo32(fifoch->ramfc, 0xe4, 0x00000000);
 146         nv_wo32(fifoch->ramfc, 0xe8, chan->id);
 147         nv_wo32(fifoch->ramfc, 0xf8, 0x10003080); /* 0x002310 */
 148         nv_wo32(fifoch->ramfc, 0xfc, 0x10000010); /* 0x002350 */
 149         pinstmem->flush(dev);
 150
 151         nv_wr32(dev, 0x800000 + (chan->id * 8), 0x80000000 |
 152                                                 (chan->ramin->vinst >> 12));
 153         nv_mask(dev, 0x800004 + (chan->id * 8), 0x00000400, 0x00000400);
 154         nve0_fifo_playlist_update(dev, fifoch->engine);
 155         nv_mask(dev, 0x800004 + (chan->id * 8), 0x00000400, 0x00000400);
 156         return 0;
 157
 158 error:
 159         pfifo->destroy_context(chan);
 160         return ret;
 161 }
 162
 163 void
 164 nve0_fifo_destroy_context(struct nouveau_channel *chan)
 165 {
 166         struct nve0_fifo_chan *fifoch = chan->fifo_priv;
 167         struct drm_device *dev = chan->dev;
 168
 169         if (!fifoch)
 170                 return;
 171
 172         nv_mask(dev, 0x800004 + (chan->id * 8), 0x00000800, 0x00000800);
 173         nv_wr32(dev, 0x002634, chan->id);
 174         if (!nv_wait(dev, 0x0002634, 0xffffffff, chan->id))
 175                 NV_WARN(dev, "0x2634 != chid: 0x%08x\n", nv_rd32(dev, 0x2634));
 176         nve0_fifo_playlist_update(dev, fifoch->engine);
 177         nv_wr32(dev, 0x800000 + (chan->id * 8), 0x00000000);
 178
 179         if (chan->user) {
 180                 iounmap(chan->user);
 181                 chan->user = NULL;
 182         }
 183
 184         nouveau_gpuobj_ref(NULL, &fifoch->ramfc);
 185         chan->fifo_priv = NULL;
 186         kfree(fifoch);
 187 }
 188
 189 int
 190 nve0_fifo_load_context(struct nouveau_channel *chan)
 191 {
 192         return 0;
 193 }
 194
 195 int
 196 nve0_fifo_unload_context(struct drm_device *dev)
 197 {
 198         struct drm_nouveau_private *dev_priv = dev->dev_private;
 199         struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
 200         int i;
 201
 202         for (i = 0; i < pfifo->channels; i++) {
 203                 if (!(nv_rd32(dev, 0x800004 + (i * 8)) & 1))
 204                         continue;
 205
 206                 nv_mask(dev, 0x800004 + (i * 8), 0x00000800, 0x00000800);
 207                 nv_wr32(dev, 0x002634, i);
 208                 if (!nv_wait(dev, 0x002634, 0xffffffff, i)) {
 209                         NV_INFO(dev, "PFIFO: kick ch %d failed: 0x%08x\n",
 210                                 i, nv_rd32(dev, 0x002634));
 211                         return -EBUSY;
 212                 }
 213         }
 214
 215         return 0;
 216 }
 217
 218 static void
 219 nve0_fifo_destroy(struct drm_device *dev)
 220 {
 221         struct drm_nouveau_private *dev_priv = dev->dev_private;
 222         struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
 223         struct nve0_fifo_priv *priv;
 224         int i;
 225
 226         priv = pfifo->priv;
 227         if (!priv)
 228                 return;
 229
 230         nouveau_vm_put(&priv->user.bar);
 231         nouveau_gpuobj_ref(NULL, &priv->user.mem);
 232
 233         for (i = 0; i < NVE0_FIFO_ENGINE_NUM; i++) {
 234                 nouveau_gpuobj_ref(NULL, &priv->engine[i].playlist[0]);
 235                 nouveau_gpuobj_ref(NULL, &priv->engine[i].playlist[1]);
 236         }
 237         kfree(priv);
 238 }
 239
 240 void
 241 nve0_fifo_takedown(struct drm_device *dev)
 242 {
 243         nv_wr32(dev, 0x002140, 0x00000000);
 244         nve0_fifo_destroy(dev);
 245 }
 246
 247 static int
 248 nve0_fifo_create(struct drm_device *dev)
 249 {
 250         struct drm_nouveau_private *dev_priv = dev->dev_private;
 251         struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
 252         struct nve0_fifo_priv *priv;
 253         int ret;
 254
 255         priv = kzalloc(sizeof(*priv), GFP_KERNEL);
 256         if (!priv)
 257                 return -ENOMEM;
 258         pfifo->priv = priv;
 259
 260         ret = nouveau_gpuobj_new(dev, NULL, pfifo->channels * 512, 0x1000,
 261                                  NVOBJ_FLAG_ZERO_ALLOC, &priv->user.mem);
 262         if (ret)
 263                 goto error;
 264
 265         ret = nouveau_vm_get(dev_priv->bar1_vm, priv->user.mem->size,
 266                              12, NV_MEM_ACCESS_RW, &priv->user.bar);
 267         if (ret)
 268                 goto error;
 269
 270         nouveau_vm_map(&priv->user.bar, *(struct nouveau_mem **)priv->user.mem->node);
 271
 272         nouveau_irq_register(dev, 8, nve0_fifo_isr);
 273         return 0;
 274
 275 error:
 276         nve0_fifo_destroy(dev);
 277         return ret;
 278 }
 279
 280 int
 281 nve0_fifo_init(struct drm_device *dev)
 282 {
 283         struct drm_nouveau_private *dev_priv = dev->dev_private;
 284         struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
 285         struct nouveau_channel *chan;
 286         struct nve0_fifo_chan *fifoch;
 287         struct nve0_fifo_priv *priv;
 288         int ret, i;
 289
 290         if (!pfifo->priv) {
 291                 ret = nve0_fifo_create(dev);
 292                 if (ret)
 293                         return ret;
 294         }
 295         priv = pfifo->priv;
 296
 297         /* reset PFIFO, enable all available PSUBFIFO areas */
 298         nv_mask(dev, 0x000200, 0x00000100, 0x00000000);
 299         nv_mask(dev, 0x000200, 0x00000100, 0x00000100);
 300         nv_wr32(dev, 0x000204, 0xffffffff);
 301
 302         priv->spoon_nr = hweight32(nv_rd32(dev, 0x000204));
 303         NV_DEBUG(dev, "PFIFO: %d subfifo(s)\n", priv->spoon_nr);
 304
 305         /* PSUBFIFO[n] */
 306         for (i = 0; i < priv->spoon_nr; i++) {
 307                 nv_mask(dev, 0x04013c + (i * 0x2000), 0x10000100, 0x00000000);
 308                 nv_wr32(dev, 0x040108 + (i * 0x2000), 0xffffffff); /* INTR */
 309                 nv_wr32(dev, 0x04010c + (i * 0x2000), 0xfffffeff); /* INTR_EN */
 310         }
 311
 312         nv_wr32(dev, 0x002254, 0x10000000 | priv->user.bar.offset >> 12);
 313
 314         nv_wr32(dev, 0x002a00, 0xffffffff);
 315         nv_wr32(dev, 0x002100, 0xffffffff);
 316         nv_wr32(dev, 0x002140, 0xbfffffff);
 317
 318         /* restore PFIFO context table */
 319         for (i = 0; i < pfifo->channels; i++) {
 320                 chan = dev_priv->channels.ptr[i];
 321                 if (!chan || !chan->fifo_priv)
 322                         continue;
 323                 fifoch = chan->fifo_priv;
 324
 325                 nv_wr32(dev, 0x800000 + (i * 8), 0x80000000 |
 326                                                  (chan->ramin->vinst >> 12));
 327                 nv_mask(dev, 0x800004 + (i * 8), 0x00000400, 0x00000400);
 328                 nve0_fifo_playlist_update(dev, fifoch->engine);
 329                 nv_mask(dev, 0x800004 + (i * 8), 0x00000400, 0x00000400);
 330         }
 331
 332         return 0;
 333 }
 334
 335 struct nouveau_enum nve0_fifo_fault_unit[] = {
 336         {}
 337 };
 338
 339 struct nouveau_enum nve0_fifo_fault_reason[] = {
 340         { 0x00, "PT_NOT_PRESENT" },
 341         { 0x01, "PT_TOO_SHORT" },
 342         { 0x02, "PAGE_NOT_PRESENT" },
 343         { 0x03, "VM_LIMIT_EXCEEDED" },
 344         { 0x04, "NO_CHANNEL" },
 345         { 0x05, "PAGE_SYSTEM_ONLY" },
 346         { 0x06, "PAGE_READ_ONLY" },
 347         { 0x0a, "COMPRESSED_SYSRAM" },
 348         { 0x0c, "INVALID_STORAGE_TYPE" },
 349         {}
 350 };
 351
 352 struct nouveau_enum nve0_fifo_fault_hubclient[] = {
 353         {}
 354 };
 355
 356 struct nouveau_enum nve0_fifo_fault_gpcclient[] = {
 357         {}
 358 };
 359
 360 struct nouveau_bitfield nve0_fifo_subfifo_intr[] = {
 361         { 0x00200000, "ILLEGAL_MTHD" },
 362         { 0x00800000, "EMPTY_SUBC" },
 363         {}
 364 };
 365
 366 static void
 367 nve0_fifo_isr_vm_fault(struct drm_device *dev, int unit)
 368 {
 369         u32 inst = nv_rd32(dev, 0x2800 + (unit * 0x10));
 370         u32 valo = nv_rd32(dev, 0x2804 + (unit * 0x10));
 371         u32 vahi = nv_rd32(dev, 0x2808 + (unit * 0x10));
 372         u32 stat = nv_rd32(dev, 0x280c + (unit * 0x10));
 373         u32 client = (stat & 0x00001f00) >> 8;
 374
 375         NV_INFO(dev, "PFIFO: %s fault at 0x%010llx [",
 376                 (stat & 0x00000080) ? "write" : "read", (u64)vahi << 32 | valo);
 377         nouveau_enum_print(nve0_fifo_fault_reason, stat & 0x0000000f);
 378         printk("] from ");
 379         nouveau_enum_print(nve0_fifo_fault_unit, unit);
 380         if (stat & 0x00000040) {
 381                 printk("/");
 382                 nouveau_enum_print(nve0_fifo_fault_hubclient, client);
 383         } else {
 384                 printk("/GPC%d/", (stat & 0x1f000000) >> 24);
 385                 nouveau_enum_print(nve0_fifo_fault_gpcclient, client);
 386         }
 387         printk(" on channel 0x%010llx\n", (u64)inst << 12);
 388 }
 389
 390 static void
 391 nve0_fifo_isr_subfifo_intr(struct drm_device *dev, int unit)
 392 {
 393         u32 stat = nv_rd32(dev, 0x040108 + (unit * 0x2000));
 394         u32 addr = nv_rd32(dev, 0x0400c0 + (unit * 0x2000));
 395         u32 data = nv_rd32(dev, 0x0400c4 + (unit * 0x2000));
 396         u32 chid = nv_rd32(dev, 0x040120 + (unit * 0x2000)) & 0x7f;
 397         u32 subc = (addr & 0x00070000);
 398         u32 mthd = (addr & 0x00003ffc);
 399
 400         NV_INFO(dev, "PSUBFIFO %d:", unit);
 401         nouveau_bitfield_print(nve0_fifo_subfifo_intr, stat);
 402         NV_INFO(dev, "PSUBFIFO %d: ch %d subc %d mthd 0x%04x data 0x%08x\n",
 403                 unit, chid, subc, mthd, data);
 404
 405         nv_wr32(dev, 0x0400c0 + (unit * 0x2000), 0x80600008);
 406         nv_wr32(dev, 0x040108 + (unit * 0x2000), stat);
 407 }
 408
 409 static void
 410 nve0_fifo_isr(struct drm_device *dev)
 411 {
 412         u32 stat = nv_rd32(dev, 0x002100);
 413
 414         if (stat & 0x00000100) {
 415                 NV_INFO(dev, "PFIFO: unknown status 0x00000100\n");
 416                 nv_wr32(dev, 0x002100, 0x00000100);
 417                 stat &= ~0x00000100;
 418         }
 419
 420         if (stat & 0x10000000) {
 421                 u32 units = nv_rd32(dev, 0x00259c);
 422                 u32 u = units;
 423
 424                 while (u) {
 425                         int i = ffs(u) - 1;
 426                         nve0_fifo_isr_vm_fault(dev, i);
 427                         u &= ~(1 << i);
 428                 }
 429
 430                 nv_wr32(dev, 0x00259c, units);
 431                 stat &= ~0x10000000;
 432         }
 433
 434         if (stat & 0x20000000) {
 435                 u32 units = nv_rd32(dev, 0x0025a0);
 436                 u32 u = units;
 437
 438                 while (u) {
 439                         int i = ffs(u) - 1;
 440                         nve0_fifo_isr_subfifo_intr(dev, i);
 441                         u &= ~(1 << i);
 442                 }
 443
 444                 nv_wr32(dev, 0x0025a0, units);
 445                 stat &= ~0x20000000;
 446         }
 447
 448         if (stat & 0x40000000) {
 449                 NV_INFO(dev, "PFIFO: unknown status 0x40000000\n");
 450                 nv_mask(dev, 0x002a00, 0x00000000, 0x00000000);
 451                 stat &= ~0x40000000;
 452         }
 453
 454         if (stat) {
 455                 NV_INFO(dev, "PFIFO: unhandled status 0x%08x\n", stat);
 456                 nv_wr32(dev, 0x002100, stat);
 457                 nv_wr32(dev, 0x002140, 0);
 458         }
 459 }