drivers/gpu/drm/nouveau/nve0_fifo.c

   1 /*
   2  * Copyright 2010 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24
  25 #include "drmP.h"
  26
  27 #include "nouveau_drv.h"
  28 #include "nouveau_mm.h"
  29
  30 #define NVE0_FIFO_ENGINE_NUM 32
  31
  32 static void nve0_fifo_isr(struct drm_device *);
  33
  34 struct nve0_fifo_engine {
  35         struct nouveau_gpuobj *playlist[2];
  36         int cur_playlist;
  37 };
  38
  39 struct nve0_fifo_priv {
  40         struct nve0_fifo_engine engine[NVE0_FIFO_ENGINE_NUM];
  41         struct {
  42                 struct nouveau_gpuobj *mem;
  43                 struct nouveau_vma bar;
  44         } user;
  45         int spoon_nr;
  46 };
  47
  48 struct nve0_fifo_chan {
  49         struct nouveau_gpuobj *ramfc;
  50         u32 engine;
  51 };
  52
  53 static void
  54 nve0_fifo_playlist_update(struct drm_device *dev, u32 engine)
  55 {
  56         struct drm_nouveau_private *dev_priv = dev->dev_private;
  57         struct nouveau_instmem_engine *pinstmem = &dev_priv->engine.instmem;
  58         struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
  59         struct nve0_fifo_priv *priv = pfifo->priv;
  60         struct nve0_fifo_engine *peng = &priv->engine[engine];
  61         struct nouveau_gpuobj *cur;
  62         u32 match = (engine << 16) | 0x00000001;
  63         int ret, i, p;
  64
  65         cur = peng->playlist[peng->cur_playlist];
  66         if (unlikely(cur == NULL)) {
  67                 ret = nouveau_gpuobj_new(dev, NULL, 0x8000, 0x1000, 0, &cur);
  68                 if (ret) {
  69                         NV_ERROR(dev, "PFIFO: playlist alloc failed\n");
  70                         return;
  71                 }
  72
  73                 peng->playlist[peng->cur_playlist] = cur;
  74         }
  75
  76         peng->cur_playlist = !peng->cur_playlist;
  77
  78         for (i = 0, p = 0; i < pfifo->channels; i++) {
  79                 u32 ctrl = nv_rd32(dev, 0x800004 + (i * 8)) & 0x001f0001;
  80                 if (ctrl != match)
  81                         continue;
  82                 nv_wo32(cur, p + 0, i);
  83                 nv_wo32(cur, p + 4, 0x00000000);
  84                 p += 8;
  85         }
  86         pinstmem->flush(dev);
  87
  88         nv_wr32(dev, 0x002270, cur->vinst >> 12);
  89         nv_wr32(dev, 0x002274, (engine << 20) | (p >> 3));
  90         if (!nv_wait(dev, 0x002284 + (engine * 4), 0x00100000, 0x00000000))
  91                 NV_ERROR(dev, "PFIFO: playlist %d update timeout\n", engine);
  92 }
  93
  94 int
  95 nve0_fifo_create_context(struct nouveau_channel *chan)
  96 {
  97         struct drm_device *dev = chan->dev;
  98         struct drm_nouveau_private *dev_priv = dev->dev_private;
  99         struct nouveau_instmem_engine *pinstmem = &dev_priv->engine.instmem;
 100         struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
 101         struct nve0_fifo_priv *priv = pfifo->priv;
 102         struct nve0_fifo_chan *fifoch;
 103         u64 usermem = priv->user.mem->vinst + chan->id * 512;
 104         u64 ib_virt = chan->pushbuf_base + chan->dma.ib_base * 4;
 105         int ret;
 106
 107         chan->fifo_priv = kzalloc(sizeof(*fifoch), GFP_KERNEL);
 108         if (!chan->fifo_priv)
 109                 return -ENOMEM;
 110         fifoch = chan->fifo_priv;
 111         fifoch->engine = 0; /* PGRAPH */
 112
 113         /* allocate vram for control regs, map into polling area */
 114         chan->user = ioremap_wc(pci_resource_start(dev->pdev, 1) +
 115                                 priv->user.bar.offset + (chan->id * 512), 512);
 116         if (!chan->user) {
 117                 ret = -ENOMEM;
 118                 goto error;
 119         }
 120
 121         /* ramfc */
 122         ret = nouveau_gpuobj_new_fake(dev, chan->ramin->pinst,
 123                                       chan->ramin->vinst, 0x100,
 124                                       NVOBJ_FLAG_ZERO_ALLOC, &fifoch->ramfc);
 125         if (ret)
 126                 goto error;
 127
 128         nv_wo32(fifoch->ramfc, 0x08, lower_32_bits(usermem));
 129         nv_wo32(fifoch->ramfc, 0x0c, upper_32_bits(usermem));
 130         nv_wo32(fifoch->ramfc, 0x10, 0x0000face);
 131         nv_wo32(fifoch->ramfc, 0x30, 0xfffff902);
 132         nv_wo32(fifoch->ramfc, 0x48, lower_32_bits(ib_virt));
 133         nv_wo32(fifoch->ramfc, 0x4c, drm_order(chan->dma.ib_max + 1) << 16 |
 134                                      upper_32_bits(ib_virt));
 135         nv_wo32(fifoch->ramfc, 0x84, 0x20400000);
 136         nv_wo32(fifoch->ramfc, 0x94, 0x30000001);
 137         nv_wo32(fifoch->ramfc, 0x9c, 0x00000100);
 138         nv_wo32(fifoch->ramfc, 0xac, 0x0000001f);
 139         nv_wo32(fifoch->ramfc, 0xe4, 0x00000000);
 140         nv_wo32(fifoch->ramfc, 0xe8, chan->id);
 141         nv_wo32(fifoch->ramfc, 0xf8, 0x10003080); /* 0x002310 */
 142         nv_wo32(fifoch->ramfc, 0xfc, 0x10000010); /* 0x002350 */
 143         pinstmem->flush(dev);
 144
 145         nv_wr32(dev, 0x800000 + (chan->id * 8), 0x80000000 |
 146                                                 (chan->ramin->vinst >> 12));
 147         nv_mask(dev, 0x800004 + (chan->id * 8), 0x00000400, 0x00000400);
 148         nve0_fifo_playlist_update(dev, fifoch->engine);
 149         nv_mask(dev, 0x800004 + (chan->id * 8), 0x00000400, 0x00000400);
 150         return 0;
 151
 152 error:
 153         pfifo->destroy_context(chan);
 154         return ret;
 155 }
 156
 157 void
 158 nve0_fifo_destroy_context(struct nouveau_channel *chan)
 159 {
 160         struct nve0_fifo_chan *fifoch = chan->fifo_priv;
 161         struct drm_device *dev = chan->dev;
 162
 163         if (!fifoch)
 164                 return;
 165
 166         nv_mask(dev, 0x800004 + (chan->id * 8), 0x00000800, 0x00000800);
 167         nv_wr32(dev, 0x002634, chan->id);
 168         if (!nv_wait(dev, 0x0002634, 0xffffffff, chan->id))
 169                 NV_WARN(dev, "0x2634 != chid: 0x%08x\n", nv_rd32(dev, 0x2634));
 170         nve0_fifo_playlist_update(dev, fifoch->engine);
 171         nv_wr32(dev, 0x800000 + (chan->id * 8), 0x00000000);
 172
 173         if (chan->user) {
 174                 iounmap(chan->user);
 175                 chan->user = NULL;
 176         }
 177
 178         nouveau_gpuobj_ref(NULL, &fifoch->ramfc);
 179         chan->fifo_priv = NULL;
 180         kfree(fifoch);
 181 }
 182
 183 int
 184 nve0_fifo_load_context(struct nouveau_channel *chan)
 185 {
 186         return 0;
 187 }
 188
 189 int
 190 nve0_fifo_unload_context(struct drm_device *dev)
 191 {
 192         struct drm_nouveau_private *dev_priv = dev->dev_private;
 193         struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
 194         int i;
 195
 196         for (i = 0; i < pfifo->channels; i++) {
 197                 if (!(nv_rd32(dev, 0x800004 + (i * 8)) & 1))
 198                         continue;
 199
 200                 nv_mask(dev, 0x800004 + (i * 8), 0x00000800, 0x00000800);
 201                 nv_wr32(dev, 0x002634, i);
 202                 if (!nv_wait(dev, 0x002634, 0xffffffff, i)) {
 203                         NV_INFO(dev, "PFIFO: kick ch %d failed: 0x%08x\n",
 204                                 i, nv_rd32(dev, 0x002634));
 205                         return -EBUSY;
 206                 }
 207         }
 208
 209         return 0;
 210 }
 211
 212 static void
 213 nve0_fifo_destroy(struct drm_device *dev)
 214 {
 215         struct drm_nouveau_private *dev_priv = dev->dev_private;
 216         struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
 217         struct nve0_fifo_priv *priv;
 218         int i;
 219
 220         priv = pfifo->priv;
 221         if (!priv)
 222                 return;
 223
 224         nouveau_vm_put(&priv->user.bar);
 225         nouveau_gpuobj_ref(NULL, &priv->user.mem);
 226
 227         for (i = 0; i < NVE0_FIFO_ENGINE_NUM; i++) {
 228                 nouveau_gpuobj_ref(NULL, &priv->engine[i].playlist[0]);
 229                 nouveau_gpuobj_ref(NULL, &priv->engine[i].playlist[1]);
 230         }
 231         kfree(priv);
 232 }
 233
 234 void
 235 nve0_fifo_takedown(struct drm_device *dev)
 236 {
 237         nv_wr32(dev, 0x002140, 0x00000000);
 238         nve0_fifo_destroy(dev);
 239 }
 240
 241 static int
 242 nve0_fifo_create(struct drm_device *dev)
 243 {
 244         struct drm_nouveau_private *dev_priv = dev->dev_private;
 245         struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
 246         struct nve0_fifo_priv *priv;
 247         int ret;
 248
 249         priv = kzalloc(sizeof(*priv), GFP_KERNEL);
 250         if (!priv)
 251                 return -ENOMEM;
 252         pfifo->priv = priv;
 253
 254         ret = nouveau_gpuobj_new(dev, NULL, pfifo->channels * 512, 0x1000,
 255                                  NVOBJ_FLAG_ZERO_ALLOC, &priv->user.mem);
 256         if (ret)
 257                 goto error;
 258
 259         ret = nouveau_vm_get(dev_priv->bar1_vm, priv->user.mem->size,
 260                              12, NV_MEM_ACCESS_RW, &priv->user.bar);
 261         if (ret)
 262                 goto error;
 263
 264         nouveau_vm_map(&priv->user.bar, *(struct nouveau_mem **)priv->user.mem->node);
 265
 266         nouveau_irq_register(dev, 8, nve0_fifo_isr);
 267         return 0;
 268
 269 error:
 270         nve0_fifo_destroy(dev);
 271         return ret;
 272 }
 273
 274 int
 275 nve0_fifo_init(struct drm_device *dev)
 276 {
 277         struct drm_nouveau_private *dev_priv = dev->dev_private;
 278         struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
 279         struct nouveau_channel *chan;
 280         struct nve0_fifo_chan *fifoch;
 281         struct nve0_fifo_priv *priv;
 282         int ret, i;
 283
 284         if (!pfifo->priv) {
 285                 ret = nve0_fifo_create(dev);
 286                 if (ret)
 287                         return ret;
 288         }
 289         priv = pfifo->priv;
 290
 291         /* reset PFIFO, enable all available PSUBFIFO areas */
 292         nv_mask(dev, 0x000200, 0x00000100, 0x00000000);
 293         nv_mask(dev, 0x000200, 0x00000100, 0x00000100);
 294         nv_wr32(dev, 0x000204, 0xffffffff);
 295
 296         priv->spoon_nr = hweight32(nv_rd32(dev, 0x000204));
 297         NV_DEBUG(dev, "PFIFO: %d subfifo(s)\n", priv->spoon_nr);
 298
 299         /* PSUBFIFO[n] */
 300         for (i = 0; i < priv->spoon_nr; i++) {
 301                 nv_mask(dev, 0x04013c + (i * 0x2000), 0x10000100, 0x00000000);
 302                 nv_wr32(dev, 0x040108 + (i * 0x2000), 0xffffffff); /* INTR */
 303                 nv_wr32(dev, 0x04010c + (i * 0x2000), 0xfffffeff); /* INTR_EN */
 304         }
 305
 306         nv_wr32(dev, 0x002254, 0x10000000 | priv->user.bar.offset >> 12);
 307
 308         nv_wr32(dev, 0x002a00, 0xffffffff);
 309         nv_wr32(dev, 0x002100, 0xffffffff);
 310         nv_wr32(dev, 0x002140, 0xbfffffff);
 311
 312         /* restore PFIFO context table */
 313         for (i = 0; i < pfifo->channels; i++) {
 314                 chan = dev_priv->channels.ptr[i];
 315                 if (!chan || !chan->fifo_priv)
 316                         continue;
 317                 fifoch = chan->fifo_priv;
 318
 319                 nv_wr32(dev, 0x800000 + (i * 8), 0x80000000 |
 320                                                  (chan->ramin->vinst >> 12));
 321                 nv_mask(dev, 0x800004 + (i * 8), 0x00000400, 0x00000400);
 322                 nve0_fifo_playlist_update(dev, fifoch->engine);
 323                 nv_mask(dev, 0x800004 + (i * 8), 0x00000400, 0x00000400);
 324         }
 325
 326         return 0;
 327 }
 328
 329 struct nouveau_enum nve0_fifo_fault_unit[] = {
 330         {}
 331 };
 332
 333 struct nouveau_enum nve0_fifo_fault_reason[] = {
 334         { 0x00, "PT_NOT_PRESENT" },
 335         { 0x01, "PT_TOO_SHORT" },
 336         { 0x02, "PAGE_NOT_PRESENT" },
 337         { 0x03, "VM_LIMIT_EXCEEDED" },
 338         { 0x04, "NO_CHANNEL" },
 339         { 0x05, "PAGE_SYSTEM_ONLY" },
 340         { 0x06, "PAGE_READ_ONLY" },
 341         { 0x0a, "COMPRESSED_SYSRAM" },
 342         { 0x0c, "INVALID_STORAGE_TYPE" },
 343         {}
 344 };
 345
 346 struct nouveau_enum nve0_fifo_fault_hubclient[] = {
 347         {}
 348 };
 349
 350 struct nouveau_enum nve0_fifo_fault_gpcclient[] = {
 351         {}
 352 };
 353
 354 struct nouveau_bitfield nve0_fifo_subfifo_intr[] = {
 355         { 0x00200000, "ILLEGAL_MTHD" },
 356         { 0x00800000, "EMPTY_SUBC" },
 357         {}
 358 };
 359
 360 static void
 361 nve0_fifo_isr_vm_fault(struct drm_device *dev, int unit)
 362 {
 363         u32 inst = nv_rd32(dev, 0x2800 + (unit * 0x10));
 364         u32 valo = nv_rd32(dev, 0x2804 + (unit * 0x10));
 365         u32 vahi = nv_rd32(dev, 0x2808 + (unit * 0x10));
 366         u32 stat = nv_rd32(dev, 0x280c + (unit * 0x10));
 367         u32 client = (stat & 0x00001f00) >> 8;
 368
 369         NV_INFO(dev, "PFIFO: %s fault at 0x%010llx [",
 370                 (stat & 0x00000080) ? "write" : "read", (u64)vahi << 32 | valo);
 371         nouveau_enum_print(nve0_fifo_fault_reason, stat & 0x0000000f);
 372         printk("] from ");
 373         nouveau_enum_print(nve0_fifo_fault_unit, unit);
 374         if (stat & 0x00000040) {
 375                 printk("/");
 376                 nouveau_enum_print(nve0_fifo_fault_hubclient, client);
 377         } else {
 378                 printk("/GPC%d/", (stat & 0x1f000000) >> 24);
 379                 nouveau_enum_print(nve0_fifo_fault_gpcclient, client);
 380         }
 381         printk(" on channel 0x%010llx\n", (u64)inst << 12);
 382 }
 383
 384 static void
 385 nve0_fifo_isr_subfifo_intr(struct drm_device *dev, int unit)
 386 {
 387         u32 stat = nv_rd32(dev, 0x040108 + (unit * 0x2000));
 388         u32 addr = nv_rd32(dev, 0x0400c0 + (unit * 0x2000));
 389         u32 data = nv_rd32(dev, 0x0400c4 + (unit * 0x2000));
 390         u32 chid = nv_rd32(dev, 0x040120 + (unit * 0x2000)) & 0x7f;
 391         u32 subc = (addr & 0x00070000);
 392         u32 mthd = (addr & 0x00003ffc);
 393
 394         NV_INFO(dev, "PSUBFIFO %d:", unit);
 395         nouveau_bitfield_print(nve0_fifo_subfifo_intr, stat);
 396         NV_INFO(dev, "PSUBFIFO %d: ch %d subc %d mthd 0x%04x data 0x%08x\n",
 397                 unit, chid, subc, mthd, data);
 398
 399         nv_wr32(dev, 0x0400c0 + (unit * 0x2000), 0x80600008);
 400         nv_wr32(dev, 0x040108 + (unit * 0x2000), stat);
 401 }
 402
 403 static void
 404 nve0_fifo_isr(struct drm_device *dev)
 405 {
 406         u32 stat = nv_rd32(dev, 0x002100);
 407
 408         if (stat & 0x00000100) {
 409                 NV_INFO(dev, "PFIFO: unknown status 0x00000100\n");
 410                 nv_wr32(dev, 0x002100, 0x00000100);
 411                 stat &= ~0x00000100;
 412         }
 413
 414         if (stat & 0x10000000) {
 415                 u32 units = nv_rd32(dev, 0x00259c);
 416                 u32 u = units;
 417
 418                 while (u) {
 419                         int i = ffs(u) - 1;
 420                         nve0_fifo_isr_vm_fault(dev, i);
 421                         u &= ~(1 << i);
 422                 }
 423
 424                 nv_wr32(dev, 0x00259c, units);
 425                 stat &= ~0x10000000;
 426         }
 427
 428         if (stat & 0x20000000) {
 429                 u32 units = nv_rd32(dev, 0x0025a0);
 430                 u32 u = units;
 431
 432                 while (u) {
 433                         int i = ffs(u) - 1;
 434                         nve0_fifo_isr_subfifo_intr(dev, i);
 435                         u &= ~(1 << i);
 436                 }
 437
 438                 nv_wr32(dev, 0x0025a0, units);
 439                 stat &= ~0x20000000;
 440         }
 441
 442         if (stat & 0x40000000) {
 443                 NV_INFO(dev, "PFIFO: unknown status 0x40000000\n");
 444                 nv_mask(dev, 0x002a00, 0x00000000, 0x00000000);
 445                 stat &= ~0x40000000;
 446         }
 447
 448         if (stat) {
 449                 NV_INFO(dev, "PFIFO: unhandled status 0x%08x\n", stat);
 450                 nv_wr32(dev, 0x002100, stat);
 451                 nv_wr32(dev, 0x002140, 0);
 452         }
 453 }