2 * Copyright 2012 Red Hat Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
28 #include <subdev/bios.h>
29 #include <subdev/bios/disp.h>
30 #include <subdev/bios/init.h>
31 #include <subdev/bios/pll.h>
32 #include <subdev/devinit.h>
34 static struct nvkm_output *
35 exec_lookup(struct nv50_disp *disp, int head, int or, u32 ctrl,
36 u32 *data, u8 *ver, u8 *hdr, u8 *cnt, u8 *len,
37 struct nvbios_outp *info)
39 struct nvkm_subdev *subdev = &disp->base.engine.subdev;
40 struct nvkm_bios *bios = subdev->device->bios;
41 struct nvkm_output *outp;
45 type = DCB_OUTPUT_ANALOG;
49 switch (ctrl & 0x00000f00) {
50 case 0x00000000: type = DCB_OUTPUT_LVDS; mask = 1; break;
51 case 0x00000100: type = DCB_OUTPUT_TMDS; mask = 1; break;
52 case 0x00000200: type = DCB_OUTPUT_TMDS; mask = 2; break;
53 case 0x00000500: type = DCB_OUTPUT_TMDS; mask = 3; break;
54 case 0x00000800: type = DCB_OUTPUT_DP; mask = 1; break;
55 case 0x00000900: type = DCB_OUTPUT_DP; mask = 2; break;
57 nvkm_error(subdev, "unknown SOR mc %08x\n", ctrl);
62 mask = 0x00c0 & (mask << 6);
64 mask |= 0x0100 << head;
66 list_for_each_entry(outp, &disp->base.outp, head) {
67 if ((outp->info.hasht & 0xff) == type &&
68 (outp->info.hashm & mask) == mask) {
69 *data = nvbios_outp_match(bios, outp->info.hasht, mask,
70 ver, hdr, cnt, len, info);
80 static struct nvkm_output *
81 exec_script(struct nv50_disp *disp, int head, int id)
83 struct nvkm_subdev *subdev = &disp->base.engine.subdev;
84 struct nvkm_device *device = subdev->device;
85 struct nvkm_bios *bios = device->bios;
86 struct nvkm_output *outp;
87 struct nvbios_outp info;
88 u8 ver, hdr, cnt, len;
92 for (or = 0; !(ctrl & (1 << head)) && or < 8; or++) {
93 ctrl = nvkm_rd32(device, 0x640180 + (or * 0x20));
94 if (ctrl & (1 << head))
101 outp = exec_lookup(disp, head, or, ctrl, &data, &ver, &hdr, &cnt, &len, &info);
103 struct nvbios_init init = {
106 .offset = info.script[id],
118 static struct nvkm_output *
119 exec_clkcmp(struct nv50_disp *disp, int head, int id, u32 pclk, u32 *conf)
121 struct nvkm_subdev *subdev = &disp->base.engine.subdev;
122 struct nvkm_device *device = subdev->device;
123 struct nvkm_bios *bios = device->bios;
124 struct nvkm_output *outp;
125 struct nvbios_outp info1;
126 struct nvbios_ocfg info2;
127 u8 ver, hdr, cnt, len;
131 for (or = 0; !(ctrl & (1 << head)) && or < 8; or++) {
132 ctrl = nvkm_rd32(device, 0x660180 + (or * 0x20));
133 if (ctrl & (1 << head))
140 outp = exec_lookup(disp, head, or, ctrl, &data, &ver, &hdr, &cnt, &len, &info1);
144 *conf = (ctrl & 0x00000f00) >> 8;
145 switch (outp->info.type) {
146 case DCB_OUTPUT_TMDS:
150 case DCB_OUTPUT_LVDS:
151 *conf |= disp->sor.lvdsconf;
157 data = nvbios_ocfg_match(bios, data, *conf & 0xff, *conf >> 8,
158 &ver, &hdr, &cnt, &len, &info2);
159 if (data && id < 0xff) {
160 data = nvbios_oclk_match(bios, info2.clkcmp[id], pclk);
162 struct nvbios_init init = {
179 gf119_disp_intr_unk1_0(struct nv50_disp *disp, int head)
181 exec_script(disp, head, 1);
185 gf119_disp_intr_unk2_0(struct nv50_disp *disp, int head)
187 struct nvkm_subdev *subdev = &disp->base.engine.subdev;
188 struct nvkm_output *outp = exec_script(disp, head, 2);
190 /* see note in nv50_disp_intr_unk20_0() */
191 if (outp && outp->info.type == DCB_OUTPUT_DP) {
192 struct nvkm_output_dp *outpdp = nvkm_output_dp(outp);
193 if (!outpdp->lt.mst) {
194 struct nvbios_init init = {
196 .bios = subdev->device->bios,
199 .offset = outpdp->info.script[4],
203 nvkm_notify_put(&outpdp->irq);
205 atomic_set(&outpdp->lt.done, 0);
211 gf119_disp_intr_unk2_1(struct nv50_disp *disp, int head)
213 struct nvkm_device *device = disp->base.engine.subdev.device;
214 struct nvkm_devinit *devinit = device->devinit;
215 u32 pclk = nvkm_rd32(device, 0x660450 + (head * 0x300)) / 1000;
217 nvkm_devinit_pll_set(devinit, PLL_VPLL0 + head, pclk);
218 nvkm_wr32(device, 0x612200 + (head * 0x800), 0x00000000);
222 gf119_disp_intr_unk2_2_tu(struct nv50_disp *disp, int head,
223 struct dcb_output *outp)
225 struct nvkm_device *device = disp->base.engine.subdev.device;
226 const int or = ffs(outp->or) - 1;
227 const u32 ctrl = nvkm_rd32(device, 0x660200 + (or * 0x020));
228 const u32 conf = nvkm_rd32(device, 0x660404 + (head * 0x300));
229 const s32 vactive = nvkm_rd32(device, 0x660414 + (head * 0x300)) & 0xffff;
230 const s32 vblanke = nvkm_rd32(device, 0x66041c + (head * 0x300)) & 0xffff;
231 const s32 vblanks = nvkm_rd32(device, 0x660420 + (head * 0x300)) & 0xffff;
232 const u32 pclk = nvkm_rd32(device, 0x660450 + (head * 0x300)) / 1000;
233 const u32 link = ((ctrl & 0xf00) == 0x800) ? 0 : 1;
234 const u32 hoff = (head * 0x800);
235 const u32 soff = ( or * 0x800);
236 const u32 loff = (link * 0x080) + soff;
237 const u32 symbol = 100000;
239 u32 dpctrl = nvkm_rd32(device, 0x61c10c + loff);
240 u32 clksor = nvkm_rd32(device, 0x612300 + soff);
241 u32 datarate, link_nr, link_bw, bits;
244 link_nr = hweight32(dpctrl & 0x000f0000);
245 link_bw = (clksor & 0x007c0000) >> 18;
248 /* symbols/hblank - algorithm taken from comments in tegra driver */
249 value = vblanke + vactive - vblanks - 7;
250 value = value * link_bw;
252 value = value - (3 * !!(dpctrl & 0x00004000)) - (12 / link_nr);
253 nvkm_mask(device, 0x616620 + hoff, 0x0000ffff, value);
255 /* symbols/vblank - algorithm taken from comments in tegra driver */
256 value = vblanks - vblanke - 25;
257 value = value * link_bw;
259 value = value - ((36 / link_nr) + 3) - 1;
260 nvkm_mask(device, 0x616624 + hoff, 0x00ffffff, value);
263 if ((conf & 0x3c0) == 0x180) bits = 30;
264 else if ((conf & 0x3c0) == 0x140) bits = 24;
266 datarate = (pclk * bits) / 8;
270 do_div(ratio, link_nr * link_bw);
272 value = (symbol - ratio) * TU;
274 do_div(value, symbol);
275 do_div(value, symbol);
280 nvkm_wr32(device, 0x616610 + hoff, value);
284 gf119_disp_intr_unk2_2(struct nv50_disp *disp, int head)
286 struct nvkm_device *device = disp->base.engine.subdev.device;
287 struct nvkm_output *outp;
288 u32 pclk = nvkm_rd32(device, 0x660450 + (head * 0x300)) / 1000;
289 u32 conf, addr, data;
291 outp = exec_clkcmp(disp, head, 0xff, pclk, &conf);
295 /* see note in nv50_disp_intr_unk20_2() */
296 if (outp->info.type == DCB_OUTPUT_DP) {
297 u32 sync = nvkm_rd32(device, 0x660404 + (head * 0x300));
298 switch ((sync & 0x000003c0) >> 6) {
299 case 6: pclk = pclk * 30; break;
300 case 5: pclk = pclk * 24; break;
307 if (nvkm_output_dp_train(outp, pclk))
308 OUTP_ERR(outp, "link not trained before attach");
310 if (disp->func->sor.magic)
311 disp->func->sor.magic(outp);
314 exec_clkcmp(disp, head, 0, pclk, &conf);
316 if (outp->info.type == DCB_OUTPUT_ANALOG) {
317 addr = 0x612280 + (ffs(outp->info.or) - 1) * 0x800;
320 addr = 0x612300 + (ffs(outp->info.or) - 1) * 0x800;
321 data = (conf & 0x0100) ? 0x00000101 : 0x00000000;
322 switch (outp->info.type) {
323 case DCB_OUTPUT_TMDS:
324 nvkm_mask(device, addr, 0x007c0000, 0x00280000);
327 gf119_disp_intr_unk2_2_tu(disp, head, &outp->info);
334 nvkm_mask(device, addr, 0x00000707, data);
338 gf119_disp_intr_unk4_0(struct nv50_disp *disp, int head)
340 struct nvkm_device *device = disp->base.engine.subdev.device;
341 u32 pclk = nvkm_rd32(device, 0x660450 + (head * 0x300)) / 1000;
344 exec_clkcmp(disp, head, 1, pclk, &conf);
348 gf119_disp_super(struct work_struct *work)
350 struct nv50_disp *disp =
351 container_of(work, struct nv50_disp, supervisor);
352 struct nvkm_subdev *subdev = &disp->base.engine.subdev;
353 struct nvkm_device *device = subdev->device;
354 struct nvkm_head *head;
357 nvkm_debug(subdev, "supervisor %d\n", ffs(disp->super));
358 list_for_each_entry(head, &disp->base.head, head) {
359 mask[head->id] = nvkm_rd32(device, 0x6101d4 + (head->id * 0x800));
360 HEAD_DBG(head, "%08x", mask[head->id]);
363 if (disp->super & 0x00000001) {
364 nv50_disp_chan_mthd(disp->chan[0], NV_DBG_DEBUG);
365 list_for_each_entry(head, &disp->base.head, head) {
366 if (!(mask[head->id] & 0x00001000))
368 nvkm_debug(subdev, "supervisor 1.0 - head %d\n", head->id);
369 gf119_disp_intr_unk1_0(disp, head->id);
372 if (disp->super & 0x00000002) {
373 list_for_each_entry(head, &disp->base.head, head) {
374 if (!(mask[head->id] & 0x00001000))
376 nvkm_debug(subdev, "supervisor 2.0 - head %d\n", head->id);
377 gf119_disp_intr_unk2_0(disp, head->id);
379 list_for_each_entry(head, &disp->base.head, head) {
380 if (!(mask[head->id] & 0x00010000))
382 nvkm_debug(subdev, "supervisor 2.1 - head %d\n", head->id);
383 gf119_disp_intr_unk2_1(disp, head->id);
385 list_for_each_entry(head, &disp->base.head, head) {
386 if (!(mask[head->id] & 0x00001000))
388 nvkm_debug(subdev, "supervisor 2.2 - head %d\n", head->id);
389 gf119_disp_intr_unk2_2(disp, head->id);
392 if (disp->super & 0x00000004) {
393 list_for_each_entry(head, &disp->base.head, head) {
394 if (!(mask[head->id] & 0x00001000))
396 nvkm_debug(subdev, "supervisor 3.0 - head %d\n", head->id);
397 gf119_disp_intr_unk4_0(disp, head->id);
401 list_for_each_entry(head, &disp->base.head, head)
402 nvkm_wr32(device, 0x6101d4 + (head->id * 0x800), 0x00000000);
403 nvkm_wr32(device, 0x6101d0, 0x80000000);
407 gf119_disp_intr_error(struct nv50_disp *disp, int chid)
409 struct nvkm_subdev *subdev = &disp->base.engine.subdev;
410 struct nvkm_device *device = subdev->device;
411 u32 mthd = nvkm_rd32(device, 0x6101f0 + (chid * 12));
412 u32 data = nvkm_rd32(device, 0x6101f4 + (chid * 12));
413 u32 unkn = nvkm_rd32(device, 0x6101f8 + (chid * 12));
415 nvkm_error(subdev, "chid %d mthd %04x data %08x %08x %08x\n",
416 chid, (mthd & 0x0000ffc), data, mthd, unkn);
418 if (chid < ARRAY_SIZE(disp->chan)) {
419 switch (mthd & 0xffc) {
421 nv50_disp_chan_mthd(disp->chan[chid], NV_DBG_ERROR);
428 nvkm_wr32(device, 0x61009c, (1 << chid));
429 nvkm_wr32(device, 0x6101f0 + (chid * 12), 0x90000000);
433 gf119_disp_intr(struct nv50_disp *disp)
435 struct nvkm_subdev *subdev = &disp->base.engine.subdev;
436 struct nvkm_device *device = subdev->device;
437 struct nvkm_head *head;
438 u32 intr = nvkm_rd32(device, 0x610088);
440 if (intr & 0x00000001) {
441 u32 stat = nvkm_rd32(device, 0x61008c);
443 int chid = __ffs(stat); stat &= ~(1 << chid);
444 nv50_disp_chan_uevent_send(disp, chid);
445 nvkm_wr32(device, 0x61008c, 1 << chid);
450 if (intr & 0x00000002) {
451 u32 stat = nvkm_rd32(device, 0x61009c);
452 int chid = ffs(stat) - 1;
454 disp->func->intr_error(disp, chid);
458 if (intr & 0x00100000) {
459 u32 stat = nvkm_rd32(device, 0x6100ac);
460 if (stat & 0x00000007) {
461 disp->super = (stat & 0x00000007);
462 schedule_work(&disp->supervisor);
463 nvkm_wr32(device, 0x6100ac, disp->super);
468 nvkm_warn(subdev, "intr24 %08x\n", stat);
469 nvkm_wr32(device, 0x6100ac, stat);
475 list_for_each_entry(head, &disp->base.head, head) {
476 const u32 hoff = head->id * 0x800;
477 u32 mask = 0x01000000 << head->id;
479 u32 stat = nvkm_rd32(device, 0x6100bc + hoff);
480 if (stat & 0x00000001)
481 nvkm_disp_vblank(&disp->base, head->id);
482 nvkm_mask(device, 0x6100bc + hoff, 0, 0);
483 nvkm_rd32(device, 0x6100c0 + hoff);
489 gf119_disp_new_(const struct nv50_disp_func *func, struct nvkm_device *device,
490 int index, struct nvkm_disp **pdisp)
492 u32 heads = nvkm_rd32(device, 0x022448);
493 return nv50_disp_new_(func, device, index, heads, pdisp);
496 static const struct nv50_disp_func
498 .intr = gf119_disp_intr,
499 .intr_error = gf119_disp_intr_error,
500 .uevent = &gf119_disp_chan_uevent,
501 .super = gf119_disp_super,
502 .root = &gf119_disp_root_oclass,
503 .head.new = gf119_head_new,
504 .outp.internal.crt = nv50_dac_output_new,
505 .outp.internal.tmds = nv50_sor_output_new,
506 .outp.internal.lvds = nv50_sor_output_new,
507 .outp.internal.dp = gf119_sor_dp_new,
509 .dac.power = nv50_dac_power,
510 .dac.sense = nv50_dac_sense,
512 .sor.power = nv50_sor_power,
513 .sor.hda_eld = gf119_hda_eld,
514 .sor.hdmi = gf119_hdmi_ctrl,
518 gf119_disp_new(struct nvkm_device *device, int index, struct nvkm_disp **pdisp)
520 return gf119_disp_new_(&gf119_disp, device, index, pdisp);