2 * Copyright 2012 Red Hat Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
29 #include <core/client.h>
30 #include <core/enum.h>
31 #include <core/gpuobj.h>
32 #include <subdev/bios.h>
33 #include <subdev/bios/disp.h>
34 #include <subdev/bios/init.h>
35 #include <subdev/bios/pll.h>
36 #include <subdev/devinit.h>
37 #include <subdev/timer.h>
39 static const struct nvkm_disp_oclass *
40 nv50_disp_root_(struct nvkm_disp *base)
42 return nv50_disp(base)->func->root;
46 nv50_disp_intr_(struct nvkm_disp *base)
48 struct nv50_disp *disp = nv50_disp(base);
49 disp->func->intr(disp);
53 nv50_disp_dtor_(struct nvkm_disp *base)
55 struct nv50_disp *disp = nv50_disp(base);
56 nvkm_event_fini(&disp->uevent);
58 destroy_workqueue(disp->wq);
62 static const struct nvkm_disp_func
64 .dtor = nv50_disp_dtor_,
65 .intr = nv50_disp_intr_,
66 .root = nv50_disp_root_,
70 nv50_disp_new_(const struct nv50_disp_func *func, struct nvkm_device *device,
71 int index, int heads, struct nvkm_disp **pdisp)
73 struct nv50_disp *disp;
76 if (!(disp = kzalloc(sizeof(*disp), GFP_KERNEL)))
81 ret = nvkm_disp_ctor(&nv50_disp_, device, index, &disp->base);
85 disp->wq = create_singlethread_workqueue("nvkm-disp");
88 INIT_WORK(&disp->supervisor, func->super);
90 for (i = 0; func->head.new && i < heads; i++) {
91 ret = func->head.new(&disp->base, i);
96 for (i = 0; func->dac.new && i < func->dac.nr; i++) {
97 ret = func->dac.new(&disp->base, i);
102 for (i = 0; func->pior.new && i < func->pior.nr; i++) {
103 ret = func->pior.new(&disp->base, i);
108 for (i = 0; func->sor.new && i < func->sor.nr; i++) {
109 ret = func->sor.new(&disp->base, i);
114 return nvkm_event_init(func->uevent, 1, 1 + (heads * 4), &disp->uevent);
118 nv50_disp_super_iedt(struct nvkm_head *head, struct nvkm_outp *outp,
119 u8 *ver, u8 *hdr, u8 *cnt, u8 *len,
120 struct nvbios_outp *iedt)
122 struct nvkm_bios *bios = head->disp->engine.subdev.device->bios;
123 const u8 l = ffs(outp->info.link);
124 const u16 t = outp->info.hasht;
125 const u16 m = (0x0100 << head->id) | (l << 6) | outp->info.or;
126 u32 data = nvbios_outp_match(bios, t, m, ver, hdr, cnt, len, iedt);
128 OUTP_DBG(outp, "missing IEDT for %04x:%04x", t, m);
133 nv50_disp_super_ied_off(struct nvkm_head *head, struct nvkm_ior *ior, int id)
135 struct nvkm_outp *outp = ior->arm.outp;
136 struct nvbios_outp iedt;
137 u8 ver, hdr, cnt, len;
141 IOR_DBG(ior, "nothing attached");
145 data = nv50_disp_super_iedt(head, outp, &ver, &hdr, &cnt, &len, &iedt);
149 nvbios_init(&head->disp->engine.subdev, iedt.script[id],
150 init.outp = &outp->info;
152 init.link = ior->arm.link;
153 init.head = head->id;
157 static struct nvkm_ior *
158 nv50_disp_super_ior_arm(struct nvkm_head *head)
160 struct nvkm_ior *ior;
161 list_for_each_entry(ior, &head->disp->ior, head) {
162 if (ior->arm.head & (1 << head->id)) {
163 HEAD_DBG(head, "on %s", ior->name);
167 HEAD_DBG(head, "nothing attached");
171 static struct nvkm_output *
172 exec_lookup(struct nv50_disp *disp, int head, int or, u32 ctrl,
173 u32 *data, u8 *ver, u8 *hdr, u8 *cnt, u8 *len,
174 struct nvbios_outp *info)
176 struct nvkm_subdev *subdev = &disp->base.engine.subdev;
177 struct nvkm_bios *bios = subdev->device->bios;
178 struct nvkm_output *outp;
182 type = DCB_OUTPUT_ANALOG;
186 switch (ctrl & 0x00000f00) {
187 case 0x00000000: type = DCB_OUTPUT_LVDS; mask = 1; break;
188 case 0x00000100: type = DCB_OUTPUT_TMDS; mask = 1; break;
189 case 0x00000200: type = DCB_OUTPUT_TMDS; mask = 2; break;
190 case 0x00000500: type = DCB_OUTPUT_TMDS; mask = 3; break;
191 case 0x00000800: type = DCB_OUTPUT_DP; mask = 1; break;
192 case 0x00000900: type = DCB_OUTPUT_DP; mask = 2; break;
194 nvkm_error(subdev, "unknown SOR mc %08x\n", ctrl);
202 switch (ctrl & 0x00000f00) {
203 case 0x00000000: type |= disp->pior.type[or]; break;
205 nvkm_error(subdev, "unknown PIOR mc %08x\n", ctrl);
210 mask = 0x00c0 & (mask << 6);
211 mask |= 0x0001 << or;
212 mask |= 0x0100 << head;
214 list_for_each_entry(outp, &disp->base.outp, head) {
215 if ((outp->info.hasht & 0xff) == type &&
216 (outp->info.hashm & mask) == mask) {
217 *data = nvbios_outp_match(bios, outp->info.hasht, mask,
218 ver, hdr, cnt, len, info);
228 static struct nvkm_output *
229 exec_script(struct nv50_disp *disp, int head, int id)
231 struct nvkm_subdev *subdev = &disp->base.engine.subdev;
232 struct nvkm_device *device = subdev->device;
233 struct nvkm_bios *bios = device->bios;
234 struct nvkm_output *outp;
235 struct nvbios_outp info;
236 u8 ver, hdr, cnt, len;
242 for (i = 0; !(ctrl & (1 << head)) && i < disp->func->dac.nr; i++)
243 ctrl = nvkm_rd32(device, 0x610b5c + (i * 8));
246 if (!(ctrl & (1 << head))) {
247 if (device->chipset < 0x90 ||
248 device->chipset == 0x92 ||
249 device->chipset == 0xa0) {
254 for (i = 0; !(ctrl & (1 << head)) && i < disp->func->sor.nr; i++)
255 ctrl = nvkm_rd32(device, reg + (i * 8));
260 if (!(ctrl & (1 << head))) {
261 for (i = 0; !(ctrl & (1 << head)) && i < disp->func->pior.nr; i++)
262 ctrl = nvkm_rd32(device, 0x610b84 + (i * 8));
266 if (!(ctrl & (1 << head)))
270 outp = exec_lookup(disp, head, i, ctrl, &data, &ver, &hdr, &cnt, &len, &info);
272 struct nvbios_init init = {
275 .offset = info.script[id],
287 static struct nvkm_output *
288 exec_clkcmp(struct nv50_disp *disp, int head, int id, u32 pclk, u32 *conf)
290 struct nvkm_subdev *subdev = &disp->base.engine.subdev;
291 struct nvkm_device *device = subdev->device;
292 struct nvkm_bios *bios = device->bios;
293 struct nvkm_output *outp;
294 struct nvbios_outp info1;
295 struct nvbios_ocfg info2;
296 u8 ver, hdr, cnt, len;
302 for (i = 0; !(ctrl & (1 << head)) && i < disp->func->dac.nr; i++)
303 ctrl = nvkm_rd32(device, 0x610b58 + (i * 8));
306 if (!(ctrl & (1 << head))) {
307 if (device->chipset < 0x90 ||
308 device->chipset == 0x92 ||
309 device->chipset == 0xa0) {
314 for (i = 0; !(ctrl & (1 << head)) && i < disp->func->sor.nr; i++)
315 ctrl = nvkm_rd32(device, reg + (i * 8));
320 if (!(ctrl & (1 << head))) {
321 for (i = 0; !(ctrl & (1 << head)) && i < disp->func->pior.nr; i++)
322 ctrl = nvkm_rd32(device, 0x610b80 + (i * 8));
326 if (!(ctrl & (1 << head)))
330 outp = exec_lookup(disp, head, i, ctrl, &data, &ver, &hdr, &cnt, &len, &info1);
334 *conf = (ctrl & 0x00000f00) >> 8;
335 if (outp->info.location == 0) {
336 switch (outp->info.type) {
337 case DCB_OUTPUT_TMDS:
341 case DCB_OUTPUT_LVDS:
342 *conf |= disp->sor.lvdsconf;
348 *conf = (ctrl & 0x00000f00) >> 8;
352 data = nvbios_ocfg_match(bios, data, *conf & 0xff, *conf >> 8,
353 &ver, &hdr, &cnt, &len, &info2);
354 if (data && id < 0xff) {
355 data = nvbios_oclk_match(bios, info2.clkcmp[id], pclk);
357 struct nvbios_init init = {
374 nv50_disp_intr_unk40_0(struct nv50_disp *disp, int head)
376 struct nvkm_device *device = disp->base.engine.subdev.device;
377 struct nvkm_output *outp;
378 u32 pclk = nvkm_rd32(device, 0x610ad0 + (head * 0x540)) & 0x3fffff;
381 outp = exec_clkcmp(disp, head, 1, pclk, &conf);
385 nv50_disp_dptmds_war_3(disp, &outp->info);
389 nv50_disp_intr_unk20_2_dp(struct nv50_disp *disp, int head,
390 struct dcb_output *outp, u32 pclk)
392 struct nvkm_subdev *subdev = &disp->base.engine.subdev;
393 struct nvkm_device *device = subdev->device;
394 const int link = !(outp->sorconf.link & 1);
395 const int or = ffs(outp->or) - 1;
396 const u32 soff = ( or * 0x800);
397 const u32 loff = (link * 0x080) + soff;
398 const u32 ctrl = nvkm_rd32(device, 0x610794 + (or * 8));
399 const u32 symbol = 100000;
400 const s32 vactive = nvkm_rd32(device, 0x610af8 + (head * 0x540)) & 0xffff;
401 const s32 vblanke = nvkm_rd32(device, 0x610ae8 + (head * 0x540)) & 0xffff;
402 const s32 vblanks = nvkm_rd32(device, 0x610af0 + (head * 0x540)) & 0xffff;
403 u32 dpctrl = nvkm_rd32(device, 0x61c10c + loff);
404 u32 clksor = nvkm_rd32(device, 0x614300 + soff);
405 int bestTU = 0, bestVTUi = 0, bestVTUf = 0, bestVTUa = 0;
406 int TU, VTUi, VTUf, VTUa;
407 u64 link_data_rate, link_ratio, unk;
408 u32 best_diff = 64 * symbol;
409 u32 link_nr, link_bw, bits;
412 link_bw = (clksor & 0x000c0000) ? 270000 : 162000;
413 link_nr = hweight32(dpctrl & 0x000f0000);
415 /* symbols/hblank - algorithm taken from comments in tegra driver */
416 value = vblanke + vactive - vblanks - 7;
417 value = value * link_bw;
419 value = value - (3 * !!(dpctrl & 0x00004000)) - (12 / link_nr);
420 nvkm_mask(device, 0x61c1e8 + soff, 0x0000ffff, value);
422 /* symbols/vblank - algorithm taken from comments in tegra driver */
423 value = vblanks - vblanke - 25;
424 value = value * link_bw;
426 value = value - ((36 / link_nr) + 3) - 1;
427 nvkm_mask(device, 0x61c1ec + soff, 0x00ffffff, value);
429 /* watermark / activesym */
430 if ((ctrl & 0xf0000) == 0x60000) bits = 30;
431 else if ((ctrl & 0xf0000) == 0x50000) bits = 24;
434 link_data_rate = (pclk * bits / 8) / link_nr;
436 /* calculate ratio of packed data rate to link symbol rate */
437 link_ratio = link_data_rate * symbol;
438 do_div(link_ratio, link_bw);
440 for (TU = 64; TU >= 32; TU--) {
441 /* calculate average number of valid symbols in each TU */
442 u32 tu_valid = link_ratio * TU;
445 /* find a hw representation for the fraction.. */
446 VTUi = tu_valid / symbol;
447 calc = VTUi * symbol;
448 diff = tu_valid - calc;
450 if (diff >= (symbol / 2)) {
451 VTUf = symbol / (symbol - diff);
452 if (symbol - (VTUf * diff))
457 calc += symbol - (symbol / VTUf);
465 VTUf = min((int)(symbol / diff), 15);
466 calc += symbol / VTUf;
469 diff = calc - tu_valid;
471 /* no remainder, but the hw doesn't like the fractional
472 * part to be zero. decrement the integer part and
473 * have the fraction add a whole symbol back
480 if (diff < best_diff) {
492 nvkm_error(subdev, "unable to find suitable dp config\n");
496 /* XXX close to vbios numbers, but not right */
497 unk = (symbol - link_ratio) * bestTU;
503 nvkm_mask(device, 0x61c10c + loff, 0x000001fc, bestTU << 2);
504 nvkm_mask(device, 0x61c128 + loff, 0x010f7f3f, bestVTUa << 24 |
506 bestVTUi << 8 | unk);
510 nv50_disp_intr_unk20_2(struct nv50_disp *disp, int head)
512 struct nvkm_device *device = disp->base.engine.subdev.device;
513 struct nvkm_output *outp;
514 u32 pclk = nvkm_rd32(device, 0x610ad0 + (head * 0x540)) & 0x3fffff;
515 u32 hval, hreg = 0x614200 + (head * 0x800);
519 outp = exec_clkcmp(disp, head, 0xff, pclk, &conf);
523 /* we allow both encoder attach and detach operations to occur
524 * within a single supervisor (ie. modeset) sequence. the
525 * encoder detach scripts quite often switch off power to the
526 * lanes, which requires the link to be re-trained.
528 * this is not generally an issue as the sink "must" (heh)
529 * signal an irq when it's lost sync so the driver can
532 * however, on some boards, if one does not configure at least
533 * the gpu side of the link *before* attaching, then various
534 * things can go horribly wrong (PDISP disappearing from mmio,
535 * third supervisor never happens, etc).
537 * the solution is simply to retrain here, if necessary. last
538 * i checked, the binary driver userspace does not appear to
539 * trigger this situation (it forces an UPDATE between steps).
541 if (outp->info.type == DCB_OUTPUT_DP) {
542 u32 soff = (ffs(outp->info.or) - 1) * 0x08;
545 if (outp->info.location == 0) {
546 ctrl = nvkm_rd32(device, 0x610794 + soff);
549 ctrl = nvkm_rd32(device, 0x610b80 + soff);
553 switch ((ctrl & 0x000f0000) >> 16) {
554 case 6: datarate = pclk * 30; break;
555 case 5: datarate = pclk * 24; break;
558 datarate = pclk * 18;
562 if (nvkm_output_dp_train(outp, datarate / soff))
563 OUTP_ERR(outp, "link not trained before attach");
566 exec_clkcmp(disp, head, 0, pclk, &conf);
568 if (!outp->info.location && outp->info.type == DCB_OUTPUT_ANALOG) {
569 oreg = 0x614280 + (ffs(outp->info.or) - 1) * 0x800;
574 if (!outp->info.location) {
575 if (outp->info.type == DCB_OUTPUT_DP)
576 nv50_disp_intr_unk20_2_dp(disp, head, &outp->info, pclk);
577 oreg = 0x614300 + (ffs(outp->info.or) - 1) * 0x800;
578 oval = (conf & 0x0100) ? 0x00000101 : 0x00000000;
582 oreg = 0x614380 + (ffs(outp->info.or) - 1) * 0x800;
588 nvkm_mask(device, hreg, 0x0000000f, hval);
589 nvkm_mask(device, oreg, mask, oval);
591 nv50_disp_dptmds_war_2(disp, &outp->info);
595 nv50_disp_intr_unk20_1(struct nv50_disp *disp, int head)
597 struct nvkm_device *device = disp->base.engine.subdev.device;
598 struct nvkm_devinit *devinit = device->devinit;
599 u32 pclk = nvkm_rd32(device, 0x610ad0 + (head * 0x540)) & 0x3fffff;
601 nvkm_devinit_pll_set(devinit, PLL_VPLL0 + head, pclk);
605 nv50_disp_intr_unk20_0(struct nv50_disp *disp, int head)
607 struct nvkm_subdev *subdev = &disp->base.engine.subdev;
608 struct nvkm_output *outp = exec_script(disp, head, 2);
610 /* the binary driver does this outside of the supervisor handling
611 * (after the third supervisor from a detach). we (currently?)
612 * allow both detach/attach to happen in the same set of
613 * supervisor interrupts, so it would make sense to execute this
614 * (full power down?) script after all the detach phases of the
615 * supervisor handling. like with training if needed from the
616 * second supervisor, nvidia doesn't do this, so who knows if it's
617 * entirely safe, but it does appear to work..
619 * without this script being run, on some configurations i've
620 * seen, switching from DP to TMDS on a DP connector may result
621 * in a blank screen (SOR_PWR off/on can restore it)
623 if (outp && outp->info.type == DCB_OUTPUT_DP) {
624 struct nvkm_output_dp *outpdp = nvkm_output_dp(outp);
625 struct nvbios_init init = {
627 .bios = subdev->device->bios,
630 .offset = outpdp->info.script[4],
634 atomic_set(&outpdp->lt.done, 0);
640 nv50_disp_super_1_0(struct nv50_disp *disp, struct nvkm_head *head)
642 struct nvkm_ior *ior;
644 /* Determine which OR, if any, we're detaching from the head. */
645 HEAD_DBG(head, "supervisor 1.0");
646 ior = nv50_disp_super_ior_arm(head);
650 /* Execute OffInt1 IED script. */
651 nv50_disp_super_ied_off(head, ior, 1);
655 nv50_disp_super_1(struct nv50_disp *disp)
657 struct nvkm_head *head;
658 struct nvkm_ior *ior;
660 list_for_each_entry(head, &disp->base.head, head) {
661 head->func->state(head, &head->arm);
662 head->func->state(head, &head->asy);
665 list_for_each_entry(ior, &disp->base.ior, head) {
666 ior->func->state(ior, &ior->arm);
667 ior->func->state(ior, &ior->asy);
672 nv50_disp_super(struct work_struct *work)
674 struct nv50_disp *disp =
675 container_of(work, struct nv50_disp, supervisor);
676 struct nvkm_subdev *subdev = &disp->base.engine.subdev;
677 struct nvkm_device *device = subdev->device;
678 struct nvkm_head *head;
679 u32 super = nvkm_rd32(device, 0x610030);
681 nvkm_debug(subdev, "supervisor %08x %08x\n", disp->super, super);
683 if (disp->super & 0x00000010) {
684 nv50_disp_chan_mthd(disp->chan[0], NV_DBG_DEBUG);
685 nv50_disp_super_1(disp);
686 list_for_each_entry(head, &disp->base.head, head) {
687 if (!(super & (0x00000020 << head->id)))
689 if (!(super & (0x00000080 << head->id)))
691 nv50_disp_super_1_0(disp, head);
694 if (disp->super & 0x00000020) {
695 list_for_each_entry(head, &disp->base.head, head) {
696 if (!(super & (0x00000080 << head->id)))
698 nv50_disp_intr_unk20_0(disp, head->id);
700 nvkm_outp_route(&disp->base);
701 list_for_each_entry(head, &disp->base.head, head) {
702 if (!(super & (0x00000200 << head->id)))
704 nv50_disp_intr_unk20_1(disp, head->id);
706 list_for_each_entry(head, &disp->base.head, head) {
707 if (!(super & (0x00000080 << head->id)))
709 nv50_disp_intr_unk20_2(disp, head->id);
712 if (disp->super & 0x00000040) {
713 list_for_each_entry(head, &disp->base.head, head) {
714 if (!(super & (0x00000080 << head->id)))
716 nv50_disp_intr_unk40_0(disp, head->id);
718 nv50_disp_update_sppll1(disp);
721 nvkm_wr32(device, 0x610030, 0x80000000);
724 static const struct nvkm_enum
725 nv50_disp_intr_error_type[] = {
726 { 3, "ILLEGAL_MTHD" },
727 { 4, "INVALID_VALUE" },
728 { 5, "INVALID_STATE" },
729 { 7, "INVALID_HANDLE" },
733 static const struct nvkm_enum
734 nv50_disp_intr_error_code[] = {
740 nv50_disp_intr_error(struct nv50_disp *disp, int chid)
742 struct nvkm_subdev *subdev = &disp->base.engine.subdev;
743 struct nvkm_device *device = subdev->device;
744 u32 data = nvkm_rd32(device, 0x610084 + (chid * 0x08));
745 u32 addr = nvkm_rd32(device, 0x610080 + (chid * 0x08));
746 u32 code = (addr & 0x00ff0000) >> 16;
747 u32 type = (addr & 0x00007000) >> 12;
748 u32 mthd = (addr & 0x00000ffc);
749 const struct nvkm_enum *ec, *et;
751 et = nvkm_enum_find(nv50_disp_intr_error_type, type);
752 ec = nvkm_enum_find(nv50_disp_intr_error_code, code);
755 "ERROR %d [%s] %02x [%s] chid %d mthd %04x data %08x\n",
756 type, et ? et->name : "", code, ec ? ec->name : "",
759 if (chid < ARRAY_SIZE(disp->chan)) {
762 nv50_disp_chan_mthd(disp->chan[chid], NV_DBG_ERROR);
769 nvkm_wr32(device, 0x610020, 0x00010000 << chid);
770 nvkm_wr32(device, 0x610080 + (chid * 0x08), 0x90000000);
774 nv50_disp_intr(struct nv50_disp *disp)
776 struct nvkm_device *device = disp->base.engine.subdev.device;
777 u32 intr0 = nvkm_rd32(device, 0x610020);
778 u32 intr1 = nvkm_rd32(device, 0x610024);
780 while (intr0 & 0x001f0000) {
781 u32 chid = __ffs(intr0 & 0x001f0000) - 16;
782 nv50_disp_intr_error(disp, chid);
783 intr0 &= ~(0x00010000 << chid);
786 while (intr0 & 0x0000001f) {
787 u32 chid = __ffs(intr0 & 0x0000001f);
788 nv50_disp_chan_uevent_send(disp, chid);
789 intr0 &= ~(0x00000001 << chid);
792 if (intr1 & 0x00000004) {
793 nvkm_disp_vblank(&disp->base, 0);
794 nvkm_wr32(device, 0x610024, 0x00000004);
797 if (intr1 & 0x00000008) {
798 nvkm_disp_vblank(&disp->base, 1);
799 nvkm_wr32(device, 0x610024, 0x00000008);
802 if (intr1 & 0x00000070) {
803 disp->super = (intr1 & 0x00000070);
804 queue_work(disp->wq, &disp->supervisor);
805 nvkm_wr32(device, 0x610024, disp->super);
809 static const struct nv50_disp_func
811 .intr = nv50_disp_intr,
812 .uevent = &nv50_disp_chan_uevent,
813 .super = nv50_disp_super,
814 .root = &nv50_disp_root_oclass,
815 .head.new = nv50_head_new,
816 .dac = { .nr = 3, .new = nv50_dac_new },
817 .sor = { .nr = 2, .new = nv50_sor_new },
818 .pior = { .nr = 3, .new = nv50_pior_new },
822 nv50_disp_new(struct nvkm_device *device, int index, struct nvkm_disp **pdisp)
824 return nv50_disp_new_(&nv50_disp, device, index, 2, pdisp);