drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c

   1 /*
   2  * Copyright 2012 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24 #include "gk104.h"
  25 #include "changk104.h"
  26
  27 #include <core/client.h>
  28 #include <core/gpuobj.h>
  29 #include <subdev/bar.h>
  30 #include <subdev/top.h>
  31 #include <engine/sw.h>
  32
  33 #include <nvif/class.h>
  34
  35 static int
  36 gk104_fifo_class_get(struct nvkm_fifo *base, int index,
  37                      const struct nvkm_fifo_chan_oclass **psclass)
  38 {
  39         struct gk104_fifo *fifo = gk104_fifo(base);
  40         int c = 0;
  41
  42         while ((*psclass = fifo->func->chan[c])) {
  43                 if (c++ == index)
  44                         return 0;
  45         }
  46
  47         return c;
  48 }
  49
  50 static void
  51 gk104_fifo_uevent_fini(struct nvkm_fifo *fifo)
  52 {
  53         struct nvkm_device *device = fifo->engine.subdev.device;
  54         nvkm_mask(device, 0x002140, 0x80000000, 0x00000000);
  55 }
  56
  57 static void
  58 gk104_fifo_uevent_init(struct nvkm_fifo *fifo)
  59 {
  60         struct nvkm_device *device = fifo->engine.subdev.device;
  61         nvkm_mask(device, 0x002140, 0x80000000, 0x80000000);
  62 }
  63
  64 void
  65 gk104_fifo_runlist_commit(struct gk104_fifo *fifo, int runl)
  66 {
  67         struct gk104_fifo_chan *chan;
  68         struct nvkm_subdev *subdev = &fifo->base.engine.subdev;
  69         struct nvkm_device *device = subdev->device;
  70         struct nvkm_memory *mem;
  71         int nr = 0;
  72         int target;
  73
  74         mutex_lock(&subdev->mutex);
  75         mem = fifo->runlist[runl].mem[fifo->runlist[runl].next];
  76         fifo->runlist[runl].next = !fifo->runlist[runl].next;
  77
  78         nvkm_kmap(mem);
  79         list_for_each_entry(chan, &fifo->runlist[runl].chan, head) {
  80                 nvkm_wo32(mem, (nr * 8) + 0, chan->base.chid);
  81                 nvkm_wo32(mem, (nr * 8) + 4, 0x00000000);
  82                 nr++;
  83         }
  84         nvkm_done(mem);
  85
  86         if (nvkm_memory_target(mem) == NVKM_MEM_TARGET_VRAM)
  87                 target = 0;
  88         else
  89                 target = 3;
  90
  91         nvkm_wr32(device, 0x002270, (nvkm_memory_addr(mem) >> 12) |
  92                                     (target << 28));
  93         nvkm_wr32(device, 0x002274, (runl << 20) | nr);
  94
  95         if (wait_event_timeout(fifo->runlist[runl].wait,
  96                                !(nvkm_rd32(device, 0x002284 + (runl * 0x08))
  97                                        & 0x00100000),
  98                                msecs_to_jiffies(2000)) == 0)
  99                 nvkm_error(subdev, "runlist %d update timeout\n", runl);
 100         mutex_unlock(&subdev->mutex);
 101 }
 102
 103 void
 104 gk104_fifo_runlist_remove(struct gk104_fifo *fifo, struct gk104_fifo_chan *chan)
 105 {
 106         mutex_lock(&fifo->base.engine.subdev.mutex);
 107         list_del_init(&chan->head);
 108         mutex_unlock(&fifo->base.engine.subdev.mutex);
 109 }
 110
 111 void
 112 gk104_fifo_runlist_insert(struct gk104_fifo *fifo, struct gk104_fifo_chan *chan)
 113 {
 114         mutex_lock(&fifo->base.engine.subdev.mutex);
 115         list_add_tail(&chan->head, &fifo->runlist[chan->runl].chan);
 116         mutex_unlock(&fifo->base.engine.subdev.mutex);
 117 }
 118
 119 static void
 120 gk104_fifo_recover_work(struct work_struct *w)
 121 {
 122         struct gk104_fifo *fifo = container_of(w, typeof(*fifo), recover.work);
 123         struct nvkm_device *device = fifo->base.engine.subdev.device;
 124         struct nvkm_engine *engine;
 125         unsigned long flags;
 126         u32 engm, runm, todo;
 127         int engn, runl;
 128
 129         spin_lock_irqsave(&fifo->base.lock, flags);
 130         runm = fifo->recover.runm;
 131         engm = fifo->recover.engm;
 132         fifo->recover.engm = 0;
 133         fifo->recover.runm = 0;
 134         spin_unlock_irqrestore(&fifo->base.lock, flags);
 135
 136         nvkm_mask(device, 0x002630, runm, runm);
 137
 138         for (todo = engm; engn = __ffs(todo), todo; todo &= ~BIT(engn)) {
 139                 if ((engine = fifo->engine[engn].engine)) {
 140                         nvkm_subdev_fini(&engine->subdev, false);
 141                         WARN_ON(nvkm_subdev_init(&engine->subdev));
 142                 }
 143         }
 144
 145         for (todo = runm; runl = __ffs(todo), todo; todo &= ~BIT(runl))
 146                 gk104_fifo_runlist_commit(fifo, runl);
 147
 148         nvkm_wr32(device, 0x00262c, runm);
 149         nvkm_mask(device, 0x002630, runm, 0x00000000);
 150 }
 151
 152 static void
 153 gk104_fifo_recover(struct gk104_fifo *fifo, struct nvkm_engine *engine,
 154                    struct gk104_fifo_chan *chan)
 155 {
 156         struct nvkm_subdev *subdev = &fifo->base.engine.subdev;
 157         struct nvkm_device *device = subdev->device;
 158         u32 chid = chan->base.chid;
 159         int engn;
 160
 161         nvkm_error(subdev, "%s engine fault on channel %d, recovering...\n",
 162                    nvkm_subdev_name[engine->subdev.index], chid);
 163         assert_spin_locked(&fifo->base.lock);
 164
 165         nvkm_mask(device, 0x800004 + (chid * 0x08), 0x00000800, 0x00000800);
 166         list_del_init(&chan->head);
 167         chan->killed = true;
 168
 169         for (engn = 0; engn < fifo->engine_nr; engn++) {
 170                 if (fifo->engine[engn].engine == engine) {
 171                         fifo->recover.engm |= BIT(engn);
 172                         break;
 173                 }
 174         }
 175
 176         fifo->recover.runm |= BIT(chan->runl);
 177         schedule_work(&fifo->recover.work);
 178 }
 179
 180 static const struct nvkm_enum
 181 gk104_fifo_bind_reason[] = {
 182         { 0x01, "BIND_NOT_UNBOUND" },
 183         { 0x02, "SNOOP_WITHOUT_BAR1" },
 184         { 0x03, "UNBIND_WHILE_RUNNING" },
 185         { 0x05, "INVALID_RUNLIST" },
 186         { 0x06, "INVALID_CTX_TGT" },
 187         { 0x0b, "UNBIND_WHILE_PARKED" },
 188         {}
 189 };
 190
 191 static void
 192 gk104_fifo_intr_bind(struct gk104_fifo *fifo)
 193 {
 194         struct nvkm_subdev *subdev = &fifo->base.engine.subdev;
 195         struct nvkm_device *device = subdev->device;
 196         u32 intr = nvkm_rd32(device, 0x00252c);
 197         u32 code = intr & 0x000000ff;
 198         const struct nvkm_enum *en =
 199                 nvkm_enum_find(gk104_fifo_bind_reason, code);
 200
 201         nvkm_error(subdev, "BIND_ERROR %02x [%s]\n", code, en ? en->name : "");
 202 }
 203
 204 static const struct nvkm_enum
 205 gk104_fifo_sched_reason[] = {
 206         { 0x0a, "CTXSW_TIMEOUT" },
 207         {}
 208 };
 209
 210 static void
 211 gk104_fifo_intr_sched_ctxsw(struct gk104_fifo *fifo)
 212 {
 213         struct nvkm_device *device = fifo->base.engine.subdev.device;
 214         struct gk104_fifo_chan *chan;
 215         unsigned long flags;
 216         u32 engn;
 217
 218         spin_lock_irqsave(&fifo->base.lock, flags);
 219         for (engn = 0; engn < fifo->engine_nr; engn++) {
 220                 struct nvkm_engine *engine = fifo->engine[engn].engine;
 221                 int runl = fifo->engine[engn].runl;
 222                 u32 stat = nvkm_rd32(device, 0x002640 + (engn * 0x08));
 223                 u32 busy = (stat & 0x80000000);
 224                 u32 next = (stat & 0x0fff0000) >> 16;
 225                 u32 chsw = (stat & 0x00008000);
 226                 u32 save = (stat & 0x00004000);
 227                 u32 load = (stat & 0x00002000);
 228                 u32 prev = (stat & 0x00000fff);
 229                 u32 chid = load ? next : prev;
 230                 (void)save;
 231
 232                 if (!busy || !chsw)
 233                         continue;
 234
 235                 list_for_each_entry(chan, &fifo->runlist[runl].chan, head) {
 236                         if (chan->base.chid == chid && engine) {
 237                                 gk104_fifo_recover(fifo, engine, chan);
 238                                 break;
 239                         }
 240                 }
 241         }
 242         spin_unlock_irqrestore(&fifo->base.lock, flags);
 243 }
 244
 245 static void
 246 gk104_fifo_intr_sched(struct gk104_fifo *fifo)
 247 {
 248         struct nvkm_subdev *subdev = &fifo->base.engine.subdev;
 249         struct nvkm_device *device = subdev->device;
 250         u32 intr = nvkm_rd32(device, 0x00254c);
 251         u32 code = intr & 0x000000ff;
 252         const struct nvkm_enum *en =
 253                 nvkm_enum_find(gk104_fifo_sched_reason, code);
 254
 255         nvkm_error(subdev, "SCHED_ERROR %02x [%s]\n", code, en ? en->name : "");
 256
 257         switch (code) {
 258         case 0x0a:
 259                 gk104_fifo_intr_sched_ctxsw(fifo);
 260                 break;
 261         default:
 262                 break;
 263         }
 264 }
 265
 266 static void
 267 gk104_fifo_intr_chsw(struct gk104_fifo *fifo)
 268 {
 269         struct nvkm_subdev *subdev = &fifo->base.engine.subdev;
 270         struct nvkm_device *device = subdev->device;
 271         u32 stat = nvkm_rd32(device, 0x00256c);
 272         nvkm_error(subdev, "CHSW_ERROR %08x\n", stat);
 273         nvkm_wr32(device, 0x00256c, stat);
 274 }
 275
 276 static void
 277 gk104_fifo_intr_dropped_fault(struct gk104_fifo *fifo)
 278 {
 279         struct nvkm_subdev *subdev = &fifo->base.engine.subdev;
 280         struct nvkm_device *device = subdev->device;
 281         u32 stat = nvkm_rd32(device, 0x00259c);
 282         nvkm_error(subdev, "DROPPED_MMU_FAULT %08x\n", stat);
 283 }
 284
 285 static void
 286 gk104_fifo_intr_fault(struct gk104_fifo *fifo, int unit)
 287 {
 288         struct nvkm_subdev *subdev = &fifo->base.engine.subdev;
 289         struct nvkm_device *device = subdev->device;
 290         u32 inst = nvkm_rd32(device, 0x002800 + (unit * 0x10));
 291         u32 valo = nvkm_rd32(device, 0x002804 + (unit * 0x10));
 292         u32 vahi = nvkm_rd32(device, 0x002808 + (unit * 0x10));
 293         u32 stat = nvkm_rd32(device, 0x00280c + (unit * 0x10));
 294         u32 gpc    = (stat & 0x1f000000) >> 24;
 295         u32 client = (stat & 0x00001f00) >> 8;
 296         u32 write  = (stat & 0x00000080);
 297         u32 hub    = (stat & 0x00000040);
 298         u32 reason = (stat & 0x0000000f);
 299         const struct nvkm_enum *er, *eu, *ec;
 300         struct nvkm_engine *engine = NULL;
 301         struct nvkm_fifo_chan *chan;
 302         unsigned long flags;
 303         char gpcid[8] = "";
 304
 305         er = nvkm_enum_find(fifo->func->fault.reason, reason);
 306         eu = nvkm_enum_find(fifo->func->fault.engine, unit);
 307         if (hub) {
 308                 ec = nvkm_enum_find(fifo->func->fault.hubclient, client);
 309         } else {
 310                 ec = nvkm_enum_find(fifo->func->fault.gpcclient, client);
 311                 snprintf(gpcid, sizeof(gpcid), "GPC%d/", gpc);
 312         }
 313
 314         if (eu && eu->data2) {
 315                 switch (eu->data2) {
 316                 case NVKM_SUBDEV_BAR:
 317                         nvkm_mask(device, 0x001704, 0x00000000, 0x00000000);
 318                         break;
 319                 case NVKM_SUBDEV_INSTMEM:
 320                         nvkm_mask(device, 0x001714, 0x00000000, 0x00000000);
 321                         break;
 322                 case NVKM_ENGINE_IFB:
 323                         nvkm_mask(device, 0x001718, 0x00000000, 0x00000000);
 324                         break;
 325                 default:
 326                         engine = nvkm_device_engine(device, eu->data2);
 327                         break;
 328                 }
 329         }
 330
 331         chan = nvkm_fifo_chan_inst(&fifo->base, (u64)inst << 12, &flags);
 332
 333         nvkm_error(subdev,
 334                    "%s fault at %010llx engine %02x [%s] client %02x [%s%s] "
 335                    "reason %02x [%s] on channel %d [%010llx %s]\n",
 336                    write ? "write" : "read", (u64)vahi << 32 | valo,
 337                    unit, eu ? eu->name : "", client, gpcid, ec ? ec->name : "",
 338                    reason, er ? er->name : "", chan ? chan->chid : -1,
 339                    (u64)inst << 12,
 340                    chan ? chan->object.client->name : "unknown");
 341
 342         if (engine && chan)
 343                 gk104_fifo_recover(fifo, engine, (void *)chan);
 344         nvkm_fifo_chan_put(&fifo->base, flags, &chan);
 345 }
 346
 347 static const struct nvkm_bitfield gk104_fifo_pbdma_intr_0[] = {
 348         { 0x00000001, "MEMREQ" },
 349         { 0x00000002, "MEMACK_TIMEOUT" },
 350         { 0x00000004, "MEMACK_EXTRA" },
 351         { 0x00000008, "MEMDAT_TIMEOUT" },
 352         { 0x00000010, "MEMDAT_EXTRA" },
 353         { 0x00000020, "MEMFLUSH" },
 354         { 0x00000040, "MEMOP" },
 355         { 0x00000080, "LBCONNECT" },
 356         { 0x00000100, "LBREQ" },
 357         { 0x00000200, "LBACK_TIMEOUT" },
 358         { 0x00000400, "LBACK_EXTRA" },
 359         { 0x00000800, "LBDAT_TIMEOUT" },
 360         { 0x00001000, "LBDAT_EXTRA" },
 361         { 0x00002000, "GPFIFO" },
 362         { 0x00004000, "GPPTR" },
 363         { 0x00008000, "GPENTRY" },
 364         { 0x00010000, "GPCRC" },
 365         { 0x00020000, "PBPTR" },
 366         { 0x00040000, "PBENTRY" },
 367         { 0x00080000, "PBCRC" },
 368         { 0x00100000, "XBARCONNECT" },
 369         { 0x00200000, "METHOD" },
 370         { 0x00400000, "METHODCRC" },
 371         { 0x00800000, "DEVICE" },
 372         { 0x02000000, "SEMAPHORE" },
 373         { 0x04000000, "ACQUIRE" },
 374         { 0x08000000, "PRI" },
 375         { 0x20000000, "NO_CTXSW_SEG" },
 376         { 0x40000000, "PBSEG" },
 377         { 0x80000000, "SIGNATURE" },
 378         {}
 379 };
 380
 381 static void
 382 gk104_fifo_intr_pbdma_0(struct gk104_fifo *fifo, int unit)
 383 {
 384         struct nvkm_subdev *subdev = &fifo->base.engine.subdev;
 385         struct nvkm_device *device = subdev->device;
 386         u32 mask = nvkm_rd32(device, 0x04010c + (unit * 0x2000));
 387         u32 stat = nvkm_rd32(device, 0x040108 + (unit * 0x2000)) & mask;
 388         u32 addr = nvkm_rd32(device, 0x0400c0 + (unit * 0x2000));
 389         u32 data = nvkm_rd32(device, 0x0400c4 + (unit * 0x2000));
 390         u32 chid = nvkm_rd32(device, 0x040120 + (unit * 0x2000)) & 0xfff;
 391         u32 subc = (addr & 0x00070000) >> 16;
 392         u32 mthd = (addr & 0x00003ffc);
 393         u32 show = stat;
 394         struct nvkm_fifo_chan *chan;
 395         unsigned long flags;
 396         char msg[128];
 397
 398         if (stat & 0x00800000) {
 399                 if (device->sw) {
 400                         if (nvkm_sw_mthd(device->sw, chid, subc, mthd, data))
 401                                 show &= ~0x00800000;
 402                 }
 403         }
 404
 405         nvkm_wr32(device, 0x0400c0 + (unit * 0x2000), 0x80600008);
 406
 407         if (show) {
 408                 nvkm_snprintbf(msg, sizeof(msg), gk104_fifo_pbdma_intr_0, show);
 409                 chan = nvkm_fifo_chan_chid(&fifo->base, chid, &flags);
 410                 nvkm_error(subdev, "PBDMA%d: %08x [%s] ch %d [%010llx %s] "
 411                                    "subc %d mthd %04x data %08x\n",
 412                            unit, show, msg, chid, chan ? chan->inst->addr : 0,
 413                            chan ? chan->object.client->name : "unknown",
 414                            subc, mthd, data);
 415                 nvkm_fifo_chan_put(&fifo->base, flags, &chan);
 416         }
 417
 418         nvkm_wr32(device, 0x040108 + (unit * 0x2000), stat);
 419 }
 420
 421 static const struct nvkm_bitfield gk104_fifo_pbdma_intr_1[] = {
 422         { 0x00000001, "HCE_RE_ILLEGAL_OP" },
 423         { 0x00000002, "HCE_RE_ALIGNB" },
 424         { 0x00000004, "HCE_PRIV" },
 425         { 0x00000008, "HCE_ILLEGAL_MTHD" },
 426         { 0x00000010, "HCE_ILLEGAL_CLASS" },
 427         {}
 428 };
 429
 430 static void
 431 gk104_fifo_intr_pbdma_1(struct gk104_fifo *fifo, int unit)
 432 {
 433         struct nvkm_subdev *subdev = &fifo->base.engine.subdev;
 434         struct nvkm_device *device = subdev->device;
 435         u32 mask = nvkm_rd32(device, 0x04014c + (unit * 0x2000));
 436         u32 stat = nvkm_rd32(device, 0x040148 + (unit * 0x2000)) & mask;
 437         u32 chid = nvkm_rd32(device, 0x040120 + (unit * 0x2000)) & 0xfff;
 438         char msg[128];
 439
 440         if (stat) {
 441                 nvkm_snprintbf(msg, sizeof(msg), gk104_fifo_pbdma_intr_1, stat);
 442                 nvkm_error(subdev, "PBDMA%d: %08x [%s] ch %d %08x %08x\n",
 443                            unit, stat, msg, chid,
 444                            nvkm_rd32(device, 0x040150 + (unit * 0x2000)),
 445                            nvkm_rd32(device, 0x040154 + (unit * 0x2000)));
 446         }
 447
 448         nvkm_wr32(device, 0x040148 + (unit * 0x2000), stat);
 449 }
 450
 451 static void
 452 gk104_fifo_intr_runlist(struct gk104_fifo *fifo)
 453 {
 454         struct nvkm_device *device = fifo->base.engine.subdev.device;
 455         u32 mask = nvkm_rd32(device, 0x002a00);
 456         while (mask) {
 457                 int runl = __ffs(mask);
 458                 wake_up(&fifo->runlist[runl].wait);
 459                 nvkm_wr32(device, 0x002a00, 1 << runl);
 460                 mask &= ~(1 << runl);
 461         }
 462 }
 463
 464 static void
 465 gk104_fifo_intr_engine(struct gk104_fifo *fifo)
 466 {
 467         nvkm_fifo_uevent(&fifo->base);
 468 }
 469
 470 static void
 471 gk104_fifo_intr(struct nvkm_fifo *base)
 472 {
 473         struct gk104_fifo *fifo = gk104_fifo(base);
 474         struct nvkm_subdev *subdev = &fifo->base.engine.subdev;
 475         struct nvkm_device *device = subdev->device;
 476         u32 mask = nvkm_rd32(device, 0x002140);
 477         u32 stat = nvkm_rd32(device, 0x002100) & mask;
 478
 479         if (stat & 0x00000001) {
 480                 gk104_fifo_intr_bind(fifo);
 481                 nvkm_wr32(device, 0x002100, 0x00000001);
 482                 stat &= ~0x00000001;
 483         }
 484
 485         if (stat & 0x00000010) {
 486                 nvkm_error(subdev, "PIO_ERROR\n");
 487                 nvkm_wr32(device, 0x002100, 0x00000010);
 488                 stat &= ~0x00000010;
 489         }
 490
 491         if (stat & 0x00000100) {
 492                 gk104_fifo_intr_sched(fifo);
 493                 nvkm_wr32(device, 0x002100, 0x00000100);
 494                 stat &= ~0x00000100;
 495         }
 496
 497         if (stat & 0x00010000) {
 498                 gk104_fifo_intr_chsw(fifo);
 499                 nvkm_wr32(device, 0x002100, 0x00010000);
 500                 stat &= ~0x00010000;
 501         }
 502
 503         if (stat & 0x00800000) {
 504                 nvkm_error(subdev, "FB_FLUSH_TIMEOUT\n");
 505                 nvkm_wr32(device, 0x002100, 0x00800000);
 506                 stat &= ~0x00800000;
 507         }
 508
 509         if (stat & 0x01000000) {
 510                 nvkm_error(subdev, "LB_ERROR\n");
 511                 nvkm_wr32(device, 0x002100, 0x01000000);
 512                 stat &= ~0x01000000;
 513         }
 514
 515         if (stat & 0x08000000) {
 516                 gk104_fifo_intr_dropped_fault(fifo);
 517                 nvkm_wr32(device, 0x002100, 0x08000000);
 518                 stat &= ~0x08000000;
 519         }
 520
 521         if (stat & 0x10000000) {
 522                 u32 mask = nvkm_rd32(device, 0x00259c);
 523                 while (mask) {
 524                         u32 unit = __ffs(mask);
 525                         gk104_fifo_intr_fault(fifo, unit);
 526                         nvkm_wr32(device, 0x00259c, (1 << unit));
 527                         mask &= ~(1 << unit);
 528                 }
 529                 stat &= ~0x10000000;
 530         }
 531
 532         if (stat & 0x20000000) {
 533                 u32 mask = nvkm_rd32(device, 0x0025a0);
 534                 while (mask) {
 535                         u32 unit = __ffs(mask);
 536                         gk104_fifo_intr_pbdma_0(fifo, unit);
 537                         gk104_fifo_intr_pbdma_1(fifo, unit);
 538                         nvkm_wr32(device, 0x0025a0, (1 << unit));
 539                         mask &= ~(1 << unit);
 540                 }
 541                 stat &= ~0x20000000;
 542         }
 543
 544         if (stat & 0x40000000) {
 545                 gk104_fifo_intr_runlist(fifo);
 546                 stat &= ~0x40000000;
 547         }
 548
 549         if (stat & 0x80000000) {
 550                 nvkm_wr32(device, 0x002100, 0x80000000);
 551                 gk104_fifo_intr_engine(fifo);
 552                 stat &= ~0x80000000;
 553         }
 554
 555         if (stat) {
 556                 nvkm_error(subdev, "INTR %08x\n", stat);
 557                 nvkm_mask(device, 0x002140, stat, 0x00000000);
 558                 nvkm_wr32(device, 0x002100, stat);
 559         }
 560 }
 561
 562 static void
 563 gk104_fifo_fini(struct nvkm_fifo *base)
 564 {
 565         struct gk104_fifo *fifo = gk104_fifo(base);
 566         struct nvkm_device *device = fifo->base.engine.subdev.device;
 567         flush_work(&fifo->recover.work);
 568         /* allow mmu fault interrupts, even when we're not using fifo */
 569         nvkm_mask(device, 0x002140, 0x10000000, 0x10000000);
 570 }
 571
 572 static int
 573 gk104_fifo_oneinit(struct nvkm_fifo *base)
 574 {
 575         struct gk104_fifo *fifo = gk104_fifo(base);
 576         struct nvkm_subdev *subdev = &fifo->base.engine.subdev;
 577         struct nvkm_device *device = subdev->device;
 578         struct nvkm_top *top = device->top;
 579         int engn, runl, pbid, ret, i, j;
 580         enum nvkm_devidx engidx;
 581         u32 *map;
 582
 583         /* Determine number of PBDMAs by checking valid enable bits. */
 584         nvkm_wr32(device, 0x000204, 0xffffffff);
 585         fifo->pbdma_nr = hweight32(nvkm_rd32(device, 0x000204));
 586         nvkm_debug(subdev, "%d PBDMA(s)\n", fifo->pbdma_nr);
 587
 588         /* Read PBDMA->runlist(s) mapping from HW. */
 589         if (!(map = kzalloc(sizeof(*map) * fifo->pbdma_nr, GFP_KERNEL)))
 590                 return -ENOMEM;
 591
 592         for (i = 0; i < fifo->pbdma_nr; i++)
 593                 map[i] = nvkm_rd32(device, 0x002390 + (i * 0x04));
 594
 595         /* Determine runlist configuration from topology device info. */
 596         i = 0;
 597         while ((int)(engidx = nvkm_top_engine(top, i++, &runl, &engn)) >= 0) {
 598                 /* Determine which PBDMA handles requests for this engine. */
 599                 for (j = 0, pbid = -1; j < fifo->pbdma_nr; j++) {
 600                         if (map[j] & (1 << runl)) {
 601                                 pbid = j;
 602                                 break;
 603                         }
 604                 }
 605
 606                 nvkm_debug(subdev, "engine %2d: runlist %2d pbdma %2d\n",
 607                            engn, runl, pbid);
 608
 609                 fifo->engine[engn].engine = nvkm_device_engine(device, engidx);
 610                 fifo->engine[engn].runl = runl;
 611                 fifo->engine[engn].pbid = pbid;
 612                 fifo->engine_nr = max(fifo->engine_nr, engn + 1);
 613                 fifo->runlist[runl].engm |= 1 << engn;
 614                 fifo->runlist_nr = max(fifo->runlist_nr, runl + 1);
 615         }
 616
 617         kfree(map);
 618
 619         for (i = 0; i < fifo->runlist_nr; i++) {
 620                 ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST,
 621                                       0x8000, 0x1000, false,
 622                                       &fifo->runlist[i].mem[0]);
 623                 if (ret)
 624                         return ret;
 625
 626                 ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST,
 627                                       0x8000, 0x1000, false,
 628                                       &fifo->runlist[i].mem[1]);
 629                 if (ret)
 630                         return ret;
 631
 632                 init_waitqueue_head(&fifo->runlist[i].wait);
 633                 INIT_LIST_HEAD(&fifo->runlist[i].chan);
 634         }
 635
 636         ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST,
 637                               fifo->base.nr * 0x200, 0x1000, true,
 638                               &fifo->user.mem);
 639         if (ret)
 640                 return ret;
 641
 642         ret = nvkm_bar_umap(device->bar, fifo->base.nr * 0x200, 12,
 643                             &fifo->user.bar);
 644         if (ret)
 645                 return ret;
 646
 647         nvkm_memory_map(fifo->user.mem, &fifo->user.bar, 0);
 648         return 0;
 649 }
 650
 651 static void
 652 gk104_fifo_init(struct nvkm_fifo *base)
 653 {
 654         struct gk104_fifo *fifo = gk104_fifo(base);
 655         struct nvkm_device *device = fifo->base.engine.subdev.device;
 656         int i;
 657
 658         /* Enable PBDMAs. */
 659         nvkm_wr32(device, 0x000204, (1 << fifo->pbdma_nr) - 1);
 660
 661         /* PBDMA[n] */
 662         for (i = 0; i < fifo->pbdma_nr; i++) {
 663                 nvkm_mask(device, 0x04013c + (i * 0x2000), 0x10000100, 0x00000000);
 664                 nvkm_wr32(device, 0x040108 + (i * 0x2000), 0xffffffff); /* INTR */
 665                 nvkm_wr32(device, 0x04010c + (i * 0x2000), 0xfffffeff); /* INTREN */
 666         }
 667
 668         /* PBDMA[n].HCE */
 669         for (i = 0; i < fifo->pbdma_nr; i++) {
 670                 nvkm_wr32(device, 0x040148 + (i * 0x2000), 0xffffffff); /* INTR */
 671                 nvkm_wr32(device, 0x04014c + (i * 0x2000), 0xffffffff); /* INTREN */
 672         }
 673
 674         nvkm_wr32(device, 0x002254, 0x10000000 | fifo->user.bar.offset >> 12);
 675
 676         nvkm_wr32(device, 0x002100, 0xffffffff);
 677         nvkm_wr32(device, 0x002140, 0x7fffffff);
 678 }
 679
 680 static void *
 681 gk104_fifo_dtor(struct nvkm_fifo *base)
 682 {
 683         struct gk104_fifo *fifo = gk104_fifo(base);
 684         int i;
 685
 686         nvkm_vm_put(&fifo->user.bar);
 687         nvkm_memory_del(&fifo->user.mem);
 688
 689         for (i = 0; i < fifo->runlist_nr; i++) {
 690                 nvkm_memory_del(&fifo->runlist[i].mem[1]);
 691                 nvkm_memory_del(&fifo->runlist[i].mem[0]);
 692         }
 693
 694         return fifo;
 695 }
 696
 697 static const struct nvkm_fifo_func
 698 gk104_fifo_ = {
 699         .dtor = gk104_fifo_dtor,
 700         .oneinit = gk104_fifo_oneinit,
 701         .init = gk104_fifo_init,
 702         .fini = gk104_fifo_fini,
 703         .intr = gk104_fifo_intr,
 704         .uevent_init = gk104_fifo_uevent_init,
 705         .uevent_fini = gk104_fifo_uevent_fini,
 706         .class_get = gk104_fifo_class_get,
 707 };
 708
 709 int
 710 gk104_fifo_new_(const struct gk104_fifo_func *func, struct nvkm_device *device,
 711                 int index, int nr, struct nvkm_fifo **pfifo)
 712 {
 713         struct gk104_fifo *fifo;
 714
 715         if (!(fifo = kzalloc(sizeof(*fifo), GFP_KERNEL)))
 716                 return -ENOMEM;
 717         fifo->func = func;
 718         INIT_WORK(&fifo->recover.work, gk104_fifo_recover_work);
 719         *pfifo = &fifo->base;
 720
 721         return nvkm_fifo_ctor(&gk104_fifo_, device, index, nr, &fifo->base);
 722 }
 723
 724 const struct nvkm_enum
 725 gk104_fifo_fault_engine[] = {
 726         { 0x00, "GR", NULL, NVKM_ENGINE_GR },
 727         { 0x03, "IFB", NULL, NVKM_ENGINE_IFB },
 728         { 0x04, "BAR1", NULL, NVKM_SUBDEV_BAR },
 729         { 0x05, "BAR3", NULL, NVKM_SUBDEV_INSTMEM },
 730         { 0x07, "PBDMA0", NULL, NVKM_ENGINE_FIFO },
 731         { 0x08, "PBDMA1", NULL, NVKM_ENGINE_FIFO },
 732         { 0x09, "PBDMA2", NULL, NVKM_ENGINE_FIFO },
 733         { 0x10, "MSVLD", NULL, NVKM_ENGINE_MSVLD },
 734         { 0x11, "MSPPP", NULL, NVKM_ENGINE_MSPPP },
 735         { 0x13, "PERF" },
 736         { 0x14, "MSPDEC", NULL, NVKM_ENGINE_MSPDEC },
 737         { 0x15, "CE0", NULL, NVKM_ENGINE_CE0 },
 738         { 0x16, "CE1", NULL, NVKM_ENGINE_CE1 },
 739         { 0x17, "PMU" },
 740         { 0x19, "MSENC", NULL, NVKM_ENGINE_MSENC },
 741         { 0x1b, "CE2", NULL, NVKM_ENGINE_CE2 },
 742         {}
 743 };
 744
 745 const struct nvkm_enum
 746 gk104_fifo_fault_reason[] = {
 747         { 0x00, "PDE" },
 748         { 0x01, "PDE_SIZE" },
 749         { 0x02, "PTE" },
 750         { 0x03, "VA_LIMIT_VIOLATION" },
 751         { 0x04, "UNBOUND_INST_BLOCK" },
 752         { 0x05, "PRIV_VIOLATION" },
 753         { 0x06, "RO_VIOLATION" },
 754         { 0x07, "WO_VIOLATION" },
 755         { 0x08, "PITCH_MASK_VIOLATION" },
 756         { 0x09, "WORK_CREATION" },
 757         { 0x0a, "UNSUPPORTED_APERTURE" },
 758         { 0x0b, "COMPRESSION_FAILURE" },
 759         { 0x0c, "UNSUPPORTED_KIND" },
 760         { 0x0d, "REGION_VIOLATION" },
 761         { 0x0e, "BOTH_PTES_VALID" },
 762         { 0x0f, "INFO_TYPE_POISONED" },
 763         {}
 764 };
 765
 766 const struct nvkm_enum
 767 gk104_fifo_fault_hubclient[] = {
 768         { 0x00, "VIP" },
 769         { 0x01, "CE0" },
 770         { 0x02, "CE1" },
 771         { 0x03, "DNISO" },
 772         { 0x04, "FE" },
 773         { 0x05, "FECS" },
 774         { 0x06, "HOST" },
 775         { 0x07, "HOST_CPU" },
 776         { 0x08, "HOST_CPU_NB" },
 777         { 0x09, "ISO" },
 778         { 0x0a, "MMU" },
 779         { 0x0b, "MSPDEC" },
 780         { 0x0c, "MSPPP" },
 781         { 0x0d, "MSVLD" },
 782         { 0x0e, "NISO" },
 783         { 0x0f, "P2P" },
 784         { 0x10, "PD" },
 785         { 0x11, "PERF" },
 786         { 0x12, "PMU" },
 787         { 0x13, "RASTERTWOD" },
 788         { 0x14, "SCC" },
 789         { 0x15, "SCC_NB" },
 790         { 0x16, "SEC" },
 791         { 0x17, "SSYNC" },
 792         { 0x18, "GR_CE" },
 793         { 0x19, "CE2" },
 794         { 0x1a, "XV" },
 795         { 0x1b, "MMU_NB" },
 796         { 0x1c, "MSENC" },
 797         { 0x1d, "DFALCON" },
 798         { 0x1e, "SKED" },
 799         { 0x1f, "AFALCON" },
 800         {}
 801 };
 802
 803 const struct nvkm_enum
 804 gk104_fifo_fault_gpcclient[] = {
 805         { 0x00, "L1_0" }, { 0x01, "T1_0" }, { 0x02, "PE_0" },
 806         { 0x03, "L1_1" }, { 0x04, "T1_1" }, { 0x05, "PE_1" },
 807         { 0x06, "L1_2" }, { 0x07, "T1_2" }, { 0x08, "PE_2" },
 808         { 0x09, "L1_3" }, { 0x0a, "T1_3" }, { 0x0b, "PE_3" },
 809         { 0x0c, "RAST" },
 810         { 0x0d, "GCC" },
 811         { 0x0e, "GPCCS" },
 812         { 0x0f, "PROP_0" },
 813         { 0x10, "PROP_1" },
 814         { 0x11, "PROP_2" },
 815         { 0x12, "PROP_3" },
 816         { 0x13, "L1_4" }, { 0x14, "T1_4" }, { 0x15, "PE_4" },
 817         { 0x16, "L1_5" }, { 0x17, "T1_5" }, { 0x18, "PE_5" },
 818         { 0x19, "L1_6" }, { 0x1a, "T1_6" }, { 0x1b, "PE_6" },
 819         { 0x1c, "L1_7" }, { 0x1d, "T1_7" }, { 0x1e, "PE_7" },
 820         { 0x1f, "GPM" },
 821         { 0x20, "LTP_UTLB_0" },
 822         { 0x21, "LTP_UTLB_1" },
 823         { 0x22, "LTP_UTLB_2" },
 824         { 0x23, "LTP_UTLB_3" },
 825         { 0x24, "GPC_RGG_UTLB" },
 826         {}
 827 };
 828
 829 static const struct gk104_fifo_func
 830 gk104_fifo = {
 831         .fault.engine = gk104_fifo_fault_engine,
 832         .fault.reason = gk104_fifo_fault_reason,
 833         .fault.hubclient = gk104_fifo_fault_hubclient,
 834         .fault.gpcclient = gk104_fifo_fault_gpcclient,
 835         .chan = {
 836                 &gk104_fifo_gpfifo_oclass,
 837                 NULL
 838         },
 839 };
 840
 841 int
 842 gk104_fifo_new(struct nvkm_device *device, int index, struct nvkm_fifo **pfifo)
 843 {
 844         return gk104_fifo_new_(&gk104_fifo, device, index, 4096, pfifo);
 845 }