2 * Copyright 2012 Red Hat Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
25 #include "changk104.h"
27 #include <core/client.h>
28 #include <core/gpuobj.h>
29 #include <subdev/bar.h>
30 #include <subdev/timer.h>
31 #include <subdev/top.h>
32 #include <engine/sw.h>
34 #include <nvif/class.h>
36 struct gk104_fifo_engine_status {
49 gk104_fifo_engine_status(struct gk104_fifo *fifo, int engn,
50 struct gk104_fifo_engine_status *status)
52 struct nvkm_engine *engine = fifo->engine[engn].engine;
53 struct nvkm_subdev *subdev = &fifo->base.engine.subdev;
54 struct nvkm_device *device = subdev->device;
55 u32 stat = nvkm_rd32(device, 0x002640 + (engn * 0x08));
57 status->busy = !!(stat & 0x80000000);
58 status->faulted = !!(stat & 0x40000000);
59 status->next.tsg = !!(stat & 0x10000000);
60 status->next.id = (stat & 0x0fff0000) >> 16;
61 status->chsw = !!(stat & 0x00008000);
62 status->save = !!(stat & 0x00004000);
63 status->load = !!(stat & 0x00002000);
64 status->prev.tsg = !!(stat & 0x00001000);
65 status->prev.id = (stat & 0x00000fff);
68 if (status->busy && status->chsw) {
69 if (status->load && status->save) {
70 if (engine && nvkm_engine_chsw_load(engine))
71 status->chan = &status->next;
73 status->chan = &status->prev;
76 status->chan = &status->next;
78 status->chan = &status->prev;
82 status->chan = &status->prev;
85 nvkm_debug(subdev, "engine %02d: busy %d faulted %d chsw %d "
86 "save %d load %d %sid %d%s-> %sid %d%s\n",
87 engn, status->busy, status->faulted,
88 status->chsw, status->save, status->load,
89 status->prev.tsg ? "tsg" : "ch", status->prev.id,
90 status->chan == &status->prev ? "*" : " ",
91 status->next.tsg ? "tsg" : "ch", status->next.id,
92 status->chan == &status->next ? "*" : " ");
96 gk104_fifo_class_get(struct nvkm_fifo *base, int index,
97 const struct nvkm_fifo_chan_oclass **psclass)
99 struct gk104_fifo *fifo = gk104_fifo(base);
102 while ((*psclass = fifo->func->chan[c])) {
111 gk104_fifo_uevent_fini(struct nvkm_fifo *fifo)
113 struct nvkm_device *device = fifo->engine.subdev.device;
114 nvkm_mask(device, 0x002140, 0x80000000, 0x00000000);
118 gk104_fifo_uevent_init(struct nvkm_fifo *fifo)
120 struct nvkm_device *device = fifo->engine.subdev.device;
121 nvkm_mask(device, 0x002140, 0x80000000, 0x80000000);
125 gk104_fifo_runlist_commit(struct gk104_fifo *fifo, int runl)
127 struct gk104_fifo_chan *chan;
128 struct nvkm_subdev *subdev = &fifo->base.engine.subdev;
129 struct nvkm_device *device = subdev->device;
130 struct nvkm_memory *mem;
134 mutex_lock(&subdev->mutex);
135 mem = fifo->runlist[runl].mem[fifo->runlist[runl].next];
136 fifo->runlist[runl].next = !fifo->runlist[runl].next;
139 list_for_each_entry(chan, &fifo->runlist[runl].chan, head) {
140 nvkm_wo32(mem, (nr * 8) + 0, chan->base.chid);
141 nvkm_wo32(mem, (nr * 8) + 4, 0x00000000);
146 switch (nvkm_memory_target(mem)) {
147 case NVKM_MEM_TARGET_VRAM: target = 0; break;
148 case NVKM_MEM_TARGET_NCOH: target = 3; break;
154 nvkm_wr32(device, 0x002270, (nvkm_memory_addr(mem) >> 12) |
156 nvkm_wr32(device, 0x002274, (runl << 20) | nr);
158 if (wait_event_timeout(fifo->runlist[runl].wait,
159 !(nvkm_rd32(device, 0x002284 + (runl * 0x08))
161 msecs_to_jiffies(2000)) == 0)
162 nvkm_error(subdev, "runlist %d update timeout\n", runl);
163 mutex_unlock(&subdev->mutex);
167 gk104_fifo_runlist_remove(struct gk104_fifo *fifo, struct gk104_fifo_chan *chan)
169 mutex_lock(&fifo->base.engine.subdev.mutex);
170 list_del_init(&chan->head);
171 mutex_unlock(&fifo->base.engine.subdev.mutex);
175 gk104_fifo_runlist_insert(struct gk104_fifo *fifo, struct gk104_fifo_chan *chan)
177 mutex_lock(&fifo->base.engine.subdev.mutex);
178 list_add_tail(&chan->head, &fifo->runlist[chan->runl].chan);
179 mutex_unlock(&fifo->base.engine.subdev.mutex);
183 gk104_fifo_recover_work(struct work_struct *w)
185 struct gk104_fifo *fifo = container_of(w, typeof(*fifo), recover.work);
186 struct nvkm_device *device = fifo->base.engine.subdev.device;
187 struct nvkm_engine *engine;
189 u32 engm, runm, todo;
192 spin_lock_irqsave(&fifo->base.lock, flags);
193 runm = fifo->recover.runm;
194 engm = fifo->recover.engm;
195 fifo->recover.engm = 0;
196 fifo->recover.runm = 0;
197 spin_unlock_irqrestore(&fifo->base.lock, flags);
199 nvkm_mask(device, 0x002630, runm, runm);
201 for (todo = engm; engn = __ffs(todo), todo; todo &= ~BIT(engn)) {
202 if ((engine = fifo->engine[engn].engine)) {
203 nvkm_subdev_fini(&engine->subdev, false);
204 WARN_ON(nvkm_subdev_init(&engine->subdev));
208 for (todo = runm; runl = __ffs(todo), todo; todo &= ~BIT(runl))
209 gk104_fifo_runlist_commit(fifo, runl);
211 nvkm_wr32(device, 0x00262c, runm);
212 nvkm_mask(device, 0x002630, runm, 0x00000000);
215 static void gk104_fifo_recover_engn(struct gk104_fifo *fifo, int engn);
218 gk104_fifo_recover_runl(struct gk104_fifo *fifo, int runl)
220 struct nvkm_subdev *subdev = &fifo->base.engine.subdev;
221 struct nvkm_device *device = subdev->device;
222 const u32 runm = BIT(runl);
224 assert_spin_locked(&fifo->base.lock);
225 if (fifo->recover.runm & runm)
227 fifo->recover.runm |= runm;
229 /* Block runlist to prevent channel assignment(s) from changing. */
230 nvkm_mask(device, 0x002630, runm, runm);
232 /* Schedule recovery. */
233 nvkm_warn(subdev, "runlist %d: scheduled for recovery\n", runl);
234 schedule_work(&fifo->recover.work);
238 gk104_fifo_recover_chan(struct nvkm_fifo *base, int chid)
240 struct gk104_fifo *fifo = gk104_fifo(base);
241 struct nvkm_subdev *subdev = &fifo->base.engine.subdev;
242 struct nvkm_device *device = subdev->device;
243 const u32 stat = nvkm_rd32(device, 0x800004 + (chid * 0x08));
244 const u32 runl = (stat & 0x000f0000) >> 16;
245 const bool used = (stat & 0x00000001);
246 unsigned long engn, engm = fifo->runlist[runl].engm;
247 struct gk104_fifo_chan *chan;
249 assert_spin_locked(&fifo->base.lock);
253 /* Lookup SW state for channel, and mark it as dead. */
254 list_for_each_entry(chan, &fifo->runlist[runl].chan, head) {
255 if (chan->base.chid == chid) {
256 list_del_init(&chan->head);
258 nvkm_fifo_kevent(&fifo->base, chid);
263 /* Disable channel. */
264 nvkm_wr32(device, 0x800004 + (chid * 0x08), stat | 0x00000800);
265 nvkm_warn(subdev, "channel %d: killed\n", chid);
267 /* Block channel assignments from changing during recovery. */
268 gk104_fifo_recover_runl(fifo, runl);
270 /* Schedule recovery for any engines the channel is on. */
271 for_each_set_bit(engn, &engm, fifo->engine_nr) {
272 struct gk104_fifo_engine_status status;
273 gk104_fifo_engine_status(fifo, engn, &status);
274 if (!status.chan || status.chan->id != chid)
276 gk104_fifo_recover_engn(fifo, engn);
281 gk104_fifo_recover_engn(struct gk104_fifo *fifo, int engn)
283 struct nvkm_engine *engine = fifo->engine[engn].engine;
284 struct nvkm_subdev *subdev = &fifo->base.engine.subdev;
285 struct nvkm_device *device = subdev->device;
286 const u32 runl = fifo->engine[engn].runl;
287 const u32 engm = BIT(engn);
288 struct gk104_fifo_engine_status status;
291 assert_spin_locked(&fifo->base.lock);
292 if (fifo->recover.engm & engm)
294 fifo->recover.engm |= engm;
296 /* Block channel assignments from changing during recovery. */
297 gk104_fifo_recover_runl(fifo, runl);
299 /* Determine which channel (if any) is currently on the engine. */
300 gk104_fifo_engine_status(fifo, engn, &status);
302 /* The channel is not longer viable, kill it. */
303 gk104_fifo_recover_chan(&fifo->base, status.chan->id);
306 /* Determine MMU fault ID for the engine, if we're not being
307 * called from the fault handler already.
309 if (!status.faulted && engine) {
310 mmui = nvkm_top_fault_id(device, engine->subdev.index);
312 const struct nvkm_enum *en = fifo->func->fault.engine;
313 for (; en && en->name; en++) {
314 if (en->data2 == engine->subdev.index) {
323 /* Trigger a MMU fault for the engine.
325 * No good idea why this is needed, but nvgpu does something similar,
326 * and it makes recovery from CTXSW_TIMEOUT a lot more reliable.
329 nvkm_wr32(device, 0x002a30 + (engn * 0x04), 0x00000100 | mmui);
331 /* Wait for fault to trigger. */
332 nvkm_msec(device, 2000,
333 gk104_fifo_engine_status(fifo, engn, &status);
338 /* Release MMU fault trigger, and ACK the fault. */
339 nvkm_wr32(device, 0x002a30 + (engn * 0x04), 0x00000000);
340 nvkm_wr32(device, 0x00259c, BIT(mmui));
341 nvkm_wr32(device, 0x002100, 0x10000000);
344 /* Schedule recovery. */
345 nvkm_warn(subdev, "engine %d: scheduled for recovery\n", engn);
346 schedule_work(&fifo->recover.work);
349 static const struct nvkm_enum
350 gk104_fifo_bind_reason[] = {
351 { 0x01, "BIND_NOT_UNBOUND" },
352 { 0x02, "SNOOP_WITHOUT_BAR1" },
353 { 0x03, "UNBIND_WHILE_RUNNING" },
354 { 0x05, "INVALID_RUNLIST" },
355 { 0x06, "INVALID_CTX_TGT" },
356 { 0x0b, "UNBIND_WHILE_PARKED" },
361 gk104_fifo_intr_bind(struct gk104_fifo *fifo)
363 struct nvkm_subdev *subdev = &fifo->base.engine.subdev;
364 struct nvkm_device *device = subdev->device;
365 u32 intr = nvkm_rd32(device, 0x00252c);
366 u32 code = intr & 0x000000ff;
367 const struct nvkm_enum *en =
368 nvkm_enum_find(gk104_fifo_bind_reason, code);
370 nvkm_error(subdev, "BIND_ERROR %02x [%s]\n", code, en ? en->name : "");
373 static const struct nvkm_enum
374 gk104_fifo_sched_reason[] = {
375 { 0x0a, "CTXSW_TIMEOUT" },
380 gk104_fifo_intr_sched_ctxsw(struct gk104_fifo *fifo)
382 struct nvkm_device *device = fifo->base.engine.subdev.device;
383 unsigned long flags, engm = 0;
386 /* We need to ACK the SCHED_ERROR here, and prevent it reasserting,
387 * as MMU_FAULT cannot be triggered while it's pending.
389 spin_lock_irqsave(&fifo->base.lock, flags);
390 nvkm_mask(device, 0x002140, 0x00000100, 0x00000000);
391 nvkm_wr32(device, 0x002100, 0x00000100);
393 for (engn = 0; engn < fifo->engine_nr; engn++) {
394 struct gk104_fifo_engine_status status;
396 gk104_fifo_engine_status(fifo, engn, &status);
397 if (!status.busy || !status.chsw)
403 for_each_set_bit(engn, &engm, fifo->engine_nr)
404 gk104_fifo_recover_engn(fifo, engn);
406 nvkm_mask(device, 0x002140, 0x00000100, 0x00000100);
407 spin_unlock_irqrestore(&fifo->base.lock, flags);
411 gk104_fifo_intr_sched(struct gk104_fifo *fifo)
413 struct nvkm_subdev *subdev = &fifo->base.engine.subdev;
414 struct nvkm_device *device = subdev->device;
415 u32 intr = nvkm_rd32(device, 0x00254c);
416 u32 code = intr & 0x000000ff;
417 const struct nvkm_enum *en =
418 nvkm_enum_find(gk104_fifo_sched_reason, code);
420 nvkm_error(subdev, "SCHED_ERROR %02x [%s]\n", code, en ? en->name : "");
424 gk104_fifo_intr_sched_ctxsw(fifo);
432 gk104_fifo_intr_chsw(struct gk104_fifo *fifo)
434 struct nvkm_subdev *subdev = &fifo->base.engine.subdev;
435 struct nvkm_device *device = subdev->device;
436 u32 stat = nvkm_rd32(device, 0x00256c);
437 nvkm_error(subdev, "CHSW_ERROR %08x\n", stat);
438 nvkm_wr32(device, 0x00256c, stat);
442 gk104_fifo_intr_dropped_fault(struct gk104_fifo *fifo)
444 struct nvkm_subdev *subdev = &fifo->base.engine.subdev;
445 struct nvkm_device *device = subdev->device;
446 u32 stat = nvkm_rd32(device, 0x00259c);
447 nvkm_error(subdev, "DROPPED_MMU_FAULT %08x\n", stat);
451 gk104_fifo_intr_fault(struct gk104_fifo *fifo, int unit)
453 struct nvkm_subdev *subdev = &fifo->base.engine.subdev;
454 struct nvkm_device *device = subdev->device;
455 u32 inst = nvkm_rd32(device, 0x002800 + (unit * 0x10));
456 u32 valo = nvkm_rd32(device, 0x002804 + (unit * 0x10));
457 u32 vahi = nvkm_rd32(device, 0x002808 + (unit * 0x10));
458 u32 stat = nvkm_rd32(device, 0x00280c + (unit * 0x10));
459 u32 gpc = (stat & 0x1f000000) >> 24;
460 u32 client = (stat & 0x00001f00) >> 8;
461 u32 write = (stat & 0x00000080);
462 u32 hub = (stat & 0x00000040);
463 u32 reason = (stat & 0x0000000f);
464 const struct nvkm_enum *er, *eu, *ec;
465 struct nvkm_engine *engine = NULL;
466 struct nvkm_fifo_chan *chan;
468 char gpcid[8] = "", en[16] = "";
471 er = nvkm_enum_find(fifo->func->fault.reason, reason);
472 eu = nvkm_enum_find(fifo->func->fault.engine, unit);
474 ec = nvkm_enum_find(fifo->func->fault.hubclient, client);
476 ec = nvkm_enum_find(fifo->func->fault.gpcclient, client);
477 snprintf(gpcid, sizeof(gpcid), "GPC%d/", gpc);
480 if (eu && eu->data2) {
482 case NVKM_SUBDEV_BAR:
483 nvkm_mask(device, 0x001704, 0x00000000, 0x00000000);
485 case NVKM_SUBDEV_INSTMEM:
486 nvkm_mask(device, 0x001714, 0x00000000, 0x00000000);
488 case NVKM_ENGINE_IFB:
489 nvkm_mask(device, 0x001718, 0x00000000, 0x00000000);
492 engine = nvkm_device_engine(device, eu->data2);
498 enum nvkm_devidx engidx = nvkm_top_fault(device, unit);
499 if (engidx < NVKM_SUBDEV_NR) {
500 const char *src = nvkm_subdev_name[engidx];
503 *dst++ = toupper(*src++);
505 engine = nvkm_device_engine(device, engidx);
508 snprintf(en, sizeof(en), "%s", eu->name);
511 spin_lock_irqsave(&fifo->base.lock, flags);
512 chan = nvkm_fifo_chan_inst_locked(&fifo->base, (u64)inst << 12);
515 "%s fault at %010llx engine %02x [%s] client %02x [%s%s] "
516 "reason %02x [%s] on channel %d [%010llx %s]\n",
517 write ? "write" : "read", (u64)vahi << 32 | valo,
518 unit, en, client, gpcid, ec ? ec->name : "",
519 reason, er ? er->name : "", chan ? chan->chid : -1,
521 chan ? chan->object.client->name : "unknown");
524 /* Kill the channel that caused the fault. */
526 gk104_fifo_recover_chan(&fifo->base, chan->chid);
528 /* Channel recovery will probably have already done this for the
529 * correct engine(s), but just in case we can't find the channel
532 for (engn = 0; engn < fifo->engine_nr && engine; engn++) {
533 if (fifo->engine[engn].engine == engine) {
534 gk104_fifo_recover_engn(fifo, engn);
539 spin_unlock_irqrestore(&fifo->base.lock, flags);
542 static const struct nvkm_bitfield gk104_fifo_pbdma_intr_0[] = {
543 { 0x00000001, "MEMREQ" },
544 { 0x00000002, "MEMACK_TIMEOUT" },
545 { 0x00000004, "MEMACK_EXTRA" },
546 { 0x00000008, "MEMDAT_TIMEOUT" },
547 { 0x00000010, "MEMDAT_EXTRA" },
548 { 0x00000020, "MEMFLUSH" },
549 { 0x00000040, "MEMOP" },
550 { 0x00000080, "LBCONNECT" },
551 { 0x00000100, "LBREQ" },
552 { 0x00000200, "LBACK_TIMEOUT" },
553 { 0x00000400, "LBACK_EXTRA" },
554 { 0x00000800, "LBDAT_TIMEOUT" },
555 { 0x00001000, "LBDAT_EXTRA" },
556 { 0x00002000, "GPFIFO" },
557 { 0x00004000, "GPPTR" },
558 { 0x00008000, "GPENTRY" },
559 { 0x00010000, "GPCRC" },
560 { 0x00020000, "PBPTR" },
561 { 0x00040000, "PBENTRY" },
562 { 0x00080000, "PBCRC" },
563 { 0x00100000, "XBARCONNECT" },
564 { 0x00200000, "METHOD" },
565 { 0x00400000, "METHODCRC" },
566 { 0x00800000, "DEVICE" },
567 { 0x02000000, "SEMAPHORE" },
568 { 0x04000000, "ACQUIRE" },
569 { 0x08000000, "PRI" },
570 { 0x20000000, "NO_CTXSW_SEG" },
571 { 0x40000000, "PBSEG" },
572 { 0x80000000, "SIGNATURE" },
577 gk104_fifo_intr_pbdma_0(struct gk104_fifo *fifo, int unit)
579 struct nvkm_subdev *subdev = &fifo->base.engine.subdev;
580 struct nvkm_device *device = subdev->device;
581 u32 mask = nvkm_rd32(device, 0x04010c + (unit * 0x2000));
582 u32 stat = nvkm_rd32(device, 0x040108 + (unit * 0x2000)) & mask;
583 u32 addr = nvkm_rd32(device, 0x0400c0 + (unit * 0x2000));
584 u32 data = nvkm_rd32(device, 0x0400c4 + (unit * 0x2000));
585 u32 chid = nvkm_rd32(device, 0x040120 + (unit * 0x2000)) & 0xfff;
586 u32 subc = (addr & 0x00070000) >> 16;
587 u32 mthd = (addr & 0x00003ffc);
589 struct nvkm_fifo_chan *chan;
593 if (stat & 0x00800000) {
595 if (nvkm_sw_mthd(device->sw, chid, subc, mthd, data))
600 nvkm_wr32(device, 0x0400c0 + (unit * 0x2000), 0x80600008);
603 nvkm_snprintbf(msg, sizeof(msg), gk104_fifo_pbdma_intr_0, show);
604 chan = nvkm_fifo_chan_chid(&fifo->base, chid, &flags);
605 nvkm_error(subdev, "PBDMA%d: %08x [%s] ch %d [%010llx %s] "
606 "subc %d mthd %04x data %08x\n",
607 unit, show, msg, chid, chan ? chan->inst->addr : 0,
608 chan ? chan->object.client->name : "unknown",
610 nvkm_fifo_chan_put(&fifo->base, flags, &chan);
613 nvkm_wr32(device, 0x040108 + (unit * 0x2000), stat);
616 static const struct nvkm_bitfield gk104_fifo_pbdma_intr_1[] = {
617 { 0x00000001, "HCE_RE_ILLEGAL_OP" },
618 { 0x00000002, "HCE_RE_ALIGNB" },
619 { 0x00000004, "HCE_PRIV" },
620 { 0x00000008, "HCE_ILLEGAL_MTHD" },
621 { 0x00000010, "HCE_ILLEGAL_CLASS" },
626 gk104_fifo_intr_pbdma_1(struct gk104_fifo *fifo, int unit)
628 struct nvkm_subdev *subdev = &fifo->base.engine.subdev;
629 struct nvkm_device *device = subdev->device;
630 u32 mask = nvkm_rd32(device, 0x04014c + (unit * 0x2000));
631 u32 stat = nvkm_rd32(device, 0x040148 + (unit * 0x2000)) & mask;
632 u32 chid = nvkm_rd32(device, 0x040120 + (unit * 0x2000)) & 0xfff;
636 nvkm_snprintbf(msg, sizeof(msg), gk104_fifo_pbdma_intr_1, stat);
637 nvkm_error(subdev, "PBDMA%d: %08x [%s] ch %d %08x %08x\n",
638 unit, stat, msg, chid,
639 nvkm_rd32(device, 0x040150 + (unit * 0x2000)),
640 nvkm_rd32(device, 0x040154 + (unit * 0x2000)));
643 nvkm_wr32(device, 0x040148 + (unit * 0x2000), stat);
647 gk104_fifo_intr_runlist(struct gk104_fifo *fifo)
649 struct nvkm_device *device = fifo->base.engine.subdev.device;
650 u32 mask = nvkm_rd32(device, 0x002a00);
652 int runl = __ffs(mask);
653 wake_up(&fifo->runlist[runl].wait);
654 nvkm_wr32(device, 0x002a00, 1 << runl);
655 mask &= ~(1 << runl);
660 gk104_fifo_intr_engine(struct gk104_fifo *fifo)
662 nvkm_fifo_uevent(&fifo->base);
666 gk104_fifo_intr(struct nvkm_fifo *base)
668 struct gk104_fifo *fifo = gk104_fifo(base);
669 struct nvkm_subdev *subdev = &fifo->base.engine.subdev;
670 struct nvkm_device *device = subdev->device;
671 u32 mask = nvkm_rd32(device, 0x002140);
672 u32 stat = nvkm_rd32(device, 0x002100) & mask;
674 if (stat & 0x00000001) {
675 gk104_fifo_intr_bind(fifo);
676 nvkm_wr32(device, 0x002100, 0x00000001);
680 if (stat & 0x00000010) {
681 nvkm_error(subdev, "PIO_ERROR\n");
682 nvkm_wr32(device, 0x002100, 0x00000010);
686 if (stat & 0x00000100) {
687 gk104_fifo_intr_sched(fifo);
688 nvkm_wr32(device, 0x002100, 0x00000100);
692 if (stat & 0x00010000) {
693 gk104_fifo_intr_chsw(fifo);
694 nvkm_wr32(device, 0x002100, 0x00010000);
698 if (stat & 0x00800000) {
699 nvkm_error(subdev, "FB_FLUSH_TIMEOUT\n");
700 nvkm_wr32(device, 0x002100, 0x00800000);
704 if (stat & 0x01000000) {
705 nvkm_error(subdev, "LB_ERROR\n");
706 nvkm_wr32(device, 0x002100, 0x01000000);
710 if (stat & 0x08000000) {
711 gk104_fifo_intr_dropped_fault(fifo);
712 nvkm_wr32(device, 0x002100, 0x08000000);
716 if (stat & 0x10000000) {
717 u32 mask = nvkm_rd32(device, 0x00259c);
719 u32 unit = __ffs(mask);
720 gk104_fifo_intr_fault(fifo, unit);
721 nvkm_wr32(device, 0x00259c, (1 << unit));
722 mask &= ~(1 << unit);
727 if (stat & 0x20000000) {
728 u32 mask = nvkm_rd32(device, 0x0025a0);
730 u32 unit = __ffs(mask);
731 gk104_fifo_intr_pbdma_0(fifo, unit);
732 gk104_fifo_intr_pbdma_1(fifo, unit);
733 nvkm_wr32(device, 0x0025a0, (1 << unit));
734 mask &= ~(1 << unit);
739 if (stat & 0x40000000) {
740 gk104_fifo_intr_runlist(fifo);
744 if (stat & 0x80000000) {
745 nvkm_wr32(device, 0x002100, 0x80000000);
746 gk104_fifo_intr_engine(fifo);
751 nvkm_error(subdev, "INTR %08x\n", stat);
752 nvkm_mask(device, 0x002140, stat, 0x00000000);
753 nvkm_wr32(device, 0x002100, stat);
758 gk104_fifo_fini(struct nvkm_fifo *base)
760 struct gk104_fifo *fifo = gk104_fifo(base);
761 struct nvkm_device *device = fifo->base.engine.subdev.device;
762 flush_work(&fifo->recover.work);
763 /* allow mmu fault interrupts, even when we're not using fifo */
764 nvkm_mask(device, 0x002140, 0x10000000, 0x10000000);
768 gk104_fifo_oneinit(struct nvkm_fifo *base)
770 struct gk104_fifo *fifo = gk104_fifo(base);
771 struct nvkm_subdev *subdev = &fifo->base.engine.subdev;
772 struct nvkm_device *device = subdev->device;
773 int engn, runl, pbid, ret, i, j;
774 enum nvkm_devidx engidx;
777 /* Determine number of PBDMAs by checking valid enable bits. */
778 nvkm_wr32(device, 0x000204, 0xffffffff);
779 fifo->pbdma_nr = hweight32(nvkm_rd32(device, 0x000204));
780 nvkm_debug(subdev, "%d PBDMA(s)\n", fifo->pbdma_nr);
782 /* Read PBDMA->runlist(s) mapping from HW. */
783 if (!(map = kzalloc(sizeof(*map) * fifo->pbdma_nr, GFP_KERNEL)))
786 for (i = 0; i < fifo->pbdma_nr; i++)
787 map[i] = nvkm_rd32(device, 0x002390 + (i * 0x04));
789 /* Determine runlist configuration from topology device info. */
791 while ((int)(engidx = nvkm_top_engine(device, i++, &runl, &engn)) >= 0) {
792 /* Determine which PBDMA handles requests for this engine. */
793 for (j = 0, pbid = -1; j < fifo->pbdma_nr; j++) {
794 if (map[j] & (1 << runl)) {
800 nvkm_debug(subdev, "engine %2d: runlist %2d pbdma %2d (%s)\n",
801 engn, runl, pbid, nvkm_subdev_name[engidx]);
803 fifo->engine[engn].engine = nvkm_device_engine(device, engidx);
804 fifo->engine[engn].runl = runl;
805 fifo->engine[engn].pbid = pbid;
806 fifo->engine_nr = max(fifo->engine_nr, engn + 1);
807 fifo->runlist[runl].engm |= 1 << engn;
808 fifo->runlist_nr = max(fifo->runlist_nr, runl + 1);
813 for (i = 0; i < fifo->runlist_nr; i++) {
814 ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST,
815 0x8000, 0x1000, false,
816 &fifo->runlist[i].mem[0]);
820 ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST,
821 0x8000, 0x1000, false,
822 &fifo->runlist[i].mem[1]);
826 init_waitqueue_head(&fifo->runlist[i].wait);
827 INIT_LIST_HEAD(&fifo->runlist[i].chan);
830 ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST,
831 fifo->base.nr * 0x200, 0x1000, true,
836 ret = nvkm_bar_umap(device->bar, fifo->base.nr * 0x200, 12,
841 nvkm_memory_map(fifo->user.mem, &fifo->user.bar, 0);
846 gk104_fifo_init(struct nvkm_fifo *base)
848 struct gk104_fifo *fifo = gk104_fifo(base);
849 struct nvkm_device *device = fifo->base.engine.subdev.device;
853 nvkm_wr32(device, 0x000204, (1 << fifo->pbdma_nr) - 1);
856 for (i = 0; i < fifo->pbdma_nr; i++) {
857 nvkm_mask(device, 0x04013c + (i * 0x2000), 0x10000100, 0x00000000);
858 nvkm_wr32(device, 0x040108 + (i * 0x2000), 0xffffffff); /* INTR */
859 nvkm_wr32(device, 0x04010c + (i * 0x2000), 0xfffffeff); /* INTREN */
863 for (i = 0; i < fifo->pbdma_nr; i++) {
864 nvkm_wr32(device, 0x040148 + (i * 0x2000), 0xffffffff); /* INTR */
865 nvkm_wr32(device, 0x04014c + (i * 0x2000), 0xffffffff); /* INTREN */
868 nvkm_wr32(device, 0x002254, 0x10000000 | fifo->user.bar.offset >> 12);
870 nvkm_wr32(device, 0x002100, 0xffffffff);
871 nvkm_wr32(device, 0x002140, 0x7fffffff);
875 gk104_fifo_dtor(struct nvkm_fifo *base)
877 struct gk104_fifo *fifo = gk104_fifo(base);
880 nvkm_vm_put(&fifo->user.bar);
881 nvkm_memory_del(&fifo->user.mem);
883 for (i = 0; i < fifo->runlist_nr; i++) {
884 nvkm_memory_del(&fifo->runlist[i].mem[1]);
885 nvkm_memory_del(&fifo->runlist[i].mem[0]);
891 static const struct nvkm_fifo_func
893 .dtor = gk104_fifo_dtor,
894 .oneinit = gk104_fifo_oneinit,
895 .init = gk104_fifo_init,
896 .fini = gk104_fifo_fini,
897 .intr = gk104_fifo_intr,
898 .uevent_init = gk104_fifo_uevent_init,
899 .uevent_fini = gk104_fifo_uevent_fini,
900 .recover_chan = gk104_fifo_recover_chan,
901 .class_get = gk104_fifo_class_get,
905 gk104_fifo_new_(const struct gk104_fifo_func *func, struct nvkm_device *device,
906 int index, int nr, struct nvkm_fifo **pfifo)
908 struct gk104_fifo *fifo;
910 if (!(fifo = kzalloc(sizeof(*fifo), GFP_KERNEL)))
913 INIT_WORK(&fifo->recover.work, gk104_fifo_recover_work);
914 *pfifo = &fifo->base;
916 return nvkm_fifo_ctor(&gk104_fifo_, device, index, nr, &fifo->base);
919 const struct nvkm_enum
920 gk104_fifo_fault_engine[] = {
921 { 0x00, "GR", NULL, NVKM_ENGINE_GR },
924 { 0x03, "IFB", NULL, NVKM_ENGINE_IFB },
925 { 0x04, "BAR1", NULL, NVKM_SUBDEV_BAR },
926 { 0x05, "BAR2", NULL, NVKM_SUBDEV_INSTMEM },
928 { 0x07, "HOST0", NULL, NVKM_ENGINE_FIFO },
929 { 0x08, "HOST1", NULL, NVKM_ENGINE_FIFO },
930 { 0x09, "HOST2", NULL, NVKM_ENGINE_FIFO },
931 { 0x0a, "HOST3", NULL, NVKM_ENGINE_FIFO },
932 { 0x0b, "HOST4", NULL, NVKM_ENGINE_FIFO },
933 { 0x0c, "HOST5", NULL, NVKM_ENGINE_FIFO },
934 { 0x0d, "HOST6", NULL, NVKM_ENGINE_FIFO },
935 { 0x0e, "HOST7", NULL, NVKM_ENGINE_FIFO },
937 { 0x10, "MSVLD", NULL, NVKM_ENGINE_MSVLD },
938 { 0x11, "MSPPP", NULL, NVKM_ENGINE_MSPPP },
940 { 0x14, "MSPDEC", NULL, NVKM_ENGINE_MSPDEC },
941 { 0x15, "CE0", NULL, NVKM_ENGINE_CE0 },
942 { 0x16, "CE1", NULL, NVKM_ENGINE_CE1 },
945 { 0x19, "MSENC", NULL, NVKM_ENGINE_MSENC },
946 { 0x1b, "CE2", NULL, NVKM_ENGINE_CE2 },
950 const struct nvkm_enum
951 gk104_fifo_fault_reason[] = {
953 { 0x01, "PDE_SIZE" },
955 { 0x03, "VA_LIMIT_VIOLATION" },
956 { 0x04, "UNBOUND_INST_BLOCK" },
957 { 0x05, "PRIV_VIOLATION" },
958 { 0x06, "RO_VIOLATION" },
959 { 0x07, "WO_VIOLATION" },
960 { 0x08, "PITCH_MASK_VIOLATION" },
961 { 0x09, "WORK_CREATION" },
962 { 0x0a, "UNSUPPORTED_APERTURE" },
963 { 0x0b, "COMPRESSION_FAILURE" },
964 { 0x0c, "UNSUPPORTED_KIND" },
965 { 0x0d, "REGION_VIOLATION" },
966 { 0x0e, "BOTH_PTES_VALID" },
967 { 0x0f, "INFO_TYPE_POISONED" },
971 const struct nvkm_enum
972 gk104_fifo_fault_hubclient[] = {
980 { 0x07, "HOST_CPU" },
981 { 0x08, "HOST_CPU_NB" },
992 { 0x13, "RASTERTWOD" },
1002 { 0x1d, "DFALCON" },
1004 { 0x1f, "AFALCON" },
1008 const struct nvkm_enum
1009 gk104_fifo_fault_gpcclient[] = {
1010 { 0x00, "L1_0" }, { 0x01, "T1_0" }, { 0x02, "PE_0" },
1011 { 0x03, "L1_1" }, { 0x04, "T1_1" }, { 0x05, "PE_1" },
1012 { 0x06, "L1_2" }, { 0x07, "T1_2" }, { 0x08, "PE_2" },
1013 { 0x09, "L1_3" }, { 0x0a, "T1_3" }, { 0x0b, "PE_3" },
1021 { 0x13, "L1_4" }, { 0x14, "T1_4" }, { 0x15, "PE_4" },
1022 { 0x16, "L1_5" }, { 0x17, "T1_5" }, { 0x18, "PE_5" },
1023 { 0x19, "L1_6" }, { 0x1a, "T1_6" }, { 0x1b, "PE_6" },
1024 { 0x1c, "L1_7" }, { 0x1d, "T1_7" }, { 0x1e, "PE_7" },
1026 { 0x20, "LTP_UTLB_0" },
1027 { 0x21, "LTP_UTLB_1" },
1028 { 0x22, "LTP_UTLB_2" },
1029 { 0x23, "LTP_UTLB_3" },
1030 { 0x24, "GPC_RGG_UTLB" },
1034 static const struct gk104_fifo_func
1036 .fault.engine = gk104_fifo_fault_engine,
1037 .fault.reason = gk104_fifo_fault_reason,
1038 .fault.hubclient = gk104_fifo_fault_hubclient,
1039 .fault.gpcclient = gk104_fifo_fault_gpcclient,
1041 &gk104_fifo_gpfifo_oclass,
1047 gk104_fifo_new(struct nvkm_device *device, int index, struct nvkm_fifo **pfifo)
1049 return gk104_fifo_new_(&gk104_fifo, device, index, 4096, pfifo);