drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c

   1 /*
   2  * Copyright 2012 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24
  25 #include <core/os.h>
  26 #include <core/client.h>
  27 #include <core/handle.h>
  28 #include <core/engctx.h>
  29 #include <core/enum.h>
  30
  31 #include <subdev/fb.h>
  32 #include <subdev/mmu.h>
  33 #include <subdev/timer.h>
  34
  35 #include <engine/fifo.h>
  36 #include <engine/gr.h>
  37
  38 #include "nv50.h"
  39
  40 struct nv50_gr_priv {
  41         struct nouveau_gr base;
  42         spinlock_t lock;
  43         u32 size;
  44 };
  45
  46 struct nv50_gr_chan {
  47         struct nouveau_gr_chan base;
  48 };
  49
  50 static u64
  51 nv50_gr_units(struct nouveau_gr *gr)
  52 {
  53         struct nv50_gr_priv *priv = (void *)gr;
  54
  55         return nv_rd32(priv, 0x1540);
  56 }
  57
  58 /*******************************************************************************
  59  * Graphics object classes
  60  ******************************************************************************/
  61
  62 static int
  63 nv50_gr_object_ctor(struct nouveau_object *parent,
  64                        struct nouveau_object *engine,
  65                        struct nouveau_oclass *oclass, void *data, u32 size,
  66                        struct nouveau_object **pobject)
  67 {
  68         struct nouveau_gpuobj *obj;
  69         int ret;
  70
  71         ret = nouveau_gpuobj_create(parent, engine, oclass, 0, parent,
  72                                     16, 16, 0, &obj);
  73         *pobject = nv_object(obj);
  74         if (ret)
  75                 return ret;
  76
  77         nv_wo32(obj, 0x00, nv_mclass(obj));
  78         nv_wo32(obj, 0x04, 0x00000000);
  79         nv_wo32(obj, 0x08, 0x00000000);
  80         nv_wo32(obj, 0x0c, 0x00000000);
  81         return 0;
  82 }
  83
  84 static struct nouveau_ofuncs
  85 nv50_gr_ofuncs = {
  86         .ctor = nv50_gr_object_ctor,
  87         .dtor = _nouveau_gpuobj_dtor,
  88         .init = _nouveau_gpuobj_init,
  89         .fini = _nouveau_gpuobj_fini,
  90         .rd32 = _nouveau_gpuobj_rd32,
  91         .wr32 = _nouveau_gpuobj_wr32,
  92 };
  93
  94 static struct nouveau_oclass
  95 nv50_gr_sclass[] = {
  96         { 0x0030, &nv50_gr_ofuncs },
  97         { 0x502d, &nv50_gr_ofuncs },
  98         { 0x5039, &nv50_gr_ofuncs },
  99         { 0x5097, &nv50_gr_ofuncs },
 100         { 0x50c0, &nv50_gr_ofuncs },
 101         {}
 102 };
 103
 104 static struct nouveau_oclass
 105 nv84_gr_sclass[] = {
 106         { 0x0030, &nv50_gr_ofuncs },
 107         { 0x502d, &nv50_gr_ofuncs },
 108         { 0x5039, &nv50_gr_ofuncs },
 109         { 0x50c0, &nv50_gr_ofuncs },
 110         { 0x8297, &nv50_gr_ofuncs },
 111         {}
 112 };
 113
 114 static struct nouveau_oclass
 115 nva0_gr_sclass[] = {
 116         { 0x0030, &nv50_gr_ofuncs },
 117         { 0x502d, &nv50_gr_ofuncs },
 118         { 0x5039, &nv50_gr_ofuncs },
 119         { 0x50c0, &nv50_gr_ofuncs },
 120         { 0x8397, &nv50_gr_ofuncs },
 121         {}
 122 };
 123
 124 static struct nouveau_oclass
 125 nva3_gr_sclass[] = {
 126         { 0x0030, &nv50_gr_ofuncs },
 127         { 0x502d, &nv50_gr_ofuncs },
 128         { 0x5039, &nv50_gr_ofuncs },
 129         { 0x50c0, &nv50_gr_ofuncs },
 130         { 0x8597, &nv50_gr_ofuncs },
 131         { 0x85c0, &nv50_gr_ofuncs },
 132         {}
 133 };
 134
 135 static struct nouveau_oclass
 136 nvaf_gr_sclass[] = {
 137         { 0x0030, &nv50_gr_ofuncs },
 138         { 0x502d, &nv50_gr_ofuncs },
 139         { 0x5039, &nv50_gr_ofuncs },
 140         { 0x50c0, &nv50_gr_ofuncs },
 141         { 0x85c0, &nv50_gr_ofuncs },
 142         { 0x8697, &nv50_gr_ofuncs },
 143         {}
 144 };
 145
 146 /*******************************************************************************
 147  * PGRAPH context
 148  ******************************************************************************/
 149
 150 static int
 151 nv50_gr_context_ctor(struct nouveau_object *parent,
 152                         struct nouveau_object *engine,
 153                         struct nouveau_oclass *oclass, void *data, u32 size,
 154                         struct nouveau_object **pobject)
 155 {
 156         struct nv50_gr_priv *priv = (void *)engine;
 157         struct nv50_gr_chan *chan;
 158         int ret;
 159
 160         ret = nouveau_gr_context_create(parent, engine, oclass, NULL,
 161                                            priv->size, 0,
 162                                            NVOBJ_FLAG_ZERO_ALLOC, &chan);
 163         *pobject = nv_object(chan);
 164         if (ret)
 165                 return ret;
 166
 167         nv50_grctx_fill(nv_device(priv), nv_gpuobj(chan));
 168         return 0;
 169 }
 170
 171 static struct nouveau_oclass
 172 nv50_gr_cclass = {
 173         .handle = NV_ENGCTX(GR, 0x50),
 174         .ofuncs = &(struct nouveau_ofuncs) {
 175                 .ctor = nv50_gr_context_ctor,
 176                 .dtor = _nouveau_gr_context_dtor,
 177                 .init = _nouveau_gr_context_init,
 178                 .fini = _nouveau_gr_context_fini,
 179                 .rd32 = _nouveau_gr_context_rd32,
 180                 .wr32 = _nouveau_gr_context_wr32,
 181         },
 182 };
 183
 184 /*******************************************************************************
 185  * PGRAPH engine/subdev functions
 186  ******************************************************************************/
 187
 188 static const struct nouveau_bitfield nv50_pgr_status[] = {
 189         { 0x00000001, "BUSY" }, /* set when any bit is set */
 190         { 0x00000002, "DISPATCH" },
 191         { 0x00000004, "UNK2" },
 192         { 0x00000008, "UNK3" },
 193         { 0x00000010, "UNK4" },
 194         { 0x00000020, "UNK5" },
 195         { 0x00000040, "M2MF" },
 196         { 0x00000080, "UNK7" },
 197         { 0x00000100, "CTXPROG" },
 198         { 0x00000200, "VFETCH" },
 199         { 0x00000400, "CCACHE_PREGEOM" },
 200         { 0x00000800, "STRMOUT_VATTR_POSTGEOM" },
 201         { 0x00001000, "VCLIP" },
 202         { 0x00002000, "RATTR_APLANE" },
 203         { 0x00004000, "TRAST" },
 204         { 0x00008000, "CLIPID" },
 205         { 0x00010000, "ZCULL" },
 206         { 0x00020000, "ENG2D" },
 207         { 0x00040000, "RMASK" },
 208         { 0x00080000, "TPC_RAST" },
 209         { 0x00100000, "TPC_PROP" },
 210         { 0x00200000, "TPC_TEX" },
 211         { 0x00400000, "TPC_GEOM" },
 212         { 0x00800000, "TPC_MP" },
 213         { 0x01000000, "ROP" },
 214         {}
 215 };
 216
 217 static const char *const nv50_pgr_vstatus_0[] = {
 218         "VFETCH", "CCACHE", "PREGEOM", "POSTGEOM", "VATTR", "STRMOUT", "VCLIP",
 219         NULL
 220 };
 221
 222 static const char *const nv50_pgr_vstatus_1[] = {
 223         "TPC_RAST", "TPC_PROP", "TPC_TEX", "TPC_GEOM", "TPC_MP", NULL
 224 };
 225
 226 static const char *const nv50_pgr_vstatus_2[] = {
 227         "RATTR", "APLANE", "TRAST", "CLIPID", "ZCULL", "ENG2D", "RMASK",
 228         "ROP", NULL
 229 };
 230
 231 static void nouveau_pgr_vstatus_print(struct nv50_gr_priv *priv, int r,
 232                 const char *const units[], u32 status)
 233 {
 234         int i;
 235
 236         nv_error(priv, "PGRAPH_VSTATUS%d: 0x%08x", r, status);
 237
 238         for (i = 0; units[i] && status; i++) {
 239                 if ((status & 7) == 1)
 240                         pr_cont(" %s", units[i]);
 241                 status >>= 3;
 242         }
 243         if (status)
 244                 pr_cont(" (invalid: 0x%x)", status);
 245         pr_cont("\n");
 246 }
 247
 248 static int
 249 nv84_gr_tlb_flush(struct nouveau_engine *engine)
 250 {
 251         struct nouveau_timer *ptimer = nouveau_timer(engine);
 252         struct nv50_gr_priv *priv = (void *)engine;
 253         bool idle, timeout = false;
 254         unsigned long flags;
 255         u64 start;
 256         u32 tmp;
 257
 258         spin_lock_irqsave(&priv->lock, flags);
 259         nv_mask(priv, 0x400500, 0x00000001, 0x00000000);
 260
 261         start = ptimer->read(ptimer);
 262         do {
 263                 idle = true;
 264
 265                 for (tmp = nv_rd32(priv, 0x400380); tmp && idle; tmp >>= 3) {
 266                         if ((tmp & 7) == 1)
 267                                 idle = false;
 268                 }
 269
 270                 for (tmp = nv_rd32(priv, 0x400384); tmp && idle; tmp >>= 3) {
 271                         if ((tmp & 7) == 1)
 272                                 idle = false;
 273                 }
 274
 275                 for (tmp = nv_rd32(priv, 0x400388); tmp && idle; tmp >>= 3) {
 276                         if ((tmp & 7) == 1)
 277                                 idle = false;
 278                 }
 279         } while (!idle &&
 280                  !(timeout = ptimer->read(ptimer) - start > 2000000000));
 281
 282         if (timeout) {
 283                 nv_error(priv, "PGRAPH TLB flush idle timeout fail\n");
 284
 285                 tmp = nv_rd32(priv, 0x400700);
 286                 nv_error(priv, "PGRAPH_STATUS  : 0x%08x", tmp);
 287                 nouveau_bitfield_print(nv50_pgr_status, tmp);
 288                 pr_cont("\n");
 289
 290                 nouveau_pgr_vstatus_print(priv, 0, nv50_pgr_vstatus_0,
 291                                 nv_rd32(priv, 0x400380));
 292                 nouveau_pgr_vstatus_print(priv, 1, nv50_pgr_vstatus_1,
 293                                 nv_rd32(priv, 0x400384));
 294                 nouveau_pgr_vstatus_print(priv, 2, nv50_pgr_vstatus_2,
 295                                 nv_rd32(priv, 0x400388));
 296         }
 297
 298
 299         nv_wr32(priv, 0x100c80, 0x00000001);
 300         if (!nv_wait(priv, 0x100c80, 0x00000001, 0x00000000))
 301                 nv_error(priv, "vm flush timeout\n");
 302         nv_mask(priv, 0x400500, 0x00000001, 0x00000001);
 303         spin_unlock_irqrestore(&priv->lock, flags);
 304         return timeout ? -EBUSY : 0;
 305 }
 306
 307 static const struct nouveau_bitfield nv50_mp_exec_errors[] = {
 308         { 0x01, "STACK_UNDERFLOW" },
 309         { 0x02, "STACK_MISMATCH" },
 310         { 0x04, "QUADON_ACTIVE" },
 311         { 0x08, "TIMEOUT" },
 312         { 0x10, "INVALID_OPCODE" },
 313         { 0x20, "PM_OVERFLOW" },
 314         { 0x40, "BREAKPOINT" },
 315         {}
 316 };
 317
 318 static const struct nouveau_bitfield nv50_mpc_traps[] = {
 319         { 0x0000001, "LOCAL_LIMIT_READ" },
 320         { 0x0000010, "LOCAL_LIMIT_WRITE" },
 321         { 0x0000040, "STACK_LIMIT" },
 322         { 0x0000100, "GLOBAL_LIMIT_READ" },
 323         { 0x0001000, "GLOBAL_LIMIT_WRITE" },
 324         { 0x0010000, "MP0" },
 325         { 0x0020000, "MP1" },
 326         { 0x0040000, "GLOBAL_LIMIT_RED" },
 327         { 0x0400000, "GLOBAL_LIMIT_ATOM" },
 328         { 0x4000000, "MP2" },
 329         {}
 330 };
 331
 332 static const struct nouveau_bitfield nv50_tex_traps[] = {
 333         { 0x00000001, "" }, /* any bit set? */
 334         { 0x00000002, "FAULT" },
 335         { 0x00000004, "STORAGE_TYPE_MISMATCH" },
 336         { 0x00000008, "LINEAR_MISMATCH" },
 337         { 0x00000020, "WRONG_MEMTYPE" },
 338         {}
 339 };
 340
 341 static const struct nouveau_bitfield nv50_gr_trap_m2mf[] = {
 342         { 0x00000001, "NOTIFY" },
 343         { 0x00000002, "IN" },
 344         { 0x00000004, "OUT" },
 345         {}
 346 };
 347
 348 static const struct nouveau_bitfield nv50_gr_trap_vfetch[] = {
 349         { 0x00000001, "FAULT" },
 350         {}
 351 };
 352
 353 static const struct nouveau_bitfield nv50_gr_trap_strmout[] = {
 354         { 0x00000001, "FAULT" },
 355         {}
 356 };
 357
 358 static const struct nouveau_bitfield nv50_gr_trap_ccache[] = {
 359         { 0x00000001, "FAULT" },
 360         {}
 361 };
 362
 363 /* There must be a *lot* of these. Will take some time to gather them up. */
 364 const struct nouveau_enum nv50_data_error_names[] = {
 365         { 0x00000003, "INVALID_OPERATION", NULL },
 366         { 0x00000004, "INVALID_VALUE", NULL },
 367         { 0x00000005, "INVALID_ENUM", NULL },
 368         { 0x00000008, "INVALID_OBJECT", NULL },
 369         { 0x00000009, "READ_ONLY_OBJECT", NULL },
 370         { 0x0000000a, "SUPERVISOR_OBJECT", NULL },
 371         { 0x0000000b, "INVALID_ADDRESS_ALIGNMENT", NULL },
 372         { 0x0000000c, "INVALID_BITFIELD", NULL },
 373         { 0x0000000d, "BEGIN_END_ACTIVE", NULL },
 374         { 0x0000000e, "SEMANTIC_COLOR_BACK_OVER_LIMIT", NULL },
 375         { 0x0000000f, "VIEWPORT_ID_NEEDS_GP", NULL },
 376         { 0x00000010, "RT_DOUBLE_BIND", NULL },
 377         { 0x00000011, "RT_TYPES_MISMATCH", NULL },
 378         { 0x00000012, "RT_LINEAR_WITH_ZETA", NULL },
 379         { 0x00000015, "FP_TOO_FEW_REGS", NULL },
 380         { 0x00000016, "ZETA_FORMAT_CSAA_MISMATCH", NULL },
 381         { 0x00000017, "RT_LINEAR_WITH_MSAA", NULL },
 382         { 0x00000018, "FP_INTERPOLANT_START_OVER_LIMIT", NULL },
 383         { 0x00000019, "SEMANTIC_LAYER_OVER_LIMIT", NULL },
 384         { 0x0000001a, "RT_INVALID_ALIGNMENT", NULL },
 385         { 0x0000001b, "SAMPLER_OVER_LIMIT", NULL },
 386         { 0x0000001c, "TEXTURE_OVER_LIMIT", NULL },
 387         { 0x0000001e, "GP_TOO_MANY_OUTPUTS", NULL },
 388         { 0x0000001f, "RT_BPP128_WITH_MS8", NULL },
 389         { 0x00000021, "Z_OUT_OF_BOUNDS", NULL },
 390         { 0x00000023, "XY_OUT_OF_BOUNDS", NULL },
 391         { 0x00000024, "VP_ZERO_INPUTS", NULL },
 392         { 0x00000027, "CP_MORE_PARAMS_THAN_SHARED", NULL },
 393         { 0x00000028, "CP_NO_REG_SPACE_STRIPED", NULL },
 394         { 0x00000029, "CP_NO_REG_SPACE_PACKED", NULL },
 395         { 0x0000002a, "CP_NOT_ENOUGH_WARPS", NULL },
 396         { 0x0000002b, "CP_BLOCK_SIZE_MISMATCH", NULL },
 397         { 0x0000002c, "CP_NOT_ENOUGH_LOCAL_WARPS", NULL },
 398         { 0x0000002d, "CP_NOT_ENOUGH_STACK_WARPS", NULL },
 399         { 0x0000002e, "CP_NO_BLOCKDIM_LATCH", NULL },
 400         { 0x00000031, "ENG2D_FORMAT_MISMATCH", NULL },
 401         { 0x0000003f, "PRIMITIVE_ID_NEEDS_GP", NULL },
 402         { 0x00000044, "SEMANTIC_VIEWPORT_OVER_LIMIT", NULL },
 403         { 0x00000045, "SEMANTIC_COLOR_FRONT_OVER_LIMIT", NULL },
 404         { 0x00000046, "LAYER_ID_NEEDS_GP", NULL },
 405         { 0x00000047, "SEMANTIC_CLIP_OVER_LIMIT", NULL },
 406         { 0x00000048, "SEMANTIC_PTSZ_OVER_LIMIT", NULL },
 407         {}
 408 };
 409
 410 static const struct nouveau_bitfield nv50_gr_intr_name[] = {
 411         { 0x00000001, "NOTIFY" },
 412         { 0x00000002, "COMPUTE_QUERY" },
 413         { 0x00000010, "ILLEGAL_MTHD" },
 414         { 0x00000020, "ILLEGAL_CLASS" },
 415         { 0x00000040, "DOUBLE_NOTIFY" },
 416         { 0x00001000, "CONTEXT_SWITCH" },
 417         { 0x00010000, "BUFFER_NOTIFY" },
 418         { 0x00100000, "DATA_ERROR" },
 419         { 0x00200000, "TRAP" },
 420         { 0x01000000, "SINGLE_STEP" },
 421         {}
 422 };
 423
 424 static const struct nouveau_bitfield nv50_gr_trap_prop[] = {
 425         { 0x00000004, "SURF_WIDTH_OVERRUN" },
 426         { 0x00000008, "SURF_HEIGHT_OVERRUN" },
 427         { 0x00000010, "DST2D_FAULT" },
 428         { 0x00000020, "ZETA_FAULT" },
 429         { 0x00000040, "RT_FAULT" },
 430         { 0x00000080, "CUDA_FAULT" },
 431         { 0x00000100, "DST2D_STORAGE_TYPE_MISMATCH" },
 432         { 0x00000200, "ZETA_STORAGE_TYPE_MISMATCH" },
 433         { 0x00000400, "RT_STORAGE_TYPE_MISMATCH" },
 434         { 0x00000800, "DST2D_LINEAR_MISMATCH" },
 435         { 0x00001000, "RT_LINEAR_MISMATCH" },
 436         {}
 437 };
 438
 439 static void
 440 nv50_priv_prop_trap(struct nv50_gr_priv *priv,
 441                     u32 ustatus_addr, u32 ustatus, u32 tp)
 442 {
 443         u32 e0c = nv_rd32(priv, ustatus_addr + 0x04);
 444         u32 e10 = nv_rd32(priv, ustatus_addr + 0x08);
 445         u32 e14 = nv_rd32(priv, ustatus_addr + 0x0c);
 446         u32 e18 = nv_rd32(priv, ustatus_addr + 0x10);
 447         u32 e1c = nv_rd32(priv, ustatus_addr + 0x14);
 448         u32 e20 = nv_rd32(priv, ustatus_addr + 0x18);
 449         u32 e24 = nv_rd32(priv, ustatus_addr + 0x1c);
 450
 451         /* CUDA memory: l[], g[] or stack. */
 452         if (ustatus & 0x00000080) {
 453                 if (e18 & 0x80000000) {
 454                         /* g[] read fault? */
 455                         nv_error(priv, "TRAP_PROP - TP %d - CUDA_FAULT - Global read fault at address %02x%08x\n",
 456                                          tp, e14, e10 | ((e18 >> 24) & 0x1f));
 457                         e18 &= ~0x1f000000;
 458                 } else if (e18 & 0xc) {
 459                         /* g[] write fault? */
 460                         nv_error(priv, "TRAP_PROP - TP %d - CUDA_FAULT - Global write fault at address %02x%08x\n",
 461                                  tp, e14, e10 | ((e18 >> 7) & 0x1f));
 462                         e18 &= ~0x00000f80;
 463                 } else {
 464                         nv_error(priv, "TRAP_PROP - TP %d - Unknown CUDA fault at address %02x%08x\n",
 465                                  tp, e14, e10);
 466                 }
 467                 ustatus &= ~0x00000080;
 468         }
 469         if (ustatus) {
 470                 nv_error(priv, "TRAP_PROP - TP %d -", tp);
 471                 nouveau_bitfield_print(nv50_gr_trap_prop, ustatus);
 472                 pr_cont(" - Address %02x%08x\n", e14, e10);
 473         }
 474         nv_error(priv, "TRAP_PROP - TP %d - e0c: %08x, e18: %08x, e1c: %08x, e20: %08x, e24: %08x\n",
 475                  tp, e0c, e18, e1c, e20, e24);
 476 }
 477
 478 static void
 479 nv50_priv_mp_trap(struct nv50_gr_priv *priv, int tpid, int display)
 480 {
 481         u32 units = nv_rd32(priv, 0x1540);
 482         u32 addr, mp10, status, pc, oplow, ophigh;
 483         int i;
 484         int mps = 0;
 485         for (i = 0; i < 4; i++) {
 486                 if (!(units & 1 << (i+24)))
 487                         continue;
 488                 if (nv_device(priv)->chipset < 0xa0)
 489                         addr = 0x408200 + (tpid << 12) + (i << 7);
 490                 else
 491                         addr = 0x408100 + (tpid << 11) + (i << 7);
 492                 mp10 = nv_rd32(priv, addr + 0x10);
 493                 status = nv_rd32(priv, addr + 0x14);
 494                 if (!status)
 495                         continue;
 496                 if (display) {
 497                         nv_rd32(priv, addr + 0x20);
 498                         pc = nv_rd32(priv, addr + 0x24);
 499                         oplow = nv_rd32(priv, addr + 0x70);
 500                         ophigh = nv_rd32(priv, addr + 0x74);
 501                         nv_error(priv, "TRAP_MP_EXEC - "
 502                                         "TP %d MP %d:", tpid, i);
 503                         nouveau_bitfield_print(nv50_mp_exec_errors, status);
 504                         pr_cont(" at %06x warp %d, opcode %08x %08x\n",
 505                                         pc&0xffffff, pc >> 24,
 506                                         oplow, ophigh);
 507                 }
 508                 nv_wr32(priv, addr + 0x10, mp10);
 509                 nv_wr32(priv, addr + 0x14, 0);
 510                 mps++;
 511         }
 512         if (!mps && display)
 513                 nv_error(priv, "TRAP_MP_EXEC - TP %d: "
 514                                 "No MPs claiming errors?\n", tpid);
 515 }
 516
 517 static void
 518 nv50_priv_tp_trap(struct nv50_gr_priv *priv, int type, u32 ustatus_old,
 519                 u32 ustatus_new, int display, const char *name)
 520 {
 521         int tps = 0;
 522         u32 units = nv_rd32(priv, 0x1540);
 523         int i, r;
 524         u32 ustatus_addr, ustatus;
 525         for (i = 0; i < 16; i++) {
 526                 if (!(units & (1 << i)))
 527                         continue;
 528                 if (nv_device(priv)->chipset < 0xa0)
 529                         ustatus_addr = ustatus_old + (i << 12);
 530                 else
 531                         ustatus_addr = ustatus_new + (i << 11);
 532                 ustatus = nv_rd32(priv, ustatus_addr) & 0x7fffffff;
 533                 if (!ustatus)
 534                         continue;
 535                 tps++;
 536                 switch (type) {
 537                 case 6: /* texture error... unknown for now */
 538                         if (display) {
 539                                 nv_error(priv, "magic set %d:\n", i);
 540                                 for (r = ustatus_addr + 4; r <= ustatus_addr + 0x10; r += 4)
 541                                         nv_error(priv, "\t0x%08x: 0x%08x\n", r,
 542                                                 nv_rd32(priv, r));
 543                                 if (ustatus) {
 544                                         nv_error(priv, "%s - TP%d:", name, i);
 545                                         nouveau_bitfield_print(nv50_tex_traps,
 546                                                                ustatus);
 547                                         pr_cont("\n");
 548                                         ustatus = 0;
 549                                 }
 550                         }
 551                         break;
 552                 case 7: /* MP error */
 553                         if (ustatus & 0x04030000) {
 554                                 nv50_priv_mp_trap(priv, i, display);
 555                                 ustatus &= ~0x04030000;
 556                         }
 557                         if (ustatus && display) {
 558                                 nv_error(priv, "%s - TP%d:", name, i);
 559                                 nouveau_bitfield_print(nv50_mpc_traps, ustatus);
 560                                 pr_cont("\n");
 561                                 ustatus = 0;
 562                         }
 563                         break;
 564                 case 8: /* PROP error */
 565                         if (display)
 566                                 nv50_priv_prop_trap(
 567                                                 priv, ustatus_addr, ustatus, i);
 568                         ustatus = 0;
 569                         break;
 570                 }
 571                 if (ustatus) {
 572                         if (display)
 573                                 nv_error(priv, "%s - TP%d: Unhandled ustatus 0x%08x\n", name, i, ustatus);
 574                 }
 575                 nv_wr32(priv, ustatus_addr, 0xc0000000);
 576         }
 577
 578         if (!tps && display)
 579                 nv_warn(priv, "%s - No TPs claiming errors?\n", name);
 580 }
 581
 582 static int
 583 nv50_gr_trap_handler(struct nv50_gr_priv *priv, u32 display,
 584                         int chid, u64 inst, struct nouveau_object *engctx)
 585 {
 586         u32 status = nv_rd32(priv, 0x400108);
 587         u32 ustatus;
 588
 589         if (!status && display) {
 590                 nv_error(priv, "TRAP: no units reporting traps?\n");
 591                 return 1;
 592         }
 593
 594         /* DISPATCH: Relays commands to other units and handles NOTIFY,
 595          * COND, QUERY. If you get a trap from it, the command is still stuck
 596          * in DISPATCH and you need to do something about it. */
 597         if (status & 0x001) {
 598                 ustatus = nv_rd32(priv, 0x400804) & 0x7fffffff;
 599                 if (!ustatus && display) {
 600                         nv_error(priv, "TRAP_DISPATCH - no ustatus?\n");
 601                 }
 602
 603                 nv_wr32(priv, 0x400500, 0x00000000);
 604
 605                 /* Known to be triggered by screwed up NOTIFY and COND... */
 606                 if (ustatus & 0x00000001) {
 607                         u32 addr = nv_rd32(priv, 0x400808);
 608                         u32 subc = (addr & 0x00070000) >> 16;
 609                         u32 mthd = (addr & 0x00001ffc);
 610                         u32 datal = nv_rd32(priv, 0x40080c);
 611                         u32 datah = nv_rd32(priv, 0x400810);
 612                         u32 class = nv_rd32(priv, 0x400814);
 613                         u32 r848 = nv_rd32(priv, 0x400848);
 614
 615                         nv_error(priv, "TRAP DISPATCH_FAULT\n");
 616                         if (display && (addr & 0x80000000)) {
 617                                 nv_error(priv,
 618                                          "ch %d [0x%010llx %s] subc %d class 0x%04x mthd 0x%04x data 0x%08x%08x 400808 0x%08x 400848 0x%08x\n",
 619                                          chid, inst,
 620                                          nouveau_client_name(engctx), subc,
 621                                          class, mthd, datah, datal, addr, r848);
 622                         } else
 623                         if (display) {
 624                                 nv_error(priv, "no stuck command?\n");
 625                         }
 626
 627                         nv_wr32(priv, 0x400808, 0);
 628                         nv_wr32(priv, 0x4008e8, nv_rd32(priv, 0x4008e8) & 3);
 629                         nv_wr32(priv, 0x400848, 0);
 630                         ustatus &= ~0x00000001;
 631                 }
 632
 633                 if (ustatus & 0x00000002) {
 634                         u32 addr = nv_rd32(priv, 0x40084c);
 635                         u32 subc = (addr & 0x00070000) >> 16;
 636                         u32 mthd = (addr & 0x00001ffc);
 637                         u32 data = nv_rd32(priv, 0x40085c);
 638                         u32 class = nv_rd32(priv, 0x400814);
 639
 640                         nv_error(priv, "TRAP DISPATCH_QUERY\n");
 641                         if (display && (addr & 0x80000000)) {
 642                                 nv_error(priv,
 643                                          "ch %d [0x%010llx %s] subc %d class 0x%04x mthd 0x%04x data 0x%08x 40084c 0x%08x\n",
 644                                          chid, inst,
 645                                          nouveau_client_name(engctx), subc,
 646                                          class, mthd, data, addr);
 647                         } else
 648                         if (display) {
 649                                 nv_error(priv, "no stuck command?\n");
 650                         }
 651
 652                         nv_wr32(priv, 0x40084c, 0);
 653                         ustatus &= ~0x00000002;
 654                 }
 655
 656                 if (ustatus && display) {
 657                         nv_error(priv, "TRAP_DISPATCH (unknown "
 658                                       "0x%08x)\n", ustatus);
 659                 }
 660
 661                 nv_wr32(priv, 0x400804, 0xc0000000);
 662                 nv_wr32(priv, 0x400108, 0x001);
 663                 status &= ~0x001;
 664                 if (!status)
 665                         return 0;
 666         }
 667
 668         /* M2MF: Memory to memory copy engine. */
 669         if (status & 0x002) {
 670                 u32 ustatus = nv_rd32(priv, 0x406800) & 0x7fffffff;
 671                 if (display) {
 672                         nv_error(priv, "TRAP_M2MF");
 673                         nouveau_bitfield_print(nv50_gr_trap_m2mf, ustatus);
 674                         pr_cont("\n");
 675                         nv_error(priv, "TRAP_M2MF %08x %08x %08x %08x\n",
 676                                 nv_rd32(priv, 0x406804), nv_rd32(priv, 0x406808),
 677                                 nv_rd32(priv, 0x40680c), nv_rd32(priv, 0x406810));
 678
 679                 }
 680
 681                 /* No sane way found yet -- just reset the bugger. */
 682                 nv_wr32(priv, 0x400040, 2);
 683                 nv_wr32(priv, 0x400040, 0);
 684                 nv_wr32(priv, 0x406800, 0xc0000000);
 685                 nv_wr32(priv, 0x400108, 0x002);
 686                 status &= ~0x002;
 687         }
 688
 689         /* VFETCH: Fetches data from vertex buffers. */
 690         if (status & 0x004) {
 691                 u32 ustatus = nv_rd32(priv, 0x400c04) & 0x7fffffff;
 692                 if (display) {
 693                         nv_error(priv, "TRAP_VFETCH");
 694                         nouveau_bitfield_print(nv50_gr_trap_vfetch, ustatus);
 695                         pr_cont("\n");
 696                         nv_error(priv, "TRAP_VFETCH %08x %08x %08x %08x\n",
 697                                 nv_rd32(priv, 0x400c00), nv_rd32(priv, 0x400c08),
 698                                 nv_rd32(priv, 0x400c0c), nv_rd32(priv, 0x400c10));
 699                 }
 700
 701                 nv_wr32(priv, 0x400c04, 0xc0000000);
 702                 nv_wr32(priv, 0x400108, 0x004);
 703                 status &= ~0x004;
 704         }
 705
 706         /* STRMOUT: DirectX streamout / OpenGL transform feedback. */
 707         if (status & 0x008) {
 708                 ustatus = nv_rd32(priv, 0x401800) & 0x7fffffff;
 709                 if (display) {
 710                         nv_error(priv, "TRAP_STRMOUT");
 711                         nouveau_bitfield_print(nv50_gr_trap_strmout, ustatus);
 712                         pr_cont("\n");
 713                         nv_error(priv, "TRAP_STRMOUT %08x %08x %08x %08x\n",
 714                                 nv_rd32(priv, 0x401804), nv_rd32(priv, 0x401808),
 715                                 nv_rd32(priv, 0x40180c), nv_rd32(priv, 0x401810));
 716
 717                 }
 718
 719                 /* No sane way found yet -- just reset the bugger. */
 720                 nv_wr32(priv, 0x400040, 0x80);
 721                 nv_wr32(priv, 0x400040, 0);
 722                 nv_wr32(priv, 0x401800, 0xc0000000);
 723                 nv_wr32(priv, 0x400108, 0x008);
 724                 status &= ~0x008;
 725         }
 726
 727         /* CCACHE: Handles code and c[] caches and fills them. */
 728         if (status & 0x010) {
 729                 ustatus = nv_rd32(priv, 0x405018) & 0x7fffffff;
 730                 if (display) {
 731                         nv_error(priv, "TRAP_CCACHE");
 732                         nouveau_bitfield_print(nv50_gr_trap_ccache, ustatus);
 733                         pr_cont("\n");
 734                         nv_error(priv, "TRAP_CCACHE %08x %08x %08x %08x"
 735                                      " %08x %08x %08x\n",
 736                                 nv_rd32(priv, 0x405000), nv_rd32(priv, 0x405004),
 737                                 nv_rd32(priv, 0x405008), nv_rd32(priv, 0x40500c),
 738                                 nv_rd32(priv, 0x405010), nv_rd32(priv, 0x405014),
 739                                 nv_rd32(priv, 0x40501c));
 740
 741                 }
 742
 743                 nv_wr32(priv, 0x405018, 0xc0000000);
 744                 nv_wr32(priv, 0x400108, 0x010);
 745                 status &= ~0x010;
 746         }
 747
 748         /* Unknown, not seen yet... 0x402000 is the only trap status reg
 749          * remaining, so try to handle it anyway. Perhaps related to that
 750          * unknown DMA slot on tesla? */
 751         if (status & 0x20) {
 752                 ustatus = nv_rd32(priv, 0x402000) & 0x7fffffff;
 753                 if (display)
 754                         nv_error(priv, "TRAP_UNKC04 0x%08x\n", ustatus);
 755                 nv_wr32(priv, 0x402000, 0xc0000000);
 756                 /* no status modifiction on purpose */
 757         }
 758
 759         /* TEXTURE: CUDA texturing units */
 760         if (status & 0x040) {
 761                 nv50_priv_tp_trap(priv, 6, 0x408900, 0x408600, display,
 762                                     "TRAP_TEXTURE");
 763                 nv_wr32(priv, 0x400108, 0x040);
 764                 status &= ~0x040;
 765         }
 766
 767         /* MP: CUDA execution engines. */
 768         if (status & 0x080) {
 769                 nv50_priv_tp_trap(priv, 7, 0x408314, 0x40831c, display,
 770                                     "TRAP_MP");
 771                 nv_wr32(priv, 0x400108, 0x080);
 772                 status &= ~0x080;
 773         }
 774
 775         /* PROP:  Handles TP-initiated uncached memory accesses:
 776          * l[], g[], stack, 2d surfaces, render targets. */
 777         if (status & 0x100) {
 778                 nv50_priv_tp_trap(priv, 8, 0x408e08, 0x408708, display,
 779                                     "TRAP_PROP");
 780                 nv_wr32(priv, 0x400108, 0x100);
 781                 status &= ~0x100;
 782         }
 783
 784         if (status) {
 785                 if (display)
 786                         nv_error(priv, "TRAP: unknown 0x%08x\n", status);
 787                 nv_wr32(priv, 0x400108, status);
 788         }
 789
 790         return 1;
 791 }
 792
 793 static void
 794 nv50_gr_intr(struct nouveau_subdev *subdev)
 795 {
 796         struct nouveau_fifo *pfifo = nouveau_fifo(subdev);
 797         struct nouveau_engine *engine = nv_engine(subdev);
 798         struct nouveau_object *engctx;
 799         struct nouveau_handle *handle = NULL;
 800         struct nv50_gr_priv *priv = (void *)subdev;
 801         u32 stat = nv_rd32(priv, 0x400100);
 802         u32 inst = nv_rd32(priv, 0x40032c) & 0x0fffffff;
 803         u32 addr = nv_rd32(priv, 0x400704);
 804         u32 subc = (addr & 0x00070000) >> 16;
 805         u32 mthd = (addr & 0x00001ffc);
 806         u32 data = nv_rd32(priv, 0x400708);
 807         u32 class = nv_rd32(priv, 0x400814);
 808         u32 show = stat, show_bitfield = stat;
 809         int chid;
 810
 811         engctx = nouveau_engctx_get(engine, inst);
 812         chid   = pfifo->chid(pfifo, engctx);
 813
 814         if (stat & 0x00000010) {
 815                 handle = nouveau_handle_get_class(engctx, class);
 816                 if (handle && !nv_call(handle->object, mthd, data))
 817                         show &= ~0x00000010;
 818                 nouveau_handle_put(handle);
 819         }
 820
 821         if (show & 0x00100000) {
 822                 u32 ecode = nv_rd32(priv, 0x400110);
 823                 nv_error(priv, "DATA_ERROR ");
 824                 nouveau_enum_print(nv50_data_error_names, ecode);
 825                 pr_cont("\n");
 826                 show_bitfield &= ~0x00100000;
 827         }
 828
 829         if (stat & 0x00200000) {
 830                 if (!nv50_gr_trap_handler(priv, show, chid, (u64)inst << 12,
 831                                 engctx))
 832                         show &= ~0x00200000;
 833                 show_bitfield &= ~0x00200000;
 834         }
 835
 836         nv_wr32(priv, 0x400100, stat);
 837         nv_wr32(priv, 0x400500, 0x00010001);
 838
 839         if (show) {
 840                 show &= show_bitfield;
 841                 if (show) {
 842                         nv_error(priv, "%s", "");
 843                         nouveau_bitfield_print(nv50_gr_intr_name, show);
 844                         pr_cont("\n");
 845                 }
 846                 nv_error(priv,
 847                          "ch %d [0x%010llx %s] subc %d class 0x%04x mthd 0x%04x data 0x%08x\n",
 848                          chid, (u64)inst << 12, nouveau_client_name(engctx),
 849                          subc, class, mthd, data);
 850         }
 851
 852         if (nv_rd32(priv, 0x400824) & (1 << 31))
 853                 nv_wr32(priv, 0x400824, nv_rd32(priv, 0x400824) & ~(1 << 31));
 854
 855         nouveau_engctx_put(engctx);
 856 }
 857
 858 static int
 859 nv50_gr_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
 860                struct nouveau_oclass *oclass, void *data, u32 size,
 861                struct nouveau_object **pobject)
 862 {
 863         struct nv50_gr_priv *priv;
 864         int ret;
 865
 866         ret = nouveau_gr_create(parent, engine, oclass, true, &priv);
 867         *pobject = nv_object(priv);
 868         if (ret)
 869                 return ret;
 870
 871         nv_subdev(priv)->unit = 0x00201000;
 872         nv_subdev(priv)->intr = nv50_gr_intr;
 873         nv_engine(priv)->cclass = &nv50_gr_cclass;
 874
 875         priv->base.units = nv50_gr_units;
 876
 877         switch (nv_device(priv)->chipset) {
 878         case 0x50:
 879                 nv_engine(priv)->sclass = nv50_gr_sclass;
 880                 break;
 881         case 0x84:
 882         case 0x86:
 883         case 0x92:
 884         case 0x94:
 885         case 0x96:
 886         case 0x98:
 887                 nv_engine(priv)->sclass = nv84_gr_sclass;
 888                 break;
 889         case 0xa0:
 890         case 0xaa:
 891         case 0xac:
 892                 nv_engine(priv)->sclass = nva0_gr_sclass;
 893                 break;
 894         case 0xa3:
 895         case 0xa5:
 896         case 0xa8:
 897                 nv_engine(priv)->sclass = nva3_gr_sclass;
 898                 break;
 899         case 0xaf:
 900                 nv_engine(priv)->sclass = nvaf_gr_sclass;
 901                 break;
 902
 903         }
 904
 905         /* unfortunate hw bug workaround... */
 906         if (nv_device(priv)->chipset != 0x50 &&
 907             nv_device(priv)->chipset != 0xac)
 908                 nv_engine(priv)->tlb_flush = nv84_gr_tlb_flush;
 909
 910         spin_lock_init(&priv->lock);
 911         return 0;
 912 }
 913
 914 static int
 915 nv50_gr_init(struct nouveau_object *object)
 916 {
 917         struct nv50_gr_priv *priv = (void *)object;
 918         int ret, units, i;
 919
 920         ret = nouveau_gr_init(&priv->base);
 921         if (ret)
 922                 return ret;
 923
 924         /* NV_PGRAPH_DEBUG_3_HW_CTX_SWITCH_ENABLED */
 925         nv_wr32(priv, 0x40008c, 0x00000004);
 926
 927         /* reset/enable traps and interrupts */
 928         nv_wr32(priv, 0x400804, 0xc0000000);
 929         nv_wr32(priv, 0x406800, 0xc0000000);
 930         nv_wr32(priv, 0x400c04, 0xc0000000);
 931         nv_wr32(priv, 0x401800, 0xc0000000);
 932         nv_wr32(priv, 0x405018, 0xc0000000);
 933         nv_wr32(priv, 0x402000, 0xc0000000);
 934
 935         units = nv_rd32(priv, 0x001540);
 936         for (i = 0; i < 16; i++) {
 937                 if (!(units & (1 << i)))
 938                         continue;
 939
 940                 if (nv_device(priv)->chipset < 0xa0) {
 941                         nv_wr32(priv, 0x408900 + (i << 12), 0xc0000000);
 942                         nv_wr32(priv, 0x408e08 + (i << 12), 0xc0000000);
 943                         nv_wr32(priv, 0x408314 + (i << 12), 0xc0000000);
 944                 } else {
 945                         nv_wr32(priv, 0x408600 + (i << 11), 0xc0000000);
 946                         nv_wr32(priv, 0x408708 + (i << 11), 0xc0000000);
 947                         nv_wr32(priv, 0x40831c + (i << 11), 0xc0000000);
 948                 }
 949         }
 950
 951         nv_wr32(priv, 0x400108, 0xffffffff);
 952         nv_wr32(priv, 0x400138, 0xffffffff);
 953         nv_wr32(priv, 0x400100, 0xffffffff);
 954         nv_wr32(priv, 0x40013c, 0xffffffff);
 955         nv_wr32(priv, 0x400500, 0x00010001);
 956
 957         /* upload context program, initialise ctxctl defaults */
 958         ret = nv50_grctx_init(nv_device(priv), &priv->size);
 959         if (ret)
 960                 return ret;
 961
 962         nv_wr32(priv, 0x400824, 0x00000000);
 963         nv_wr32(priv, 0x400828, 0x00000000);
 964         nv_wr32(priv, 0x40082c, 0x00000000);
 965         nv_wr32(priv, 0x400830, 0x00000000);
 966         nv_wr32(priv, 0x40032c, 0x00000000);
 967         nv_wr32(priv, 0x400330, 0x00000000);
 968
 969         /* some unknown zcull magic */
 970         switch (nv_device(priv)->chipset & 0xf0) {
 971         case 0x50:
 972         case 0x80:
 973         case 0x90:
 974                 nv_wr32(priv, 0x402ca8, 0x00000800);
 975                 break;
 976         case 0xa0:
 977         default:
 978                 if (nv_device(priv)->chipset == 0xa0 ||
 979                     nv_device(priv)->chipset == 0xaa ||
 980                     nv_device(priv)->chipset == 0xac) {
 981                         nv_wr32(priv, 0x402ca8, 0x00000802);
 982                 } else {
 983                         nv_wr32(priv, 0x402cc0, 0x00000000);
 984                         nv_wr32(priv, 0x402ca8, 0x00000002);
 985                 }
 986
 987                 break;
 988         }
 989
 990         /* zero out zcull regions */
 991         for (i = 0; i < 8; i++) {
 992                 nv_wr32(priv, 0x402c20 + (i * 0x10), 0x00000000);
 993                 nv_wr32(priv, 0x402c24 + (i * 0x10), 0x00000000);
 994                 nv_wr32(priv, 0x402c28 + (i * 0x10), 0x00000000);
 995                 nv_wr32(priv, 0x402c2c + (i * 0x10), 0x00000000);
 996         }
 997         return 0;
 998 }
 999
1000 struct nouveau_oclass
1001 nv50_gr_oclass = {
1002         .handle = NV_ENGINE(GR, 0x50),
1003         .ofuncs = &(struct nouveau_ofuncs) {
1004                 .ctor = nv50_gr_ctor,
1005                 .dtor = _nouveau_gr_dtor,
1006                 .init = nv50_gr_init,
1007                 .fini = _nouveau_gr_fini,
1008         },
1009 };