2 * Copyright 2013 Red Hat Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
22 * Authors: Ben Skeggs <bskeggs@redhat.com>
27 /*******************************************************************************
28 * PGRAPH context register lists
29 ******************************************************************************/
31 static const struct nvc0_graph_init
32 nvd7_grctx_init_ds_0[] = {
33 { 0x405800, 1, 0x04, 0x0f8000bf },
34 { 0x405830, 1, 0x04, 0x02180324 },
35 { 0x405834, 1, 0x04, 0x08000000 },
36 { 0x405838, 1, 0x04, 0x00000000 },
37 { 0x405854, 1, 0x04, 0x00000000 },
38 { 0x405870, 4, 0x04, 0x00000001 },
39 { 0x405a00, 2, 0x04, 0x00000000 },
40 { 0x405a18, 1, 0x04, 0x00000000 },
44 static const struct nvc0_graph_init
45 nvd7_grctx_init_pd_0[] = {
46 { 0x406020, 1, 0x04, 0x000103c1 },
47 { 0x406028, 4, 0x04, 0x00000001 },
48 { 0x4064a8, 1, 0x04, 0x00000000 },
49 { 0x4064ac, 1, 0x04, 0x00003fff },
50 { 0x4064b4, 3, 0x04, 0x00000000 },
51 { 0x4064c0, 1, 0x04, 0x801a0078 },
52 { 0x4064c4, 1, 0x04, 0x00c9ffff },
53 { 0x4064d0, 8, 0x04, 0x00000000 },
57 static const struct nvc0_graph_pack
58 nvd7_grctx_pack_hub[] = {
59 { nvc0_grctx_init_main_0 },
60 { nvd9_grctx_init_fe_0 },
61 { nvc0_grctx_init_pri_0 },
62 { nvc0_grctx_init_memfmt_0 },
63 { nvd7_grctx_init_ds_0 },
64 { nvd7_grctx_init_pd_0 },
65 { nvc0_grctx_init_rstr2d_0 },
66 { nvc0_grctx_init_scc_0 },
67 { nvd9_grctx_init_be_0 },
71 static const struct nvc0_graph_init
72 nvd7_grctx_init_setup_0[] = {
73 { 0x418800, 1, 0x04, 0x7006860a },
74 { 0x418808, 3, 0x04, 0x00000000 },
75 { 0x418828, 1, 0x04, 0x00008442 },
76 { 0x418830, 1, 0x04, 0x10000001 },
77 { 0x4188d8, 1, 0x04, 0x00000008 },
78 { 0x4188e0, 1, 0x04, 0x01000000 },
79 { 0x4188e8, 5, 0x04, 0x00000000 },
80 { 0x4188fc, 1, 0x04, 0x20100018 },
84 static const struct nvc0_graph_pack
85 nvd7_grctx_pack_gpc[] = {
86 { nvc0_grctx_init_gpc_unk_0 },
87 { nvd9_grctx_init_prop_0 },
88 { nvd9_grctx_init_gpc_unk_1 },
89 { nvd7_grctx_init_setup_0 },
90 { nvc0_grctx_init_zcull_0 },
91 { nvd9_grctx_init_crstr_0 },
92 { nvc1_grctx_init_gpm_0 },
93 { nvc0_grctx_init_gcc_0 },
97 const struct nvc0_graph_init
98 nvd7_grctx_init_pe_0[] = {
99 { 0x419848, 1, 0x04, 0x00000000 },
100 { 0x419864, 1, 0x04, 0x00000129 },
101 { 0x419888, 1, 0x04, 0x00000000 },
105 static const struct nvc0_graph_init
106 nvd7_grctx_init_tex_0[] = {
107 { 0x419a00, 1, 0x04, 0x000001f0 },
108 { 0x419a04, 1, 0x04, 0x00000001 },
109 { 0x419a08, 1, 0x04, 0x00000023 },
110 { 0x419a0c, 1, 0x04, 0x00020000 },
111 { 0x419a10, 1, 0x04, 0x00000000 },
112 { 0x419a14, 1, 0x04, 0x00000200 },
113 { 0x419a1c, 1, 0x04, 0x00008000 },
114 { 0x419a20, 1, 0x04, 0x00000800 },
115 { 0x419ac4, 1, 0x04, 0x0017f440 },
119 static const struct nvc0_graph_init
120 nvd7_grctx_init_mpc_0[] = {
121 { 0x419c00, 1, 0x04, 0x0000000a },
122 { 0x419c04, 1, 0x04, 0x00000006 },
123 { 0x419c08, 1, 0x04, 0x00000002 },
124 { 0x419c20, 1, 0x04, 0x00000000 },
125 { 0x419c24, 1, 0x04, 0x00084210 },
126 { 0x419c28, 1, 0x04, 0x3efbefbe },
130 static const struct nvc0_graph_pack
131 nvd7_grctx_pack_tpc[] = {
132 { nvd7_grctx_init_pe_0 },
133 { nvd7_grctx_init_tex_0 },
134 { nvd7_grctx_init_mpc_0 },
135 { nvc4_grctx_init_l1c_0 },
136 { nvd9_grctx_init_sm_0 },
140 static const struct nvc0_graph_init
141 nvd7_grctx_init_pes_0[] = {
142 { 0x41be24, 1, 0x04, 0x00000002 },
146 static const struct nvc0_graph_init
147 nvd7_grctx_init_cbm_0[] = {
148 { 0x41bec0, 1, 0x04, 0x12180000 },
149 { 0x41bec4, 1, 0x04, 0x00003fff },
150 { 0x41bee4, 1, 0x04, 0x03240218 },
154 const struct nvc0_graph_init
155 nvd7_grctx_init_wwdx_0[] = {
156 { 0x41bf00, 1, 0x04, 0x0a418820 },
157 { 0x41bf04, 1, 0x04, 0x062080e6 },
158 { 0x41bf08, 1, 0x04, 0x020398a4 },
159 { 0x41bf0c, 1, 0x04, 0x0e629062 },
160 { 0x41bf10, 1, 0x04, 0x0a418820 },
161 { 0x41bf14, 1, 0x04, 0x000000e6 },
162 { 0x41bfd0, 1, 0x04, 0x00900103 },
163 { 0x41bfe0, 1, 0x04, 0x00400001 },
164 { 0x41bfe4, 1, 0x04, 0x00000000 },
168 static const struct nvc0_graph_pack
169 nvd7_grctx_pack_ppc[] = {
170 { nvd7_grctx_init_pes_0 },
171 { nvd7_grctx_init_cbm_0 },
172 { nvd7_grctx_init_wwdx_0 },
176 /*******************************************************************************
177 * PGRAPH context implementation
178 ******************************************************************************/
181 nvd7_grctx_generate_attrib(struct nvc0_grctx *info)
183 struct nvc0_graph_priv *priv = info->priv;
184 const struct nvc0_grctx_oclass *impl = nvc0_grctx_impl(priv);
185 const u32 alpha = impl->alpha_nr;
186 const u32 beta = impl->attrib_nr;
187 const u32 size = 0x20 * (impl->attrib_nr_max + impl->alpha_nr_max);
188 const u32 access = NV_MEM_ACCESS_RW;
190 const int b = mmio_vram(info, size * priv->tpc_total, (1 << s), access);
191 const int timeslice_mode = 1;
192 const int max_batches = 0xffff;
194 u32 ao = bo + impl->attrib_nr_max * priv->tpc_total;
197 mmio_refn(info, 0x418810, 0x80000000, s, b);
198 mmio_refn(info, 0x419848, 0x10000000, s, b);
199 mmio_wr32(info, 0x405830, (beta << 16) | alpha);
200 mmio_wr32(info, 0x4064c4, ((alpha / 4) << 16) | max_batches);
202 for (gpc = 0; gpc < priv->gpc_nr; gpc++) {
203 for (ppc = 0; ppc < priv->ppc_nr[gpc]; ppc++) {
204 const u32 a = alpha * priv->ppc_tpc_nr[gpc][ppc];
205 const u32 b = beta * priv->ppc_tpc_nr[gpc][ppc];
206 const u32 t = timeslice_mode;
207 const u32 o = PPC_UNIT(gpc, ppc, 0);
208 mmio_skip(info, o + 0xc0, (t << 28) | (b << 16) | ++bo);
209 mmio_wr32(info, o + 0xc0, (t << 28) | (b << 16) | --bo);
210 bo += impl->attrib_nr_max * priv->ppc_tpc_nr[gpc][ppc];
211 mmio_wr32(info, o + 0xe4, (a << 16) | ao);
212 ao += impl->alpha_nr_max * priv->ppc_tpc_nr[gpc][ppc];
218 nvd7_grctx_generate_main(struct nvc0_graph_priv *priv, struct nvc0_grctx *info)
220 struct nvc0_grctx_oclass *oclass = (void *)nv_engine(priv)->cclass;
223 nouveau_mc(priv)->unk260(nouveau_mc(priv), 0);
225 nvc0_graph_mmio(priv, oclass->hub);
226 nvc0_graph_mmio(priv, oclass->gpc);
227 nvc0_graph_mmio(priv, oclass->zcull);
228 nvc0_graph_mmio(priv, oclass->tpc);
229 nvc0_graph_mmio(priv, oclass->ppc);
231 nv_wr32(priv, 0x404154, 0x00000000);
233 oclass->bundle(info);
234 oclass->pagepool(info);
235 oclass->attrib(info);
238 nvc0_grctx_generate_tpcid(priv);
239 nvc0_grctx_generate_r406028(priv);
240 nvc0_grctx_generate_r4060a8(priv);
241 nve4_grctx_generate_r418bb8(priv);
242 nvc0_grctx_generate_r406800(priv);
244 for (i = 0; i < 8; i++)
245 nv_wr32(priv, 0x4064d0 + (i * 0x04), 0x00000000);
247 nvc0_graph_icmd(priv, oclass->icmd);
248 nv_wr32(priv, 0x404154, 0x00000400);
249 nvc0_graph_mthd(priv, oclass->mthd);
250 nouveau_mc(priv)->unk260(nouveau_mc(priv), 1);
253 struct nouveau_oclass *
254 nvd7_grctx_oclass = &(struct nvc0_grctx_oclass) {
255 .base.handle = NV_ENGCTX(GR, 0xd7),
256 .base.ofuncs = &(struct nouveau_ofuncs) {
257 .ctor = nvc0_graph_context_ctor,
258 .dtor = nvc0_graph_context_dtor,
259 .init = _nouveau_graph_context_init,
260 .fini = _nouveau_graph_context_fini,
261 .rd32 = _nouveau_graph_context_rd32,
262 .wr32 = _nouveau_graph_context_wr32,
264 .main = nvd7_grctx_generate_main,
265 .unkn = nve4_grctx_generate_unkn,
266 .hub = nvd7_grctx_pack_hub,
267 .gpc = nvd7_grctx_pack_gpc,
268 .zcull = nvc0_grctx_pack_zcull,
269 .tpc = nvd7_grctx_pack_tpc,
270 .ppc = nvd7_grctx_pack_ppc,
271 .icmd = nvd9_grctx_pack_icmd,
272 .mthd = nvd9_grctx_pack_mthd,
273 .bundle = nvc0_grctx_generate_bundle,
274 .bundle_size = 0x1800,
275 .pagepool = nvc0_grctx_generate_pagepool,
276 .pagepool_size = 0x8000,
277 .attrib = nvd7_grctx_generate_attrib,
278 .attrib_nr_max = 0x324,
280 .alpha_nr_max = 0x7ff,