2 * Copyright 2012 Red Hat Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
26 #include <core/client.h>
27 #include <core/handle.h>
28 #include <core/engctx.h>
29 #include <core/enum.h>
31 #include <subdev/fb.h>
32 #include <subdev/mmu.h>
33 #include <subdev/timer.h>
35 #include <engine/fifo.h>
36 #include <engine/graph.h>
40 struct nv50_graph_priv {
41 struct nouveau_graph base;
46 struct nv50_graph_chan {
47 struct nouveau_graph_chan base;
51 nv50_graph_units(struct nouveau_graph *graph)
53 struct nv50_graph_priv *priv = (void *)graph;
55 return nv_rd32(priv, 0x1540);
58 /*******************************************************************************
59 * Graphics object classes
60 ******************************************************************************/
63 nv50_graph_object_ctor(struct nouveau_object *parent,
64 struct nouveau_object *engine,
65 struct nouveau_oclass *oclass, void *data, u32 size,
66 struct nouveau_object **pobject)
68 struct nouveau_gpuobj *obj;
71 ret = nouveau_gpuobj_create(parent, engine, oclass, 0, parent,
73 *pobject = nv_object(obj);
77 nv_wo32(obj, 0x00, nv_mclass(obj));
78 nv_wo32(obj, 0x04, 0x00000000);
79 nv_wo32(obj, 0x08, 0x00000000);
80 nv_wo32(obj, 0x0c, 0x00000000);
84 static struct nouveau_ofuncs
86 .ctor = nv50_graph_object_ctor,
87 .dtor = _nouveau_gpuobj_dtor,
88 .init = _nouveau_gpuobj_init,
89 .fini = _nouveau_gpuobj_fini,
90 .rd32 = _nouveau_gpuobj_rd32,
91 .wr32 = _nouveau_gpuobj_wr32,
94 static struct nouveau_oclass
95 nv50_graph_sclass[] = {
96 { 0x0030, &nv50_graph_ofuncs },
97 { 0x502d, &nv50_graph_ofuncs },
98 { 0x5039, &nv50_graph_ofuncs },
99 { 0x5097, &nv50_graph_ofuncs },
100 { 0x50c0, &nv50_graph_ofuncs },
104 static struct nouveau_oclass
105 nv84_graph_sclass[] = {
106 { 0x0030, &nv50_graph_ofuncs },
107 { 0x502d, &nv50_graph_ofuncs },
108 { 0x5039, &nv50_graph_ofuncs },
109 { 0x50c0, &nv50_graph_ofuncs },
110 { 0x8297, &nv50_graph_ofuncs },
114 static struct nouveau_oclass
115 nva0_graph_sclass[] = {
116 { 0x0030, &nv50_graph_ofuncs },
117 { 0x502d, &nv50_graph_ofuncs },
118 { 0x5039, &nv50_graph_ofuncs },
119 { 0x50c0, &nv50_graph_ofuncs },
120 { 0x8397, &nv50_graph_ofuncs },
124 static struct nouveau_oclass
125 nva3_graph_sclass[] = {
126 { 0x0030, &nv50_graph_ofuncs },
127 { 0x502d, &nv50_graph_ofuncs },
128 { 0x5039, &nv50_graph_ofuncs },
129 { 0x50c0, &nv50_graph_ofuncs },
130 { 0x8597, &nv50_graph_ofuncs },
131 { 0x85c0, &nv50_graph_ofuncs },
135 static struct nouveau_oclass
136 nvaf_graph_sclass[] = {
137 { 0x0030, &nv50_graph_ofuncs },
138 { 0x502d, &nv50_graph_ofuncs },
139 { 0x5039, &nv50_graph_ofuncs },
140 { 0x50c0, &nv50_graph_ofuncs },
141 { 0x85c0, &nv50_graph_ofuncs },
142 { 0x8697, &nv50_graph_ofuncs },
146 /*******************************************************************************
148 ******************************************************************************/
151 nv50_graph_context_ctor(struct nouveau_object *parent,
152 struct nouveau_object *engine,
153 struct nouveau_oclass *oclass, void *data, u32 size,
154 struct nouveau_object **pobject)
156 struct nv50_graph_priv *priv = (void *)engine;
157 struct nv50_graph_chan *chan;
160 ret = nouveau_graph_context_create(parent, engine, oclass, NULL,
162 NVOBJ_FLAG_ZERO_ALLOC, &chan);
163 *pobject = nv_object(chan);
167 nv50_grctx_fill(nv_device(priv), nv_gpuobj(chan));
171 static struct nouveau_oclass
172 nv50_graph_cclass = {
173 .handle = NV_ENGCTX(GR, 0x50),
174 .ofuncs = &(struct nouveau_ofuncs) {
175 .ctor = nv50_graph_context_ctor,
176 .dtor = _nouveau_graph_context_dtor,
177 .init = _nouveau_graph_context_init,
178 .fini = _nouveau_graph_context_fini,
179 .rd32 = _nouveau_graph_context_rd32,
180 .wr32 = _nouveau_graph_context_wr32,
184 /*******************************************************************************
185 * PGRAPH engine/subdev functions
186 ******************************************************************************/
188 static const struct nouveau_bitfield nv50_pgraph_status[] = {
189 { 0x00000001, "BUSY" }, /* set when any bit is set */
190 { 0x00000002, "DISPATCH" },
191 { 0x00000004, "UNK2" },
192 { 0x00000008, "UNK3" },
193 { 0x00000010, "UNK4" },
194 { 0x00000020, "UNK5" },
195 { 0x00000040, "M2MF" },
196 { 0x00000080, "UNK7" },
197 { 0x00000100, "CTXPROG" },
198 { 0x00000200, "VFETCH" },
199 { 0x00000400, "CCACHE_PREGEOM" },
200 { 0x00000800, "STRMOUT_VATTR_POSTGEOM" },
201 { 0x00001000, "VCLIP" },
202 { 0x00002000, "RATTR_APLANE" },
203 { 0x00004000, "TRAST" },
204 { 0x00008000, "CLIPID" },
205 { 0x00010000, "ZCULL" },
206 { 0x00020000, "ENG2D" },
207 { 0x00040000, "RMASK" },
208 { 0x00080000, "TPC_RAST" },
209 { 0x00100000, "TPC_PROP" },
210 { 0x00200000, "TPC_TEX" },
211 { 0x00400000, "TPC_GEOM" },
212 { 0x00800000, "TPC_MP" },
213 { 0x01000000, "ROP" },
217 static const char *const nv50_pgraph_vstatus_0[] = {
218 "VFETCH", "CCACHE", "PREGEOM", "POSTGEOM", "VATTR", "STRMOUT", "VCLIP",
222 static const char *const nv50_pgraph_vstatus_1[] = {
223 "TPC_RAST", "TPC_PROP", "TPC_TEX", "TPC_GEOM", "TPC_MP", NULL
226 static const char *const nv50_pgraph_vstatus_2[] = {
227 "RATTR", "APLANE", "TRAST", "CLIPID", "ZCULL", "ENG2D", "RMASK",
231 static void nouveau_pgraph_vstatus_print(struct nv50_graph_priv *priv, int r,
232 const char *const units[], u32 status)
236 nv_error(priv, "PGRAPH_VSTATUS%d: 0x%08x", r, status);
238 for (i = 0; units[i] && status; i++) {
239 if ((status & 7) == 1)
240 pr_cont(" %s", units[i]);
244 pr_cont(" (invalid: 0x%x)", status);
249 nv84_graph_tlb_flush(struct nouveau_engine *engine)
251 struct nouveau_timer *ptimer = nouveau_timer(engine);
252 struct nv50_graph_priv *priv = (void *)engine;
253 bool idle, timeout = false;
258 spin_lock_irqsave(&priv->lock, flags);
259 nv_mask(priv, 0x400500, 0x00000001, 0x00000000);
261 start = ptimer->read(ptimer);
265 for (tmp = nv_rd32(priv, 0x400380); tmp && idle; tmp >>= 3) {
270 for (tmp = nv_rd32(priv, 0x400384); tmp && idle; tmp >>= 3) {
275 for (tmp = nv_rd32(priv, 0x400388); tmp && idle; tmp >>= 3) {
280 !(timeout = ptimer->read(ptimer) - start > 2000000000));
283 nv_error(priv, "PGRAPH TLB flush idle timeout fail\n");
285 tmp = nv_rd32(priv, 0x400700);
286 nv_error(priv, "PGRAPH_STATUS : 0x%08x", tmp);
287 nouveau_bitfield_print(nv50_pgraph_status, tmp);
290 nouveau_pgraph_vstatus_print(priv, 0, nv50_pgraph_vstatus_0,
291 nv_rd32(priv, 0x400380));
292 nouveau_pgraph_vstatus_print(priv, 1, nv50_pgraph_vstatus_1,
293 nv_rd32(priv, 0x400384));
294 nouveau_pgraph_vstatus_print(priv, 2, nv50_pgraph_vstatus_2,
295 nv_rd32(priv, 0x400388));
299 nv_wr32(priv, 0x100c80, 0x00000001);
300 if (!nv_wait(priv, 0x100c80, 0x00000001, 0x00000000))
301 nv_error(priv, "vm flush timeout\n");
302 nv_mask(priv, 0x400500, 0x00000001, 0x00000001);
303 spin_unlock_irqrestore(&priv->lock, flags);
304 return timeout ? -EBUSY : 0;
307 static const struct nouveau_bitfield nv50_mp_exec_errors[] = {
308 { 0x01, "STACK_UNDERFLOW" },
309 { 0x02, "STACK_MISMATCH" },
310 { 0x04, "QUADON_ACTIVE" },
312 { 0x10, "INVALID_OPCODE" },
313 { 0x20, "PM_OVERFLOW" },
314 { 0x40, "BREAKPOINT" },
318 static const struct nouveau_bitfield nv50_mpc_traps[] = {
319 { 0x0000001, "LOCAL_LIMIT_READ" },
320 { 0x0000010, "LOCAL_LIMIT_WRITE" },
321 { 0x0000040, "STACK_LIMIT" },
322 { 0x0000100, "GLOBAL_LIMIT_READ" },
323 { 0x0001000, "GLOBAL_LIMIT_WRITE" },
324 { 0x0010000, "MP0" },
325 { 0x0020000, "MP1" },
326 { 0x0040000, "GLOBAL_LIMIT_RED" },
327 { 0x0400000, "GLOBAL_LIMIT_ATOM" },
328 { 0x4000000, "MP2" },
332 static const struct nouveau_bitfield nv50_tex_traps[] = {
333 { 0x00000001, "" }, /* any bit set? */
334 { 0x00000002, "FAULT" },
335 { 0x00000004, "STORAGE_TYPE_MISMATCH" },
336 { 0x00000008, "LINEAR_MISMATCH" },
337 { 0x00000020, "WRONG_MEMTYPE" },
341 static const struct nouveau_bitfield nv50_graph_trap_m2mf[] = {
342 { 0x00000001, "NOTIFY" },
343 { 0x00000002, "IN" },
344 { 0x00000004, "OUT" },
348 static const struct nouveau_bitfield nv50_graph_trap_vfetch[] = {
349 { 0x00000001, "FAULT" },
353 static const struct nouveau_bitfield nv50_graph_trap_strmout[] = {
354 { 0x00000001, "FAULT" },
358 static const struct nouveau_bitfield nv50_graph_trap_ccache[] = {
359 { 0x00000001, "FAULT" },
363 /* There must be a *lot* of these. Will take some time to gather them up. */
364 const struct nouveau_enum nv50_data_error_names[] = {
365 { 0x00000003, "INVALID_OPERATION", NULL },
366 { 0x00000004, "INVALID_VALUE", NULL },
367 { 0x00000005, "INVALID_ENUM", NULL },
368 { 0x00000008, "INVALID_OBJECT", NULL },
369 { 0x00000009, "READ_ONLY_OBJECT", NULL },
370 { 0x0000000a, "SUPERVISOR_OBJECT", NULL },
371 { 0x0000000b, "INVALID_ADDRESS_ALIGNMENT", NULL },
372 { 0x0000000c, "INVALID_BITFIELD", NULL },
373 { 0x0000000d, "BEGIN_END_ACTIVE", NULL },
374 { 0x0000000e, "SEMANTIC_COLOR_BACK_OVER_LIMIT", NULL },
375 { 0x0000000f, "VIEWPORT_ID_NEEDS_GP", NULL },
376 { 0x00000010, "RT_DOUBLE_BIND", NULL },
377 { 0x00000011, "RT_TYPES_MISMATCH", NULL },
378 { 0x00000012, "RT_LINEAR_WITH_ZETA", NULL },
379 { 0x00000015, "FP_TOO_FEW_REGS", NULL },
380 { 0x00000016, "ZETA_FORMAT_CSAA_MISMATCH", NULL },
381 { 0x00000017, "RT_LINEAR_WITH_MSAA", NULL },
382 { 0x00000018, "FP_INTERPOLANT_START_OVER_LIMIT", NULL },
383 { 0x00000019, "SEMANTIC_LAYER_OVER_LIMIT", NULL },
384 { 0x0000001a, "RT_INVALID_ALIGNMENT", NULL },
385 { 0x0000001b, "SAMPLER_OVER_LIMIT", NULL },
386 { 0x0000001c, "TEXTURE_OVER_LIMIT", NULL },
387 { 0x0000001e, "GP_TOO_MANY_OUTPUTS", NULL },
388 { 0x0000001f, "RT_BPP128_WITH_MS8", NULL },
389 { 0x00000021, "Z_OUT_OF_BOUNDS", NULL },
390 { 0x00000023, "XY_OUT_OF_BOUNDS", NULL },
391 { 0x00000024, "VP_ZERO_INPUTS", NULL },
392 { 0x00000027, "CP_MORE_PARAMS_THAN_SHARED", NULL },
393 { 0x00000028, "CP_NO_REG_SPACE_STRIPED", NULL },
394 { 0x00000029, "CP_NO_REG_SPACE_PACKED", NULL },
395 { 0x0000002a, "CP_NOT_ENOUGH_WARPS", NULL },
396 { 0x0000002b, "CP_BLOCK_SIZE_MISMATCH", NULL },
397 { 0x0000002c, "CP_NOT_ENOUGH_LOCAL_WARPS", NULL },
398 { 0x0000002d, "CP_NOT_ENOUGH_STACK_WARPS", NULL },
399 { 0x0000002e, "CP_NO_BLOCKDIM_LATCH", NULL },
400 { 0x00000031, "ENG2D_FORMAT_MISMATCH", NULL },
401 { 0x0000003f, "PRIMITIVE_ID_NEEDS_GP", NULL },
402 { 0x00000044, "SEMANTIC_VIEWPORT_OVER_LIMIT", NULL },
403 { 0x00000045, "SEMANTIC_COLOR_FRONT_OVER_LIMIT", NULL },
404 { 0x00000046, "LAYER_ID_NEEDS_GP", NULL },
405 { 0x00000047, "SEMANTIC_CLIP_OVER_LIMIT", NULL },
406 { 0x00000048, "SEMANTIC_PTSZ_OVER_LIMIT", NULL },
410 static const struct nouveau_bitfield nv50_graph_intr_name[] = {
411 { 0x00000001, "NOTIFY" },
412 { 0x00000002, "COMPUTE_QUERY" },
413 { 0x00000010, "ILLEGAL_MTHD" },
414 { 0x00000020, "ILLEGAL_CLASS" },
415 { 0x00000040, "DOUBLE_NOTIFY" },
416 { 0x00001000, "CONTEXT_SWITCH" },
417 { 0x00010000, "BUFFER_NOTIFY" },
418 { 0x00100000, "DATA_ERROR" },
419 { 0x00200000, "TRAP" },
420 { 0x01000000, "SINGLE_STEP" },
424 static const struct nouveau_bitfield nv50_graph_trap_prop[] = {
425 { 0x00000004, "SURF_WIDTH_OVERRUN" },
426 { 0x00000008, "SURF_HEIGHT_OVERRUN" },
427 { 0x00000010, "DST2D_FAULT" },
428 { 0x00000020, "ZETA_FAULT" },
429 { 0x00000040, "RT_FAULT" },
430 { 0x00000080, "CUDA_FAULT" },
431 { 0x00000100, "DST2D_STORAGE_TYPE_MISMATCH" },
432 { 0x00000200, "ZETA_STORAGE_TYPE_MISMATCH" },
433 { 0x00000400, "RT_STORAGE_TYPE_MISMATCH" },
434 { 0x00000800, "DST2D_LINEAR_MISMATCH" },
435 { 0x00001000, "RT_LINEAR_MISMATCH" },
440 nv50_priv_prop_trap(struct nv50_graph_priv *priv,
441 u32 ustatus_addr, u32 ustatus, u32 tp)
443 u32 e0c = nv_rd32(priv, ustatus_addr + 0x04);
444 u32 e10 = nv_rd32(priv, ustatus_addr + 0x08);
445 u32 e14 = nv_rd32(priv, ustatus_addr + 0x0c);
446 u32 e18 = nv_rd32(priv, ustatus_addr + 0x10);
447 u32 e1c = nv_rd32(priv, ustatus_addr + 0x14);
448 u32 e20 = nv_rd32(priv, ustatus_addr + 0x18);
449 u32 e24 = nv_rd32(priv, ustatus_addr + 0x1c);
451 /* CUDA memory: l[], g[] or stack. */
452 if (ustatus & 0x00000080) {
453 if (e18 & 0x80000000) {
454 /* g[] read fault? */
455 nv_error(priv, "TRAP_PROP - TP %d - CUDA_FAULT - Global read fault at address %02x%08x\n",
456 tp, e14, e10 | ((e18 >> 24) & 0x1f));
458 } else if (e18 & 0xc) {
459 /* g[] write fault? */
460 nv_error(priv, "TRAP_PROP - TP %d - CUDA_FAULT - Global write fault at address %02x%08x\n",
461 tp, e14, e10 | ((e18 >> 7) & 0x1f));
464 nv_error(priv, "TRAP_PROP - TP %d - Unknown CUDA fault at address %02x%08x\n",
467 ustatus &= ~0x00000080;
470 nv_error(priv, "TRAP_PROP - TP %d -", tp);
471 nouveau_bitfield_print(nv50_graph_trap_prop, ustatus);
472 pr_cont(" - Address %02x%08x\n", e14, e10);
474 nv_error(priv, "TRAP_PROP - TP %d - e0c: %08x, e18: %08x, e1c: %08x, e20: %08x, e24: %08x\n",
475 tp, e0c, e18, e1c, e20, e24);
479 nv50_priv_mp_trap(struct nv50_graph_priv *priv, int tpid, int display)
481 u32 units = nv_rd32(priv, 0x1540);
482 u32 addr, mp10, status, pc, oplow, ophigh;
485 for (i = 0; i < 4; i++) {
486 if (!(units & 1 << (i+24)))
488 if (nv_device(priv)->chipset < 0xa0)
489 addr = 0x408200 + (tpid << 12) + (i << 7);
491 addr = 0x408100 + (tpid << 11) + (i << 7);
492 mp10 = nv_rd32(priv, addr + 0x10);
493 status = nv_rd32(priv, addr + 0x14);
497 nv_rd32(priv, addr + 0x20);
498 pc = nv_rd32(priv, addr + 0x24);
499 oplow = nv_rd32(priv, addr + 0x70);
500 ophigh = nv_rd32(priv, addr + 0x74);
501 nv_error(priv, "TRAP_MP_EXEC - "
502 "TP %d MP %d:", tpid, i);
503 nouveau_bitfield_print(nv50_mp_exec_errors, status);
504 pr_cont(" at %06x warp %d, opcode %08x %08x\n",
505 pc&0xffffff, pc >> 24,
508 nv_wr32(priv, addr + 0x10, mp10);
509 nv_wr32(priv, addr + 0x14, 0);
513 nv_error(priv, "TRAP_MP_EXEC - TP %d: "
514 "No MPs claiming errors?\n", tpid);
518 nv50_priv_tp_trap(struct nv50_graph_priv *priv, int type, u32 ustatus_old,
519 u32 ustatus_new, int display, const char *name)
522 u32 units = nv_rd32(priv, 0x1540);
524 u32 ustatus_addr, ustatus;
525 for (i = 0; i < 16; i++) {
526 if (!(units & (1 << i)))
528 if (nv_device(priv)->chipset < 0xa0)
529 ustatus_addr = ustatus_old + (i << 12);
531 ustatus_addr = ustatus_new + (i << 11);
532 ustatus = nv_rd32(priv, ustatus_addr) & 0x7fffffff;
537 case 6: /* texture error... unknown for now */
539 nv_error(priv, "magic set %d:\n", i);
540 for (r = ustatus_addr + 4; r <= ustatus_addr + 0x10; r += 4)
541 nv_error(priv, "\t0x%08x: 0x%08x\n", r,
544 nv_error(priv, "%s - TP%d:", name, i);
545 nouveau_bitfield_print(nv50_tex_traps,
552 case 7: /* MP error */
553 if (ustatus & 0x04030000) {
554 nv50_priv_mp_trap(priv, i, display);
555 ustatus &= ~0x04030000;
557 if (ustatus && display) {
558 nv_error(priv, "%s - TP%d:", name, i);
559 nouveau_bitfield_print(nv50_mpc_traps, ustatus);
564 case 8: /* PROP error */
567 priv, ustatus_addr, ustatus, i);
573 nv_error(priv, "%s - TP%d: Unhandled ustatus 0x%08x\n", name, i, ustatus);
575 nv_wr32(priv, ustatus_addr, 0xc0000000);
579 nv_warn(priv, "%s - No TPs claiming errors?\n", name);
583 nv50_graph_trap_handler(struct nv50_graph_priv *priv, u32 display,
584 int chid, u64 inst, struct nouveau_object *engctx)
586 u32 status = nv_rd32(priv, 0x400108);
589 if (!status && display) {
590 nv_error(priv, "TRAP: no units reporting traps?\n");
594 /* DISPATCH: Relays commands to other units and handles NOTIFY,
595 * COND, QUERY. If you get a trap from it, the command is still stuck
596 * in DISPATCH and you need to do something about it. */
597 if (status & 0x001) {
598 ustatus = nv_rd32(priv, 0x400804) & 0x7fffffff;
599 if (!ustatus && display) {
600 nv_error(priv, "TRAP_DISPATCH - no ustatus?\n");
603 nv_wr32(priv, 0x400500, 0x00000000);
605 /* Known to be triggered by screwed up NOTIFY and COND... */
606 if (ustatus & 0x00000001) {
607 u32 addr = nv_rd32(priv, 0x400808);
608 u32 subc = (addr & 0x00070000) >> 16;
609 u32 mthd = (addr & 0x00001ffc);
610 u32 datal = nv_rd32(priv, 0x40080c);
611 u32 datah = nv_rd32(priv, 0x400810);
612 u32 class = nv_rd32(priv, 0x400814);
613 u32 r848 = nv_rd32(priv, 0x400848);
615 nv_error(priv, "TRAP DISPATCH_FAULT\n");
616 if (display && (addr & 0x80000000)) {
618 "ch %d [0x%010llx %s] subc %d class 0x%04x mthd 0x%04x data 0x%08x%08x 400808 0x%08x 400848 0x%08x\n",
620 nouveau_client_name(engctx), subc,
621 class, mthd, datah, datal, addr, r848);
624 nv_error(priv, "no stuck command?\n");
627 nv_wr32(priv, 0x400808, 0);
628 nv_wr32(priv, 0x4008e8, nv_rd32(priv, 0x4008e8) & 3);
629 nv_wr32(priv, 0x400848, 0);
630 ustatus &= ~0x00000001;
633 if (ustatus & 0x00000002) {
634 u32 addr = nv_rd32(priv, 0x40084c);
635 u32 subc = (addr & 0x00070000) >> 16;
636 u32 mthd = (addr & 0x00001ffc);
637 u32 data = nv_rd32(priv, 0x40085c);
638 u32 class = nv_rd32(priv, 0x400814);
640 nv_error(priv, "TRAP DISPATCH_QUERY\n");
641 if (display && (addr & 0x80000000)) {
643 "ch %d [0x%010llx %s] subc %d class 0x%04x mthd 0x%04x data 0x%08x 40084c 0x%08x\n",
645 nouveau_client_name(engctx), subc,
646 class, mthd, data, addr);
649 nv_error(priv, "no stuck command?\n");
652 nv_wr32(priv, 0x40084c, 0);
653 ustatus &= ~0x00000002;
656 if (ustatus && display) {
657 nv_error(priv, "TRAP_DISPATCH (unknown "
658 "0x%08x)\n", ustatus);
661 nv_wr32(priv, 0x400804, 0xc0000000);
662 nv_wr32(priv, 0x400108, 0x001);
668 /* M2MF: Memory to memory copy engine. */
669 if (status & 0x002) {
670 u32 ustatus = nv_rd32(priv, 0x406800) & 0x7fffffff;
672 nv_error(priv, "TRAP_M2MF");
673 nouveau_bitfield_print(nv50_graph_trap_m2mf, ustatus);
675 nv_error(priv, "TRAP_M2MF %08x %08x %08x %08x\n",
676 nv_rd32(priv, 0x406804), nv_rd32(priv, 0x406808),
677 nv_rd32(priv, 0x40680c), nv_rd32(priv, 0x406810));
681 /* No sane way found yet -- just reset the bugger. */
682 nv_wr32(priv, 0x400040, 2);
683 nv_wr32(priv, 0x400040, 0);
684 nv_wr32(priv, 0x406800, 0xc0000000);
685 nv_wr32(priv, 0x400108, 0x002);
689 /* VFETCH: Fetches data from vertex buffers. */
690 if (status & 0x004) {
691 u32 ustatus = nv_rd32(priv, 0x400c04) & 0x7fffffff;
693 nv_error(priv, "TRAP_VFETCH");
694 nouveau_bitfield_print(nv50_graph_trap_vfetch, ustatus);
696 nv_error(priv, "TRAP_VFETCH %08x %08x %08x %08x\n",
697 nv_rd32(priv, 0x400c00), nv_rd32(priv, 0x400c08),
698 nv_rd32(priv, 0x400c0c), nv_rd32(priv, 0x400c10));
701 nv_wr32(priv, 0x400c04, 0xc0000000);
702 nv_wr32(priv, 0x400108, 0x004);
706 /* STRMOUT: DirectX streamout / OpenGL transform feedback. */
707 if (status & 0x008) {
708 ustatus = nv_rd32(priv, 0x401800) & 0x7fffffff;
710 nv_error(priv, "TRAP_STRMOUT");
711 nouveau_bitfield_print(nv50_graph_trap_strmout, ustatus);
713 nv_error(priv, "TRAP_STRMOUT %08x %08x %08x %08x\n",
714 nv_rd32(priv, 0x401804), nv_rd32(priv, 0x401808),
715 nv_rd32(priv, 0x40180c), nv_rd32(priv, 0x401810));
719 /* No sane way found yet -- just reset the bugger. */
720 nv_wr32(priv, 0x400040, 0x80);
721 nv_wr32(priv, 0x400040, 0);
722 nv_wr32(priv, 0x401800, 0xc0000000);
723 nv_wr32(priv, 0x400108, 0x008);
727 /* CCACHE: Handles code and c[] caches and fills them. */
728 if (status & 0x010) {
729 ustatus = nv_rd32(priv, 0x405018) & 0x7fffffff;
731 nv_error(priv, "TRAP_CCACHE");
732 nouveau_bitfield_print(nv50_graph_trap_ccache, ustatus);
734 nv_error(priv, "TRAP_CCACHE %08x %08x %08x %08x"
736 nv_rd32(priv, 0x405000), nv_rd32(priv, 0x405004),
737 nv_rd32(priv, 0x405008), nv_rd32(priv, 0x40500c),
738 nv_rd32(priv, 0x405010), nv_rd32(priv, 0x405014),
739 nv_rd32(priv, 0x40501c));
743 nv_wr32(priv, 0x405018, 0xc0000000);
744 nv_wr32(priv, 0x400108, 0x010);
748 /* Unknown, not seen yet... 0x402000 is the only trap status reg
749 * remaining, so try to handle it anyway. Perhaps related to that
750 * unknown DMA slot on tesla? */
752 ustatus = nv_rd32(priv, 0x402000) & 0x7fffffff;
754 nv_error(priv, "TRAP_UNKC04 0x%08x\n", ustatus);
755 nv_wr32(priv, 0x402000, 0xc0000000);
756 /* no status modifiction on purpose */
759 /* TEXTURE: CUDA texturing units */
760 if (status & 0x040) {
761 nv50_priv_tp_trap(priv, 6, 0x408900, 0x408600, display,
763 nv_wr32(priv, 0x400108, 0x040);
767 /* MP: CUDA execution engines. */
768 if (status & 0x080) {
769 nv50_priv_tp_trap(priv, 7, 0x408314, 0x40831c, display,
771 nv_wr32(priv, 0x400108, 0x080);
775 /* PROP: Handles TP-initiated uncached memory accesses:
776 * l[], g[], stack, 2d surfaces, render targets. */
777 if (status & 0x100) {
778 nv50_priv_tp_trap(priv, 8, 0x408e08, 0x408708, display,
780 nv_wr32(priv, 0x400108, 0x100);
786 nv_error(priv, "TRAP: unknown 0x%08x\n", status);
787 nv_wr32(priv, 0x400108, status);
794 nv50_graph_intr(struct nouveau_subdev *subdev)
796 struct nouveau_fifo *pfifo = nouveau_fifo(subdev);
797 struct nouveau_engine *engine = nv_engine(subdev);
798 struct nouveau_object *engctx;
799 struct nouveau_handle *handle = NULL;
800 struct nv50_graph_priv *priv = (void *)subdev;
801 u32 stat = nv_rd32(priv, 0x400100);
802 u32 inst = nv_rd32(priv, 0x40032c) & 0x0fffffff;
803 u32 addr = nv_rd32(priv, 0x400704);
804 u32 subc = (addr & 0x00070000) >> 16;
805 u32 mthd = (addr & 0x00001ffc);
806 u32 data = nv_rd32(priv, 0x400708);
807 u32 class = nv_rd32(priv, 0x400814);
808 u32 show = stat, show_bitfield = stat;
811 engctx = nouveau_engctx_get(engine, inst);
812 chid = pfifo->chid(pfifo, engctx);
814 if (stat & 0x00000010) {
815 handle = nouveau_handle_get_class(engctx, class);
816 if (handle && !nv_call(handle->object, mthd, data))
818 nouveau_handle_put(handle);
821 if (show & 0x00100000) {
822 u32 ecode = nv_rd32(priv, 0x400110);
823 nv_error(priv, "DATA_ERROR ");
824 nouveau_enum_print(nv50_data_error_names, ecode);
826 show_bitfield &= ~0x00100000;
829 if (stat & 0x00200000) {
830 if (!nv50_graph_trap_handler(priv, show, chid, (u64)inst << 12,
833 show_bitfield &= ~0x00200000;
836 nv_wr32(priv, 0x400100, stat);
837 nv_wr32(priv, 0x400500, 0x00010001);
840 show &= show_bitfield;
842 nv_error(priv, "%s", "");
843 nouveau_bitfield_print(nv50_graph_intr_name, show);
847 "ch %d [0x%010llx %s] subc %d class 0x%04x mthd 0x%04x data 0x%08x\n",
848 chid, (u64)inst << 12, nouveau_client_name(engctx),
849 subc, class, mthd, data);
852 if (nv_rd32(priv, 0x400824) & (1 << 31))
853 nv_wr32(priv, 0x400824, nv_rd32(priv, 0x400824) & ~(1 << 31));
855 nouveau_engctx_put(engctx);
859 nv50_graph_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
860 struct nouveau_oclass *oclass, void *data, u32 size,
861 struct nouveau_object **pobject)
863 struct nv50_graph_priv *priv;
866 ret = nouveau_graph_create(parent, engine, oclass, true, &priv);
867 *pobject = nv_object(priv);
871 nv_subdev(priv)->unit = 0x00201000;
872 nv_subdev(priv)->intr = nv50_graph_intr;
873 nv_engine(priv)->cclass = &nv50_graph_cclass;
875 priv->base.units = nv50_graph_units;
877 switch (nv_device(priv)->chipset) {
879 nv_engine(priv)->sclass = nv50_graph_sclass;
887 nv_engine(priv)->sclass = nv84_graph_sclass;
892 nv_engine(priv)->sclass = nva0_graph_sclass;
897 nv_engine(priv)->sclass = nva3_graph_sclass;
900 nv_engine(priv)->sclass = nvaf_graph_sclass;
905 /* unfortunate hw bug workaround... */
906 if (nv_device(priv)->chipset != 0x50 &&
907 nv_device(priv)->chipset != 0xac)
908 nv_engine(priv)->tlb_flush = nv84_graph_tlb_flush;
910 spin_lock_init(&priv->lock);
915 nv50_graph_init(struct nouveau_object *object)
917 struct nv50_graph_priv *priv = (void *)object;
920 ret = nouveau_graph_init(&priv->base);
924 /* NV_PGRAPH_DEBUG_3_HW_CTX_SWITCH_ENABLED */
925 nv_wr32(priv, 0x40008c, 0x00000004);
927 /* reset/enable traps and interrupts */
928 nv_wr32(priv, 0x400804, 0xc0000000);
929 nv_wr32(priv, 0x406800, 0xc0000000);
930 nv_wr32(priv, 0x400c04, 0xc0000000);
931 nv_wr32(priv, 0x401800, 0xc0000000);
932 nv_wr32(priv, 0x405018, 0xc0000000);
933 nv_wr32(priv, 0x402000, 0xc0000000);
935 units = nv_rd32(priv, 0x001540);
936 for (i = 0; i < 16; i++) {
937 if (!(units & (1 << i)))
940 if (nv_device(priv)->chipset < 0xa0) {
941 nv_wr32(priv, 0x408900 + (i << 12), 0xc0000000);
942 nv_wr32(priv, 0x408e08 + (i << 12), 0xc0000000);
943 nv_wr32(priv, 0x408314 + (i << 12), 0xc0000000);
945 nv_wr32(priv, 0x408600 + (i << 11), 0xc0000000);
946 nv_wr32(priv, 0x408708 + (i << 11), 0xc0000000);
947 nv_wr32(priv, 0x40831c + (i << 11), 0xc0000000);
951 nv_wr32(priv, 0x400108, 0xffffffff);
952 nv_wr32(priv, 0x400138, 0xffffffff);
953 nv_wr32(priv, 0x400100, 0xffffffff);
954 nv_wr32(priv, 0x40013c, 0xffffffff);
955 nv_wr32(priv, 0x400500, 0x00010001);
957 /* upload context program, initialise ctxctl defaults */
958 ret = nv50_grctx_init(nv_device(priv), &priv->size);
962 nv_wr32(priv, 0x400824, 0x00000000);
963 nv_wr32(priv, 0x400828, 0x00000000);
964 nv_wr32(priv, 0x40082c, 0x00000000);
965 nv_wr32(priv, 0x400830, 0x00000000);
966 nv_wr32(priv, 0x40032c, 0x00000000);
967 nv_wr32(priv, 0x400330, 0x00000000);
969 /* some unknown zcull magic */
970 switch (nv_device(priv)->chipset & 0xf0) {
974 nv_wr32(priv, 0x402ca8, 0x00000800);
978 if (nv_device(priv)->chipset == 0xa0 ||
979 nv_device(priv)->chipset == 0xaa ||
980 nv_device(priv)->chipset == 0xac) {
981 nv_wr32(priv, 0x402ca8, 0x00000802);
983 nv_wr32(priv, 0x402cc0, 0x00000000);
984 nv_wr32(priv, 0x402ca8, 0x00000002);
990 /* zero out zcull regions */
991 for (i = 0; i < 8; i++) {
992 nv_wr32(priv, 0x402c20 + (i * 0x10), 0x00000000);
993 nv_wr32(priv, 0x402c24 + (i * 0x10), 0x00000000);
994 nv_wr32(priv, 0x402c28 + (i * 0x10), 0x00000000);
995 nv_wr32(priv, 0x402c2c + (i * 0x10), 0x00000000);
1000 struct nouveau_oclass
1001 nv50_graph_oclass = {
1002 .handle = NV_ENGINE(GR, 0x50),
1003 .ofuncs = &(struct nouveau_ofuncs) {
1004 .ctor = nv50_graph_ctor,
1005 .dtor = _nouveau_graph_dtor,
1006 .init = nv50_graph_init,
1007 .fini = _nouveau_graph_fini,