drivers/gpu/drm/nouveau/nvkm/subdev/clk/gf100.c

   1 /*
   2  * Copyright 2012 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24 #include <subdev/clk.h>
  25 #include "pll.h"
  26
  27 #include <subdev/bios.h>
  28 #include <subdev/bios/pll.h>
  29 #include <subdev/timer.h>
  30
  31 struct gf100_clk_info {
  32         u32 freq;
  33         u32 ssel;
  34         u32 mdiv;
  35         u32 dsrc;
  36         u32 ddiv;
  37         u32 coef;
  38 };
  39
  40 struct gf100_clk {
  41         struct nvkm_clk base;
  42         struct gf100_clk_info eng[16];
  43 };
  44
  45 static u32 read_div(struct gf100_clk *, int, u32, u32);
  46
  47 static u32
  48 read_vco(struct gf100_clk *clk, u32 dsrc)
  49 {
  50         struct nvkm_device *device = clk->base.subdev.device;
  51         u32 ssrc = nvkm_rd32(device, dsrc);
  52         if (!(ssrc & 0x00000100))
  53                 return clk->base.read(&clk->base, nv_clk_src_sppll0);
  54         return clk->base.read(&clk->base, nv_clk_src_sppll1);
  55 }
  56
  57 static u32
  58 read_pll(struct gf100_clk *clk, u32 pll)
  59 {
  60         struct nvkm_device *device = clk->base.subdev.device;
  61         u32 ctrl = nvkm_rd32(device, pll + 0x00);
  62         u32 coef = nvkm_rd32(device, pll + 0x04);
  63         u32 P = (coef & 0x003f0000) >> 16;
  64         u32 N = (coef & 0x0000ff00) >> 8;
  65         u32 M = (coef & 0x000000ff) >> 0;
  66         u32 sclk;
  67
  68         if (!(ctrl & 0x00000001))
  69                 return 0;
  70
  71         switch (pll) {
  72         case 0x00e800:
  73         case 0x00e820:
  74                 sclk = device->crystal;
  75                 P = 1;
  76                 break;
  77         case 0x132000:
  78                 sclk = clk->base.read(&clk->base, nv_clk_src_mpllsrc);
  79                 break;
  80         case 0x132020:
  81                 sclk = clk->base.read(&clk->base, nv_clk_src_mpllsrcref);
  82                 break;
  83         case 0x137000:
  84         case 0x137020:
  85         case 0x137040:
  86         case 0x1370e0:
  87                 sclk = read_div(clk, (pll & 0xff) / 0x20, 0x137120, 0x137140);
  88                 break;
  89         default:
  90                 return 0;
  91         }
  92
  93         return sclk * N / M / P;
  94 }
  95
  96 static u32
  97 read_div(struct gf100_clk *clk, int doff, u32 dsrc, u32 dctl)
  98 {
  99         struct nvkm_device *device = clk->base.subdev.device;
 100         u32 ssrc = nvkm_rd32(device, dsrc + (doff * 4));
 101         u32 sctl = nvkm_rd32(device, dctl + (doff * 4));
 102
 103         switch (ssrc & 0x00000003) {
 104         case 0:
 105                 if ((ssrc & 0x00030000) != 0x00030000)
 106                         return device->crystal;
 107                 return 108000;
 108         case 2:
 109                 return 100000;
 110         case 3:
 111                 if (sctl & 0x80000000) {
 112                         u32 sclk = read_vco(clk, dsrc + (doff * 4));
 113                         u32 sdiv = (sctl & 0x0000003f) + 2;
 114                         return (sclk * 2) / sdiv;
 115                 }
 116
 117                 return read_vco(clk, dsrc + (doff * 4));
 118         default:
 119                 return 0;
 120         }
 121 }
 122
 123 static u32
 124 read_clk(struct gf100_clk *clk, int idx)
 125 {
 126         struct nvkm_device *device = clk->base.subdev.device;
 127         u32 sctl = nvkm_rd32(device, 0x137250 + (idx * 4));
 128         u32 ssel = nvkm_rd32(device, 0x137100);
 129         u32 sclk, sdiv;
 130
 131         if (ssel & (1 << idx)) {
 132                 if (idx < 7)
 133                         sclk = read_pll(clk, 0x137000 + (idx * 0x20));
 134                 else
 135                         sclk = read_pll(clk, 0x1370e0);
 136                 sdiv = ((sctl & 0x00003f00) >> 8) + 2;
 137         } else {
 138                 sclk = read_div(clk, idx, 0x137160, 0x1371d0);
 139                 sdiv = ((sctl & 0x0000003f) >> 0) + 2;
 140         }
 141
 142         if (sctl & 0x80000000)
 143                 return (sclk * 2) / sdiv;
 144
 145         return sclk;
 146 }
 147
 148 static int
 149 gf100_clk_read(struct nvkm_clk *obj, enum nv_clk_src src)
 150 {
 151         struct gf100_clk *clk = container_of(obj, typeof(*clk), base);
 152         struct nvkm_device *device = clk->base.subdev.device;
 153
 154         switch (src) {
 155         case nv_clk_src_crystal:
 156                 return device->crystal;
 157         case nv_clk_src_href:
 158                 return 100000;
 159         case nv_clk_src_sppll0:
 160                 return read_pll(clk, 0x00e800);
 161         case nv_clk_src_sppll1:
 162                 return read_pll(clk, 0x00e820);
 163
 164         case nv_clk_src_mpllsrcref:
 165                 return read_div(clk, 0, 0x137320, 0x137330);
 166         case nv_clk_src_mpllsrc:
 167                 return read_pll(clk, 0x132020);
 168         case nv_clk_src_mpll:
 169                 return read_pll(clk, 0x132000);
 170         case nv_clk_src_mdiv:
 171                 return read_div(clk, 0, 0x137300, 0x137310);
 172         case nv_clk_src_mem:
 173                 if (nvkm_rd32(device, 0x1373f0) & 0x00000002)
 174                         return clk->base.read(&clk->base, nv_clk_src_mpll);
 175                 return clk->base.read(&clk->base, nv_clk_src_mdiv);
 176
 177         case nv_clk_src_gpc:
 178                 return read_clk(clk, 0x00);
 179         case nv_clk_src_rop:
 180                 return read_clk(clk, 0x01);
 181         case nv_clk_src_hubk07:
 182                 return read_clk(clk, 0x02);
 183         case nv_clk_src_hubk06:
 184                 return read_clk(clk, 0x07);
 185         case nv_clk_src_hubk01:
 186                 return read_clk(clk, 0x08);
 187         case nv_clk_src_copy:
 188                 return read_clk(clk, 0x09);
 189         case nv_clk_src_daemon:
 190                 return read_clk(clk, 0x0c);
 191         case nv_clk_src_vdec:
 192                 return read_clk(clk, 0x0e);
 193         default:
 194                 nv_error(clk, "invalid clock source %d\n", src);
 195                 return -EINVAL;
 196         }
 197 }
 198
 199 static u32
 200 calc_div(struct gf100_clk *clk, int idx, u32 ref, u32 freq, u32 *ddiv)
 201 {
 202         u32 div = min((ref * 2) / freq, (u32)65);
 203         if (div < 2)
 204                 div = 2;
 205
 206         *ddiv = div - 2;
 207         return (ref * 2) / div;
 208 }
 209
 210 static u32
 211 calc_src(struct gf100_clk *clk, int idx, u32 freq, u32 *dsrc, u32 *ddiv)
 212 {
 213         u32 sclk;
 214
 215         /* use one of the fixed frequencies if possible */
 216         *ddiv = 0x00000000;
 217         switch (freq) {
 218         case  27000:
 219         case 108000:
 220                 *dsrc = 0x00000000;
 221                 if (freq == 108000)
 222                         *dsrc |= 0x00030000;
 223                 return freq;
 224         case 100000:
 225                 *dsrc = 0x00000002;
 226                 return freq;
 227         default:
 228                 *dsrc = 0x00000003;
 229                 break;
 230         }
 231
 232         /* otherwise, calculate the closest divider */
 233         sclk = read_vco(clk, 0x137160 + (idx * 4));
 234         if (idx < 7)
 235                 sclk = calc_div(clk, idx, sclk, freq, ddiv);
 236         return sclk;
 237 }
 238
 239 static u32
 240 calc_pll(struct gf100_clk *clk, int idx, u32 freq, u32 *coef)
 241 {
 242         struct nvkm_bios *bios = nvkm_bios(clk);
 243         struct nvbios_pll limits;
 244         int N, M, P, ret;
 245
 246         ret = nvbios_pll_parse(bios, 0x137000 + (idx * 0x20), &limits);
 247         if (ret)
 248                 return 0;
 249
 250         limits.refclk = read_div(clk, idx, 0x137120, 0x137140);
 251         if (!limits.refclk)
 252                 return 0;
 253
 254         ret = gt215_pll_calc(nv_subdev(clk), &limits, freq, &N, NULL, &M, &P);
 255         if (ret <= 0)
 256                 return 0;
 257
 258         *coef = (P << 16) | (N << 8) | M;
 259         return ret;
 260 }
 261
 262 static int
 263 calc_clk(struct gf100_clk *clk, struct nvkm_cstate *cstate, int idx, int dom)
 264 {
 265         struct gf100_clk_info *info = &clk->eng[idx];
 266         u32 freq = cstate->domain[dom];
 267         u32 src0, div0, div1D, div1P = 0;
 268         u32 clk0, clk1 = 0;
 269
 270         /* invalid clock domain */
 271         if (!freq)
 272                 return 0;
 273
 274         /* first possible path, using only dividers */
 275         clk0 = calc_src(clk, idx, freq, &src0, &div0);
 276         clk0 = calc_div(clk, idx, clk0, freq, &div1D);
 277
 278         /* see if we can get any closer using PLLs */
 279         if (clk0 != freq && (0x00004387 & (1 << idx))) {
 280                 if (idx <= 7)
 281                         clk1 = calc_pll(clk, idx, freq, &info->coef);
 282                 else
 283                         clk1 = cstate->domain[nv_clk_src_hubk06];
 284                 clk1 = calc_div(clk, idx, clk1, freq, &div1P);
 285         }
 286
 287         /* select the method which gets closest to target freq */
 288         if (abs((int)freq - clk0) <= abs((int)freq - clk1)) {
 289                 info->dsrc = src0;
 290                 if (div0) {
 291                         info->ddiv |= 0x80000000;
 292                         info->ddiv |= div0 << 8;
 293                         info->ddiv |= div0;
 294                 }
 295                 if (div1D) {
 296                         info->mdiv |= 0x80000000;
 297                         info->mdiv |= div1D;
 298                 }
 299                 info->ssel = info->coef = 0;
 300                 info->freq = clk0;
 301         } else {
 302                 if (div1P) {
 303                         info->mdiv |= 0x80000000;
 304                         info->mdiv |= div1P << 8;
 305                 }
 306                 info->ssel = (1 << idx);
 307                 info->freq = clk1;
 308         }
 309
 310         return 0;
 311 }
 312
 313 static int
 314 gf100_clk_calc(struct nvkm_clk *obj, struct nvkm_cstate *cstate)
 315 {
 316         struct gf100_clk *clk = container_of(obj, typeof(*clk), base);
 317         int ret;
 318
 319         if ((ret = calc_clk(clk, cstate, 0x00, nv_clk_src_gpc)) ||
 320             (ret = calc_clk(clk, cstate, 0x01, nv_clk_src_rop)) ||
 321             (ret = calc_clk(clk, cstate, 0x02, nv_clk_src_hubk07)) ||
 322             (ret = calc_clk(clk, cstate, 0x07, nv_clk_src_hubk06)) ||
 323             (ret = calc_clk(clk, cstate, 0x08, nv_clk_src_hubk01)) ||
 324             (ret = calc_clk(clk, cstate, 0x09, nv_clk_src_copy)) ||
 325             (ret = calc_clk(clk, cstate, 0x0c, nv_clk_src_daemon)) ||
 326             (ret = calc_clk(clk, cstate, 0x0e, nv_clk_src_vdec)))
 327                 return ret;
 328
 329         return 0;
 330 }
 331
 332 static void
 333 gf100_clk_prog_0(struct gf100_clk *clk, int idx)
 334 {
 335         struct gf100_clk_info *info = &clk->eng[idx];
 336         struct nvkm_device *device = clk->base.subdev.device;
 337         if (idx < 7 && !info->ssel) {
 338                 nvkm_mask(device, 0x1371d0 + (idx * 0x04), 0x80003f3f, info->ddiv);
 339                 nvkm_wr32(device, 0x137160 + (idx * 0x04), info->dsrc);
 340         }
 341 }
 342
 343 static void
 344 gf100_clk_prog_1(struct gf100_clk *clk, int idx)
 345 {
 346         struct nvkm_device *device = clk->base.subdev.device;
 347         nvkm_mask(device, 0x137100, (1 << idx), 0x00000000);
 348         nvkm_msec(device, 2000,
 349                 if (!(nvkm_rd32(device, 0x137100) & (1 << idx)))
 350                         break;
 351         );
 352 }
 353
 354 static void
 355 gf100_clk_prog_2(struct gf100_clk *clk, int idx)
 356 {
 357         struct gf100_clk_info *info = &clk->eng[idx];
 358         struct nvkm_device *device = clk->base.subdev.device;
 359         const u32 addr = 0x137000 + (idx * 0x20);
 360         if (idx <= 7) {
 361                 nvkm_mask(device, addr + 0x00, 0x00000004, 0x00000000);
 362                 nvkm_mask(device, addr + 0x00, 0x00000001, 0x00000000);
 363                 if (info->coef) {
 364                         nvkm_wr32(device, addr + 0x04, info->coef);
 365                         nvkm_mask(device, addr + 0x00, 0x00000001, 0x00000001);
 366                         nvkm_msec(device, 2000,
 367                                 if (nvkm_rd32(device, addr + 0x00) & 0x00020000)
 368                                         break;
 369                         );
 370                         nvkm_mask(device, addr + 0x00, 0x00020004, 0x00000004);
 371                 }
 372         }
 373 }
 374
 375 static void
 376 gf100_clk_prog_3(struct gf100_clk *clk, int idx)
 377 {
 378         struct gf100_clk_info *info = &clk->eng[idx];
 379         struct nvkm_device *device = clk->base.subdev.device;
 380         if (info->ssel) {
 381                 nvkm_mask(device, 0x137100, (1 << idx), info->ssel);
 382                 nvkm_msec(device, 2000,
 383                         u32 tmp = nvkm_rd32(device, 0x137100) & (1 << idx);
 384                         if (tmp == info->ssel)
 385                                 break;
 386                 );
 387         }
 388 }
 389
 390 static void
 391 gf100_clk_prog_4(struct gf100_clk *clk, int idx)
 392 {
 393         struct gf100_clk_info *info = &clk->eng[idx];
 394         struct nvkm_device *device = clk->base.subdev.device;
 395         nvkm_mask(device, 0x137250 + (idx * 0x04), 0x00003f3f, info->mdiv);
 396 }
 397
 398 static int
 399 gf100_clk_prog(struct nvkm_clk *obj)
 400 {
 401         struct gf100_clk *clk = container_of(obj, typeof(*clk), base);
 402         struct {
 403                 void (*exec)(struct gf100_clk *, int);
 404         } stage[] = {
 405                 { gf100_clk_prog_0 }, /* div programming */
 406                 { gf100_clk_prog_1 }, /* select div mode */
 407                 { gf100_clk_prog_2 }, /* (maybe) program pll */
 408                 { gf100_clk_prog_3 }, /* (maybe) select pll mode */
 409                 { gf100_clk_prog_4 }, /* final divider */
 410         };
 411         int i, j;
 412
 413         for (i = 0; i < ARRAY_SIZE(stage); i++) {
 414                 for (j = 0; j < ARRAY_SIZE(clk->eng); j++) {
 415                         if (!clk->eng[j].freq)
 416                                 continue;
 417                         stage[i].exec(clk, j);
 418                 }
 419         }
 420
 421         return 0;
 422 }
 423
 424 static void
 425 gf100_clk_tidy(struct nvkm_clk *obj)
 426 {
 427         struct gf100_clk *clk = container_of(obj, typeof(*clk), base);
 428         memset(clk->eng, 0x00, sizeof(clk->eng));
 429 }
 430
 431 static struct nvkm_domain
 432 gf100_domain[] = {
 433         { nv_clk_src_crystal, 0xff },
 434         { nv_clk_src_href   , 0xff },
 435         { nv_clk_src_hubk06 , 0x00 },
 436         { nv_clk_src_hubk01 , 0x01 },
 437         { nv_clk_src_copy   , 0x02 },
 438         { nv_clk_src_gpc    , 0x03, 0, "core", 2000 },
 439         { nv_clk_src_rop    , 0x04 },
 440         { nv_clk_src_mem    , 0x05, 0, "memory", 1000 },
 441         { nv_clk_src_vdec   , 0x06 },
 442         { nv_clk_src_daemon , 0x0a },
 443         { nv_clk_src_hubk07 , 0x0b },
 444         { nv_clk_src_max }
 445 };
 446
 447 static int
 448 gf100_clk_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
 449                struct nvkm_oclass *oclass, void *data, u32 size,
 450                struct nvkm_object **pobject)
 451 {
 452         struct gf100_clk *clk;
 453         int ret;
 454
 455         ret = nvkm_clk_create(parent, engine, oclass, gf100_domain,
 456                               NULL, 0, false, &clk);
 457         *pobject = nv_object(clk);
 458         if (ret)
 459                 return ret;
 460
 461         clk->base.read = gf100_clk_read;
 462         clk->base.calc = gf100_clk_calc;
 463         clk->base.prog = gf100_clk_prog;
 464         clk->base.tidy = gf100_clk_tidy;
 465         return 0;
 466 }
 467
 468 struct nvkm_oclass
 469 gf100_clk_oclass = {
 470         .handle = NV_SUBDEV(CLK, 0xc0),
 471         .ofuncs = &(struct nvkm_ofuncs) {
 472                 .ctor = gf100_clk_ctor,
 473                 .dtor = _nvkm_clk_dtor,
 474                 .init = _nvkm_clk_init,
 475                 .fini = _nvkm_clk_fini,
 476         },
 477 };