drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c

   1 /*
   2  * Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  18  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  19  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  20  * DEALINGS IN THE SOFTWARE.
  21  *
  22  * Shamelessly ripped off from ChromeOS's gk20a/clk_pllg.c
  23  *
  24  */
  25 #define gk20a_clk(p) container_of((p), struct gk20a_clk, base)
  26 #include "priv.h"
  27
  28 #include <core/tegra.h>
  29 #include <subdev/timer.h>
  30
  31 #define KHZ (1000)
  32 #define MHZ (KHZ * 1000)
  33
  34 #define MASK(w) ((1 << w) - 1)
  35
  36 #define SYS_GPCPLL_CFG_BASE                     0x00137000
  37 #define GPC_BCASE_GPCPLL_CFG_BASE               0x00132800
  38
  39 #define GPCPLL_CFG              (SYS_GPCPLL_CFG_BASE + 0)
  40 #define GPCPLL_CFG_ENABLE       BIT(0)
  41 #define GPCPLL_CFG_IDDQ         BIT(1)
  42 #define GPCPLL_CFG_LOCK_DET_OFF BIT(4)
  43 #define GPCPLL_CFG_LOCK         BIT(17)
  44
  45 #define GPCPLL_COEFF            (SYS_GPCPLL_CFG_BASE + 4)
  46 #define GPCPLL_COEFF_M_SHIFT    0
  47 #define GPCPLL_COEFF_M_WIDTH    8
  48 #define GPCPLL_COEFF_N_SHIFT    8
  49 #define GPCPLL_COEFF_N_WIDTH    8
  50 #define GPCPLL_COEFF_P_SHIFT    16
  51 #define GPCPLL_COEFF_P_WIDTH    6
  52
  53 #define GPCPLL_CFG2                     (SYS_GPCPLL_CFG_BASE + 0xc)
  54 #define GPCPLL_CFG2_SETUP2_SHIFT        16
  55 #define GPCPLL_CFG2_PLL_STEPA_SHIFT     24
  56
  57 #define GPCPLL_CFG3                     (SYS_GPCPLL_CFG_BASE + 0x18)
  58 #define GPCPLL_CFG3_PLL_STEPB_SHIFT     16
  59
  60 #define GPCPLL_NDIV_SLOWDOWN                    (SYS_GPCPLL_CFG_BASE + 0x1c)
  61 #define GPCPLL_NDIV_SLOWDOWN_NDIV_LO_SHIFT      0
  62 #define GPCPLL_NDIV_SLOWDOWN_NDIV_MID_SHIFT     8
  63 #define GPCPLL_NDIV_SLOWDOWN_STEP_SIZE_LO2MID_SHIFT     16
  64 #define GPCPLL_NDIV_SLOWDOWN_SLOWDOWN_USING_PLL_SHIFT   22
  65 #define GPCPLL_NDIV_SLOWDOWN_EN_DYNRAMP_SHIFT   31
  66
  67 #define SEL_VCO                         (SYS_GPCPLL_CFG_BASE + 0x100)
  68 #define SEL_VCO_GPC2CLK_OUT_SHIFT       0
  69
  70 #define GPC2CLK_OUT                     (SYS_GPCPLL_CFG_BASE + 0x250)
  71 #define GPC2CLK_OUT_SDIV14_INDIV4_WIDTH 1
  72 #define GPC2CLK_OUT_SDIV14_INDIV4_SHIFT 31
  73 #define GPC2CLK_OUT_SDIV14_INDIV4_MODE  1
  74 #define GPC2CLK_OUT_VCODIV_WIDTH        6
  75 #define GPC2CLK_OUT_VCODIV_SHIFT        8
  76 #define GPC2CLK_OUT_VCODIV1             0
  77 #define GPC2CLK_OUT_VCODIV_MASK         (MASK(GPC2CLK_OUT_VCODIV_WIDTH) << \
  78                                         GPC2CLK_OUT_VCODIV_SHIFT)
  79 #define GPC2CLK_OUT_BYPDIV_WIDTH        6
  80 #define GPC2CLK_OUT_BYPDIV_SHIFT        0
  81 #define GPC2CLK_OUT_BYPDIV31            0x3c
  82 #define GPC2CLK_OUT_INIT_MASK   ((MASK(GPC2CLK_OUT_SDIV14_INDIV4_WIDTH) << \
  83                 GPC2CLK_OUT_SDIV14_INDIV4_SHIFT)\
  84                 | (MASK(GPC2CLK_OUT_VCODIV_WIDTH) << GPC2CLK_OUT_VCODIV_SHIFT)\
  85                 | (MASK(GPC2CLK_OUT_BYPDIV_WIDTH) << GPC2CLK_OUT_BYPDIV_SHIFT))
  86 #define GPC2CLK_OUT_INIT_VAL    ((GPC2CLK_OUT_SDIV14_INDIV4_MODE << \
  87                 GPC2CLK_OUT_SDIV14_INDIV4_SHIFT) \
  88                 | (GPC2CLK_OUT_VCODIV1 << GPC2CLK_OUT_VCODIV_SHIFT) \
  89                 | (GPC2CLK_OUT_BYPDIV31 << GPC2CLK_OUT_BYPDIV_SHIFT))
  90
  91 #define GPC_BCAST_NDIV_SLOWDOWN_DEBUG   (GPC_BCASE_GPCPLL_CFG_BASE + 0xa0)
  92 #define GPC_BCAST_NDIV_SLOWDOWN_DEBUG_PLL_DYNRAMP_DONE_SYNCED_SHIFT     24
  93 #define GPC_BCAST_NDIV_SLOWDOWN_DEBUG_PLL_DYNRAMP_DONE_SYNCED_MASK \
  94             (0x1 << GPC_BCAST_NDIV_SLOWDOWN_DEBUG_PLL_DYNRAMP_DONE_SYNCED_SHIFT)
  95
  96 static const u8 pl_to_div[] = {
  97 /* PL:   0, 1, 2, 3, 4, 5, 6,  7,  8,  9, 10, 11, 12, 13, 14 */
  98 /* p: */ 1, 2, 3, 4, 5, 6, 8, 10, 12, 16, 12, 16, 20, 24, 32,
  99 };
 100
 101 /* All frequencies in Khz */
 102 struct gk20a_clk_pllg_params {
 103         u32 min_vco, max_vco;
 104         u32 min_u, max_u;
 105         u32 min_m, max_m;
 106         u32 min_n, max_n;
 107         u32 min_pl, max_pl;
 108 };
 109
 110 static const struct gk20a_clk_pllg_params gk20a_pllg_params = {
 111         .min_vco = 1000000, .max_vco = 2064000,
 112         .min_u = 12000, .max_u = 38000,
 113         .min_m = 1, .max_m = 255,
 114         .min_n = 8, .max_n = 255,
 115         .min_pl = 1, .max_pl = 32,
 116 };
 117
 118 struct gk20a_pll {
 119         u32 m;
 120         u32 n;
 121         u32 pl;
 122 };
 123
 124 struct gk20a_clk {
 125         struct nvkm_clk base;
 126         const struct gk20a_clk_pllg_params *params;
 127         struct gk20a_pll pll;
 128         u32 parent_rate;
 129 };
 130
 131 static void
 132 gk20a_pllg_read_mnp(struct gk20a_clk *clk, struct gk20a_pll *pll)
 133 {
 134         struct nvkm_device *device = clk->base.subdev.device;
 135         u32 val;
 136
 137         val = nvkm_rd32(device, GPCPLL_COEFF);
 138         pll->m = (val >> GPCPLL_COEFF_M_SHIFT) & MASK(GPCPLL_COEFF_M_WIDTH);
 139         pll->n = (val >> GPCPLL_COEFF_N_SHIFT) & MASK(GPCPLL_COEFF_N_WIDTH);
 140         pll->pl = (val >> GPCPLL_COEFF_P_SHIFT) & MASK(GPCPLL_COEFF_P_WIDTH);
 141 }
 142
 143 static u32
 144 gk20a_pllg_calc_rate(struct gk20a_clk *clk)
 145 {
 146         u32 rate;
 147         u32 divider;
 148
 149         rate = clk->parent_rate * clk->pll.n;
 150         divider = clk->pll.m * pl_to_div[clk->pll.pl];
 151
 152         return rate / divider / 2;
 153 }
 154
 155 static int
 156 gk20a_pllg_calc_mnp(struct gk20a_clk *clk, unsigned long rate)
 157 {
 158         struct nvkm_subdev *subdev = &clk->base.subdev;
 159         u32 target_clk_f, ref_clk_f, target_freq;
 160         u32 min_vco_f, max_vco_f;
 161         u32 low_pl, high_pl, best_pl;
 162         u32 target_vco_f;
 163         u32 best_m, best_n;
 164         u32 best_delta = ~0;
 165         u32 pl;
 166
 167         target_clk_f = rate * 2 / KHZ;
 168         ref_clk_f = clk->parent_rate / KHZ;
 169
 170         max_vco_f = clk->params->max_vco;
 171         min_vco_f = clk->params->min_vco;
 172         best_m = clk->params->max_m;
 173         best_n = clk->params->min_n;
 174         best_pl = clk->params->min_pl;
 175
 176         target_vco_f = target_clk_f + target_clk_f / 50;
 177         if (max_vco_f < target_vco_f)
 178                 max_vco_f = target_vco_f;
 179
 180         /* min_pl <= high_pl <= max_pl */
 181         high_pl = (max_vco_f + target_vco_f - 1) / target_vco_f;
 182         high_pl = min(high_pl, clk->params->max_pl);
 183         high_pl = max(high_pl, clk->params->min_pl);
 184
 185         /* min_pl <= low_pl <= max_pl */
 186         low_pl = min_vco_f / target_vco_f;
 187         low_pl = min(low_pl, clk->params->max_pl);
 188         low_pl = max(low_pl, clk->params->min_pl);
 189
 190         /* Find Indices of high_pl and low_pl */
 191         for (pl = 0; pl < ARRAY_SIZE(pl_to_div) - 1; pl++) {
 192                 if (pl_to_div[pl] >= low_pl) {
 193                         low_pl = pl;
 194                         break;
 195                 }
 196         }
 197         for (pl = 0; pl < ARRAY_SIZE(pl_to_div) - 1; pl++) {
 198                 if (pl_to_div[pl] >= high_pl) {
 199                         high_pl = pl;
 200                         break;
 201                 }
 202         }
 203
 204         nvkm_debug(subdev, "low_PL %d(div%d), high_PL %d(div%d)", low_pl,
 205                    pl_to_div[low_pl], high_pl, pl_to_div[high_pl]);
 206
 207         /* Select lowest possible VCO */
 208         for (pl = low_pl; pl <= high_pl; pl++) {
 209                 u32 m, n, n2;
 210
 211                 target_vco_f = target_clk_f * pl_to_div[pl];
 212                 for (m = clk->params->min_m; m <= clk->params->max_m; m++) {
 213                         u32 u_f, vco_f;
 214
 215                         u_f = ref_clk_f / m;
 216
 217                         if (u_f < clk->params->min_u)
 218                                 break;
 219                         if (u_f > clk->params->max_u)
 220                                 continue;
 221
 222                         n = (target_vco_f * m) / ref_clk_f;
 223                         n2 = ((target_vco_f * m) + (ref_clk_f - 1)) / ref_clk_f;
 224
 225                         if (n > clk->params->max_n)
 226                                 break;
 227
 228                         for (; n <= n2; n++) {
 229                                 if (n < clk->params->min_n)
 230                                         continue;
 231                                 if (n > clk->params->max_n)
 232                                         break;
 233
 234                                 vco_f = ref_clk_f * n / m;
 235
 236                                 if (vco_f >= min_vco_f && vco_f <= max_vco_f) {
 237                                         u32 delta, lwv;
 238
 239                                         lwv = (vco_f + (pl_to_div[pl] / 2))
 240                                                 / pl_to_div[pl];
 241                                         delta = abs(lwv - target_clk_f);
 242
 243                                         if (delta < best_delta) {
 244                                                 best_delta = delta;
 245                                                 best_m = m;
 246                                                 best_n = n;
 247                                                 best_pl = pl;
 248
 249                                                 if (best_delta == 0)
 250                                                         goto found_match;
 251                                         }
 252                                 }
 253                         }
 254                 }
 255         }
 256
 257 found_match:
 258         WARN_ON(best_delta == ~0);
 259
 260         if (best_delta != 0)
 261                 nvkm_debug(subdev,
 262                            "no best match for target @ %dMHz on gpc_pll",
 263                            target_clk_f / KHZ);
 264
 265         clk->pll.m = best_m;
 266         clk->pll.n = best_n;
 267         clk->pll.pl = best_pl;
 268
 269         target_freq = gk20a_pllg_calc_rate(clk);
 270
 271         nvkm_debug(subdev,
 272                    "actual target freq %d MHz, M %d, N %d, PL %d(div%d)\n",
 273                    target_freq / MHZ, clk->pll.m, clk->pll.n, clk->pll.pl,
 274                    pl_to_div[clk->pll.pl]);
 275         return 0;
 276 }
 277
 278 static int
 279 gk20a_pllg_slide(struct gk20a_clk *clk, u32 n)
 280 {
 281         struct nvkm_subdev *subdev = &clk->base.subdev;
 282         struct nvkm_device *device = subdev->device;
 283         u32 val;
 284         int ramp_timeout;
 285
 286         /* get old coefficients */
 287         val = nvkm_rd32(device, GPCPLL_COEFF);
 288         /* do nothing if NDIV is the same */
 289         if (n == ((val >> GPCPLL_COEFF_N_SHIFT) & MASK(GPCPLL_COEFF_N_WIDTH)))
 290                 return 0;
 291
 292         /* setup */
 293         nvkm_mask(device, GPCPLL_CFG2, 0xff << GPCPLL_CFG2_PLL_STEPA_SHIFT,
 294                 0x2b << GPCPLL_CFG2_PLL_STEPA_SHIFT);
 295         nvkm_mask(device, GPCPLL_CFG3, 0xff << GPCPLL_CFG3_PLL_STEPB_SHIFT,
 296                 0xb << GPCPLL_CFG3_PLL_STEPB_SHIFT);
 297
 298         /* pll slowdown mode */
 299         nvkm_mask(device, GPCPLL_NDIV_SLOWDOWN,
 300                 BIT(GPCPLL_NDIV_SLOWDOWN_SLOWDOWN_USING_PLL_SHIFT),
 301                 BIT(GPCPLL_NDIV_SLOWDOWN_SLOWDOWN_USING_PLL_SHIFT));
 302
 303         /* new ndiv ready for ramp */
 304         val = nvkm_rd32(device, GPCPLL_COEFF);
 305         val &= ~(MASK(GPCPLL_COEFF_N_WIDTH) << GPCPLL_COEFF_N_SHIFT);
 306         val |= (n & MASK(GPCPLL_COEFF_N_WIDTH)) << GPCPLL_COEFF_N_SHIFT;
 307         udelay(1);
 308         nvkm_wr32(device, GPCPLL_COEFF, val);
 309
 310         /* dynamic ramp to new ndiv */
 311         val = nvkm_rd32(device, GPCPLL_NDIV_SLOWDOWN);
 312         val |= 0x1 << GPCPLL_NDIV_SLOWDOWN_EN_DYNRAMP_SHIFT;
 313         udelay(1);
 314         nvkm_wr32(device, GPCPLL_NDIV_SLOWDOWN, val);
 315
 316         for (ramp_timeout = 500; ramp_timeout > 0; ramp_timeout--) {
 317                 udelay(1);
 318                 val = nvkm_rd32(device, GPC_BCAST_NDIV_SLOWDOWN_DEBUG);
 319                 if (val & GPC_BCAST_NDIV_SLOWDOWN_DEBUG_PLL_DYNRAMP_DONE_SYNCED_MASK)
 320                         break;
 321         }
 322
 323         /* exit slowdown mode */
 324         nvkm_mask(device, GPCPLL_NDIV_SLOWDOWN,
 325                 BIT(GPCPLL_NDIV_SLOWDOWN_SLOWDOWN_USING_PLL_SHIFT) |
 326                 BIT(GPCPLL_NDIV_SLOWDOWN_EN_DYNRAMP_SHIFT), 0);
 327         nvkm_rd32(device, GPCPLL_NDIV_SLOWDOWN);
 328
 329         if (ramp_timeout <= 0) {
 330                 nvkm_error(subdev, "gpcpll dynamic ramp timeout\n");
 331                 return -ETIMEDOUT;
 332         }
 333
 334         return 0;
 335 }
 336
 337 static void
 338 gk20a_pllg_enable(struct gk20a_clk *clk)
 339 {
 340         struct nvkm_device *device = clk->base.subdev.device;
 341
 342         nvkm_mask(device, GPCPLL_CFG, GPCPLL_CFG_ENABLE, GPCPLL_CFG_ENABLE);
 343         nvkm_rd32(device, GPCPLL_CFG);
 344 }
 345
 346 static void
 347 gk20a_pllg_disable(struct gk20a_clk *clk)
 348 {
 349         struct nvkm_device *device = clk->base.subdev.device;
 350
 351         nvkm_mask(device, GPCPLL_CFG, GPCPLL_CFG_ENABLE, 0);
 352         nvkm_rd32(device, GPCPLL_CFG);
 353 }
 354
 355 static int
 356 _gk20a_pllg_program_mnp(struct gk20a_clk *clk, bool allow_slide)
 357 {
 358         struct nvkm_subdev *subdev = &clk->base.subdev;
 359         struct nvkm_device *device = subdev->device;
 360         u32 val, cfg;
 361         struct gk20a_pll old_pll;
 362         u32 n_lo;
 363
 364         /* get old coefficients */
 365         gk20a_pllg_read_mnp(clk, &old_pll);
 366
 367         /* do NDIV slide if there is no change in M and PL */
 368         cfg = nvkm_rd32(device, GPCPLL_CFG);
 369         if (allow_slide && clk->pll.m == old_pll.m &&
 370             clk->pll.pl == old_pll.pl && (cfg & GPCPLL_CFG_ENABLE)) {
 371                 return gk20a_pllg_slide(clk, clk->pll.n);
 372         }
 373
 374         /* slide down to NDIV_LO */
 375         if (allow_slide && (cfg & GPCPLL_CFG_ENABLE)) {
 376                 int ret;
 377
 378                 n_lo = DIV_ROUND_UP(old_pll.m * clk->params->min_vco,
 379                                     clk->parent_rate / KHZ);
 380                 ret = gk20a_pllg_slide(clk, n_lo);
 381
 382                 if (ret)
 383                         return ret;
 384         }
 385
 386         /* split FO-to-bypass jump in halfs by setting out divider 1:2 */
 387         nvkm_mask(device, GPC2CLK_OUT, GPC2CLK_OUT_VCODIV_MASK,
 388                 0x2 << GPC2CLK_OUT_VCODIV_SHIFT);
 389
 390         /* put PLL in bypass before programming it */
 391         val = nvkm_rd32(device, SEL_VCO);
 392         val &= ~(BIT(SEL_VCO_GPC2CLK_OUT_SHIFT));
 393         udelay(2);
 394         nvkm_wr32(device, SEL_VCO, val);
 395
 396         /* get out from IDDQ */
 397         val = nvkm_rd32(device, GPCPLL_CFG);
 398         if (val & GPCPLL_CFG_IDDQ) {
 399                 val &= ~GPCPLL_CFG_IDDQ;
 400                 nvkm_wr32(device, GPCPLL_CFG, val);
 401                 nvkm_rd32(device, GPCPLL_CFG);
 402                 udelay(2);
 403         }
 404
 405         gk20a_pllg_disable(clk);
 406
 407         nvkm_debug(subdev, "%s: m=%d n=%d pl=%d\n", __func__,
 408                    clk->pll.m, clk->pll.n, clk->pll.pl);
 409
 410         n_lo = DIV_ROUND_UP(clk->pll.m * clk->params->min_vco,
 411                             clk->parent_rate / KHZ);
 412         val = clk->pll.m << GPCPLL_COEFF_M_SHIFT;
 413         val |= (allow_slide ? n_lo : clk->pll.n) << GPCPLL_COEFF_N_SHIFT;
 414         val |= clk->pll.pl << GPCPLL_COEFF_P_SHIFT;
 415         nvkm_wr32(device, GPCPLL_COEFF, val);
 416
 417         gk20a_pllg_enable(clk);
 418
 419         val = nvkm_rd32(device, GPCPLL_CFG);
 420         if (val & GPCPLL_CFG_LOCK_DET_OFF) {
 421                 val &= ~GPCPLL_CFG_LOCK_DET_OFF;
 422                 nvkm_wr32(device, GPCPLL_CFG, val);
 423         }
 424
 425         if (nvkm_usec(device, 300,
 426                 if (nvkm_rd32(device, GPCPLL_CFG) & GPCPLL_CFG_LOCK)
 427                         break;
 428         ) < 0)
 429                 return -ETIMEDOUT;
 430
 431         /* switch to VCO mode */
 432         nvkm_mask(device, SEL_VCO, BIT(SEL_VCO_GPC2CLK_OUT_SHIFT),
 433                   BIT(SEL_VCO_GPC2CLK_OUT_SHIFT));
 434
 435         /* restore out divider 1:1 */
 436         val = nvkm_rd32(device, GPC2CLK_OUT);
 437         if ((val & GPC2CLK_OUT_VCODIV_MASK) !=
 438             (GPC2CLK_OUT_VCODIV1 << GPC2CLK_OUT_VCODIV_SHIFT)) {
 439                 val &= ~GPC2CLK_OUT_VCODIV_MASK;
 440                 val |= GPC2CLK_OUT_VCODIV1 << GPC2CLK_OUT_VCODIV_SHIFT;
 441                 udelay(2);
 442                 nvkm_wr32(device, GPC2CLK_OUT, val);
 443                 /* Intentional 2nd write to assure linear divider operation */
 444                 nvkm_wr32(device, GPC2CLK_OUT, val);
 445                 nvkm_rd32(device, GPC2CLK_OUT);
 446         }
 447
 448         /* slide up to new NDIV */
 449         return allow_slide ? gk20a_pllg_slide(clk, clk->pll.n) : 0;
 450 }
 451
 452 static int
 453 gk20a_pllg_program_mnp(struct gk20a_clk *clk)
 454 {
 455         int err;
 456
 457         err = _gk20a_pllg_program_mnp(clk, true);
 458         if (err)
 459                 err = _gk20a_pllg_program_mnp(clk, false);
 460
 461         return err;
 462 }
 463
 464 #define GK20A_CLK_GPC_MDIV 1000
 465
 466 static struct nvkm_pstate
 467 gk20a_pstates[] = {
 468         {
 469                 .base = {
 470                         .domain[nv_clk_src_gpc] = 72000,
 471                         .voltage = 0,
 472                 },
 473         },
 474         {
 475                 .base = {
 476                         .domain[nv_clk_src_gpc] = 108000,
 477                         .voltage = 1,
 478                 },
 479         },
 480         {
 481                 .base = {
 482                         .domain[nv_clk_src_gpc] = 180000,
 483                         .voltage = 2,
 484                 },
 485         },
 486         {
 487                 .base = {
 488                         .domain[nv_clk_src_gpc] = 252000,
 489                         .voltage = 3,
 490                 },
 491         },
 492         {
 493                 .base = {
 494                         .domain[nv_clk_src_gpc] = 324000,
 495                         .voltage = 4,
 496                 },
 497         },
 498         {
 499                 .base = {
 500                         .domain[nv_clk_src_gpc] = 396000,
 501                         .voltage = 5,
 502                 },
 503         },
 504         {
 505                 .base = {
 506                         .domain[nv_clk_src_gpc] = 468000,
 507                         .voltage = 6,
 508                 },
 509         },
 510         {
 511                 .base = {
 512                         .domain[nv_clk_src_gpc] = 540000,
 513                         .voltage = 7,
 514                 },
 515         },
 516         {
 517                 .base = {
 518                         .domain[nv_clk_src_gpc] = 612000,
 519                         .voltage = 8,
 520                 },
 521         },
 522         {
 523                 .base = {
 524                         .domain[nv_clk_src_gpc] = 648000,
 525                         .voltage = 9,
 526                 },
 527         },
 528         {
 529                 .base = {
 530                         .domain[nv_clk_src_gpc] = 684000,
 531                         .voltage = 10,
 532                 },
 533         },
 534         {
 535                 .base = {
 536                         .domain[nv_clk_src_gpc] = 708000,
 537                         .voltage = 11,
 538                 },
 539         },
 540         {
 541                 .base = {
 542                         .domain[nv_clk_src_gpc] = 756000,
 543                         .voltage = 12,
 544                 },
 545         },
 546         {
 547                 .base = {
 548                         .domain[nv_clk_src_gpc] = 804000,
 549                         .voltage = 13,
 550                 },
 551         },
 552         {
 553                 .base = {
 554                         .domain[nv_clk_src_gpc] = 852000,
 555                         .voltage = 14,
 556                 },
 557         },
 558 };
 559
 560 static int
 561 gk20a_clk_read(struct nvkm_clk *base, enum nv_clk_src src)
 562 {
 563         struct gk20a_clk *clk = gk20a_clk(base);
 564         struct nvkm_subdev *subdev = &clk->base.subdev;
 565         struct nvkm_device *device = subdev->device;
 566
 567         switch (src) {
 568         case nv_clk_src_crystal:
 569                 return device->crystal;
 570         case nv_clk_src_gpc:
 571                 gk20a_pllg_read_mnp(clk, &clk->pll);
 572                 return gk20a_pllg_calc_rate(clk) / GK20A_CLK_GPC_MDIV;
 573         default:
 574                 nvkm_error(subdev, "invalid clock source %d\n", src);
 575                 return -EINVAL;
 576         }
 577 }
 578
 579 static int
 580 gk20a_clk_calc(struct nvkm_clk *base, struct nvkm_cstate *cstate)
 581 {
 582         struct gk20a_clk *clk = gk20a_clk(base);
 583
 584         return gk20a_pllg_calc_mnp(clk, cstate->domain[nv_clk_src_gpc] *
 585                                          GK20A_CLK_GPC_MDIV);
 586 }
 587
 588 static int
 589 gk20a_clk_prog(struct nvkm_clk *base)
 590 {
 591         struct gk20a_clk *clk = gk20a_clk(base);
 592
 593         return gk20a_pllg_program_mnp(clk);
 594 }
 595
 596 static void
 597 gk20a_clk_tidy(struct nvkm_clk *base)
 598 {
 599 }
 600
 601 static void
 602 gk20a_clk_fini(struct nvkm_clk *base)
 603 {
 604         struct nvkm_device *device = base->subdev.device;
 605         struct gk20a_clk *clk = gk20a_clk(base);
 606         u32 val;
 607
 608         /* slide to VCO min */
 609         val = nvkm_rd32(device, GPCPLL_CFG);
 610         if (val & GPCPLL_CFG_ENABLE) {
 611                 struct gk20a_pll pll;
 612                 u32 n_lo;
 613
 614                 gk20a_pllg_read_mnp(clk, &pll);
 615                 n_lo = DIV_ROUND_UP(pll.m * clk->params->min_vco,
 616                                     clk->parent_rate / KHZ);
 617                 gk20a_pllg_slide(clk, n_lo);
 618         }
 619
 620         /* put PLL in bypass before disabling it */
 621         nvkm_mask(device, SEL_VCO, BIT(SEL_VCO_GPC2CLK_OUT_SHIFT), 0);
 622
 623         gk20a_pllg_disable(clk);
 624 }
 625
 626 static int
 627 gk20a_clk_init(struct nvkm_clk *base)
 628 {
 629         struct gk20a_clk *clk = gk20a_clk(base);
 630         struct nvkm_subdev *subdev = &clk->base.subdev;
 631         struct nvkm_device *device = subdev->device;
 632         int ret;
 633
 634         nvkm_mask(device, GPC2CLK_OUT, GPC2CLK_OUT_INIT_MASK, GPC2CLK_OUT_INIT_VAL);
 635
 636         ret = gk20a_clk_prog(&clk->base);
 637         if (ret) {
 638                 nvkm_error(subdev, "cannot initialize clock\n");
 639                 return ret;
 640         }
 641
 642         return 0;
 643 }
 644
 645 static const struct nvkm_clk_func
 646 gk20a_clk = {
 647         .init = gk20a_clk_init,
 648         .fini = gk20a_clk_fini,
 649         .read = gk20a_clk_read,
 650         .calc = gk20a_clk_calc,
 651         .prog = gk20a_clk_prog,
 652         .tidy = gk20a_clk_tidy,
 653         .pstates = gk20a_pstates,
 654         .nr_pstates = ARRAY_SIZE(gk20a_pstates),
 655         .domains = {
 656                 { nv_clk_src_crystal, 0xff },
 657                 { nv_clk_src_gpc, 0xff, 0, "core", GK20A_CLK_GPC_MDIV },
 658                 { nv_clk_src_max }
 659         }
 660 };
 661
 662 int
 663 gk20a_clk_new(struct nvkm_device *device, int index, struct nvkm_clk **pclk)
 664 {
 665         struct nvkm_device_tegra *tdev = device->func->tegra(device);
 666         struct gk20a_clk *clk;
 667         int ret, i;
 668
 669         if (!(clk = kzalloc(sizeof(*clk), GFP_KERNEL)))
 670                 return -ENOMEM;
 671         *pclk = &clk->base;
 672
 673         /* Finish initializing the pstates */
 674         for (i = 0; i < ARRAY_SIZE(gk20a_pstates); i++) {
 675                 INIT_LIST_HEAD(&gk20a_pstates[i].list);
 676                 gk20a_pstates[i].pstate = i + 1;
 677         }
 678
 679         clk->params = &gk20a_pllg_params;
 680         clk->parent_rate = clk_get_rate(tdev->clk);
 681
 682         ret = nvkm_clk_ctor(&gk20a_clk, device, index, true, &clk->base);
 683         nvkm_debug(&clk->base.subdev, "parent clock rate: %d Khz\n",
 684                    clk->parent_rate / KHZ);
 685         return ret;
 686 }