2 * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
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9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
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15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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20 * DEALINGS IN THE SOFTWARE.
23 #include <subdev/clk.h>
24 #include <core/device.h>
30 #define MHZ (KHZ * 1000)
32 #define MASK(w) ((1 << w) - 1)
34 #define BYPASSCTRL_SYS (SYS_GPCPLL_CFG_BASE + 0x340)
35 #define BYPASSCTRL_SYS_GPCPLL_SHIFT 0
36 #define BYPASSCTRL_SYS_GPCPLL_WIDTH 1
38 static u32 pl_to_div(u32 pl)
43 static u32 div_to_pl(u32 div)
48 static const struct gk20a_clk_pllg_params gm20b_pllg_params = {
49 .min_vco = 1300000, .max_vco = 2600000,
50 .min_u = 12000, .max_u = 38400,
51 .min_m = 1, .max_m = 255,
52 .min_n = 8, .max_n = 255,
53 .min_pl = 1, .max_pl = 31,
56 static struct nvkm_pstate
60 .domain[nv_clk_src_gpc] = 76800,
66 .domain[nv_clk_src_gpc] = 153600,
72 .domain[nv_clk_src_gpc] = 230400,
78 .domain[nv_clk_src_gpc] = 307200,
84 .domain[nv_clk_src_gpc] = 384000,
90 .domain[nv_clk_src_gpc] = 460800,
96 .domain[nv_clk_src_gpc] = 537600,
102 .domain[nv_clk_src_gpc] = 614400,
108 .domain[nv_clk_src_gpc] = 691200,
114 .domain[nv_clk_src_gpc] = 768000,
120 .domain[nv_clk_src_gpc] = 844800,
126 .domain[nv_clk_src_gpc] = 921600,
132 .domain[nv_clk_src_gpc] = 998400,
140 gm20b_clk_init(struct nvkm_clk *base)
142 struct gk20a_clk *clk = gk20a_clk(base);
143 struct nvkm_subdev *subdev = &clk->base.subdev;
144 struct nvkm_device *device = subdev->device;
147 /* Set the global bypass control to VCO */
148 nvkm_mask(device, BYPASSCTRL_SYS,
149 MASK(BYPASSCTRL_SYS_GPCPLL_WIDTH) << BYPASSCTRL_SYS_GPCPLL_SHIFT,
152 /* Start with lowest frequency */
153 base->func->calc(base, &base->func->pstates[0].base);
154 ret = base->func->prog(&clk->base);
156 nvkm_error(subdev, "cannot initialize clock\n");
163 static const struct nvkm_clk_func
164 gm20b_clk_speedo0 = {
165 .init = gm20b_clk_init,
166 .fini = gk20a_clk_fini,
167 .read = gk20a_clk_read,
168 .calc = gk20a_clk_calc,
169 .prog = gk20a_clk_prog,
170 .tidy = gk20a_clk_tidy,
171 .pstates = gm20b_pstates,
172 .nr_pstates = ARRAY_SIZE(gm20b_pstates) - 1,
174 { nv_clk_src_crystal, 0xff },
175 { nv_clk_src_gpc, 0xff, 0, "core", GK20A_CLK_GPC_MDIV },
181 gm20b_clk_new(struct nvkm_device *device, int index, struct nvkm_clk **pclk)
183 struct gk20a_clk *clk;
186 clk = kzalloc(sizeof(*clk), GFP_KERNEL);
191 ret = _gk20a_clk_ctor(device, index, &gm20b_clk_speedo0,
192 &gm20b_pllg_params, clk);
194 clk->pl_to_div = pl_to_div;
195 clk->div_to_pl = div_to_pl;