2 * Copyright 2013 Red Hat Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
22 * Authors: Ben Skeggs <bskeggs@redhat.com>
23 * Roy Spliet <rspliet@eclipso.eu>
26 #include <subdev/bios.h>
35 ramxlat(const struct ramxlat *xlat, int id)
37 while (xlat->id >= 0) {
45 static const struct ramxlat
47 { 7, 7 }, { 8, 0 }, { 9, 1 }, { 10, 2 }, { 11, 3 },
48 /* the below are mentioned in some, but not all, gddr3 docs */
49 { 12, 4 }, { 13, 5 }, { 14, 6 },
50 /* XXX: Per Samsung docs, are these used? They overlap with Qimonda */
51 /* { 4, 4 }, { 5, 5 }, { 6, 6 }, { 12, 8 }, { 13, 9 }, { 14, 10 },
56 static const struct ramxlat
58 { 10, 2 }, { 11, 3 }, { 12, 4 }, { 13, 5 }, { 14, 6 }, { 15, 7 },
63 static const struct ramxlat
65 { 5, 2 }, { 7, 4 }, { 8, 5 }, { 9, 6 }, { 10, 7 },
67 /* the below are mentioned in some, but not all, gddr3 docs */
68 { 4, 1 }, { 6, 3 }, { 12, 1 }, { 13 , 2 },
73 nouveau_gddr3_calc(struct nouveau_ram *ram)
75 int CL, WR, CWL, DLL = 0, ODT = 0, hi;
77 switch (ram->next->bios.timing_ver) {
79 CWL = ram->next->bios.timing_10_CWL;
80 CL = ram->next->bios.timing_10_CL;
81 WR = ram->next->bios.timing_10_WR;
82 DLL = !ram->next->bios.ramcfg_10_DLLoff;
83 ODT = ram->next->bios.timing_10_ODT;
86 CWL = (ram->next->bios.timing[1] & 0x00000f80) >> 7;
87 CL = (ram->next->bios.timing[1] & 0x0000001f) >> 0;
88 WR = (ram->next->bios.timing[2] & 0x007f0000) >> 16;
89 /* XXX: Get these values from the VBIOS instead */
90 DLL = !(ram->mr[1] & 0x1);
91 ODT = (ram->mr[1] & 0x004) >> 2 |
92 (ram->mr[1] & 0x040) >> 5 |
93 (ram->mr[1] & 0x200) >> 7;
99 hi = ram->mr[2] & 0x1;
100 CL = ramxlat(hi ? ramgddr3_cl_hi : ramgddr3_cl_lo, CL);
101 WR = ramxlat(ramgddr3_wr_lo, WR);
102 if (CL < 0 || CWL < 1 || CWL > 7 || WR < 0)
105 ram->mr[0] &= ~0xf74;
106 ram->mr[0] |= (CWL & 0x07) << 9;
107 ram->mr[0] |= (CL & 0x07) << 4;
108 ram->mr[0] |= (CL & 0x08) >> 1;
110 ram->mr[1] &= ~0x3fc;
111 ram->mr[1] |= (ODT & 0x03) << 2;
112 ram->mr[1] |= (ODT & 0x03) << 8;
113 ram->mr[1] |= (WR & 0x03) << 4;
114 ram->mr[1] |= (WR & 0x04) << 5;
115 ram->mr[1] |= !DLL << 6;