drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.c

   1 /*
   2  * Copyright 2013 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  *          Roy Spliet <rspliet@eclipso.eu>
  24  */
  25
  26 #include "ramfuc.h"
  27 #include "nv50.h"
  28
  29 #include <core/option.h>
  30 #include <subdev/bios.h>
  31 #include <subdev/bios/M0205.h>
  32 #include <subdev/bios/rammap.h>
  33 #include <subdev/bios/timing.h>
  34 #include <subdev/clk/gt215.h>
  35 #include <subdev/gpio.h>
  36
  37 /* XXX: Remove when memx gains GPIO support */
  38 extern int nv50_gpio_location(int line, u32 *reg, u32 *shift);
  39
  40 struct gt215_ramfuc {
  41         struct ramfuc base;
  42         struct ramfuc_reg r_0x001610;
  43         struct ramfuc_reg r_0x001700;
  44         struct ramfuc_reg r_0x002504;
  45         struct ramfuc_reg r_0x004000;
  46         struct ramfuc_reg r_0x004004;
  47         struct ramfuc_reg r_0x004018;
  48         struct ramfuc_reg r_0x004128;
  49         struct ramfuc_reg r_0x004168;
  50         struct ramfuc_reg r_0x100080;
  51         struct ramfuc_reg r_0x100200;
  52         struct ramfuc_reg r_0x100210;
  53         struct ramfuc_reg r_0x100220[9];
  54         struct ramfuc_reg r_0x100264;
  55         struct ramfuc_reg r_0x1002d0;
  56         struct ramfuc_reg r_0x1002d4;
  57         struct ramfuc_reg r_0x1002dc;
  58         struct ramfuc_reg r_0x10053c;
  59         struct ramfuc_reg r_0x1005a0;
  60         struct ramfuc_reg r_0x1005a4;
  61         struct ramfuc_reg r_0x100700;
  62         struct ramfuc_reg r_0x100714;
  63         struct ramfuc_reg r_0x100718;
  64         struct ramfuc_reg r_0x10071c;
  65         struct ramfuc_reg r_0x100720;
  66         struct ramfuc_reg r_0x100760;
  67         struct ramfuc_reg r_0x1007a0;
  68         struct ramfuc_reg r_0x1007e0;
  69         struct ramfuc_reg r_0x100da0;
  70         struct ramfuc_reg r_0x10f804;
  71         struct ramfuc_reg r_0x1110e0;
  72         struct ramfuc_reg r_0x111100;
  73         struct ramfuc_reg r_0x111104;
  74         struct ramfuc_reg r_0x1111e0;
  75         struct ramfuc_reg r_0x111400;
  76         struct ramfuc_reg r_0x611200;
  77         struct ramfuc_reg r_mr[4];
  78         struct ramfuc_reg r_gpioFBVREF;
  79 };
  80
  81 struct gt215_ltrain {
  82         enum {
  83                 NVA3_TRAIN_UNKNOWN,
  84                 NVA3_TRAIN_UNSUPPORTED,
  85                 NVA3_TRAIN_ONCE,
  86                 NVA3_TRAIN_EXEC,
  87                 NVA3_TRAIN_DONE
  88         } state;
  89         u32 r_100720;
  90         u32 r_1111e0;
  91         u32 r_111400;
  92         struct nvkm_mem *mem;
  93 };
  94
  95 struct gt215_ram {
  96         struct nvkm_ram base;
  97         struct gt215_ramfuc fuc;
  98         struct gt215_ltrain ltrain;
  99 };
 100
 101 void
 102 gt215_link_train_calc(u32 *vals, struct gt215_ltrain *train)
 103 {
 104         int i, lo, hi;
 105         u8 median[8], bins[4] = {0, 0, 0, 0}, bin = 0, qty = 0;
 106
 107         for (i = 0; i < 8; i++) {
 108                 for (lo = 0; lo < 0x40; lo++) {
 109                         if (!(vals[lo] & 0x80000000))
 110                                 continue;
 111                         if (vals[lo] & (0x101 << i))
 112                                 break;
 113                 }
 114
 115                 if (lo == 0x40)
 116                         return;
 117
 118                 for (hi = lo + 1; hi < 0x40; hi++) {
 119                         if (!(vals[lo] & 0x80000000))
 120                                 continue;
 121                         if (!(vals[hi] & (0x101 << i))) {
 122                                 hi--;
 123                                 break;
 124                         }
 125                 }
 126
 127                 median[i] = ((hi - lo) >> 1) + lo;
 128                 bins[(median[i] & 0xf0) >> 4]++;
 129                 median[i] += 0x30;
 130         }
 131
 132         /* Find the best value for 0x1111e0 */
 133         for (i = 0; i < 4; i++) {
 134                 if (bins[i] > qty) {
 135                         bin = i + 3;
 136                         qty = bins[i];
 137                 }
 138         }
 139
 140         train->r_100720 = 0;
 141         for (i = 0; i < 8; i++) {
 142                 median[i] = max(median[i], (u8) (bin << 4));
 143                 median[i] = min(median[i], (u8) ((bin << 4) | 0xf));
 144
 145                 train->r_100720 |= ((median[i] & 0x0f) << (i << 2));
 146         }
 147
 148         train->r_1111e0 = 0x02000000 | (bin * 0x101);
 149         train->r_111400 = 0x0;
 150 }
 151
 152 /*
 153  * Link training for (at least) DDR3
 154  */
 155 int
 156 gt215_link_train(struct nvkm_fb *pfb)
 157 {
 158         struct nvkm_bios *bios = nvkm_bios(pfb);
 159         struct gt215_ram *ram = (void *)pfb->ram;
 160         struct nvkm_clk *clk = nvkm_clk(pfb);
 161         struct gt215_ltrain *train = &ram->ltrain;
 162         struct nvkm_device *device = nv_device(pfb);
 163         struct gt215_ramfuc *fuc = &ram->fuc;
 164         u32 *result, r1700;
 165         int ret, i;
 166         struct nvbios_M0205T M0205T = { 0 };
 167         u8 ver, hdr, cnt, len, snr, ssz;
 168         unsigned int clk_current;
 169         unsigned long flags;
 170         unsigned long *f = &flags;
 171
 172         if (nvkm_boolopt(device->cfgopt, "NvMemExec", true) != true)
 173                 return -ENOSYS;
 174
 175         /* XXX: Multiple partitions? */
 176         result = kmalloc(64 * sizeof(u32), GFP_KERNEL);
 177         if (!result)
 178                 return -ENOMEM;
 179
 180         train->state = NVA3_TRAIN_EXEC;
 181
 182         /* Clock speeds for training and back */
 183         nvbios_M0205Tp(bios, &ver, &hdr, &cnt, &len, &snr, &ssz, &M0205T);
 184         if (M0205T.freq == 0)
 185                 return -ENOENT;
 186
 187         clk_current = clk->read(clk, nv_clk_src_mem);
 188
 189         ret = gt215_clk_pre(clk, f);
 190         if (ret)
 191                 goto out;
 192
 193         /* First: clock up/down */
 194         ret = ram->base.calc(pfb, (u32) M0205T.freq * 1000);
 195         if (ret)
 196                 goto out;
 197
 198         /* Do this *after* calc, eliminates write in script */
 199         nv_wr32(pfb, 0x111400, 0x00000000);
 200         /* XXX: Magic writes that improve train reliability? */
 201         nv_mask(pfb, 0x100674, 0x0000ffff, 0x00000000);
 202         nv_mask(pfb, 0x1005e4, 0x0000ffff, 0x00000000);
 203         nv_mask(pfb, 0x100b0c, 0x000000ff, 0x00000000);
 204         nv_wr32(pfb, 0x100c04, 0x00000400);
 205
 206         /* Now the training script */
 207         r1700 = ram_rd32(fuc, 0x001700);
 208
 209         ram_mask(fuc, 0x100200, 0x00000800, 0x00000000);
 210         ram_wr32(fuc, 0x611200, 0x3300);
 211         ram_wait_vblank(fuc);
 212         ram_wait(fuc, 0x611200, 0x00000003, 0x00000000, 500000);
 213         ram_mask(fuc, 0x001610, 0x00000083, 0x00000003);
 214         ram_mask(fuc, 0x100080, 0x00000020, 0x00000000);
 215         ram_mask(fuc, 0x10f804, 0x80000000, 0x00000000);
 216         ram_wr32(fuc, 0x001700, 0x00000000);
 217
 218         ram_train(fuc);
 219
 220         /* Reset */
 221         ram_mask(fuc, 0x10f804, 0x80000000, 0x80000000);
 222         ram_wr32(fuc, 0x10053c, 0x0);
 223         ram_wr32(fuc, 0x100720, train->r_100720);
 224         ram_wr32(fuc, 0x1111e0, train->r_1111e0);
 225         ram_wr32(fuc, 0x111400, train->r_111400);
 226         ram_nuke(fuc, 0x100080);
 227         ram_mask(fuc, 0x100080, 0x00000020, 0x00000020);
 228         ram_nsec(fuc, 1000);
 229
 230         ram_wr32(fuc, 0x001700, r1700);
 231         ram_mask(fuc, 0x001610, 0x00000083, 0x00000080);
 232         ram_wr32(fuc, 0x611200, 0x3330);
 233         ram_mask(fuc, 0x100200, 0x00000800, 0x00000800);
 234
 235         ram_exec(fuc, true);
 236
 237         ram->base.calc(pfb, clk_current);
 238         ram_exec(fuc, true);
 239
 240         /* Post-processing, avoids flicker */
 241         nv_mask(pfb, 0x616308, 0x10, 0x10);
 242         nv_mask(pfb, 0x616b08, 0x10, 0x10);
 243
 244         gt215_clk_post(clk, f);
 245
 246         ram_train_result(pfb, result, 64);
 247         for (i = 0; i < 64; i++)
 248                 nv_debug(pfb, "Train: %08x", result[i]);
 249         gt215_link_train_calc(result, train);
 250
 251         nv_debug(pfb, "Train: %08x %08x %08x", train->r_100720,
 252                         train->r_1111e0, train->r_111400);
 253
 254         kfree(result);
 255
 256         train->state = NVA3_TRAIN_DONE;
 257
 258         return ret;
 259
 260 out:
 261         if(ret == -EBUSY)
 262                 f = NULL;
 263
 264         train->state = NVA3_TRAIN_UNSUPPORTED;
 265
 266         gt215_clk_post(clk, f);
 267         return ret;
 268 }
 269
 270 int
 271 gt215_link_train_init(struct nvkm_fb *pfb)
 272 {
 273         static const u32 pattern[16] = {
 274                 0xaaaaaaaa, 0xcccccccc, 0xdddddddd, 0xeeeeeeee,
 275                 0x00000000, 0x11111111, 0x44444444, 0xdddddddd,
 276                 0x33333333, 0x55555555, 0x77777777, 0x66666666,
 277                 0x99999999, 0x88888888, 0xeeeeeeee, 0xbbbbbbbb,
 278         };
 279         struct nvkm_bios *bios = nvkm_bios(pfb);
 280         struct gt215_ram *ram = (void *)pfb->ram;
 281         struct gt215_ltrain *train = &ram->ltrain;
 282         struct nvkm_mem *mem;
 283         struct nvbios_M0205E M0205E;
 284         u8 ver, hdr, cnt, len;
 285         u32 r001700;
 286         int ret, i = 0;
 287
 288         train->state = NVA3_TRAIN_UNSUPPORTED;
 289
 290         /* We support type "5"
 291          * XXX: training pattern table appears to be unused for this routine */
 292         if (!nvbios_M0205Ep(bios, i, &ver, &hdr, &cnt, &len, &M0205E))
 293                 return -ENOENT;
 294
 295         if (M0205E.type != 5)
 296                 return 0;
 297
 298         train->state = NVA3_TRAIN_ONCE;
 299
 300         ret = pfb->ram->get(pfb, 0x8000, 0x10000, 0, 0x800, &ram->ltrain.mem);
 301         if (ret)
 302                 return ret;
 303
 304         mem = ram->ltrain.mem;
 305
 306         nv_wr32(pfb, 0x100538, 0x10000000 | (mem->offset >> 16));
 307         nv_wr32(pfb, 0x1005a8, 0x0000ffff);
 308         nv_mask(pfb, 0x10f800, 0x00000001, 0x00000001);
 309
 310         for (i = 0; i < 0x30; i++) {
 311                 nv_wr32(pfb, 0x10f8c0, (i << 8) | i);
 312                 nv_wr32(pfb, 0x10f900, pattern[i % 16]);
 313         }
 314
 315         for (i = 0; i < 0x30; i++) {
 316                 nv_wr32(pfb, 0x10f8e0, (i << 8) | i);
 317                 nv_wr32(pfb, 0x10f920, pattern[i % 16]);
 318         }
 319
 320         /* And upload the pattern */
 321         r001700 = nv_rd32(pfb, 0x1700);
 322         nv_wr32(pfb, 0x1700, mem->offset >> 16);
 323         for (i = 0; i < 16; i++)
 324                 nv_wr32(pfb, 0x700000 + (i << 2), pattern[i]);
 325         for (i = 0; i < 16; i++)
 326                 nv_wr32(pfb, 0x700100 + (i << 2), pattern[i]);
 327         nv_wr32(pfb, 0x1700, r001700);
 328
 329         train->r_100720 = nv_rd32(pfb, 0x100720);
 330         train->r_1111e0 = nv_rd32(pfb, 0x1111e0);
 331         train->r_111400 = nv_rd32(pfb, 0x111400);
 332         return 0;
 333 }
 334
 335 void
 336 gt215_link_train_fini(struct nvkm_fb *pfb)
 337 {
 338         struct gt215_ram *ram = (void *)pfb->ram;
 339
 340         if (ram->ltrain.mem)
 341                 pfb->ram->put(pfb, &ram->ltrain.mem);
 342 }
 343
 344 /*
 345  * RAM reclocking
 346  */
 347 #define T(t) cfg->timing_10_##t
 348 static int
 349 gt215_ram_timing_calc(struct nvkm_fb *pfb, u32 *timing)
 350 {
 351         struct gt215_ram *ram = (void *)pfb->ram;
 352         struct nvbios_ramcfg *cfg = &ram->base.target.bios;
 353         int tUNK_base, tUNK_40_0, prevCL;
 354         u32 cur2, cur3, cur7, cur8;
 355
 356         cur2 = nv_rd32(pfb, 0x100228);
 357         cur3 = nv_rd32(pfb, 0x10022c);
 358         cur7 = nv_rd32(pfb, 0x10023c);
 359         cur8 = nv_rd32(pfb, 0x100240);
 360
 361
 362         switch ((!T(CWL)) * ram->base.type) {
 363         case NV_MEM_TYPE_DDR2:
 364                 T(CWL) = T(CL) - 1;
 365                 break;
 366         case NV_MEM_TYPE_GDDR3:
 367                 T(CWL) = ((cur2 & 0xff000000) >> 24) + 1;
 368                 break;
 369         }
 370
 371         prevCL = (cur3 & 0x000000ff) + 1;
 372         tUNK_base = ((cur7 & 0x00ff0000) >> 16) - prevCL;
 373
 374         timing[0] = (T(RP) << 24 | T(RAS) << 16 | T(RFC) << 8 | T(RC));
 375         timing[1] = (T(WR) + 1 + T(CWL)) << 24 |
 376                     max_t(u8,T(18), 1) << 16 |
 377                     (T(WTR) + 1 + T(CWL)) << 8 |
 378                     (5 + T(CL) - T(CWL));
 379         timing[2] = (T(CWL) - 1) << 24 |
 380                     (T(RRD) << 16) |
 381                     (T(RCDWR) << 8) |
 382                     T(RCDRD);
 383         timing[3] = (cur3 & 0x00ff0000) |
 384                     (0x30 + T(CL)) << 24 |
 385                     (0xb + T(CL)) << 8 |
 386                     (T(CL) - 1);
 387         timing[4] = T(20) << 24 |
 388                     T(21) << 16 |
 389                     T(13) << 8 |
 390                     T(13);
 391         timing[5] = T(RFC) << 24 |
 392                     max_t(u8,T(RCDRD), T(RCDWR)) << 16 |
 393                     max_t(u8, (T(CWL) + 6), (T(CL) + 2)) << 8 |
 394                     T(RP);
 395         timing[6] = (0x5a + T(CL)) << 16 |
 396                     max_t(u8, 1, (6 - T(CL) + T(CWL))) << 8 |
 397                     (0x50 + T(CL) - T(CWL));
 398         timing[7] = (cur7 & 0xff000000) |
 399                     ((tUNK_base + T(CL)) << 16) |
 400                     0x202;
 401         timing[8] = cur8 & 0xffffff00;
 402
 403         switch (ram->base.type) {
 404         case NV_MEM_TYPE_DDR2:
 405         case NV_MEM_TYPE_GDDR3:
 406                 tUNK_40_0 = prevCL - (cur8 & 0xff);
 407                 if (tUNK_40_0 > 0)
 408                         timing[8] |= T(CL);
 409                 break;
 410         default:
 411                 break;
 412         }
 413
 414         nv_debug(pfb, "Entry: 220: %08x %08x %08x %08x\n",
 415                         timing[0], timing[1], timing[2], timing[3]);
 416         nv_debug(pfb, "  230: %08x %08x %08x %08x\n",
 417                         timing[4], timing[5], timing[6], timing[7]);
 418         nv_debug(pfb, "  240: %08x\n", timing[8]);
 419         return 0;
 420 }
 421 #undef T
 422
 423 static void
 424 nvkm_sddr2_dll_reset(struct gt215_ramfuc *fuc)
 425 {
 426         ram_mask(fuc, mr[0], 0x100, 0x100);
 427         ram_nsec(fuc, 1000);
 428         ram_mask(fuc, mr[0], 0x100, 0x000);
 429         ram_nsec(fuc, 1000);
 430 }
 431
 432 static void
 433 nvkm_sddr3_dll_disable(struct gt215_ramfuc *fuc, u32 *mr)
 434 {
 435         u32 mr1_old = ram_rd32(fuc, mr[1]);
 436
 437         if (!(mr1_old & 0x1)) {
 438                 ram_wr32(fuc, 0x1002d4, 0x00000001);
 439                 ram_wr32(fuc, mr[1], mr[1]);
 440                 ram_nsec(fuc, 1000);
 441         }
 442 }
 443
 444 static void
 445 nvkm_gddr3_dll_disable(struct gt215_ramfuc *fuc, u32 *mr)
 446 {
 447         u32 mr1_old = ram_rd32(fuc, mr[1]);
 448
 449         if (!(mr1_old & 0x40)) {
 450                 ram_wr32(fuc, mr[1], mr[1]);
 451                 ram_nsec(fuc, 1000);
 452         }
 453 }
 454
 455 static void
 456 gt215_ram_lock_pll(struct gt215_ramfuc *fuc, struct gt215_clk_info *mclk)
 457 {
 458         ram_wr32(fuc, 0x004004, mclk->pll);
 459         ram_mask(fuc, 0x004000, 0x00000001, 0x00000001);
 460         ram_mask(fuc, 0x004000, 0x00000010, 0x00000000);
 461         ram_wait(fuc, 0x004000, 0x00020000, 0x00020000, 64000);
 462         ram_mask(fuc, 0x004000, 0x00000010, 0x00000010);
 463 }
 464
 465 static void
 466 gt215_ram_fbvref(struct gt215_ramfuc *fuc, u32 val)
 467 {
 468         struct nvkm_gpio *gpio = nvkm_gpio(fuc->base.pfb);
 469         struct dcb_gpio_func func;
 470         u32 reg, sh, gpio_val;
 471         int ret;
 472
 473         if (gpio->get(gpio, 0, 0x2e, DCB_GPIO_UNUSED) != val) {
 474                 ret = gpio->find(gpio, 0, 0x2e, DCB_GPIO_UNUSED, &func);
 475                 if (ret)
 476                         return;
 477
 478                 nv50_gpio_location(func.line, &reg, &sh);
 479                 gpio_val = ram_rd32(fuc, gpioFBVREF);
 480                 if (gpio_val & (8 << sh))
 481                         val = !val;
 482
 483                 ram_mask(fuc, gpioFBVREF, (0x3 << sh), ((val | 0x2) << sh));
 484                 ram_nsec(fuc, 20000);
 485         }
 486 }
 487
 488 static int
 489 gt215_ram_calc(struct nvkm_fb *pfb, u32 freq)
 490 {
 491         struct nvkm_bios *bios = nvkm_bios(pfb);
 492         struct gt215_ram *ram = (void *)pfb->ram;
 493         struct gt215_ramfuc *fuc = &ram->fuc;
 494         struct gt215_ltrain *train = &ram->ltrain;
 495         struct gt215_clk_info mclk;
 496         struct nvkm_ram_data *next;
 497         u8  ver, hdr, cnt, len, strap;
 498         u32 data;
 499         u32 r004018, r100760, r100da0, r111100, ctrl;
 500         u32 unk714, unk718, unk71c;
 501         int ret, i;
 502         u32 timing[9];
 503         bool pll2pll;
 504
 505         next = &ram->base.target;
 506         next->freq = freq;
 507         ram->base.next = next;
 508
 509         if (ram->ltrain.state == NVA3_TRAIN_ONCE)
 510                 gt215_link_train(pfb);
 511
 512         /* lookup memory config data relevant to the target frequency */
 513         i = 0;
 514         data = nvbios_rammapEm(bios, freq / 1000, &ver, &hdr, &cnt, &len,
 515                                &next->bios);
 516         if (!data || ver != 0x10 || hdr < 0x05) {
 517                 nv_error(pfb, "invalid/missing rammap entry\n");
 518                 return -EINVAL;
 519         }
 520
 521         /* locate specific data set for the attached memory */
 522         strap = nvbios_ramcfg_index(nv_subdev(pfb));
 523         if (strap >= cnt) {
 524                 nv_error(pfb, "invalid ramcfg strap\n");
 525                 return -EINVAL;
 526         }
 527
 528         data = nvbios_rammapSp(bios, data, ver, hdr, cnt, len, strap,
 529                                &ver, &hdr, &next->bios);
 530         if (!data || ver != 0x10 || hdr < 0x09) {
 531                 nv_error(pfb, "invalid/missing ramcfg entry\n");
 532                 return -EINVAL;
 533         }
 534
 535         /* lookup memory timings, if bios says they're present */
 536         if (next->bios.ramcfg_timing != 0xff) {
 537                 data = nvbios_timingEp(bios, next->bios.ramcfg_timing,
 538                                        &ver, &hdr, &cnt, &len,
 539                                        &next->bios);
 540                 if (!data || ver != 0x10 || hdr < 0x17) {
 541                         nv_error(pfb, "invalid/missing timing entry\n");
 542                         return -EINVAL;
 543                 }
 544         }
 545
 546         ret = gt215_pll_info(nvkm_clk(pfb), 0x12, 0x4000, freq, &mclk);
 547         if (ret < 0) {
 548                 nv_error(pfb, "failed mclk calculation\n");
 549                 return ret;
 550         }
 551
 552         gt215_ram_timing_calc(pfb, timing);
 553
 554         ret = ram_init(fuc, pfb);
 555         if (ret)
 556                 return ret;
 557
 558         /* Determine ram-specific MR values */
 559         ram->base.mr[0] = ram_rd32(fuc, mr[0]);
 560         ram->base.mr[1] = ram_rd32(fuc, mr[1]);
 561         ram->base.mr[2] = ram_rd32(fuc, mr[2]);
 562
 563         switch (ram->base.type) {
 564         case NV_MEM_TYPE_DDR2:
 565                 ret = nvkm_sddr2_calc(&ram->base);
 566                 break;
 567         case NV_MEM_TYPE_DDR3:
 568                 ret = nvkm_sddr3_calc(&ram->base);
 569                 break;
 570         case NV_MEM_TYPE_GDDR3:
 571                 ret = nvkm_gddr3_calc(&ram->base);
 572                 break;
 573         default:
 574                 ret = -ENOSYS;
 575                 break;
 576         }
 577
 578         if (ret)
 579                 return ret;
 580
 581         /* XXX: where the fuck does 750MHz come from? */
 582         if (freq <= 750000) {
 583                 r004018 = 0x10000000;
 584                 r100760 = 0x22222222;
 585                 r100da0 = 0x00000010;
 586         } else {
 587                 r004018 = 0x00000000;
 588                 r100760 = 0x00000000;
 589                 r100da0 = 0x00000000;
 590         }
 591
 592         if (!next->bios.ramcfg_10_DLLoff)
 593                 r004018 |= 0x00004000;
 594
 595         /* pll2pll requires to switch to a safe clock first */
 596         ctrl = ram_rd32(fuc, 0x004000);
 597         pll2pll = (!(ctrl & 0x00000008)) && mclk.pll;
 598
 599         /* Pre, NVIDIA does this outside the script */
 600         if (next->bios.ramcfg_10_02_10) {
 601                 ram_mask(fuc, 0x111104, 0x00000600, 0x00000000);
 602         } else {
 603                 ram_mask(fuc, 0x111100, 0x40000000, 0x40000000);
 604                 ram_mask(fuc, 0x111104, 0x00000180, 0x00000000);
 605         }
 606         /* Always disable this bit during reclock */
 607         ram_mask(fuc, 0x100200, 0x00000800, 0x00000000);
 608
 609         /* If switching from non-pll to pll, lock before disabling FB */
 610         if (mclk.pll && !pll2pll) {
 611                 ram_mask(fuc, 0x004128, 0x003f3141, mclk.clk | 0x00000101);
 612                 gt215_ram_lock_pll(fuc, &mclk);
 613         }
 614
 615         /* Start with disabling some CRTCs and PFIFO? */
 616         ram_wait_vblank(fuc);
 617         ram_wr32(fuc, 0x611200, 0x3300);
 618         ram_mask(fuc, 0x002504, 0x1, 0x1);
 619         ram_nsec(fuc, 10000);
 620         ram_wait(fuc, 0x002504, 0x10, 0x10, 20000); /* XXX: or longer? */
 621         ram_block(fuc);
 622         ram_nsec(fuc, 2000);
 623
 624         if (!next->bios.ramcfg_10_02_10) {
 625                 if (ram->base.type == NV_MEM_TYPE_GDDR3)
 626                         ram_mask(fuc, 0x111100, 0x04020000, 0x00020000);
 627                 else
 628                         ram_mask(fuc, 0x111100, 0x04020000, 0x04020000);
 629         }
 630
 631         /* If we're disabling the DLL, do it now */
 632         switch (next->bios.ramcfg_10_DLLoff * ram->base.type) {
 633         case NV_MEM_TYPE_DDR3:
 634                 nvkm_sddr3_dll_disable(fuc, ram->base.mr);
 635                 break;
 636         case NV_MEM_TYPE_GDDR3:
 637                 nvkm_gddr3_dll_disable(fuc, ram->base.mr);
 638                 break;
 639         }
 640
 641         if (fuc->r_gpioFBVREF.addr && next->bios.timing_10_ODT)
 642                 gt215_ram_fbvref(fuc, 0);
 643
 644         /* Brace RAM for impact */
 645         ram_wr32(fuc, 0x1002d4, 0x00000001);
 646         ram_wr32(fuc, 0x1002d0, 0x00000001);
 647         ram_wr32(fuc, 0x1002d0, 0x00000001);
 648         ram_wr32(fuc, 0x100210, 0x00000000);
 649         ram_wr32(fuc, 0x1002dc, 0x00000001);
 650         ram_nsec(fuc, 2000);
 651
 652         if (nv_device(pfb)->chipset == 0xa3 && freq <= 500000)
 653                 ram_mask(fuc, 0x100700, 0x00000006, 0x00000006);
 654
 655         /* Fiddle with clocks */
 656         /* There's 4 scenario's
 657          * pll->pll: first switch to a 324MHz clock, set up new PLL, switch
 658          * clk->pll: Set up new PLL, switch
 659          * pll->clk: Set up clock, switch
 660          * clk->clk: Overwrite ctrl and other bits, switch */
 661
 662         /* Switch to regular clock - 324MHz */
 663         if (pll2pll) {
 664                 ram_mask(fuc, 0x004000, 0x00000004, 0x00000004);
 665                 ram_mask(fuc, 0x004168, 0x003f3141, 0x00083101);
 666                 ram_mask(fuc, 0x004000, 0x00000008, 0x00000008);
 667                 ram_mask(fuc, 0x1110e0, 0x00088000, 0x00088000);
 668                 ram_wr32(fuc, 0x004018, 0x00001000);
 669                 gt215_ram_lock_pll(fuc, &mclk);
 670         }
 671
 672         if (mclk.pll) {
 673                 ram_mask(fuc, 0x004000, 0x00000105, 0x00000105);
 674                 ram_wr32(fuc, 0x004018, 0x00001000 | r004018);
 675                 ram_wr32(fuc, 0x100da0, r100da0);
 676         } else {
 677                 ram_mask(fuc, 0x004168, 0x003f3141, mclk.clk | 0x00000101);
 678                 ram_mask(fuc, 0x004000, 0x00000108, 0x00000008);
 679                 ram_mask(fuc, 0x1110e0, 0x00088000, 0x00088000);
 680                 ram_wr32(fuc, 0x004018, 0x00009000 | r004018);
 681                 ram_wr32(fuc, 0x100da0, r100da0);
 682         }
 683         ram_nsec(fuc, 20000);
 684
 685         if (next->bios.rammap_10_04_08) {
 686                 ram_wr32(fuc, 0x1005a0, next->bios.ramcfg_10_06 << 16 |
 687                                         next->bios.ramcfg_10_05 << 8 |
 688                                         next->bios.ramcfg_10_05);
 689                 ram_wr32(fuc, 0x1005a4, next->bios.ramcfg_10_08 << 8 |
 690                                         next->bios.ramcfg_10_07);
 691                 ram_wr32(fuc, 0x10f804, next->bios.ramcfg_10_09_f0 << 20 |
 692                                         next->bios.ramcfg_10_03_0f << 16 |
 693                                         next->bios.ramcfg_10_09_0f |
 694                                         0x80000000);
 695                 ram_mask(fuc, 0x10053c, 0x00001000, 0x00000000);
 696         } else {
 697                 if (train->state == NVA3_TRAIN_DONE) {
 698                         ram_wr32(fuc, 0x100080, 0x1020);
 699                         ram_mask(fuc, 0x111400, 0xffffffff, train->r_111400);
 700                         ram_mask(fuc, 0x1111e0, 0xffffffff, train->r_1111e0);
 701                         ram_mask(fuc, 0x100720, 0xffffffff, train->r_100720);
 702                 }
 703                 ram_mask(fuc, 0x10053c, 0x00001000, 0x00001000);
 704                 ram_mask(fuc, 0x10f804, 0x80000000, 0x00000000);
 705                 ram_mask(fuc, 0x100760, 0x22222222, r100760);
 706                 ram_mask(fuc, 0x1007a0, 0x22222222, r100760);
 707                 ram_mask(fuc, 0x1007e0, 0x22222222, r100760);
 708         }
 709
 710         if (nv_device(pfb)->chipset == 0xa3 && freq > 500000) {
 711                 ram_mask(fuc, 0x100700, 0x00000006, 0x00000000);
 712         }
 713
 714         /* Final switch */
 715         if (mclk.pll) {
 716                 ram_mask(fuc, 0x1110e0, 0x00088000, 0x00011000);
 717                 ram_mask(fuc, 0x004000, 0x00000008, 0x00000000);
 718         }
 719
 720         ram_wr32(fuc, 0x1002dc, 0x00000000);
 721         ram_wr32(fuc, 0x1002d4, 0x00000001);
 722         ram_wr32(fuc, 0x100210, 0x80000000);
 723         ram_nsec(fuc, 2000);
 724
 725         /* Set RAM MR parameters and timings */
 726         for (i = 2; i >= 0; i--) {
 727                 if (ram_rd32(fuc, mr[i]) != ram->base.mr[i]) {
 728                         ram_wr32(fuc, mr[i], ram->base.mr[i]);
 729                         ram_nsec(fuc, 1000);
 730                 }
 731         }
 732
 733         ram_wr32(fuc, 0x100220[3], timing[3]);
 734         ram_wr32(fuc, 0x100220[1], timing[1]);
 735         ram_wr32(fuc, 0x100220[6], timing[6]);
 736         ram_wr32(fuc, 0x100220[7], timing[7]);
 737         ram_wr32(fuc, 0x100220[2], timing[2]);
 738         ram_wr32(fuc, 0x100220[4], timing[4]);
 739         ram_wr32(fuc, 0x100220[5], timing[5]);
 740         ram_wr32(fuc, 0x100220[0], timing[0]);
 741         ram_wr32(fuc, 0x100220[8], timing[8]);
 742
 743         /* Misc */
 744         ram_mask(fuc, 0x100200, 0x00001000, !next->bios.ramcfg_10_02_08 << 12);
 745
 746         /* XXX: A lot of "chipset"/"ram type" specific stuff...? */
 747         unk714  = ram_rd32(fuc, 0x100714) & ~0xf0000130;
 748         unk718  = ram_rd32(fuc, 0x100718) & ~0x00000100;
 749         unk71c  = ram_rd32(fuc, 0x10071c) & ~0x00000100;
 750         r111100 = ram_rd32(fuc, 0x111100) & ~0x3a800000;
 751
 752         if (next->bios.ramcfg_10_02_04) {
 753                 switch (ram->base.type) {
 754                 case NV_MEM_TYPE_DDR3:
 755                         if (nv_device(pfb)->chipset != 0xa8)
 756                                 r111100 |= 0x00000004;
 757                         /* no break */
 758                 case NV_MEM_TYPE_DDR2:
 759                         r111100 |= 0x08000000;
 760                         break;
 761                 default:
 762                         break;
 763                 }
 764         } else {
 765                 switch (ram->base.type) {
 766                 case NV_MEM_TYPE_DDR2:
 767                         r111100 |= 0x1a800000;
 768                         unk714  |= 0x00000010;
 769                         break;
 770                 case NV_MEM_TYPE_DDR3:
 771                         if (nv_device(pfb)->chipset == 0xa8) {
 772                                 r111100 |=  0x08000000;
 773                         } else {
 774                                 r111100 &= ~0x00000004;
 775                                 r111100 |=  0x12800000;
 776                         }
 777                         unk714  |= 0x00000010;
 778                         break;
 779                 case NV_MEM_TYPE_GDDR3:
 780                         r111100 |= 0x30000000;
 781                         unk714  |= 0x00000020;
 782                         break;
 783                 default:
 784                         break;
 785                 }
 786         }
 787
 788         unk714 |= (next->bios.ramcfg_10_04_01) << 8;
 789
 790         if (next->bios.ramcfg_10_02_20)
 791                 unk714 |= 0xf0000000;
 792         if (next->bios.ramcfg_10_02_02)
 793                 unk718 |= 0x00000100;
 794         if (next->bios.ramcfg_10_02_01)
 795                 unk71c |= 0x00000100;
 796         if (next->bios.timing_10_24 != 0xff) {
 797                 unk718 &= ~0xf0000000;
 798                 unk718 |= next->bios.timing_10_24 << 28;
 799         }
 800         if (next->bios.ramcfg_10_02_10)
 801                 r111100 &= ~0x04020000;
 802
 803         ram_mask(fuc, 0x100714, 0xffffffff, unk714);
 804         ram_mask(fuc, 0x10071c, 0xffffffff, unk71c);
 805         ram_mask(fuc, 0x100718, 0xffffffff, unk718);
 806         ram_mask(fuc, 0x111100, 0xffffffff, r111100);
 807
 808         if (fuc->r_gpioFBVREF.addr && !next->bios.timing_10_ODT)
 809                 gt215_ram_fbvref(fuc, 1);
 810
 811         /* Reset DLL */
 812         if (!next->bios.ramcfg_10_DLLoff)
 813                 nvkm_sddr2_dll_reset(fuc);
 814
 815         if (ram->base.type == NV_MEM_TYPE_GDDR3) {
 816                 ram_nsec(fuc, 31000);
 817         } else {
 818                 ram_nsec(fuc, 14000);
 819         }
 820
 821         if (ram->base.type == NV_MEM_TYPE_DDR3) {
 822                 ram_wr32(fuc, 0x100264, 0x1);
 823                 ram_nsec(fuc, 2000);
 824         }
 825
 826         ram_nuke(fuc, 0x100700);
 827         ram_mask(fuc, 0x100700, 0x01000000, 0x01000000);
 828         ram_mask(fuc, 0x100700, 0x01000000, 0x00000000);
 829
 830         /* Re-enable FB */
 831         ram_unblock(fuc);
 832         ram_wr32(fuc, 0x611200, 0x3330);
 833
 834         /* Post fiddlings */
 835         if (next->bios.rammap_10_04_02)
 836                 ram_mask(fuc, 0x100200, 0x00000800, 0x00000800);
 837         if (next->bios.ramcfg_10_02_10) {
 838                 ram_mask(fuc, 0x111104, 0x00000180, 0x00000180);
 839                 ram_mask(fuc, 0x111100, 0x40000000, 0x00000000);
 840         } else {
 841                 ram_mask(fuc, 0x111104, 0x00000600, 0x00000600);
 842         }
 843
 844         if (mclk.pll) {
 845                 ram_mask(fuc, 0x004168, 0x00000001, 0x00000000);
 846                 ram_mask(fuc, 0x004168, 0x00000100, 0x00000000);
 847         } else {
 848                 ram_mask(fuc, 0x004000, 0x00000001, 0x00000000);
 849                 ram_mask(fuc, 0x004128, 0x00000001, 0x00000000);
 850                 ram_mask(fuc, 0x004128, 0x00000100, 0x00000000);
 851         }
 852
 853         return 0;
 854 }
 855
 856 static int
 857 gt215_ram_prog(struct nvkm_fb *pfb)
 858 {
 859         struct nvkm_device *device = nv_device(pfb);
 860         struct gt215_ram *ram = (void *)pfb->ram;
 861         struct gt215_ramfuc *fuc = &ram->fuc;
 862         bool exec = nvkm_boolopt(device->cfgopt, "NvMemExec", true);
 863
 864         if (exec) {
 865                 nv_mask(pfb, 0x001534, 0x2, 0x2);
 866
 867                 ram_exec(fuc, true);
 868
 869                 /* Post-processing, avoids flicker */
 870                 nv_mask(pfb, 0x002504, 0x1, 0x0);
 871                 nv_mask(pfb, 0x001534, 0x2, 0x0);
 872
 873                 nv_mask(pfb, 0x616308, 0x10, 0x10);
 874                 nv_mask(pfb, 0x616b08, 0x10, 0x10);
 875         } else {
 876                 ram_exec(fuc, false);
 877         }
 878         return 0;
 879 }
 880
 881 static void
 882 gt215_ram_tidy(struct nvkm_fb *pfb)
 883 {
 884         struct gt215_ram *ram = (void *)pfb->ram;
 885         struct gt215_ramfuc *fuc = &ram->fuc;
 886         ram_exec(fuc, false);
 887 }
 888
 889 static int
 890 gt215_ram_init(struct nvkm_object *object)
 891 {
 892         struct nvkm_fb *pfb = (void *)object->parent;
 893         struct gt215_ram   *ram = (void *)object;
 894         int ret;
 895
 896         ret = nvkm_ram_init(&ram->base);
 897         if (ret)
 898                 return ret;
 899
 900         gt215_link_train_init(pfb);
 901         return 0;
 902 }
 903
 904 static int
 905 gt215_ram_fini(struct nvkm_object *object, bool suspend)
 906 {
 907         struct nvkm_fb *pfb = (void *)object->parent;
 908
 909         if (!suspend)
 910                 gt215_link_train_fini(pfb);
 911
 912         return 0;
 913 }
 914
 915 static int
 916 gt215_ram_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
 917                struct nvkm_oclass *oclass, void *data, u32 datasize,
 918                struct nvkm_object **pobject)
 919 {
 920         struct nvkm_fb *pfb = nvkm_fb(parent);
 921         struct nvkm_gpio *gpio = nvkm_gpio(pfb);
 922         struct dcb_gpio_func func;
 923         struct gt215_ram *ram;
 924         int ret, i;
 925         u32 reg, shift;
 926
 927         ret = nv50_ram_create(parent, engine, oclass, &ram);
 928         *pobject = nv_object(ram);
 929         if (ret)
 930                 return ret;
 931
 932         switch (ram->base.type) {
 933         case NV_MEM_TYPE_DDR2:
 934         case NV_MEM_TYPE_DDR3:
 935         case NV_MEM_TYPE_GDDR3:
 936                 ram->base.calc = gt215_ram_calc;
 937                 ram->base.prog = gt215_ram_prog;
 938                 ram->base.tidy = gt215_ram_tidy;
 939                 break;
 940         default:
 941                 nv_warn(ram, "reclocking of this ram type unsupported\n");
 942                 return 0;
 943         }
 944
 945         ram->fuc.r_0x001610 = ramfuc_reg(0x001610);
 946         ram->fuc.r_0x001700 = ramfuc_reg(0x001700);
 947         ram->fuc.r_0x002504 = ramfuc_reg(0x002504);
 948         ram->fuc.r_0x004000 = ramfuc_reg(0x004000);
 949         ram->fuc.r_0x004004 = ramfuc_reg(0x004004);
 950         ram->fuc.r_0x004018 = ramfuc_reg(0x004018);
 951         ram->fuc.r_0x004128 = ramfuc_reg(0x004128);
 952         ram->fuc.r_0x004168 = ramfuc_reg(0x004168);
 953         ram->fuc.r_0x100080 = ramfuc_reg(0x100080);
 954         ram->fuc.r_0x100200 = ramfuc_reg(0x100200);
 955         ram->fuc.r_0x100210 = ramfuc_reg(0x100210);
 956         for (i = 0; i < 9; i++)
 957                 ram->fuc.r_0x100220[i] = ramfuc_reg(0x100220 + (i * 4));
 958         ram->fuc.r_0x100264 = ramfuc_reg(0x100264);
 959         ram->fuc.r_0x1002d0 = ramfuc_reg(0x1002d0);
 960         ram->fuc.r_0x1002d4 = ramfuc_reg(0x1002d4);
 961         ram->fuc.r_0x1002dc = ramfuc_reg(0x1002dc);
 962         ram->fuc.r_0x10053c = ramfuc_reg(0x10053c);
 963         ram->fuc.r_0x1005a0 = ramfuc_reg(0x1005a0);
 964         ram->fuc.r_0x1005a4 = ramfuc_reg(0x1005a4);
 965         ram->fuc.r_0x100700 = ramfuc_reg(0x100700);
 966         ram->fuc.r_0x100714 = ramfuc_reg(0x100714);
 967         ram->fuc.r_0x100718 = ramfuc_reg(0x100718);
 968         ram->fuc.r_0x10071c = ramfuc_reg(0x10071c);
 969         ram->fuc.r_0x100720 = ramfuc_reg(0x100720);
 970         ram->fuc.r_0x100760 = ramfuc_stride(0x100760, 4, ram->base.part_mask);
 971         ram->fuc.r_0x1007a0 = ramfuc_stride(0x1007a0, 4, ram->base.part_mask);
 972         ram->fuc.r_0x1007e0 = ramfuc_stride(0x1007e0, 4, ram->base.part_mask);
 973         ram->fuc.r_0x100da0 = ramfuc_stride(0x100da0, 4, ram->base.part_mask);
 974         ram->fuc.r_0x10f804 = ramfuc_reg(0x10f804);
 975         ram->fuc.r_0x1110e0 = ramfuc_stride(0x1110e0, 4, ram->base.part_mask);
 976         ram->fuc.r_0x111100 = ramfuc_reg(0x111100);
 977         ram->fuc.r_0x111104 = ramfuc_reg(0x111104);
 978         ram->fuc.r_0x1111e0 = ramfuc_reg(0x1111e0);
 979         ram->fuc.r_0x111400 = ramfuc_reg(0x111400);
 980         ram->fuc.r_0x611200 = ramfuc_reg(0x611200);
 981
 982         if (ram->base.ranks > 1) {
 983                 ram->fuc.r_mr[0] = ramfuc_reg2(0x1002c0, 0x1002c8);
 984                 ram->fuc.r_mr[1] = ramfuc_reg2(0x1002c4, 0x1002cc);
 985                 ram->fuc.r_mr[2] = ramfuc_reg2(0x1002e0, 0x1002e8);
 986                 ram->fuc.r_mr[3] = ramfuc_reg2(0x1002e4, 0x1002ec);
 987         } else {
 988                 ram->fuc.r_mr[0] = ramfuc_reg(0x1002c0);
 989                 ram->fuc.r_mr[1] = ramfuc_reg(0x1002c4);
 990                 ram->fuc.r_mr[2] = ramfuc_reg(0x1002e0);
 991                 ram->fuc.r_mr[3] = ramfuc_reg(0x1002e4);
 992         }
 993
 994         ret = gpio->find(gpio, 0, 0x2e, DCB_GPIO_UNUSED, &func);
 995         if (ret == 0) {
 996                 nv50_gpio_location(func.line, &reg, &shift);
 997                 ram->fuc.r_gpioFBVREF = ramfuc_reg(reg);
 998         }
 999
1000         return 0;
1001 }
1002
1003 struct nvkm_oclass
1004 gt215_ram_oclass = {
1005         .ofuncs = &(struct nvkm_ofuncs) {
1006                 .ctor = gt215_ram_ctor,
1007                 .dtor = _nvkm_ram_dtor,
1008                 .init = gt215_ram_init,
1009                 .fini = gt215_ram_fini,
1010         },
1011 };