drivers/gpu/drm/omapdrm/displays/panel-tpo-td028ttec1.c

   1 /*
   2  * Toppoly TD028TTEC1 panel support
   3  *
   4  * Copyright (C) 2008 Nokia Corporation
   5  * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
   6  *
   7  * Neo 1973 code (jbt6k74.c):
   8  * Copyright (C) 2006-2007 by OpenMoko, Inc.
   9  * Author: Harald Welte <laforge@openmoko.org>
  10  *
  11  * Ported and adapted from Neo 1973 U-Boot by:
  12  * H. Nikolaus Schaller <hns@goldelico.com>
  13  *
  14  * This program is free software; you can redistribute it and/or modify it
  15  * under the terms of the GNU General Public License version 2 as published by
  16  * the Free Software Foundation.
  17  *
  18  * This program is distributed in the hope that it will be useful, but WITHOUT
  19  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  20  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  21  * more details.
  22  *
  23  * You should have received a copy of the GNU General Public License along with
  24  * this program.  If not, see <http://www.gnu.org/licenses/>.
  25  */
  26
  27 #include <linux/module.h>
  28 #include <linux/delay.h>
  29 #include <linux/spi/spi.h>
  30 #include <linux/gpio.h>
  31
  32 #include "../dss/omapdss.h"
  33
  34 struct panel_drv_data {
  35         struct omap_dss_device dssdev;
  36         struct omap_dss_device *in;
  37
  38         int data_lines;
  39
  40         struct omap_video_timings videomode;
  41
  42         struct spi_device *spi_dev;
  43 };
  44
  45 static struct omap_video_timings td028ttec1_panel_timings = {
  46         .hactive        = 480,
  47         .vactive        = 640,
  48         .pixelclock     = 22153000,
  49         .hfront_porch   = 24,
  50         .hsync_len      = 8,
  51         .hback_porch    = 8,
  52         .vfront_porch   = 4,
  53         .vsync_len      = 2,
  54         .vback_porch    = 2,
  55
  56         .sync_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE,
  57
  58         .flags          = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
  59                           DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE,
  60 };
  61
  62 #define JBT_COMMAND     0x000
  63 #define JBT_DATA        0x100
  64
  65 static int jbt_ret_write_0(struct panel_drv_data *ddata, u8 reg)
  66 {
  67         int rc;
  68         u16 tx_buf = JBT_COMMAND | reg;
  69
  70         rc = spi_write(ddata->spi_dev, (u8 *)&tx_buf,
  71                         1*sizeof(u16));
  72         if (rc != 0)
  73                 dev_err(&ddata->spi_dev->dev,
  74                         "jbt_ret_write_0 spi_write ret %d\n", rc);
  75
  76         return rc;
  77 }
  78
  79 static int jbt_reg_write_1(struct panel_drv_data *ddata, u8 reg, u8 data)
  80 {
  81         int rc;
  82         u16 tx_buf[2];
  83
  84         tx_buf[0] = JBT_COMMAND | reg;
  85         tx_buf[1] = JBT_DATA | data;
  86         rc = spi_write(ddata->spi_dev, (u8 *)tx_buf,
  87                         2*sizeof(u16));
  88         if (rc != 0)
  89                 dev_err(&ddata->spi_dev->dev,
  90                         "jbt_reg_write_1 spi_write ret %d\n", rc);
  91
  92         return rc;
  93 }
  94
  95 static int jbt_reg_write_2(struct panel_drv_data *ddata, u8 reg, u16 data)
  96 {
  97         int rc;
  98         u16 tx_buf[3];
  99
 100         tx_buf[0] = JBT_COMMAND | reg;
 101         tx_buf[1] = JBT_DATA | (data >> 8);
 102         tx_buf[2] = JBT_DATA | (data & 0xff);
 103
 104         rc = spi_write(ddata->spi_dev, (u8 *)tx_buf,
 105                         3*sizeof(u16));
 106
 107         if (rc != 0)
 108                 dev_err(&ddata->spi_dev->dev,
 109                         "jbt_reg_write_2 spi_write ret %d\n", rc);
 110
 111         return rc;
 112 }
 113
 114 enum jbt_register {
 115         JBT_REG_SLEEP_IN                = 0x10,
 116         JBT_REG_SLEEP_OUT               = 0x11,
 117
 118         JBT_REG_DISPLAY_OFF             = 0x28,
 119         JBT_REG_DISPLAY_ON              = 0x29,
 120
 121         JBT_REG_RGB_FORMAT              = 0x3a,
 122         JBT_REG_QUAD_RATE               = 0x3b,
 123
 124         JBT_REG_POWER_ON_OFF            = 0xb0,
 125         JBT_REG_BOOSTER_OP              = 0xb1,
 126         JBT_REG_BOOSTER_MODE            = 0xb2,
 127         JBT_REG_BOOSTER_FREQ            = 0xb3,
 128         JBT_REG_OPAMP_SYSCLK            = 0xb4,
 129         JBT_REG_VSC_VOLTAGE             = 0xb5,
 130         JBT_REG_VCOM_VOLTAGE            = 0xb6,
 131         JBT_REG_EXT_DISPL               = 0xb7,
 132         JBT_REG_OUTPUT_CONTROL          = 0xb8,
 133         JBT_REG_DCCLK_DCEV              = 0xb9,
 134         JBT_REG_DISPLAY_MODE1           = 0xba,
 135         JBT_REG_DISPLAY_MODE2           = 0xbb,
 136         JBT_REG_DISPLAY_MODE            = 0xbc,
 137         JBT_REG_ASW_SLEW                = 0xbd,
 138         JBT_REG_DUMMY_DISPLAY           = 0xbe,
 139         JBT_REG_DRIVE_SYSTEM            = 0xbf,
 140
 141         JBT_REG_SLEEP_OUT_FR_A          = 0xc0,
 142         JBT_REG_SLEEP_OUT_FR_B          = 0xc1,
 143         JBT_REG_SLEEP_OUT_FR_C          = 0xc2,
 144         JBT_REG_SLEEP_IN_LCCNT_D        = 0xc3,
 145         JBT_REG_SLEEP_IN_LCCNT_E        = 0xc4,
 146         JBT_REG_SLEEP_IN_LCCNT_F        = 0xc5,
 147         JBT_REG_SLEEP_IN_LCCNT_G        = 0xc6,
 148
 149         JBT_REG_GAMMA1_FINE_1           = 0xc7,
 150         JBT_REG_GAMMA1_FINE_2           = 0xc8,
 151         JBT_REG_GAMMA1_INCLINATION      = 0xc9,
 152         JBT_REG_GAMMA1_BLUE_OFFSET      = 0xca,
 153
 154         JBT_REG_BLANK_CONTROL           = 0xcf,
 155         JBT_REG_BLANK_TH_TV             = 0xd0,
 156         JBT_REG_CKV_ON_OFF              = 0xd1,
 157         JBT_REG_CKV_1_2                 = 0xd2,
 158         JBT_REG_OEV_TIMING              = 0xd3,
 159         JBT_REG_ASW_TIMING_1            = 0xd4,
 160         JBT_REG_ASW_TIMING_2            = 0xd5,
 161
 162         JBT_REG_HCLOCK_VGA              = 0xec,
 163         JBT_REG_HCLOCK_QVGA             = 0xed,
 164 };
 165
 166 #define to_panel_data(p) container_of(p, struct panel_drv_data, dssdev)
 167
 168 static int td028ttec1_panel_connect(struct omap_dss_device *dssdev)
 169 {
 170         struct panel_drv_data *ddata = to_panel_data(dssdev);
 171         struct omap_dss_device *in = ddata->in;
 172         int r;
 173
 174         if (omapdss_device_is_connected(dssdev))
 175                 return 0;
 176
 177         r = in->ops.dpi->connect(in, dssdev);
 178         if (r)
 179                 return r;
 180
 181         return 0;
 182 }
 183
 184 static void td028ttec1_panel_disconnect(struct omap_dss_device *dssdev)
 185 {
 186         struct panel_drv_data *ddata = to_panel_data(dssdev);
 187         struct omap_dss_device *in = ddata->in;
 188
 189         if (!omapdss_device_is_connected(dssdev))
 190                 return;
 191
 192         in->ops.dpi->disconnect(in, dssdev);
 193 }
 194
 195 static int td028ttec1_panel_enable(struct omap_dss_device *dssdev)
 196 {
 197         struct panel_drv_data *ddata = to_panel_data(dssdev);
 198         struct omap_dss_device *in = ddata->in;
 199         int r;
 200
 201         if (!omapdss_device_is_connected(dssdev))
 202                 return -ENODEV;
 203
 204         if (omapdss_device_is_enabled(dssdev))
 205                 return 0;
 206
 207         if (ddata->data_lines)
 208                 in->ops.dpi->set_data_lines(in, ddata->data_lines);
 209         in->ops.dpi->set_timings(in, &ddata->videomode);
 210
 211         r = in->ops.dpi->enable(in);
 212         if (r)
 213                 return r;
 214
 215         dev_dbg(dssdev->dev, "td028ttec1_panel_enable() - state %d\n",
 216                 dssdev->state);
 217
 218         /* three times command zero */
 219         r |= jbt_ret_write_0(ddata, 0x00);
 220         usleep_range(1000, 2000);
 221         r |= jbt_ret_write_0(ddata, 0x00);
 222         usleep_range(1000, 2000);
 223         r |= jbt_ret_write_0(ddata, 0x00);
 224         usleep_range(1000, 2000);
 225
 226         if (r) {
 227                 dev_warn(dssdev->dev, "transfer error\n");
 228                 goto transfer_err;
 229         }
 230
 231         /* deep standby out */
 232         r |= jbt_reg_write_1(ddata, JBT_REG_POWER_ON_OFF, 0x17);
 233
 234         /* RGB I/F on, RAM write off, QVGA through, SIGCON enable */
 235         r |= jbt_reg_write_1(ddata, JBT_REG_DISPLAY_MODE, 0x80);
 236
 237         /* Quad mode off */
 238         r |= jbt_reg_write_1(ddata, JBT_REG_QUAD_RATE, 0x00);
 239
 240         /* AVDD on, XVDD on */
 241         r |= jbt_reg_write_1(ddata, JBT_REG_POWER_ON_OFF, 0x16);
 242
 243         /* Output control */
 244         r |= jbt_reg_write_2(ddata, JBT_REG_OUTPUT_CONTROL, 0xfff9);
 245
 246         /* Sleep mode off */
 247         r |= jbt_ret_write_0(ddata, JBT_REG_SLEEP_OUT);
 248
 249         /* at this point we have like 50% grey */
 250
 251         /* initialize register set */
 252         r |= jbt_reg_write_1(ddata, JBT_REG_DISPLAY_MODE1, 0x01);
 253         r |= jbt_reg_write_1(ddata, JBT_REG_DISPLAY_MODE2, 0x00);
 254         r |= jbt_reg_write_1(ddata, JBT_REG_RGB_FORMAT, 0x60);
 255         r |= jbt_reg_write_1(ddata, JBT_REG_DRIVE_SYSTEM, 0x10);
 256         r |= jbt_reg_write_1(ddata, JBT_REG_BOOSTER_OP, 0x56);
 257         r |= jbt_reg_write_1(ddata, JBT_REG_BOOSTER_MODE, 0x33);
 258         r |= jbt_reg_write_1(ddata, JBT_REG_BOOSTER_FREQ, 0x11);
 259         r |= jbt_reg_write_1(ddata, JBT_REG_BOOSTER_FREQ, 0x11);
 260         r |= jbt_reg_write_1(ddata, JBT_REG_OPAMP_SYSCLK, 0x02);
 261         r |= jbt_reg_write_1(ddata, JBT_REG_VSC_VOLTAGE, 0x2b);
 262         r |= jbt_reg_write_1(ddata, JBT_REG_VCOM_VOLTAGE, 0x40);
 263         r |= jbt_reg_write_1(ddata, JBT_REG_EXT_DISPL, 0x03);
 264         r |= jbt_reg_write_1(ddata, JBT_REG_DCCLK_DCEV, 0x04);
 265         /*
 266          * default of 0x02 in JBT_REG_ASW_SLEW responsible for 72Hz requirement
 267          * to avoid red / blue flicker
 268          */
 269         r |= jbt_reg_write_1(ddata, JBT_REG_ASW_SLEW, 0x04);
 270         r |= jbt_reg_write_1(ddata, JBT_REG_DUMMY_DISPLAY, 0x00);
 271
 272         r |= jbt_reg_write_1(ddata, JBT_REG_SLEEP_OUT_FR_A, 0x11);
 273         r |= jbt_reg_write_1(ddata, JBT_REG_SLEEP_OUT_FR_B, 0x11);
 274         r |= jbt_reg_write_1(ddata, JBT_REG_SLEEP_OUT_FR_C, 0x11);
 275         r |= jbt_reg_write_2(ddata, JBT_REG_SLEEP_IN_LCCNT_D, 0x2040);
 276         r |= jbt_reg_write_2(ddata, JBT_REG_SLEEP_IN_LCCNT_E, 0x60c0);
 277         r |= jbt_reg_write_2(ddata, JBT_REG_SLEEP_IN_LCCNT_F, 0x1020);
 278         r |= jbt_reg_write_2(ddata, JBT_REG_SLEEP_IN_LCCNT_G, 0x60c0);
 279
 280         r |= jbt_reg_write_2(ddata, JBT_REG_GAMMA1_FINE_1, 0x5533);
 281         r |= jbt_reg_write_1(ddata, JBT_REG_GAMMA1_FINE_2, 0x00);
 282         r |= jbt_reg_write_1(ddata, JBT_REG_GAMMA1_INCLINATION, 0x00);
 283         r |= jbt_reg_write_1(ddata, JBT_REG_GAMMA1_BLUE_OFFSET, 0x00);
 284
 285         r |= jbt_reg_write_2(ddata, JBT_REG_HCLOCK_VGA, 0x1f0);
 286         r |= jbt_reg_write_1(ddata, JBT_REG_BLANK_CONTROL, 0x02);
 287         r |= jbt_reg_write_2(ddata, JBT_REG_BLANK_TH_TV, 0x0804);
 288
 289         r |= jbt_reg_write_1(ddata, JBT_REG_CKV_ON_OFF, 0x01);
 290         r |= jbt_reg_write_2(ddata, JBT_REG_CKV_1_2, 0x0000);
 291
 292         r |= jbt_reg_write_2(ddata, JBT_REG_OEV_TIMING, 0x0d0e);
 293         r |= jbt_reg_write_2(ddata, JBT_REG_ASW_TIMING_1, 0x11a4);
 294         r |= jbt_reg_write_1(ddata, JBT_REG_ASW_TIMING_2, 0x0e);
 295
 296         r |= jbt_ret_write_0(ddata, JBT_REG_DISPLAY_ON);
 297
 298         dssdev->state = OMAP_DSS_DISPLAY_ACTIVE;
 299
 300 transfer_err:
 301
 302         return r ? -EIO : 0;
 303 }
 304
 305 static void td028ttec1_panel_disable(struct omap_dss_device *dssdev)
 306 {
 307         struct panel_drv_data *ddata = to_panel_data(dssdev);
 308         struct omap_dss_device *in = ddata->in;
 309
 310         if (!omapdss_device_is_enabled(dssdev))
 311                 return;
 312
 313         dev_dbg(dssdev->dev, "td028ttec1_panel_disable()\n");
 314
 315         jbt_ret_write_0(ddata, JBT_REG_DISPLAY_OFF);
 316         jbt_reg_write_2(ddata, JBT_REG_OUTPUT_CONTROL, 0x8002);
 317         jbt_ret_write_0(ddata, JBT_REG_SLEEP_IN);
 318         jbt_reg_write_1(ddata, JBT_REG_POWER_ON_OFF, 0x00);
 319
 320         in->ops.dpi->disable(in);
 321
 322         dssdev->state = OMAP_DSS_DISPLAY_DISABLED;
 323 }
 324
 325 static void td028ttec1_panel_set_timings(struct omap_dss_device *dssdev,
 326                 struct omap_video_timings *timings)
 327 {
 328         struct panel_drv_data *ddata = to_panel_data(dssdev);
 329         struct omap_dss_device *in = ddata->in;
 330
 331         ddata->videomode = *timings;
 332         dssdev->panel.timings = *timings;
 333
 334         in->ops.dpi->set_timings(in, timings);
 335 }
 336
 337 static void td028ttec1_panel_get_timings(struct omap_dss_device *dssdev,
 338                 struct omap_video_timings *timings)
 339 {
 340         struct panel_drv_data *ddata = to_panel_data(dssdev);
 341
 342         *timings = ddata->videomode;
 343 }
 344
 345 static int td028ttec1_panel_check_timings(struct omap_dss_device *dssdev,
 346                 struct omap_video_timings *timings)
 347 {
 348         struct panel_drv_data *ddata = to_panel_data(dssdev);
 349         struct omap_dss_device *in = ddata->in;
 350
 351         return in->ops.dpi->check_timings(in, timings);
 352 }
 353
 354 static struct omap_dss_driver td028ttec1_ops = {
 355         .connect        = td028ttec1_panel_connect,
 356         .disconnect     = td028ttec1_panel_disconnect,
 357
 358         .enable         = td028ttec1_panel_enable,
 359         .disable        = td028ttec1_panel_disable,
 360
 361         .set_timings    = td028ttec1_panel_set_timings,
 362         .get_timings    = td028ttec1_panel_get_timings,
 363         .check_timings  = td028ttec1_panel_check_timings,
 364 };
 365
 366 static int td028ttec1_probe_of(struct spi_device *spi)
 367 {
 368         struct device_node *node = spi->dev.of_node;
 369         struct panel_drv_data *ddata = dev_get_drvdata(&spi->dev);
 370         struct omap_dss_device *in;
 371
 372         in = omapdss_of_find_source_for_first_ep(node);
 373         if (IS_ERR(in)) {
 374                 dev_err(&spi->dev, "failed to find video source\n");
 375                 return PTR_ERR(in);
 376         }
 377
 378         ddata->in = in;
 379
 380         return 0;
 381 }
 382
 383 static int td028ttec1_panel_probe(struct spi_device *spi)
 384 {
 385         struct panel_drv_data *ddata;
 386         struct omap_dss_device *dssdev;
 387         int r;
 388
 389         dev_dbg(&spi->dev, "%s\n", __func__);
 390
 391         spi->bits_per_word = 9;
 392         spi->mode = SPI_MODE_3;
 393
 394         r = spi_setup(spi);
 395         if (r < 0) {
 396                 dev_err(&spi->dev, "spi_setup failed: %d\n", r);
 397                 return r;
 398         }
 399
 400         ddata = devm_kzalloc(&spi->dev, sizeof(*ddata), GFP_KERNEL);
 401         if (ddata == NULL)
 402                 return -ENOMEM;
 403
 404         dev_set_drvdata(&spi->dev, ddata);
 405
 406         ddata->spi_dev = spi;
 407
 408         if (!spi->dev.of_node)
 409                 return -ENODEV;
 410
 411         r = td028ttec1_probe_of(spi);
 412         if (r)
 413                 return r;
 414
 415         ddata->videomode = td028ttec1_panel_timings;
 416
 417         dssdev = &ddata->dssdev;
 418         dssdev->dev = &spi->dev;
 419         dssdev->driver = &td028ttec1_ops;
 420         dssdev->type = OMAP_DISPLAY_TYPE_DPI;
 421         dssdev->owner = THIS_MODULE;
 422         dssdev->panel.timings = ddata->videomode;
 423         dssdev->phy.dpi.data_lines = ddata->data_lines;
 424
 425         r = omapdss_register_display(dssdev);
 426         if (r) {
 427                 dev_err(&spi->dev, "Failed to register panel\n");
 428                 goto err_reg;
 429         }
 430
 431         return 0;
 432
 433 err_reg:
 434         omap_dss_put_device(ddata->in);
 435         return r;
 436 }
 437
 438 static int td028ttec1_panel_remove(struct spi_device *spi)
 439 {
 440         struct panel_drv_data *ddata = dev_get_drvdata(&spi->dev);
 441         struct omap_dss_device *dssdev = &ddata->dssdev;
 442         struct omap_dss_device *in = ddata->in;
 443
 444         dev_dbg(&ddata->spi_dev->dev, "%s\n", __func__);
 445
 446         omapdss_unregister_display(dssdev);
 447
 448         td028ttec1_panel_disable(dssdev);
 449         td028ttec1_panel_disconnect(dssdev);
 450
 451         omap_dss_put_device(in);
 452
 453         return 0;
 454 }
 455
 456 static const struct of_device_id td028ttec1_of_match[] = {
 457         { .compatible = "omapdss,toppoly,td028ttec1", },
 458         {},
 459 };
 460
 461 MODULE_DEVICE_TABLE(of, td028ttec1_of_match);
 462
 463 static struct spi_driver td028ttec1_spi_driver = {
 464         .probe          = td028ttec1_panel_probe,
 465         .remove         = td028ttec1_panel_remove,
 466
 467         .driver         = {
 468                 .name   = "panel-tpo-td028ttec1",
 469                 .of_match_table = td028ttec1_of_match,
 470                 .suppress_bind_attrs = true,
 471         },
 472 };
 473
 474 module_spi_driver(td028ttec1_spi_driver);
 475
 476 MODULE_ALIAS("spi:toppoly,td028ttec1");
 477 MODULE_AUTHOR("H. Nikolaus Schaller <hns@goldelico.com>");
 478 MODULE_DESCRIPTION("Toppoly TD028TTEC1 panel driver");
 479 MODULE_LICENSE("GPL");