drivers/gpu/drm/omapdrm/dss/venc.c

   1 /*
   2  * linux/drivers/video/omap2/dss/venc.c
   3  *
   4  * Copyright (C) 2009 Nokia Corporation
   5  * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
   6  *
   7  * VENC settings from TI's DSS driver
   8  *
   9  * This program is free software; you can redistribute it and/or modify it
  10  * under the terms of the GNU General Public License version 2 as published by
  11  * the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful, but WITHOUT
  14  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  15  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  16  * more details.
  17  *
  18  * You should have received a copy of the GNU General Public License along with
  19  * this program.  If not, see <http://www.gnu.org/licenses/>.
  20  */
  21
  22 #define DSS_SUBSYS_NAME "VENC"
  23
  24 #include <linux/kernel.h>
  25 #include <linux/module.h>
  26 #include <linux/clk.h>
  27 #include <linux/err.h>
  28 #include <linux/io.h>
  29 #include <linux/mutex.h>
  30 #include <linux/completion.h>
  31 #include <linux/delay.h>
  32 #include <linux/string.h>
  33 #include <linux/seq_file.h>
  34 #include <linux/platform_device.h>
  35 #include <linux/regulator/consumer.h>
  36 #include <linux/pm_runtime.h>
  37 #include <linux/of.h>
  38 #include <linux/of_graph.h>
  39 #include <linux/component.h>
  40
  41 #include "omapdss.h"
  42 #include "dss.h"
  43 #include "dss_features.h"
  44
  45 /* Venc registers */
  46 #define VENC_REV_ID                             0x00
  47 #define VENC_STATUS                             0x04
  48 #define VENC_F_CONTROL                          0x08
  49 #define VENC_VIDOUT_CTRL                        0x10
  50 #define VENC_SYNC_CTRL                          0x14
  51 #define VENC_LLEN                               0x1C
  52 #define VENC_FLENS                              0x20
  53 #define VENC_HFLTR_CTRL                         0x24
  54 #define VENC_CC_CARR_WSS_CARR                   0x28
  55 #define VENC_C_PHASE                            0x2C
  56 #define VENC_GAIN_U                             0x30
  57 #define VENC_GAIN_V                             0x34
  58 #define VENC_GAIN_Y                             0x38
  59 #define VENC_BLACK_LEVEL                        0x3C
  60 #define VENC_BLANK_LEVEL                        0x40
  61 #define VENC_X_COLOR                            0x44
  62 #define VENC_M_CONTROL                          0x48
  63 #define VENC_BSTAMP_WSS_DATA                    0x4C
  64 #define VENC_S_CARR                             0x50
  65 #define VENC_LINE21                             0x54
  66 #define VENC_LN_SEL                             0x58
  67 #define VENC_L21__WC_CTL                        0x5C
  68 #define VENC_HTRIGGER_VTRIGGER                  0x60
  69 #define VENC_SAVID__EAVID                       0x64
  70 #define VENC_FLEN__FAL                          0x68
  71 #define VENC_LAL__PHASE_RESET                   0x6C
  72 #define VENC_HS_INT_START_STOP_X                0x70
  73 #define VENC_HS_EXT_START_STOP_X                0x74
  74 #define VENC_VS_INT_START_X                     0x78
  75 #define VENC_VS_INT_STOP_X__VS_INT_START_Y      0x7C
  76 #define VENC_VS_INT_STOP_Y__VS_EXT_START_X      0x80
  77 #define VENC_VS_EXT_STOP_X__VS_EXT_START_Y      0x84
  78 #define VENC_VS_EXT_STOP_Y                      0x88
  79 #define VENC_AVID_START_STOP_X                  0x90
  80 #define VENC_AVID_START_STOP_Y                  0x94
  81 #define VENC_FID_INT_START_X__FID_INT_START_Y   0xA0
  82 #define VENC_FID_INT_OFFSET_Y__FID_EXT_START_X  0xA4
  83 #define VENC_FID_EXT_START_Y__FID_EXT_OFFSET_Y  0xA8
  84 #define VENC_TVDETGP_INT_START_STOP_X           0xB0
  85 #define VENC_TVDETGP_INT_START_STOP_Y           0xB4
  86 #define VENC_GEN_CTRL                           0xB8
  87 #define VENC_OUTPUT_CONTROL                     0xC4
  88 #define VENC_OUTPUT_TEST                        0xC8
  89 #define VENC_DAC_B__DAC_C                       0xC8
  90
  91 struct venc_config {
  92         u32 f_control;
  93         u32 vidout_ctrl;
  94         u32 sync_ctrl;
  95         u32 llen;
  96         u32 flens;
  97         u32 hfltr_ctrl;
  98         u32 cc_carr_wss_carr;
  99         u32 c_phase;
 100         u32 gain_u;
 101         u32 gain_v;
 102         u32 gain_y;
 103         u32 black_level;
 104         u32 blank_level;
 105         u32 x_color;
 106         u32 m_control;
 107         u32 bstamp_wss_data;
 108         u32 s_carr;
 109         u32 line21;
 110         u32 ln_sel;
 111         u32 l21__wc_ctl;
 112         u32 htrigger_vtrigger;
 113         u32 savid__eavid;
 114         u32 flen__fal;
 115         u32 lal__phase_reset;
 116         u32 hs_int_start_stop_x;
 117         u32 hs_ext_start_stop_x;
 118         u32 vs_int_start_x;
 119         u32 vs_int_stop_x__vs_int_start_y;
 120         u32 vs_int_stop_y__vs_ext_start_x;
 121         u32 vs_ext_stop_x__vs_ext_start_y;
 122         u32 vs_ext_stop_y;
 123         u32 avid_start_stop_x;
 124         u32 avid_start_stop_y;
 125         u32 fid_int_start_x__fid_int_start_y;
 126         u32 fid_int_offset_y__fid_ext_start_x;
 127         u32 fid_ext_start_y__fid_ext_offset_y;
 128         u32 tvdetgp_int_start_stop_x;
 129         u32 tvdetgp_int_start_stop_y;
 130         u32 gen_ctrl;
 131 };
 132
 133 /* from TRM */
 134 static const struct venc_config venc_config_pal_trm = {
 135         .f_control                              = 0,
 136         .vidout_ctrl                            = 1,
 137         .sync_ctrl                              = 0x40,
 138         .llen                                   = 0x35F, /* 863 */
 139         .flens                                  = 0x270, /* 624 */
 140         .hfltr_ctrl                             = 0,
 141         .cc_carr_wss_carr                       = 0x2F7225ED,
 142         .c_phase                                = 0,
 143         .gain_u                                 = 0x111,
 144         .gain_v                                 = 0x181,
 145         .gain_y                                 = 0x140,
 146         .black_level                            = 0x3B,
 147         .blank_level                            = 0x3B,
 148         .x_color                                = 0x7,
 149         .m_control                              = 0x2,
 150         .bstamp_wss_data                        = 0x3F,
 151         .s_carr                                 = 0x2A098ACB,
 152         .line21                                 = 0,
 153         .ln_sel                                 = 0x01290015,
 154         .l21__wc_ctl                            = 0x0000F603,
 155         .htrigger_vtrigger                      = 0,
 156
 157         .savid__eavid                           = 0x06A70108,
 158         .flen__fal                              = 0x00180270,
 159         .lal__phase_reset                       = 0x00040135,
 160         .hs_int_start_stop_x                    = 0x00880358,
 161         .hs_ext_start_stop_x                    = 0x000F035F,
 162         .vs_int_start_x                         = 0x01A70000,
 163         .vs_int_stop_x__vs_int_start_y          = 0x000001A7,
 164         .vs_int_stop_y__vs_ext_start_x          = 0x01AF0000,
 165         .vs_ext_stop_x__vs_ext_start_y          = 0x000101AF,
 166         .vs_ext_stop_y                          = 0x00000025,
 167         .avid_start_stop_x                      = 0x03530083,
 168         .avid_start_stop_y                      = 0x026C002E,
 169         .fid_int_start_x__fid_int_start_y       = 0x0001008A,
 170         .fid_int_offset_y__fid_ext_start_x      = 0x002E0138,
 171         .fid_ext_start_y__fid_ext_offset_y      = 0x01380001,
 172
 173         .tvdetgp_int_start_stop_x               = 0x00140001,
 174         .tvdetgp_int_start_stop_y               = 0x00010001,
 175         .gen_ctrl                               = 0x00FF0000,
 176 };
 177
 178 /* from TRM */
 179 static const struct venc_config venc_config_ntsc_trm = {
 180         .f_control                              = 0,
 181         .vidout_ctrl                            = 1,
 182         .sync_ctrl                              = 0x8040,
 183         .llen                                   = 0x359,
 184         .flens                                  = 0x20C,
 185         .hfltr_ctrl                             = 0,
 186         .cc_carr_wss_carr                       = 0x043F2631,
 187         .c_phase                                = 0,
 188         .gain_u                                 = 0x102,
 189         .gain_v                                 = 0x16C,
 190         .gain_y                                 = 0x12F,
 191         .black_level                            = 0x43,
 192         .blank_level                            = 0x38,
 193         .x_color                                = 0x7,
 194         .m_control                              = 0x1,
 195         .bstamp_wss_data                        = 0x38,
 196         .s_carr                                 = 0x21F07C1F,
 197         .line21                                 = 0,
 198         .ln_sel                                 = 0x01310011,
 199         .l21__wc_ctl                            = 0x0000F003,
 200         .htrigger_vtrigger                      = 0,
 201
 202         .savid__eavid                           = 0x069300F4,
 203         .flen__fal                              = 0x0016020C,
 204         .lal__phase_reset                       = 0x00060107,
 205         .hs_int_start_stop_x                    = 0x008E0350,
 206         .hs_ext_start_stop_x                    = 0x000F0359,
 207         .vs_int_start_x                         = 0x01A00000,
 208         .vs_int_stop_x__vs_int_start_y          = 0x020701A0,
 209         .vs_int_stop_y__vs_ext_start_x          = 0x01AC0024,
 210         .vs_ext_stop_x__vs_ext_start_y          = 0x020D01AC,
 211         .vs_ext_stop_y                          = 0x00000006,
 212         .avid_start_stop_x                      = 0x03480078,
 213         .avid_start_stop_y                      = 0x02060024,
 214         .fid_int_start_x__fid_int_start_y       = 0x0001008A,
 215         .fid_int_offset_y__fid_ext_start_x      = 0x01AC0106,
 216         .fid_ext_start_y__fid_ext_offset_y      = 0x01060006,
 217
 218         .tvdetgp_int_start_stop_x               = 0x00140001,
 219         .tvdetgp_int_start_stop_y               = 0x00010001,
 220         .gen_ctrl                               = 0x00F90000,
 221 };
 222
 223 static const struct venc_config venc_config_pal_bdghi = {
 224         .f_control                              = 0,
 225         .vidout_ctrl                            = 0,
 226         .sync_ctrl                              = 0,
 227         .hfltr_ctrl                             = 0,
 228         .x_color                                = 0,
 229         .line21                                 = 0,
 230         .ln_sel                                 = 21,
 231         .htrigger_vtrigger                      = 0,
 232         .tvdetgp_int_start_stop_x               = 0x00140001,
 233         .tvdetgp_int_start_stop_y               = 0x00010001,
 234         .gen_ctrl                               = 0x00FB0000,
 235
 236         .llen                                   = 864-1,
 237         .flens                                  = 625-1,
 238         .cc_carr_wss_carr                       = 0x2F7625ED,
 239         .c_phase                                = 0xDF,
 240         .gain_u                                 = 0x111,
 241         .gain_v                                 = 0x181,
 242         .gain_y                                 = 0x140,
 243         .black_level                            = 0x3e,
 244         .blank_level                            = 0x3e,
 245         .m_control                              = 0<<2 | 1<<1,
 246         .bstamp_wss_data                        = 0x42,
 247         .s_carr                                 = 0x2a098acb,
 248         .l21__wc_ctl                            = 0<<13 | 0x16<<8 | 0<<0,
 249         .savid__eavid                           = 0x06A70108,
 250         .flen__fal                              = 23<<16 | 624<<0,
 251         .lal__phase_reset                       = 2<<17 | 310<<0,
 252         .hs_int_start_stop_x                    = 0x00920358,
 253         .hs_ext_start_stop_x                    = 0x000F035F,
 254         .vs_int_start_x                         = 0x1a7<<16,
 255         .vs_int_stop_x__vs_int_start_y          = 0x000601A7,
 256         .vs_int_stop_y__vs_ext_start_x          = 0x01AF0036,
 257         .vs_ext_stop_x__vs_ext_start_y          = 0x27101af,
 258         .vs_ext_stop_y                          = 0x05,
 259         .avid_start_stop_x                      = 0x03530082,
 260         .avid_start_stop_y                      = 0x0270002E,
 261         .fid_int_start_x__fid_int_start_y       = 0x0005008A,
 262         .fid_int_offset_y__fid_ext_start_x      = 0x002E0138,
 263         .fid_ext_start_y__fid_ext_offset_y      = 0x01380005,
 264 };
 265
 266 const struct videomode omap_dss_pal_vm = {
 267         .hactive        = 720,
 268         .vactive        = 574,
 269         .pixelclock     = 13500000,
 270         .hsync_len      = 64,
 271         .hfront_porch   = 12,
 272         .hback_porch    = 68,
 273         .vsync_len      = 5,
 274         .vfront_porch   = 5,
 275         .vback_porch    = 41,
 276
 277         .flags          = DISPLAY_FLAGS_INTERLACED | DISPLAY_FLAGS_HSYNC_LOW |
 278                           DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_DE_HIGH |
 279                           DISPLAY_FLAGS_PIXDATA_POSEDGE |
 280                           DISPLAY_FLAGS_SYNC_NEGEDGE,
 281 };
 282 EXPORT_SYMBOL(omap_dss_pal_vm);
 283
 284 const struct videomode omap_dss_ntsc_vm = {
 285         .hactive        = 720,
 286         .vactive        = 482,
 287         .pixelclock     = 13500000,
 288         .hsync_len      = 64,
 289         .hfront_porch   = 16,
 290         .hback_porch    = 58,
 291         .vsync_len      = 6,
 292         .vfront_porch   = 6,
 293         .vback_porch    = 31,
 294
 295         .flags          = DISPLAY_FLAGS_INTERLACED | DISPLAY_FLAGS_HSYNC_LOW |
 296                           DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_DE_HIGH |
 297                           DISPLAY_FLAGS_PIXDATA_POSEDGE |
 298                           DISPLAY_FLAGS_SYNC_NEGEDGE,
 299 };
 300 EXPORT_SYMBOL(omap_dss_ntsc_vm);
 301
 302 static struct {
 303         struct platform_device *pdev;
 304         void __iomem *base;
 305         struct mutex venc_lock;
 306         u32 wss_data;
 307         struct regulator *vdda_dac_reg;
 308
 309         struct clk      *tv_dac_clk;
 310
 311         struct videomode vm;
 312         enum omap_dss_venc_type type;
 313         bool invert_polarity;
 314
 315         struct omap_dss_device output;
 316 } venc;
 317
 318 static inline void venc_write_reg(int idx, u32 val)
 319 {
 320         __raw_writel(val, venc.base + idx);
 321 }
 322
 323 static inline u32 venc_read_reg(int idx)
 324 {
 325         u32 l = __raw_readl(venc.base + idx);
 326         return l;
 327 }
 328
 329 static void venc_write_config(const struct venc_config *config)
 330 {
 331         DSSDBG("write venc conf\n");
 332
 333         venc_write_reg(VENC_LLEN, config->llen);
 334         venc_write_reg(VENC_FLENS, config->flens);
 335         venc_write_reg(VENC_CC_CARR_WSS_CARR, config->cc_carr_wss_carr);
 336         venc_write_reg(VENC_C_PHASE, config->c_phase);
 337         venc_write_reg(VENC_GAIN_U, config->gain_u);
 338         venc_write_reg(VENC_GAIN_V, config->gain_v);
 339         venc_write_reg(VENC_GAIN_Y, config->gain_y);
 340         venc_write_reg(VENC_BLACK_LEVEL, config->black_level);
 341         venc_write_reg(VENC_BLANK_LEVEL, config->blank_level);
 342         venc_write_reg(VENC_M_CONTROL, config->m_control);
 343         venc_write_reg(VENC_BSTAMP_WSS_DATA, config->bstamp_wss_data |
 344                         venc.wss_data);
 345         venc_write_reg(VENC_S_CARR, config->s_carr);
 346         venc_write_reg(VENC_L21__WC_CTL, config->l21__wc_ctl);
 347         venc_write_reg(VENC_SAVID__EAVID, config->savid__eavid);
 348         venc_write_reg(VENC_FLEN__FAL, config->flen__fal);
 349         venc_write_reg(VENC_LAL__PHASE_RESET, config->lal__phase_reset);
 350         venc_write_reg(VENC_HS_INT_START_STOP_X, config->hs_int_start_stop_x);
 351         venc_write_reg(VENC_HS_EXT_START_STOP_X, config->hs_ext_start_stop_x);
 352         venc_write_reg(VENC_VS_INT_START_X, config->vs_int_start_x);
 353         venc_write_reg(VENC_VS_INT_STOP_X__VS_INT_START_Y,
 354                        config->vs_int_stop_x__vs_int_start_y);
 355         venc_write_reg(VENC_VS_INT_STOP_Y__VS_EXT_START_X,
 356                        config->vs_int_stop_y__vs_ext_start_x);
 357         venc_write_reg(VENC_VS_EXT_STOP_X__VS_EXT_START_Y,
 358                        config->vs_ext_stop_x__vs_ext_start_y);
 359         venc_write_reg(VENC_VS_EXT_STOP_Y, config->vs_ext_stop_y);
 360         venc_write_reg(VENC_AVID_START_STOP_X, config->avid_start_stop_x);
 361         venc_write_reg(VENC_AVID_START_STOP_Y, config->avid_start_stop_y);
 362         venc_write_reg(VENC_FID_INT_START_X__FID_INT_START_Y,
 363                        config->fid_int_start_x__fid_int_start_y);
 364         venc_write_reg(VENC_FID_INT_OFFSET_Y__FID_EXT_START_X,
 365                        config->fid_int_offset_y__fid_ext_start_x);
 366         venc_write_reg(VENC_FID_EXT_START_Y__FID_EXT_OFFSET_Y,
 367                        config->fid_ext_start_y__fid_ext_offset_y);
 368
 369         venc_write_reg(VENC_DAC_B__DAC_C,  venc_read_reg(VENC_DAC_B__DAC_C));
 370         venc_write_reg(VENC_VIDOUT_CTRL, config->vidout_ctrl);
 371         venc_write_reg(VENC_HFLTR_CTRL, config->hfltr_ctrl);
 372         venc_write_reg(VENC_X_COLOR, config->x_color);
 373         venc_write_reg(VENC_LINE21, config->line21);
 374         venc_write_reg(VENC_LN_SEL, config->ln_sel);
 375         venc_write_reg(VENC_HTRIGGER_VTRIGGER, config->htrigger_vtrigger);
 376         venc_write_reg(VENC_TVDETGP_INT_START_STOP_X,
 377                        config->tvdetgp_int_start_stop_x);
 378         venc_write_reg(VENC_TVDETGP_INT_START_STOP_Y,
 379                        config->tvdetgp_int_start_stop_y);
 380         venc_write_reg(VENC_GEN_CTRL, config->gen_ctrl);
 381         venc_write_reg(VENC_F_CONTROL, config->f_control);
 382         venc_write_reg(VENC_SYNC_CTRL, config->sync_ctrl);
 383 }
 384
 385 static void venc_reset(void)
 386 {
 387         int t = 1000;
 388
 389         venc_write_reg(VENC_F_CONTROL, 1<<8);
 390         while (venc_read_reg(VENC_F_CONTROL) & (1<<8)) {
 391                 if (--t == 0) {
 392                         DSSERR("Failed to reset venc\n");
 393                         return;
 394                 }
 395         }
 396
 397 #ifdef CONFIG_OMAP2_DSS_SLEEP_AFTER_VENC_RESET
 398         /* the magical sleep that makes things work */
 399         /* XXX more info? What bug this circumvents? */
 400         msleep(20);
 401 #endif
 402 }
 403
 404 static int venc_runtime_get(void)
 405 {
 406         int r;
 407
 408         DSSDBG("venc_runtime_get\n");
 409
 410         r = pm_runtime_get_sync(&venc.pdev->dev);
 411         WARN_ON(r < 0);
 412         return r < 0 ? r : 0;
 413 }
 414
 415 static void venc_runtime_put(void)
 416 {
 417         int r;
 418
 419         DSSDBG("venc_runtime_put\n");
 420
 421         r = pm_runtime_put_sync(&venc.pdev->dev);
 422         WARN_ON(r < 0 && r != -ENOSYS);
 423 }
 424
 425 static const struct venc_config *venc_timings_to_config(struct videomode *vm)
 426 {
 427         if (memcmp(&omap_dss_pal_vm, vm, sizeof(*vm)) == 0)
 428                 return &venc_config_pal_trm;
 429
 430         if (memcmp(&omap_dss_ntsc_vm, vm, sizeof(*vm)) == 0)
 431                 return &venc_config_ntsc_trm;
 432
 433         BUG();
 434         return NULL;
 435 }
 436
 437 static int venc_power_on(struct omap_dss_device *dssdev)
 438 {
 439         enum omap_channel channel = dssdev->dispc_channel;
 440         u32 l;
 441         int r;
 442
 443         r = venc_runtime_get();
 444         if (r)
 445                 goto err0;
 446
 447         venc_reset();
 448         venc_write_config(venc_timings_to_config(&venc.vm));
 449
 450         dss_set_venc_output(venc.type);
 451         dss_set_dac_pwrdn_bgz(1);
 452
 453         l = 0;
 454
 455         if (venc.type == OMAP_DSS_VENC_TYPE_COMPOSITE)
 456                 l |= 1 << 1;
 457         else /* S-Video */
 458                 l |= (1 << 0) | (1 << 2);
 459
 460         if (venc.invert_polarity == false)
 461                 l |= 1 << 3;
 462
 463         venc_write_reg(VENC_OUTPUT_CONTROL, l);
 464
 465         dss_mgr_set_timings(channel, &venc.vm);
 466
 467         r = regulator_enable(venc.vdda_dac_reg);
 468         if (r)
 469                 goto err1;
 470
 471         r = dss_mgr_enable(channel);
 472         if (r)
 473                 goto err2;
 474
 475         return 0;
 476
 477 err2:
 478         regulator_disable(venc.vdda_dac_reg);
 479 err1:
 480         venc_write_reg(VENC_OUTPUT_CONTROL, 0);
 481         dss_set_dac_pwrdn_bgz(0);
 482
 483         venc_runtime_put();
 484 err0:
 485         return r;
 486 }
 487
 488 static void venc_power_off(struct omap_dss_device *dssdev)
 489 {
 490         enum omap_channel channel = dssdev->dispc_channel;
 491
 492         venc_write_reg(VENC_OUTPUT_CONTROL, 0);
 493         dss_set_dac_pwrdn_bgz(0);
 494
 495         dss_mgr_disable(channel);
 496
 497         regulator_disable(venc.vdda_dac_reg);
 498
 499         venc_runtime_put();
 500 }
 501
 502 static int venc_display_enable(struct omap_dss_device *dssdev)
 503 {
 504         struct omap_dss_device *out = &venc.output;
 505         int r;
 506
 507         DSSDBG("venc_display_enable\n");
 508
 509         mutex_lock(&venc.venc_lock);
 510
 511         if (!out->dispc_channel_connected) {
 512                 DSSERR("Failed to enable display: no output/manager\n");
 513                 r = -ENODEV;
 514                 goto err0;
 515         }
 516
 517         r = venc_power_on(dssdev);
 518         if (r)
 519                 goto err0;
 520
 521         venc.wss_data = 0;
 522
 523         mutex_unlock(&venc.venc_lock);
 524
 525         return 0;
 526 err0:
 527         mutex_unlock(&venc.venc_lock);
 528         return r;
 529 }
 530
 531 static void venc_display_disable(struct omap_dss_device *dssdev)
 532 {
 533         DSSDBG("venc_display_disable\n");
 534
 535         mutex_lock(&venc.venc_lock);
 536
 537         venc_power_off(dssdev);
 538
 539         mutex_unlock(&venc.venc_lock);
 540 }
 541
 542 static void venc_set_timings(struct omap_dss_device *dssdev,
 543                              struct videomode *vm)
 544 {
 545         DSSDBG("venc_set_timings\n");
 546
 547         mutex_lock(&venc.venc_lock);
 548
 549         /* Reset WSS data when the TV standard changes. */
 550         if (memcmp(&venc.vm, vm, sizeof(*vm)))
 551                 venc.wss_data = 0;
 552
 553         venc.vm = *vm;
 554
 555         dispc_set_tv_pclk(13500000);
 556
 557         mutex_unlock(&venc.venc_lock);
 558 }
 559
 560 static int venc_check_timings(struct omap_dss_device *dssdev,
 561                               struct videomode *vm)
 562 {
 563         DSSDBG("venc_check_timings\n");
 564
 565         if (memcmp(&omap_dss_pal_vm, vm, sizeof(*vm)) == 0)
 566                 return 0;
 567
 568         if (memcmp(&omap_dss_ntsc_vm, vm, sizeof(*vm)) == 0)
 569                 return 0;
 570
 571         return -EINVAL;
 572 }
 573
 574 static void venc_get_timings(struct omap_dss_device *dssdev,
 575                              struct videomode *vm)
 576 {
 577         mutex_lock(&venc.venc_lock);
 578
 579         *vm = venc.vm;
 580
 581         mutex_unlock(&venc.venc_lock);
 582 }
 583
 584 static u32 venc_get_wss(struct omap_dss_device *dssdev)
 585 {
 586         /* Invert due to VENC_L21_WC_CTL:INV=1 */
 587         return (venc.wss_data >> 8) ^ 0xfffff;
 588 }
 589
 590 static int venc_set_wss(struct omap_dss_device *dssdev, u32 wss)
 591 {
 592         const struct venc_config *config;
 593         int r;
 594
 595         DSSDBG("venc_set_wss\n");
 596
 597         mutex_lock(&venc.venc_lock);
 598
 599         config = venc_timings_to_config(&venc.vm);
 600
 601         /* Invert due to VENC_L21_WC_CTL:INV=1 */
 602         venc.wss_data = (wss ^ 0xfffff) << 8;
 603
 604         r = venc_runtime_get();
 605         if (r)
 606                 goto err;
 607
 608         venc_write_reg(VENC_BSTAMP_WSS_DATA, config->bstamp_wss_data |
 609                         venc.wss_data);
 610
 611         venc_runtime_put();
 612
 613 err:
 614         mutex_unlock(&venc.venc_lock);
 615
 616         return r;
 617 }
 618
 619 static void venc_set_type(struct omap_dss_device *dssdev,
 620                 enum omap_dss_venc_type type)
 621 {
 622         mutex_lock(&venc.venc_lock);
 623
 624         venc.type = type;
 625
 626         mutex_unlock(&venc.venc_lock);
 627 }
 628
 629 static void venc_invert_vid_out_polarity(struct omap_dss_device *dssdev,
 630                 bool invert_polarity)
 631 {
 632         mutex_lock(&venc.venc_lock);
 633
 634         venc.invert_polarity = invert_polarity;
 635
 636         mutex_unlock(&venc.venc_lock);
 637 }
 638
 639 static int venc_init_regulator(void)
 640 {
 641         struct regulator *vdda_dac;
 642
 643         if (venc.vdda_dac_reg != NULL)
 644                 return 0;
 645
 646         if (venc.pdev->dev.of_node)
 647                 vdda_dac = devm_regulator_get(&venc.pdev->dev, "vdda");
 648         else
 649                 vdda_dac = devm_regulator_get(&venc.pdev->dev, "vdda_dac");
 650
 651         if (IS_ERR(vdda_dac)) {
 652                 if (PTR_ERR(vdda_dac) != -EPROBE_DEFER)
 653                         DSSERR("can't get VDDA_DAC regulator\n");
 654                 return PTR_ERR(vdda_dac);
 655         }
 656
 657         venc.vdda_dac_reg = vdda_dac;
 658
 659         return 0;
 660 }
 661
 662 static void venc_dump_regs(struct seq_file *s)
 663 {
 664 #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, venc_read_reg(r))
 665
 666         if (venc_runtime_get())
 667                 return;
 668
 669         DUMPREG(VENC_F_CONTROL);
 670         DUMPREG(VENC_VIDOUT_CTRL);
 671         DUMPREG(VENC_SYNC_CTRL);
 672         DUMPREG(VENC_LLEN);
 673         DUMPREG(VENC_FLENS);
 674         DUMPREG(VENC_HFLTR_CTRL);
 675         DUMPREG(VENC_CC_CARR_WSS_CARR);
 676         DUMPREG(VENC_C_PHASE);
 677         DUMPREG(VENC_GAIN_U);
 678         DUMPREG(VENC_GAIN_V);
 679         DUMPREG(VENC_GAIN_Y);
 680         DUMPREG(VENC_BLACK_LEVEL);
 681         DUMPREG(VENC_BLANK_LEVEL);
 682         DUMPREG(VENC_X_COLOR);
 683         DUMPREG(VENC_M_CONTROL);
 684         DUMPREG(VENC_BSTAMP_WSS_DATA);
 685         DUMPREG(VENC_S_CARR);
 686         DUMPREG(VENC_LINE21);
 687         DUMPREG(VENC_LN_SEL);
 688         DUMPREG(VENC_L21__WC_CTL);
 689         DUMPREG(VENC_HTRIGGER_VTRIGGER);
 690         DUMPREG(VENC_SAVID__EAVID);
 691         DUMPREG(VENC_FLEN__FAL);
 692         DUMPREG(VENC_LAL__PHASE_RESET);
 693         DUMPREG(VENC_HS_INT_START_STOP_X);
 694         DUMPREG(VENC_HS_EXT_START_STOP_X);
 695         DUMPREG(VENC_VS_INT_START_X);
 696         DUMPREG(VENC_VS_INT_STOP_X__VS_INT_START_Y);
 697         DUMPREG(VENC_VS_INT_STOP_Y__VS_EXT_START_X);
 698         DUMPREG(VENC_VS_EXT_STOP_X__VS_EXT_START_Y);
 699         DUMPREG(VENC_VS_EXT_STOP_Y);
 700         DUMPREG(VENC_AVID_START_STOP_X);
 701         DUMPREG(VENC_AVID_START_STOP_Y);
 702         DUMPREG(VENC_FID_INT_START_X__FID_INT_START_Y);
 703         DUMPREG(VENC_FID_INT_OFFSET_Y__FID_EXT_START_X);
 704         DUMPREG(VENC_FID_EXT_START_Y__FID_EXT_OFFSET_Y);
 705         DUMPREG(VENC_TVDETGP_INT_START_STOP_X);
 706         DUMPREG(VENC_TVDETGP_INT_START_STOP_Y);
 707         DUMPREG(VENC_GEN_CTRL);
 708         DUMPREG(VENC_OUTPUT_CONTROL);
 709         DUMPREG(VENC_OUTPUT_TEST);
 710
 711         venc_runtime_put();
 712
 713 #undef DUMPREG
 714 }
 715
 716 static int venc_get_clocks(struct platform_device *pdev)
 717 {
 718         struct clk *clk;
 719
 720         if (dss_has_feature(FEAT_VENC_REQUIRES_TV_DAC_CLK)) {
 721                 clk = devm_clk_get(&pdev->dev, "tv_dac_clk");
 722                 if (IS_ERR(clk)) {
 723                         DSSERR("can't get tv_dac_clk\n");
 724                         return PTR_ERR(clk);
 725                 }
 726         } else {
 727                 clk = NULL;
 728         }
 729
 730         venc.tv_dac_clk = clk;
 731
 732         return 0;
 733 }
 734
 735 static int venc_connect(struct omap_dss_device *dssdev,
 736                 struct omap_dss_device *dst)
 737 {
 738         enum omap_channel channel = dssdev->dispc_channel;
 739         int r;
 740
 741         r = venc_init_regulator();
 742         if (r)
 743                 return r;
 744
 745         r = dss_mgr_connect(channel, dssdev);
 746         if (r)
 747                 return r;
 748
 749         r = omapdss_output_set_device(dssdev, dst);
 750         if (r) {
 751                 DSSERR("failed to connect output to new device: %s\n",
 752                                 dst->name);
 753                 dss_mgr_disconnect(channel, dssdev);
 754                 return r;
 755         }
 756
 757         return 0;
 758 }
 759
 760 static void venc_disconnect(struct omap_dss_device *dssdev,
 761                 struct omap_dss_device *dst)
 762 {
 763         enum omap_channel channel = dssdev->dispc_channel;
 764
 765         WARN_ON(dst != dssdev->dst);
 766
 767         if (dst != dssdev->dst)
 768                 return;
 769
 770         omapdss_output_unset_device(dssdev);
 771
 772         dss_mgr_disconnect(channel, dssdev);
 773 }
 774
 775 static const struct omapdss_atv_ops venc_ops = {
 776         .connect = venc_connect,
 777         .disconnect = venc_disconnect,
 778
 779         .enable = venc_display_enable,
 780         .disable = venc_display_disable,
 781
 782         .check_timings = venc_check_timings,
 783         .set_timings = venc_set_timings,
 784         .get_timings = venc_get_timings,
 785
 786         .set_type = venc_set_type,
 787         .invert_vid_out_polarity = venc_invert_vid_out_polarity,
 788
 789         .set_wss = venc_set_wss,
 790         .get_wss = venc_get_wss,
 791 };
 792
 793 static void venc_init_output(struct platform_device *pdev)
 794 {
 795         struct omap_dss_device *out = &venc.output;
 796
 797         out->dev = &pdev->dev;
 798         out->id = OMAP_DSS_OUTPUT_VENC;
 799         out->output_type = OMAP_DISPLAY_TYPE_VENC;
 800         out->name = "venc.0";
 801         out->dispc_channel = OMAP_DSS_CHANNEL_DIGIT;
 802         out->ops.atv = &venc_ops;
 803         out->owner = THIS_MODULE;
 804
 805         omapdss_register_output(out);
 806 }
 807
 808 static void venc_uninit_output(struct platform_device *pdev)
 809 {
 810         struct omap_dss_device *out = &venc.output;
 811
 812         omapdss_unregister_output(out);
 813 }
 814
 815 static int venc_probe_of(struct platform_device *pdev)
 816 {
 817         struct device_node *node = pdev->dev.of_node;
 818         struct device_node *ep;
 819         u32 channels;
 820         int r;
 821
 822         ep = of_graph_get_endpoint_by_regs(node, 0, 0);
 823         if (!ep)
 824                 return 0;
 825
 826         venc.invert_polarity = of_property_read_bool(ep, "ti,invert-polarity");
 827
 828         r = of_property_read_u32(ep, "ti,channels", &channels);
 829         if (r) {
 830                 dev_err(&pdev->dev,
 831                         "failed to read property 'ti,channels': %d\n", r);
 832                 goto err;
 833         }
 834
 835         switch (channels) {
 836         case 1:
 837                 venc.type = OMAP_DSS_VENC_TYPE_COMPOSITE;
 838                 break;
 839         case 2:
 840                 venc.type = OMAP_DSS_VENC_TYPE_SVIDEO;
 841                 break;
 842         default:
 843                 dev_err(&pdev->dev, "bad channel propert '%d'\n", channels);
 844                 r = -EINVAL;
 845                 goto err;
 846         }
 847
 848         of_node_put(ep);
 849
 850         return 0;
 851 err:
 852         of_node_put(ep);
 853
 854         return 0;
 855 }
 856
 857 /* VENC HW IP initialisation */
 858 static int venc_bind(struct device *dev, struct device *master, void *data)
 859 {
 860         struct platform_device *pdev = to_platform_device(dev);
 861         u8 rev_id;
 862         struct resource *venc_mem;
 863         int r;
 864
 865         venc.pdev = pdev;
 866
 867         mutex_init(&venc.venc_lock);
 868
 869         venc.wss_data = 0;
 870
 871         venc_mem = platform_get_resource(venc.pdev, IORESOURCE_MEM, 0);
 872         if (!venc_mem) {
 873                 DSSERR("can't get IORESOURCE_MEM VENC\n");
 874                 return -EINVAL;
 875         }
 876
 877         venc.base = devm_ioremap(&pdev->dev, venc_mem->start,
 878                                  resource_size(venc_mem));
 879         if (!venc.base) {
 880                 DSSERR("can't ioremap VENC\n");
 881                 return -ENOMEM;
 882         }
 883
 884         r = venc_get_clocks(pdev);
 885         if (r)
 886                 return r;
 887
 888         pm_runtime_enable(&pdev->dev);
 889
 890         r = venc_runtime_get();
 891         if (r)
 892                 goto err_runtime_get;
 893
 894         rev_id = (u8)(venc_read_reg(VENC_REV_ID) & 0xff);
 895         dev_dbg(&pdev->dev, "OMAP VENC rev %d\n", rev_id);
 896
 897         venc_runtime_put();
 898
 899         if (pdev->dev.of_node) {
 900                 r = venc_probe_of(pdev);
 901                 if (r) {
 902                         DSSERR("Invalid DT data\n");
 903                         goto err_probe_of;
 904                 }
 905         }
 906
 907         dss_debugfs_create_file("venc", venc_dump_regs);
 908
 909         venc_init_output(pdev);
 910
 911         return 0;
 912
 913 err_probe_of:
 914 err_runtime_get:
 915         pm_runtime_disable(&pdev->dev);
 916         return r;
 917 }
 918
 919 static void venc_unbind(struct device *dev, struct device *master, void *data)
 920 {
 921         struct platform_device *pdev = to_platform_device(dev);
 922
 923         venc_uninit_output(pdev);
 924
 925         pm_runtime_disable(&pdev->dev);
 926 }
 927
 928 static const struct component_ops venc_component_ops = {
 929         .bind   = venc_bind,
 930         .unbind = venc_unbind,
 931 };
 932
 933 static int venc_probe(struct platform_device *pdev)
 934 {
 935         return component_add(&pdev->dev, &venc_component_ops);
 936 }
 937
 938 static int venc_remove(struct platform_device *pdev)
 939 {
 940         component_del(&pdev->dev, &venc_component_ops);
 941         return 0;
 942 }
 943
 944 static int venc_runtime_suspend(struct device *dev)
 945 {
 946         if (venc.tv_dac_clk)
 947                 clk_disable_unprepare(venc.tv_dac_clk);
 948
 949         dispc_runtime_put();
 950
 951         return 0;
 952 }
 953
 954 static int venc_runtime_resume(struct device *dev)
 955 {
 956         int r;
 957
 958         r = dispc_runtime_get();
 959         if (r < 0)
 960                 return r;
 961
 962         if (venc.tv_dac_clk)
 963                 clk_prepare_enable(venc.tv_dac_clk);
 964
 965         return 0;
 966 }
 967
 968 static const struct dev_pm_ops venc_pm_ops = {
 969         .runtime_suspend = venc_runtime_suspend,
 970         .runtime_resume = venc_runtime_resume,
 971 };
 972
 973 static const struct of_device_id venc_of_match[] = {
 974         { .compatible = "ti,omap2-venc", },
 975         { .compatible = "ti,omap3-venc", },
 976         { .compatible = "ti,omap4-venc", },
 977         {},
 978 };
 979
 980 static struct platform_driver omap_venchw_driver = {
 981         .probe          = venc_probe,
 982         .remove         = venc_remove,
 983         .driver         = {
 984                 .name   = "omapdss_venc",
 985                 .pm     = &venc_pm_ops,
 986                 .of_match_table = venc_of_match,
 987                 .suppress_bind_attrs = true,
 988         },
 989 };
 990
 991 int __init venc_init_platform_driver(void)
 992 {
 993         return platform_driver_register(&omap_venchw_driver);
 994 }
 995
 996 void venc_uninit_platform_driver(void)
 997 {
 998         platform_driver_unregister(&omap_venchw_driver);
 999 }