drivers/gpu/drm/omapdrm/dss/venc.c

   1 /*
   2  * linux/drivers/video/omap2/dss/venc.c
   3  *
   4  * Copyright (C) 2009 Nokia Corporation
   5  * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
   6  *
   7  * VENC settings from TI's DSS driver
   8  *
   9  * This program is free software; you can redistribute it and/or modify it
  10  * under the terms of the GNU General Public License version 2 as published by
  11  * the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful, but WITHOUT
  14  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  15  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  16  * more details.
  17  *
  18  * You should have received a copy of the GNU General Public License along with
  19  * this program.  If not, see <http://www.gnu.org/licenses/>.
  20  */
  21
  22 #define DSS_SUBSYS_NAME "VENC"
  23
  24 #include <linux/kernel.h>
  25 #include <linux/module.h>
  26 #include <linux/clk.h>
  27 #include <linux/err.h>
  28 #include <linux/io.h>
  29 #include <linux/mutex.h>
  30 #include <linux/completion.h>
  31 #include <linux/delay.h>
  32 #include <linux/string.h>
  33 #include <linux/seq_file.h>
  34 #include <linux/platform_device.h>
  35 #include <linux/regulator/consumer.h>
  36 #include <linux/pm_runtime.h>
  37 #include <linux/of.h>
  38 #include <linux/component.h>
  39
  40 #include "omapdss.h"
  41 #include "dss.h"
  42 #include "dss_features.h"
  43
  44 /* Venc registers */
  45 #define VENC_REV_ID                             0x00
  46 #define VENC_STATUS                             0x04
  47 #define VENC_F_CONTROL                          0x08
  48 #define VENC_VIDOUT_CTRL                        0x10
  49 #define VENC_SYNC_CTRL                          0x14
  50 #define VENC_LLEN                               0x1C
  51 #define VENC_FLENS                              0x20
  52 #define VENC_HFLTR_CTRL                         0x24
  53 #define VENC_CC_CARR_WSS_CARR                   0x28
  54 #define VENC_C_PHASE                            0x2C
  55 #define VENC_GAIN_U                             0x30
  56 #define VENC_GAIN_V                             0x34
  57 #define VENC_GAIN_Y                             0x38
  58 #define VENC_BLACK_LEVEL                        0x3C
  59 #define VENC_BLANK_LEVEL                        0x40
  60 #define VENC_X_COLOR                            0x44
  61 #define VENC_M_CONTROL                          0x48
  62 #define VENC_BSTAMP_WSS_DATA                    0x4C
  63 #define VENC_S_CARR                             0x50
  64 #define VENC_LINE21                             0x54
  65 #define VENC_LN_SEL                             0x58
  66 #define VENC_L21__WC_CTL                        0x5C
  67 #define VENC_HTRIGGER_VTRIGGER                  0x60
  68 #define VENC_SAVID__EAVID                       0x64
  69 #define VENC_FLEN__FAL                          0x68
  70 #define VENC_LAL__PHASE_RESET                   0x6C
  71 #define VENC_HS_INT_START_STOP_X                0x70
  72 #define VENC_HS_EXT_START_STOP_X                0x74
  73 #define VENC_VS_INT_START_X                     0x78
  74 #define VENC_VS_INT_STOP_X__VS_INT_START_Y      0x7C
  75 #define VENC_VS_INT_STOP_Y__VS_EXT_START_X      0x80
  76 #define VENC_VS_EXT_STOP_X__VS_EXT_START_Y      0x84
  77 #define VENC_VS_EXT_STOP_Y                      0x88
  78 #define VENC_AVID_START_STOP_X                  0x90
  79 #define VENC_AVID_START_STOP_Y                  0x94
  80 #define VENC_FID_INT_START_X__FID_INT_START_Y   0xA0
  81 #define VENC_FID_INT_OFFSET_Y__FID_EXT_START_X  0xA4
  82 #define VENC_FID_EXT_START_Y__FID_EXT_OFFSET_Y  0xA8
  83 #define VENC_TVDETGP_INT_START_STOP_X           0xB0
  84 #define VENC_TVDETGP_INT_START_STOP_Y           0xB4
  85 #define VENC_GEN_CTRL                           0xB8
  86 #define VENC_OUTPUT_CONTROL                     0xC4
  87 #define VENC_OUTPUT_TEST                        0xC8
  88 #define VENC_DAC_B__DAC_C                       0xC8
  89
  90 struct venc_config {
  91         u32 f_control;
  92         u32 vidout_ctrl;
  93         u32 sync_ctrl;
  94         u32 llen;
  95         u32 flens;
  96         u32 hfltr_ctrl;
  97         u32 cc_carr_wss_carr;
  98         u32 c_phase;
  99         u32 gain_u;
 100         u32 gain_v;
 101         u32 gain_y;
 102         u32 black_level;
 103         u32 blank_level;
 104         u32 x_color;
 105         u32 m_control;
 106         u32 bstamp_wss_data;
 107         u32 s_carr;
 108         u32 line21;
 109         u32 ln_sel;
 110         u32 l21__wc_ctl;
 111         u32 htrigger_vtrigger;
 112         u32 savid__eavid;
 113         u32 flen__fal;
 114         u32 lal__phase_reset;
 115         u32 hs_int_start_stop_x;
 116         u32 hs_ext_start_stop_x;
 117         u32 vs_int_start_x;
 118         u32 vs_int_stop_x__vs_int_start_y;
 119         u32 vs_int_stop_y__vs_ext_start_x;
 120         u32 vs_ext_stop_x__vs_ext_start_y;
 121         u32 vs_ext_stop_y;
 122         u32 avid_start_stop_x;
 123         u32 avid_start_stop_y;
 124         u32 fid_int_start_x__fid_int_start_y;
 125         u32 fid_int_offset_y__fid_ext_start_x;
 126         u32 fid_ext_start_y__fid_ext_offset_y;
 127         u32 tvdetgp_int_start_stop_x;
 128         u32 tvdetgp_int_start_stop_y;
 129         u32 gen_ctrl;
 130 };
 131
 132 /* from TRM */
 133 static const struct venc_config venc_config_pal_trm = {
 134         .f_control                              = 0,
 135         .vidout_ctrl                            = 1,
 136         .sync_ctrl                              = 0x40,
 137         .llen                                   = 0x35F, /* 863 */
 138         .flens                                  = 0x270, /* 624 */
 139         .hfltr_ctrl                             = 0,
 140         .cc_carr_wss_carr                       = 0x2F7225ED,
 141         .c_phase                                = 0,
 142         .gain_u                                 = 0x111,
 143         .gain_v                                 = 0x181,
 144         .gain_y                                 = 0x140,
 145         .black_level                            = 0x3B,
 146         .blank_level                            = 0x3B,
 147         .x_color                                = 0x7,
 148         .m_control                              = 0x2,
 149         .bstamp_wss_data                        = 0x3F,
 150         .s_carr                                 = 0x2A098ACB,
 151         .line21                                 = 0,
 152         .ln_sel                                 = 0x01290015,
 153         .l21__wc_ctl                            = 0x0000F603,
 154         .htrigger_vtrigger                      = 0,
 155
 156         .savid__eavid                           = 0x06A70108,
 157         .flen__fal                              = 0x00180270,
 158         .lal__phase_reset                       = 0x00040135,
 159         .hs_int_start_stop_x                    = 0x00880358,
 160         .hs_ext_start_stop_x                    = 0x000F035F,
 161         .vs_int_start_x                         = 0x01A70000,
 162         .vs_int_stop_x__vs_int_start_y          = 0x000001A7,
 163         .vs_int_stop_y__vs_ext_start_x          = 0x01AF0000,
 164         .vs_ext_stop_x__vs_ext_start_y          = 0x000101AF,
 165         .vs_ext_stop_y                          = 0x00000025,
 166         .avid_start_stop_x                      = 0x03530083,
 167         .avid_start_stop_y                      = 0x026C002E,
 168         .fid_int_start_x__fid_int_start_y       = 0x0001008A,
 169         .fid_int_offset_y__fid_ext_start_x      = 0x002E0138,
 170         .fid_ext_start_y__fid_ext_offset_y      = 0x01380001,
 171
 172         .tvdetgp_int_start_stop_x               = 0x00140001,
 173         .tvdetgp_int_start_stop_y               = 0x00010001,
 174         .gen_ctrl                               = 0x00FF0000,
 175 };
 176
 177 /* from TRM */
 178 static const struct venc_config venc_config_ntsc_trm = {
 179         .f_control                              = 0,
 180         .vidout_ctrl                            = 1,
 181         .sync_ctrl                              = 0x8040,
 182         .llen                                   = 0x359,
 183         .flens                                  = 0x20C,
 184         .hfltr_ctrl                             = 0,
 185         .cc_carr_wss_carr                       = 0x043F2631,
 186         .c_phase                                = 0,
 187         .gain_u                                 = 0x102,
 188         .gain_v                                 = 0x16C,
 189         .gain_y                                 = 0x12F,
 190         .black_level                            = 0x43,
 191         .blank_level                            = 0x38,
 192         .x_color                                = 0x7,
 193         .m_control                              = 0x1,
 194         .bstamp_wss_data                        = 0x38,
 195         .s_carr                                 = 0x21F07C1F,
 196         .line21                                 = 0,
 197         .ln_sel                                 = 0x01310011,
 198         .l21__wc_ctl                            = 0x0000F003,
 199         .htrigger_vtrigger                      = 0,
 200
 201         .savid__eavid                           = 0x069300F4,
 202         .flen__fal                              = 0x0016020C,
 203         .lal__phase_reset                       = 0x00060107,
 204         .hs_int_start_stop_x                    = 0x008E0350,
 205         .hs_ext_start_stop_x                    = 0x000F0359,
 206         .vs_int_start_x                         = 0x01A00000,
 207         .vs_int_stop_x__vs_int_start_y          = 0x020701A0,
 208         .vs_int_stop_y__vs_ext_start_x          = 0x01AC0024,
 209         .vs_ext_stop_x__vs_ext_start_y          = 0x020D01AC,
 210         .vs_ext_stop_y                          = 0x00000006,
 211         .avid_start_stop_x                      = 0x03480078,
 212         .avid_start_stop_y                      = 0x02060024,
 213         .fid_int_start_x__fid_int_start_y       = 0x0001008A,
 214         .fid_int_offset_y__fid_ext_start_x      = 0x01AC0106,
 215         .fid_ext_start_y__fid_ext_offset_y      = 0x01060006,
 216
 217         .tvdetgp_int_start_stop_x               = 0x00140001,
 218         .tvdetgp_int_start_stop_y               = 0x00010001,
 219         .gen_ctrl                               = 0x00F90000,
 220 };
 221
 222 static const struct venc_config venc_config_pal_bdghi = {
 223         .f_control                              = 0,
 224         .vidout_ctrl                            = 0,
 225         .sync_ctrl                              = 0,
 226         .hfltr_ctrl                             = 0,
 227         .x_color                                = 0,
 228         .line21                                 = 0,
 229         .ln_sel                                 = 21,
 230         .htrigger_vtrigger                      = 0,
 231         .tvdetgp_int_start_stop_x               = 0x00140001,
 232         .tvdetgp_int_start_stop_y               = 0x00010001,
 233         .gen_ctrl                               = 0x00FB0000,
 234
 235         .llen                                   = 864-1,
 236         .flens                                  = 625-1,
 237         .cc_carr_wss_carr                       = 0x2F7625ED,
 238         .c_phase                                = 0xDF,
 239         .gain_u                                 = 0x111,
 240         .gain_v                                 = 0x181,
 241         .gain_y                                 = 0x140,
 242         .black_level                            = 0x3e,
 243         .blank_level                            = 0x3e,
 244         .m_control                              = 0<<2 | 1<<1,
 245         .bstamp_wss_data                        = 0x42,
 246         .s_carr                                 = 0x2a098acb,
 247         .l21__wc_ctl                            = 0<<13 | 0x16<<8 | 0<<0,
 248         .savid__eavid                           = 0x06A70108,
 249         .flen__fal                              = 23<<16 | 624<<0,
 250         .lal__phase_reset                       = 2<<17 | 310<<0,
 251         .hs_int_start_stop_x                    = 0x00920358,
 252         .hs_ext_start_stop_x                    = 0x000F035F,
 253         .vs_int_start_x                         = 0x1a7<<16,
 254         .vs_int_stop_x__vs_int_start_y          = 0x000601A7,
 255         .vs_int_stop_y__vs_ext_start_x          = 0x01AF0036,
 256         .vs_ext_stop_x__vs_ext_start_y          = 0x27101af,
 257         .vs_ext_stop_y                          = 0x05,
 258         .avid_start_stop_x                      = 0x03530082,
 259         .avid_start_stop_y                      = 0x0270002E,
 260         .fid_int_start_x__fid_int_start_y       = 0x0005008A,
 261         .fid_int_offset_y__fid_ext_start_x      = 0x002E0138,
 262         .fid_ext_start_y__fid_ext_offset_y      = 0x01380005,
 263 };
 264
 265 const struct omap_video_timings omap_dss_pal_timings = {
 266         .hactive        = 720,
 267         .vactive        = 574,
 268         .pixelclock     = 13500000,
 269         .hsw            = 64,
 270         .hfp            = 12,
 271         .hbp            = 68,
 272         .vsw            = 5,
 273         .vfp            = 5,
 274         .vbp            = 41,
 275
 276         .interlace      = true,
 277
 278         .hsync_level = OMAPDSS_SIG_ACTIVE_LOW,
 279         .vsync_level = OMAPDSS_SIG_ACTIVE_LOW,
 280         .data_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE,
 281         .de_level = OMAPDSS_SIG_ACTIVE_HIGH,
 282         .sync_pclk_edge = OMAPDSS_DRIVE_SIG_FALLING_EDGE,
 283 };
 284 EXPORT_SYMBOL(omap_dss_pal_timings);
 285
 286 const struct omap_video_timings omap_dss_ntsc_timings = {
 287         .hactive        = 720,
 288         .vactive        = 482,
 289         .pixelclock     = 13500000,
 290         .hsw            = 64,
 291         .hfp            = 16,
 292         .hbp            = 58,
 293         .vsw            = 6,
 294         .vfp            = 6,
 295         .vbp            = 31,
 296
 297         .interlace      = true,
 298
 299         .hsync_level = OMAPDSS_SIG_ACTIVE_LOW,
 300         .vsync_level = OMAPDSS_SIG_ACTIVE_LOW,
 301         .data_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE,
 302         .de_level = OMAPDSS_SIG_ACTIVE_HIGH,
 303         .sync_pclk_edge = OMAPDSS_DRIVE_SIG_FALLING_EDGE,
 304 };
 305 EXPORT_SYMBOL(omap_dss_ntsc_timings);
 306
 307 static struct {
 308         struct platform_device *pdev;
 309         void __iomem *base;
 310         struct mutex venc_lock;
 311         u32 wss_data;
 312         struct regulator *vdda_dac_reg;
 313
 314         struct clk      *tv_dac_clk;
 315
 316         struct omap_video_timings timings;
 317         enum omap_dss_venc_type type;
 318         bool invert_polarity;
 319
 320         struct omap_dss_device output;
 321 } venc;
 322
 323 static inline void venc_write_reg(int idx, u32 val)
 324 {
 325         __raw_writel(val, venc.base + idx);
 326 }
 327
 328 static inline u32 venc_read_reg(int idx)
 329 {
 330         u32 l = __raw_readl(venc.base + idx);
 331         return l;
 332 }
 333
 334 static void venc_write_config(const struct venc_config *config)
 335 {
 336         DSSDBG("write venc conf\n");
 337
 338         venc_write_reg(VENC_LLEN, config->llen);
 339         venc_write_reg(VENC_FLENS, config->flens);
 340         venc_write_reg(VENC_CC_CARR_WSS_CARR, config->cc_carr_wss_carr);
 341         venc_write_reg(VENC_C_PHASE, config->c_phase);
 342         venc_write_reg(VENC_GAIN_U, config->gain_u);
 343         venc_write_reg(VENC_GAIN_V, config->gain_v);
 344         venc_write_reg(VENC_GAIN_Y, config->gain_y);
 345         venc_write_reg(VENC_BLACK_LEVEL, config->black_level);
 346         venc_write_reg(VENC_BLANK_LEVEL, config->blank_level);
 347         venc_write_reg(VENC_M_CONTROL, config->m_control);
 348         venc_write_reg(VENC_BSTAMP_WSS_DATA, config->bstamp_wss_data |
 349                         venc.wss_data);
 350         venc_write_reg(VENC_S_CARR, config->s_carr);
 351         venc_write_reg(VENC_L21__WC_CTL, config->l21__wc_ctl);
 352         venc_write_reg(VENC_SAVID__EAVID, config->savid__eavid);
 353         venc_write_reg(VENC_FLEN__FAL, config->flen__fal);
 354         venc_write_reg(VENC_LAL__PHASE_RESET, config->lal__phase_reset);
 355         venc_write_reg(VENC_HS_INT_START_STOP_X, config->hs_int_start_stop_x);
 356         venc_write_reg(VENC_HS_EXT_START_STOP_X, config->hs_ext_start_stop_x);
 357         venc_write_reg(VENC_VS_INT_START_X, config->vs_int_start_x);
 358         venc_write_reg(VENC_VS_INT_STOP_X__VS_INT_START_Y,
 359                        config->vs_int_stop_x__vs_int_start_y);
 360         venc_write_reg(VENC_VS_INT_STOP_Y__VS_EXT_START_X,
 361                        config->vs_int_stop_y__vs_ext_start_x);
 362         venc_write_reg(VENC_VS_EXT_STOP_X__VS_EXT_START_Y,
 363                        config->vs_ext_stop_x__vs_ext_start_y);
 364         venc_write_reg(VENC_VS_EXT_STOP_Y, config->vs_ext_stop_y);
 365         venc_write_reg(VENC_AVID_START_STOP_X, config->avid_start_stop_x);
 366         venc_write_reg(VENC_AVID_START_STOP_Y, config->avid_start_stop_y);
 367         venc_write_reg(VENC_FID_INT_START_X__FID_INT_START_Y,
 368                        config->fid_int_start_x__fid_int_start_y);
 369         venc_write_reg(VENC_FID_INT_OFFSET_Y__FID_EXT_START_X,
 370                        config->fid_int_offset_y__fid_ext_start_x);
 371         venc_write_reg(VENC_FID_EXT_START_Y__FID_EXT_OFFSET_Y,
 372                        config->fid_ext_start_y__fid_ext_offset_y);
 373
 374         venc_write_reg(VENC_DAC_B__DAC_C,  venc_read_reg(VENC_DAC_B__DAC_C));
 375         venc_write_reg(VENC_VIDOUT_CTRL, config->vidout_ctrl);
 376         venc_write_reg(VENC_HFLTR_CTRL, config->hfltr_ctrl);
 377         venc_write_reg(VENC_X_COLOR, config->x_color);
 378         venc_write_reg(VENC_LINE21, config->line21);
 379         venc_write_reg(VENC_LN_SEL, config->ln_sel);
 380         venc_write_reg(VENC_HTRIGGER_VTRIGGER, config->htrigger_vtrigger);
 381         venc_write_reg(VENC_TVDETGP_INT_START_STOP_X,
 382                        config->tvdetgp_int_start_stop_x);
 383         venc_write_reg(VENC_TVDETGP_INT_START_STOP_Y,
 384                        config->tvdetgp_int_start_stop_y);
 385         venc_write_reg(VENC_GEN_CTRL, config->gen_ctrl);
 386         venc_write_reg(VENC_F_CONTROL, config->f_control);
 387         venc_write_reg(VENC_SYNC_CTRL, config->sync_ctrl);
 388 }
 389
 390 static void venc_reset(void)
 391 {
 392         int t = 1000;
 393
 394         venc_write_reg(VENC_F_CONTROL, 1<<8);
 395         while (venc_read_reg(VENC_F_CONTROL) & (1<<8)) {
 396                 if (--t == 0) {
 397                         DSSERR("Failed to reset venc\n");
 398                         return;
 399                 }
 400         }
 401
 402 #ifdef CONFIG_OMAP2_DSS_SLEEP_AFTER_VENC_RESET
 403         /* the magical sleep that makes things work */
 404         /* XXX more info? What bug this circumvents? */
 405         msleep(20);
 406 #endif
 407 }
 408
 409 static int venc_runtime_get(void)
 410 {
 411         int r;
 412
 413         DSSDBG("venc_runtime_get\n");
 414
 415         r = pm_runtime_get_sync(&venc.pdev->dev);
 416         WARN_ON(r < 0);
 417         return r < 0 ? r : 0;
 418 }
 419
 420 static void venc_runtime_put(void)
 421 {
 422         int r;
 423
 424         DSSDBG("venc_runtime_put\n");
 425
 426         r = pm_runtime_put_sync(&venc.pdev->dev);
 427         WARN_ON(r < 0 && r != -ENOSYS);
 428 }
 429
 430 static const struct venc_config *venc_timings_to_config(
 431                 struct omap_video_timings *timings)
 432 {
 433         if (memcmp(&omap_dss_pal_timings, timings, sizeof(*timings)) == 0)
 434                 return &venc_config_pal_trm;
 435
 436         if (memcmp(&omap_dss_ntsc_timings, timings, sizeof(*timings)) == 0)
 437                 return &venc_config_ntsc_trm;
 438
 439         BUG();
 440         return NULL;
 441 }
 442
 443 static int venc_power_on(struct omap_dss_device *dssdev)
 444 {
 445         enum omap_channel channel = dssdev->dispc_channel;
 446         u32 l;
 447         int r;
 448
 449         r = venc_runtime_get();
 450         if (r)
 451                 goto err0;
 452
 453         venc_reset();
 454         venc_write_config(venc_timings_to_config(&venc.timings));
 455
 456         dss_set_venc_output(venc.type);
 457         dss_set_dac_pwrdn_bgz(1);
 458
 459         l = 0;
 460
 461         if (venc.type == OMAP_DSS_VENC_TYPE_COMPOSITE)
 462                 l |= 1 << 1;
 463         else /* S-Video */
 464                 l |= (1 << 0) | (1 << 2);
 465
 466         if (venc.invert_polarity == false)
 467                 l |= 1 << 3;
 468
 469         venc_write_reg(VENC_OUTPUT_CONTROL, l);
 470
 471         dss_mgr_set_timings(channel, &venc.timings);
 472
 473         r = regulator_enable(venc.vdda_dac_reg);
 474         if (r)
 475                 goto err1;
 476
 477         r = dss_mgr_enable(channel);
 478         if (r)
 479                 goto err2;
 480
 481         return 0;
 482
 483 err2:
 484         regulator_disable(venc.vdda_dac_reg);
 485 err1:
 486         venc_write_reg(VENC_OUTPUT_CONTROL, 0);
 487         dss_set_dac_pwrdn_bgz(0);
 488
 489         venc_runtime_put();
 490 err0:
 491         return r;
 492 }
 493
 494 static void venc_power_off(struct omap_dss_device *dssdev)
 495 {
 496         enum omap_channel channel = dssdev->dispc_channel;
 497
 498         venc_write_reg(VENC_OUTPUT_CONTROL, 0);
 499         dss_set_dac_pwrdn_bgz(0);
 500
 501         dss_mgr_disable(channel);
 502
 503         regulator_disable(venc.vdda_dac_reg);
 504
 505         venc_runtime_put();
 506 }
 507
 508 static int venc_display_enable(struct omap_dss_device *dssdev)
 509 {
 510         struct omap_dss_device *out = &venc.output;
 511         int r;
 512
 513         DSSDBG("venc_display_enable\n");
 514
 515         mutex_lock(&venc.venc_lock);
 516
 517         if (!out->dispc_channel_connected) {
 518                 DSSERR("Failed to enable display: no output/manager\n");
 519                 r = -ENODEV;
 520                 goto err0;
 521         }
 522
 523         r = venc_power_on(dssdev);
 524         if (r)
 525                 goto err0;
 526
 527         venc.wss_data = 0;
 528
 529         mutex_unlock(&venc.venc_lock);
 530
 531         return 0;
 532 err0:
 533         mutex_unlock(&venc.venc_lock);
 534         return r;
 535 }
 536
 537 static void venc_display_disable(struct omap_dss_device *dssdev)
 538 {
 539         DSSDBG("venc_display_disable\n");
 540
 541         mutex_lock(&venc.venc_lock);
 542
 543         venc_power_off(dssdev);
 544
 545         mutex_unlock(&venc.venc_lock);
 546 }
 547
 548 static void venc_set_timings(struct omap_dss_device *dssdev,
 549                 struct omap_video_timings *timings)
 550 {
 551         DSSDBG("venc_set_timings\n");
 552
 553         mutex_lock(&venc.venc_lock);
 554
 555         /* Reset WSS data when the TV standard changes. */
 556         if (memcmp(&venc.timings, timings, sizeof(*timings)))
 557                 venc.wss_data = 0;
 558
 559         venc.timings = *timings;
 560
 561         dispc_set_tv_pclk(13500000);
 562
 563         mutex_unlock(&venc.venc_lock);
 564 }
 565
 566 static int venc_check_timings(struct omap_dss_device *dssdev,
 567                 struct omap_video_timings *timings)
 568 {
 569         DSSDBG("venc_check_timings\n");
 570
 571         if (memcmp(&omap_dss_pal_timings, timings, sizeof(*timings)) == 0)
 572                 return 0;
 573
 574         if (memcmp(&omap_dss_ntsc_timings, timings, sizeof(*timings)) == 0)
 575                 return 0;
 576
 577         return -EINVAL;
 578 }
 579
 580 static void venc_get_timings(struct omap_dss_device *dssdev,
 581                 struct omap_video_timings *timings)
 582 {
 583         mutex_lock(&venc.venc_lock);
 584
 585         *timings = venc.timings;
 586
 587         mutex_unlock(&venc.venc_lock);
 588 }
 589
 590 static u32 venc_get_wss(struct omap_dss_device *dssdev)
 591 {
 592         /* Invert due to VENC_L21_WC_CTL:INV=1 */
 593         return (venc.wss_data >> 8) ^ 0xfffff;
 594 }
 595
 596 static int venc_set_wss(struct omap_dss_device *dssdev, u32 wss)
 597 {
 598         const struct venc_config *config;
 599         int r;
 600
 601         DSSDBG("venc_set_wss\n");
 602
 603         mutex_lock(&venc.venc_lock);
 604
 605         config = venc_timings_to_config(&venc.timings);
 606
 607         /* Invert due to VENC_L21_WC_CTL:INV=1 */
 608         venc.wss_data = (wss ^ 0xfffff) << 8;
 609
 610         r = venc_runtime_get();
 611         if (r)
 612                 goto err;
 613
 614         venc_write_reg(VENC_BSTAMP_WSS_DATA, config->bstamp_wss_data |
 615                         venc.wss_data);
 616
 617         venc_runtime_put();
 618
 619 err:
 620         mutex_unlock(&venc.venc_lock);
 621
 622         return r;
 623 }
 624
 625 static void venc_set_type(struct omap_dss_device *dssdev,
 626                 enum omap_dss_venc_type type)
 627 {
 628         mutex_lock(&venc.venc_lock);
 629
 630         venc.type = type;
 631
 632         mutex_unlock(&venc.venc_lock);
 633 }
 634
 635 static void venc_invert_vid_out_polarity(struct omap_dss_device *dssdev,
 636                 bool invert_polarity)
 637 {
 638         mutex_lock(&venc.venc_lock);
 639
 640         venc.invert_polarity = invert_polarity;
 641
 642         mutex_unlock(&venc.venc_lock);
 643 }
 644
 645 static int venc_init_regulator(void)
 646 {
 647         struct regulator *vdda_dac;
 648
 649         if (venc.vdda_dac_reg != NULL)
 650                 return 0;
 651
 652         if (venc.pdev->dev.of_node)
 653                 vdda_dac = devm_regulator_get(&venc.pdev->dev, "vdda");
 654         else
 655                 vdda_dac = devm_regulator_get(&venc.pdev->dev, "vdda_dac");
 656
 657         if (IS_ERR(vdda_dac)) {
 658                 if (PTR_ERR(vdda_dac) != -EPROBE_DEFER)
 659                         DSSERR("can't get VDDA_DAC regulator\n");
 660                 return PTR_ERR(vdda_dac);
 661         }
 662
 663         venc.vdda_dac_reg = vdda_dac;
 664
 665         return 0;
 666 }
 667
 668 static void venc_dump_regs(struct seq_file *s)
 669 {
 670 #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, venc_read_reg(r))
 671
 672         if (venc_runtime_get())
 673                 return;
 674
 675         DUMPREG(VENC_F_CONTROL);
 676         DUMPREG(VENC_VIDOUT_CTRL);
 677         DUMPREG(VENC_SYNC_CTRL);
 678         DUMPREG(VENC_LLEN);
 679         DUMPREG(VENC_FLENS);
 680         DUMPREG(VENC_HFLTR_CTRL);
 681         DUMPREG(VENC_CC_CARR_WSS_CARR);
 682         DUMPREG(VENC_C_PHASE);
 683         DUMPREG(VENC_GAIN_U);
 684         DUMPREG(VENC_GAIN_V);
 685         DUMPREG(VENC_GAIN_Y);
 686         DUMPREG(VENC_BLACK_LEVEL);
 687         DUMPREG(VENC_BLANK_LEVEL);
 688         DUMPREG(VENC_X_COLOR);
 689         DUMPREG(VENC_M_CONTROL);
 690         DUMPREG(VENC_BSTAMP_WSS_DATA);
 691         DUMPREG(VENC_S_CARR);
 692         DUMPREG(VENC_LINE21);
 693         DUMPREG(VENC_LN_SEL);
 694         DUMPREG(VENC_L21__WC_CTL);
 695         DUMPREG(VENC_HTRIGGER_VTRIGGER);
 696         DUMPREG(VENC_SAVID__EAVID);
 697         DUMPREG(VENC_FLEN__FAL);
 698         DUMPREG(VENC_LAL__PHASE_RESET);
 699         DUMPREG(VENC_HS_INT_START_STOP_X);
 700         DUMPREG(VENC_HS_EXT_START_STOP_X);
 701         DUMPREG(VENC_VS_INT_START_X);
 702         DUMPREG(VENC_VS_INT_STOP_X__VS_INT_START_Y);
 703         DUMPREG(VENC_VS_INT_STOP_Y__VS_EXT_START_X);
 704         DUMPREG(VENC_VS_EXT_STOP_X__VS_EXT_START_Y);
 705         DUMPREG(VENC_VS_EXT_STOP_Y);
 706         DUMPREG(VENC_AVID_START_STOP_X);
 707         DUMPREG(VENC_AVID_START_STOP_Y);
 708         DUMPREG(VENC_FID_INT_START_X__FID_INT_START_Y);
 709         DUMPREG(VENC_FID_INT_OFFSET_Y__FID_EXT_START_X);
 710         DUMPREG(VENC_FID_EXT_START_Y__FID_EXT_OFFSET_Y);
 711         DUMPREG(VENC_TVDETGP_INT_START_STOP_X);
 712         DUMPREG(VENC_TVDETGP_INT_START_STOP_Y);
 713         DUMPREG(VENC_GEN_CTRL);
 714         DUMPREG(VENC_OUTPUT_CONTROL);
 715         DUMPREG(VENC_OUTPUT_TEST);
 716
 717         venc_runtime_put();
 718
 719 #undef DUMPREG
 720 }
 721
 722 static int venc_get_clocks(struct platform_device *pdev)
 723 {
 724         struct clk *clk;
 725
 726         if (dss_has_feature(FEAT_VENC_REQUIRES_TV_DAC_CLK)) {
 727                 clk = devm_clk_get(&pdev->dev, "tv_dac_clk");
 728                 if (IS_ERR(clk)) {
 729                         DSSERR("can't get tv_dac_clk\n");
 730                         return PTR_ERR(clk);
 731                 }
 732         } else {
 733                 clk = NULL;
 734         }
 735
 736         venc.tv_dac_clk = clk;
 737
 738         return 0;
 739 }
 740
 741 static int venc_connect(struct omap_dss_device *dssdev,
 742                 struct omap_dss_device *dst)
 743 {
 744         enum omap_channel channel = dssdev->dispc_channel;
 745         int r;
 746
 747         r = venc_init_regulator();
 748         if (r)
 749                 return r;
 750
 751         r = dss_mgr_connect(channel, dssdev);
 752         if (r)
 753                 return r;
 754
 755         r = omapdss_output_set_device(dssdev, dst);
 756         if (r) {
 757                 DSSERR("failed to connect output to new device: %s\n",
 758                                 dst->name);
 759                 dss_mgr_disconnect(channel, dssdev);
 760                 return r;
 761         }
 762
 763         return 0;
 764 }
 765
 766 static void venc_disconnect(struct omap_dss_device *dssdev,
 767                 struct omap_dss_device *dst)
 768 {
 769         enum omap_channel channel = dssdev->dispc_channel;
 770
 771         WARN_ON(dst != dssdev->dst);
 772
 773         if (dst != dssdev->dst)
 774                 return;
 775
 776         omapdss_output_unset_device(dssdev);
 777
 778         dss_mgr_disconnect(channel, dssdev);
 779 }
 780
 781 static const struct omapdss_atv_ops venc_ops = {
 782         .connect = venc_connect,
 783         .disconnect = venc_disconnect,
 784
 785         .enable = venc_display_enable,
 786         .disable = venc_display_disable,
 787
 788         .check_timings = venc_check_timings,
 789         .set_timings = venc_set_timings,
 790         .get_timings = venc_get_timings,
 791
 792         .set_type = venc_set_type,
 793         .invert_vid_out_polarity = venc_invert_vid_out_polarity,
 794
 795         .set_wss = venc_set_wss,
 796         .get_wss = venc_get_wss,
 797 };
 798
 799 static void venc_init_output(struct platform_device *pdev)
 800 {
 801         struct omap_dss_device *out = &venc.output;
 802
 803         out->dev = &pdev->dev;
 804         out->id = OMAP_DSS_OUTPUT_VENC;
 805         out->output_type = OMAP_DISPLAY_TYPE_VENC;
 806         out->name = "venc.0";
 807         out->dispc_channel = OMAP_DSS_CHANNEL_DIGIT;
 808         out->ops.atv = &venc_ops;
 809         out->owner = THIS_MODULE;
 810
 811         omapdss_register_output(out);
 812 }
 813
 814 static void venc_uninit_output(struct platform_device *pdev)
 815 {
 816         struct omap_dss_device *out = &venc.output;
 817
 818         omapdss_unregister_output(out);
 819 }
 820
 821 static int venc_probe_of(struct platform_device *pdev)
 822 {
 823         struct device_node *node = pdev->dev.of_node;
 824         struct device_node *ep;
 825         u32 channels;
 826         int r;
 827
 828         ep = omapdss_of_get_first_endpoint(node);
 829         if (!ep)
 830                 return 0;
 831
 832         venc.invert_polarity = of_property_read_bool(ep, "ti,invert-polarity");
 833
 834         r = of_property_read_u32(ep, "ti,channels", &channels);
 835         if (r) {
 836                 dev_err(&pdev->dev,
 837                         "failed to read property 'ti,channels': %d\n", r);
 838                 goto err;
 839         }
 840
 841         switch (channels) {
 842         case 1:
 843                 venc.type = OMAP_DSS_VENC_TYPE_COMPOSITE;
 844                 break;
 845         case 2:
 846                 venc.type = OMAP_DSS_VENC_TYPE_SVIDEO;
 847                 break;
 848         default:
 849                 dev_err(&pdev->dev, "bad channel propert '%d'\n", channels);
 850                 r = -EINVAL;
 851                 goto err;
 852         }
 853
 854         of_node_put(ep);
 855
 856         return 0;
 857 err:
 858         of_node_put(ep);
 859
 860         return 0;
 861 }
 862
 863 /* VENC HW IP initialisation */
 864 static int venc_bind(struct device *dev, struct device *master, void *data)
 865 {
 866         struct platform_device *pdev = to_platform_device(dev);
 867         u8 rev_id;
 868         struct resource *venc_mem;
 869         int r;
 870
 871         venc.pdev = pdev;
 872
 873         mutex_init(&venc.venc_lock);
 874
 875         venc.wss_data = 0;
 876
 877         venc_mem = platform_get_resource(venc.pdev, IORESOURCE_MEM, 0);
 878         if (!venc_mem) {
 879                 DSSERR("can't get IORESOURCE_MEM VENC\n");
 880                 return -EINVAL;
 881         }
 882
 883         venc.base = devm_ioremap(&pdev->dev, venc_mem->start,
 884                                  resource_size(venc_mem));
 885         if (!venc.base) {
 886                 DSSERR("can't ioremap VENC\n");
 887                 return -ENOMEM;
 888         }
 889
 890         r = venc_get_clocks(pdev);
 891         if (r)
 892                 return r;
 893
 894         pm_runtime_enable(&pdev->dev);
 895
 896         r = venc_runtime_get();
 897         if (r)
 898                 goto err_runtime_get;
 899
 900         rev_id = (u8)(venc_read_reg(VENC_REV_ID) & 0xff);
 901         dev_dbg(&pdev->dev, "OMAP VENC rev %d\n", rev_id);
 902
 903         venc_runtime_put();
 904
 905         if (pdev->dev.of_node) {
 906                 r = venc_probe_of(pdev);
 907                 if (r) {
 908                         DSSERR("Invalid DT data\n");
 909                         goto err_probe_of;
 910                 }
 911         }
 912
 913         dss_debugfs_create_file("venc", venc_dump_regs);
 914
 915         venc_init_output(pdev);
 916
 917         return 0;
 918
 919 err_probe_of:
 920 err_runtime_get:
 921         pm_runtime_disable(&pdev->dev);
 922         return r;
 923 }
 924
 925 static void venc_unbind(struct device *dev, struct device *master, void *data)
 926 {
 927         struct platform_device *pdev = to_platform_device(dev);
 928
 929         venc_uninit_output(pdev);
 930
 931         pm_runtime_disable(&pdev->dev);
 932 }
 933
 934 static const struct component_ops venc_component_ops = {
 935         .bind   = venc_bind,
 936         .unbind = venc_unbind,
 937 };
 938
 939 static int venc_probe(struct platform_device *pdev)
 940 {
 941         return component_add(&pdev->dev, &venc_component_ops);
 942 }
 943
 944 static int venc_remove(struct platform_device *pdev)
 945 {
 946         component_del(&pdev->dev, &venc_component_ops);
 947         return 0;
 948 }
 949
 950 static int venc_runtime_suspend(struct device *dev)
 951 {
 952         if (venc.tv_dac_clk)
 953                 clk_disable_unprepare(venc.tv_dac_clk);
 954
 955         dispc_runtime_put();
 956
 957         return 0;
 958 }
 959
 960 static int venc_runtime_resume(struct device *dev)
 961 {
 962         int r;
 963
 964         r = dispc_runtime_get();
 965         if (r < 0)
 966                 return r;
 967
 968         if (venc.tv_dac_clk)
 969                 clk_prepare_enable(venc.tv_dac_clk);
 970
 971         return 0;
 972 }
 973
 974 static const struct dev_pm_ops venc_pm_ops = {
 975         .runtime_suspend = venc_runtime_suspend,
 976         .runtime_resume = venc_runtime_resume,
 977 };
 978
 979 static const struct of_device_id venc_of_match[] = {
 980         { .compatible = "ti,omap2-venc", },
 981         { .compatible = "ti,omap3-venc", },
 982         { .compatible = "ti,omap4-venc", },
 983         {},
 984 };
 985
 986 static struct platform_driver omap_venchw_driver = {
 987         .probe          = venc_probe,
 988         .remove         = venc_remove,
 989         .driver         = {
 990                 .name   = "omapdss_venc",
 991                 .pm     = &venc_pm_ops,
 992                 .of_match_table = venc_of_match,
 993                 .suppress_bind_attrs = true,
 994         },
 995 };
 996
 997 int __init venc_init_platform_driver(void)
 998 {
 999         return platform_driver_register(&omap_venchw_driver);
1000 }
1001
1002 void venc_uninit_platform_driver(void)
1003 {
1004         platform_driver_unregister(&omap_venchw_driver);
1005 }