2 * drivers/gpu/drm/omapdrm/omap_crtc.c
4 * Copyright (C) 2011 Texas Instruments
5 * Author: Rob Clark <rob@ti.com>
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published by
9 * the Free Software Foundation.
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * You should have received a copy of the GNU General Public License along with
17 * this program. If not, see <http://www.gnu.org/licenses/>.
20 #include <drm/drm_atomic.h>
21 #include <drm/drm_atomic_helper.h>
22 #include <drm/drm_crtc.h>
23 #include <drm/drm_crtc_helper.h>
24 #include <drm/drm_mode.h>
25 #include <drm/drm_plane_helper.h>
29 #define to_omap_crtc(x) container_of(x, struct omap_crtc, base)
35 enum omap_channel channel;
38 * Temporary: eventually this will go away, but it is needed
39 * for now to keep the output's happy. (They only need
40 * mgr->id.) Eventually this will be replaced w/ something
41 * more common-panel-framework-y
43 struct omap_overlay_manager *mgr;
45 struct omap_video_timings timings;
47 struct omap_drm_irq vblank_irq;
48 struct omap_drm_irq error_irq;
50 bool ignore_digit_sync_lost;
53 wait_queue_head_t pending_wait;
56 /* -----------------------------------------------------------------------------
60 uint32_t pipe2vbl(struct drm_crtc *crtc)
62 struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
64 return dispc_mgr_get_vsync_irq(omap_crtc->channel);
67 struct omap_video_timings *omap_crtc_timings(struct drm_crtc *crtc)
69 struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
70 return &omap_crtc->timings;
73 enum omap_channel omap_crtc_channel(struct drm_crtc *crtc)
75 struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
76 return omap_crtc->channel;
79 int omap_crtc_wait_pending(struct drm_crtc *crtc)
81 struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
83 return wait_event_timeout(omap_crtc->pending_wait,
85 msecs_to_jiffies(50));
88 /* -----------------------------------------------------------------------------
89 * DSS Manager Functions
93 * Manager-ops, callbacks from output when they need to configure
94 * the upstream part of the video pipe.
96 * Most of these we can ignore until we add support for command-mode
97 * panels.. for video-mode the crtc-helpers already do an adequate
98 * job of sequencing the setup of the video pipe in the proper order
101 /* ovl-mgr-id -> crtc */
102 static struct omap_crtc *omap_crtcs[8];
104 /* we can probably ignore these until we support command-mode panels: */
105 static int omap_crtc_dss_connect(struct omap_overlay_manager *mgr,
106 struct omap_dss_device *dst)
111 if ((mgr->supported_outputs & dst->id) == 0)
120 static void omap_crtc_dss_disconnect(struct omap_overlay_manager *mgr,
121 struct omap_dss_device *dst)
123 mgr->output->manager = NULL;
127 static void omap_crtc_dss_start_update(struct omap_overlay_manager *mgr)
131 /* Called only from the encoder enable/disable and suspend/resume handlers. */
132 static void omap_crtc_set_enabled(struct drm_crtc *crtc, bool enable)
134 struct drm_device *dev = crtc->dev;
135 struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
136 enum omap_channel channel = omap_crtc->channel;
137 struct omap_irq_wait *wait;
138 u32 framedone_irq, vsync_irq;
141 if (dispc_mgr_is_enabled(channel) == enable)
144 if (omap_crtc->channel == OMAP_DSS_CHANNEL_DIGIT) {
146 * Digit output produces some sync lost interrupts during the
147 * first frame when enabling, so we need to ignore those.
149 omap_crtc->ignore_digit_sync_lost = true;
152 framedone_irq = dispc_mgr_get_framedone_irq(channel);
153 vsync_irq = dispc_mgr_get_vsync_irq(channel);
156 wait = omap_irq_wait_init(dev, vsync_irq, 1);
159 * When we disable the digit output, we need to wait for
160 * FRAMEDONE to know that DISPC has finished with the output.
162 * OMAP2/3 does not have FRAMEDONE irq for digit output, and in
163 * that case we need to use vsync interrupt, and wait for both
164 * even and odd frames.
168 wait = omap_irq_wait_init(dev, framedone_irq, 1);
170 wait = omap_irq_wait_init(dev, vsync_irq, 2);
173 dispc_mgr_enable(channel, enable);
175 ret = omap_irq_wait(dev, wait, msecs_to_jiffies(100));
177 dev_err(dev->dev, "%s: timeout waiting for %s\n",
178 omap_crtc->name, enable ? "enable" : "disable");
181 if (omap_crtc->channel == OMAP_DSS_CHANNEL_DIGIT) {
182 omap_crtc->ignore_digit_sync_lost = false;
183 /* make sure the irq handler sees the value above */
189 static int omap_crtc_dss_enable(struct omap_overlay_manager *mgr)
191 struct omap_crtc *omap_crtc = omap_crtcs[mgr->id];
192 struct omap_overlay_manager_info info;
194 memset(&info, 0, sizeof(info));
195 info.default_color = 0x00000000;
196 info.trans_key = 0x00000000;
197 info.trans_key_type = OMAP_DSS_COLOR_KEY_GFX_DST;
198 info.trans_enabled = false;
200 dispc_mgr_setup(omap_crtc->channel, &info);
201 dispc_mgr_set_timings(omap_crtc->channel,
202 &omap_crtc->timings);
203 omap_crtc_set_enabled(&omap_crtc->base, true);
208 static void omap_crtc_dss_disable(struct omap_overlay_manager *mgr)
210 struct omap_crtc *omap_crtc = omap_crtcs[mgr->id];
212 omap_crtc_set_enabled(&omap_crtc->base, false);
215 static void omap_crtc_dss_set_timings(struct omap_overlay_manager *mgr,
216 const struct omap_video_timings *timings)
218 struct omap_crtc *omap_crtc = omap_crtcs[mgr->id];
219 DBG("%s", omap_crtc->name);
220 omap_crtc->timings = *timings;
223 static void omap_crtc_dss_set_lcd_config(struct omap_overlay_manager *mgr,
224 const struct dss_lcd_mgr_config *config)
226 struct omap_crtc *omap_crtc = omap_crtcs[mgr->id];
227 DBG("%s", omap_crtc->name);
228 dispc_mgr_set_lcd_config(omap_crtc->channel, config);
231 static int omap_crtc_dss_register_framedone(
232 struct omap_overlay_manager *mgr,
233 void (*handler)(void *), void *data)
238 static void omap_crtc_dss_unregister_framedone(
239 struct omap_overlay_manager *mgr,
240 void (*handler)(void *), void *data)
244 static const struct dss_mgr_ops mgr_ops = {
245 .connect = omap_crtc_dss_connect,
246 .disconnect = omap_crtc_dss_disconnect,
247 .start_update = omap_crtc_dss_start_update,
248 .enable = omap_crtc_dss_enable,
249 .disable = omap_crtc_dss_disable,
250 .set_timings = omap_crtc_dss_set_timings,
251 .set_lcd_config = omap_crtc_dss_set_lcd_config,
252 .register_framedone_handler = omap_crtc_dss_register_framedone,
253 .unregister_framedone_handler = omap_crtc_dss_unregister_framedone,
256 /* -----------------------------------------------------------------------------
257 * Setup, Flush and Page Flip
260 static void omap_crtc_complete_page_flip(struct drm_crtc *crtc)
262 struct drm_pending_vblank_event *event;
263 struct drm_device *dev = crtc->dev;
266 event = crtc->state->event;
271 spin_lock_irqsave(&dev->event_lock, flags);
272 drm_crtc_send_vblank_event(crtc, event);
273 spin_unlock_irqrestore(&dev->event_lock, flags);
276 static void omap_crtc_error_irq(struct omap_drm_irq *irq, uint32_t irqstatus)
278 struct omap_crtc *omap_crtc =
279 container_of(irq, struct omap_crtc, error_irq);
281 if (omap_crtc->ignore_digit_sync_lost) {
282 irqstatus &= ~DISPC_IRQ_SYNC_LOST_DIGIT;
287 DRM_ERROR_RATELIMITED("%s: errors: %08x\n", omap_crtc->name, irqstatus);
290 static void omap_crtc_vblank_irq(struct omap_drm_irq *irq, uint32_t irqstatus)
292 struct omap_crtc *omap_crtc =
293 container_of(irq, struct omap_crtc, vblank_irq);
294 struct drm_device *dev = omap_crtc->base.dev;
296 if (dispc_mgr_go_busy(omap_crtc->channel))
299 DBG("%s: apply done", omap_crtc->name);
301 __omap_irq_unregister(dev, &omap_crtc->vblank_irq);
304 WARN_ON(!omap_crtc->pending);
305 omap_crtc->pending = false;
308 /* wake up userspace */
309 omap_crtc_complete_page_flip(&omap_crtc->base);
311 /* wake up omap_atomic_complete */
312 wake_up(&omap_crtc->pending_wait);
315 /* -----------------------------------------------------------------------------
319 static void omap_crtc_destroy(struct drm_crtc *crtc)
321 struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
323 DBG("%s", omap_crtc->name);
325 WARN_ON(omap_crtc->vblank_irq.registered);
326 omap_irq_unregister(crtc->dev, &omap_crtc->error_irq);
328 drm_crtc_cleanup(crtc);
333 static bool omap_crtc_mode_fixup(struct drm_crtc *crtc,
334 const struct drm_display_mode *mode,
335 struct drm_display_mode *adjusted_mode)
340 static void omap_crtc_enable(struct drm_crtc *crtc)
342 struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
344 DBG("%s", omap_crtc->name);
347 WARN_ON(omap_crtc->pending);
348 omap_crtc->pending = true;
351 omap_irq_register(crtc->dev, &omap_crtc->vblank_irq);
353 drm_crtc_vblank_on(crtc);
356 static void omap_crtc_disable(struct drm_crtc *crtc)
358 struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
360 DBG("%s", omap_crtc->name);
362 drm_crtc_vblank_off(crtc);
365 static void omap_crtc_mode_set_nofb(struct drm_crtc *crtc)
367 struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
368 struct drm_display_mode *mode = &crtc->state->adjusted_mode;
370 DBG("%s: set mode: %d:\"%s\" %d %d %d %d %d %d %d %d %d %d 0x%x 0x%x",
371 omap_crtc->name, mode->base.id, mode->name,
372 mode->vrefresh, mode->clock,
373 mode->hdisplay, mode->hsync_start, mode->hsync_end, mode->htotal,
374 mode->vdisplay, mode->vsync_start, mode->vsync_end, mode->vtotal,
375 mode->type, mode->flags);
377 copy_timings_drm_to_omap(&omap_crtc->timings, mode);
380 static void omap_crtc_atomic_begin(struct drm_crtc *crtc,
381 struct drm_crtc_state *old_crtc_state)
385 static void omap_crtc_atomic_flush(struct drm_crtc *crtc,
386 struct drm_crtc_state *old_crtc_state)
388 struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
390 WARN_ON(omap_crtc->vblank_irq.registered);
392 if (dispc_mgr_is_enabled(omap_crtc->channel)) {
394 DBG("%s: GO", omap_crtc->name);
397 WARN_ON(omap_crtc->pending);
398 omap_crtc->pending = true;
401 dispc_mgr_go(omap_crtc->channel);
402 omap_irq_register(crtc->dev, &omap_crtc->vblank_irq);
406 static int omap_crtc_atomic_set_property(struct drm_crtc *crtc,
407 struct drm_crtc_state *state,
408 struct drm_property *property,
411 struct drm_plane_state *plane_state;
412 struct drm_plane *plane = crtc->primary;
415 * Delegate property set to the primary plane. Get the plane state and
416 * set the property directly.
419 plane_state = drm_atomic_get_plane_state(state->state, plane);
423 return drm_atomic_plane_set_property(plane, plane_state, property, val);
426 static int omap_crtc_atomic_get_property(struct drm_crtc *crtc,
427 const struct drm_crtc_state *state,
428 struct drm_property *property,
432 * Delegate property get to the primary plane. The
433 * drm_atomic_plane_get_property() function isn't exported, but can be
434 * called through drm_object_property_get_value() as that will call
435 * drm_atomic_get_property() for atomic drivers.
437 return drm_object_property_get_value(&crtc->primary->base, property,
441 static const struct drm_crtc_funcs omap_crtc_funcs = {
442 .reset = drm_atomic_helper_crtc_reset,
443 .set_config = drm_atomic_helper_set_config,
444 .destroy = omap_crtc_destroy,
445 .page_flip = drm_atomic_helper_page_flip,
446 .set_property = drm_atomic_helper_crtc_set_property,
447 .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
448 .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
449 .atomic_set_property = omap_crtc_atomic_set_property,
450 .atomic_get_property = omap_crtc_atomic_get_property,
453 static const struct drm_crtc_helper_funcs omap_crtc_helper_funcs = {
454 .mode_fixup = omap_crtc_mode_fixup,
455 .mode_set_nofb = omap_crtc_mode_set_nofb,
456 .disable = omap_crtc_disable,
457 .enable = omap_crtc_enable,
458 .atomic_begin = omap_crtc_atomic_begin,
459 .atomic_flush = omap_crtc_atomic_flush,
462 /* -----------------------------------------------------------------------------
466 static const char *channel_names[] = {
467 [OMAP_DSS_CHANNEL_LCD] = "lcd",
468 [OMAP_DSS_CHANNEL_DIGIT] = "tv",
469 [OMAP_DSS_CHANNEL_LCD2] = "lcd2",
470 [OMAP_DSS_CHANNEL_LCD3] = "lcd3",
473 void omap_crtc_pre_init(void)
475 dss_install_mgr_ops(&mgr_ops);
478 void omap_crtc_pre_uninit(void)
480 dss_uninstall_mgr_ops();
483 /* initialize crtc */
484 struct drm_crtc *omap_crtc_init(struct drm_device *dev,
485 struct drm_plane *plane, enum omap_channel channel, int id)
487 struct drm_crtc *crtc = NULL;
488 struct omap_crtc *omap_crtc;
491 DBG("%s", channel_names[channel]);
493 omap_crtc = kzalloc(sizeof(*omap_crtc), GFP_KERNEL);
497 crtc = &omap_crtc->base;
499 init_waitqueue_head(&omap_crtc->pending_wait);
501 omap_crtc->channel = channel;
502 omap_crtc->name = channel_names[channel];
504 omap_crtc->vblank_irq.irqmask = pipe2vbl(crtc);
505 omap_crtc->vblank_irq.irq = omap_crtc_vblank_irq;
507 omap_crtc->error_irq.irqmask =
508 dispc_mgr_get_sync_lost_irq(channel);
509 omap_crtc->error_irq.irq = omap_crtc_error_irq;
510 omap_irq_register(dev, &omap_crtc->error_irq);
513 omap_crtc->mgr = omap_dss_get_overlay_manager(channel);
515 ret = drm_crtc_init_with_planes(dev, crtc, plane, NULL,
516 &omap_crtc_funcs, NULL);
522 drm_crtc_helper_add(crtc, &omap_crtc_helper_funcs);
524 omap_plane_install_properties(crtc->primary, &crtc->base);
526 omap_crtcs[channel] = omap_crtc;