drivers/gpu/drm/omapdrm/omap_crtc.c

   1 /*
   2  * drivers/gpu/drm/omapdrm/omap_crtc.c
   3  *
   4  * Copyright (C) 2011 Texas Instruments
   5  * Author: Rob Clark <rob@ti.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms of the GNU General Public License version 2 as published by
   9  * the Free Software Foundation.
  10  *
  11  * This program is distributed in the hope that it will be useful, but WITHOUT
  12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  14  * more details.
  15  *
  16  * You should have received a copy of the GNU General Public License along with
  17  * this program.  If not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include <drm/drm_atomic.h>
  21 #include <drm/drm_atomic_helper.h>
  22 #include <drm/drm_crtc.h>
  23 #include <drm/drm_crtc_helper.h>
  24 #include <drm/drm_mode.h>
  25 #include <drm/drm_plane_helper.h>
  26
  27 #include "omap_drv.h"
  28
  29 #define to_omap_crtc(x) container_of(x, struct omap_crtc, base)
  30
  31 struct omap_crtc {
  32         struct drm_crtc base;
  33
  34         const char *name;
  35         enum omap_channel channel;
  36
  37         struct videomode vm;
  38
  39         bool ignore_digit_sync_lost;
  40
  41         bool enabled;
  42         bool pending;
  43         wait_queue_head_t pending_wait;
  44         struct drm_pending_vblank_event *event;
  45 };
  46
  47 /* -----------------------------------------------------------------------------
  48  * Helper Functions
  49  */
  50
  51 struct videomode *omap_crtc_timings(struct drm_crtc *crtc)
  52 {
  53         struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
  54         return &omap_crtc->vm;
  55 }
  56
  57 enum omap_channel omap_crtc_channel(struct drm_crtc *crtc)
  58 {
  59         struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
  60         return omap_crtc->channel;
  61 }
  62
  63 static bool omap_crtc_is_pending(struct drm_crtc *crtc)
  64 {
  65         struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
  66         unsigned long flags;
  67         bool pending;
  68
  69         spin_lock_irqsave(&crtc->dev->event_lock, flags);
  70         pending = omap_crtc->pending;
  71         spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
  72
  73         return pending;
  74 }
  75
  76 int omap_crtc_wait_pending(struct drm_crtc *crtc)
  77 {
  78         struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
  79
  80         /*
  81          * Timeout is set to a "sufficiently" high value, which should cover
  82          * a single frame refresh even on slower displays.
  83          */
  84         return wait_event_timeout(omap_crtc->pending_wait,
  85                                   !omap_crtc_is_pending(crtc),
  86                                   msecs_to_jiffies(250));
  87 }
  88
  89 /* -----------------------------------------------------------------------------
  90  * DSS Manager Functions
  91  */
  92
  93 /*
  94  * Manager-ops, callbacks from output when they need to configure
  95  * the upstream part of the video pipe.
  96  *
  97  * Most of these we can ignore until we add support for command-mode
  98  * panels.. for video-mode the crtc-helpers already do an adequate
  99  * job of sequencing the setup of the video pipe in the proper order
 100  */
 101
 102 /* ovl-mgr-id -> crtc */
 103 static struct omap_crtc *omap_crtcs[8];
 104 static struct omap_dss_device *omap_crtc_output[8];
 105
 106 /* we can probably ignore these until we support command-mode panels: */
 107 static int omap_crtc_dss_connect(enum omap_channel channel,
 108                 struct omap_dss_device *dst)
 109 {
 110         const struct dispc_ops *dispc_ops = dispc_get_ops();
 111
 112         if (omap_crtc_output[channel])
 113                 return -EINVAL;
 114
 115         if ((dispc_ops->mgr_get_supported_outputs(channel) & dst->id) == 0)
 116                 return -EINVAL;
 117
 118         omap_crtc_output[channel] = dst;
 119         dst->dispc_channel_connected = true;
 120
 121         return 0;
 122 }
 123
 124 static void omap_crtc_dss_disconnect(enum omap_channel channel,
 125                 struct omap_dss_device *dst)
 126 {
 127         omap_crtc_output[channel] = NULL;
 128         dst->dispc_channel_connected = false;
 129 }
 130
 131 static void omap_crtc_dss_start_update(enum omap_channel channel)
 132 {
 133 }
 134
 135 /* Called only from the encoder enable/disable and suspend/resume handlers. */
 136 static void omap_crtc_set_enabled(struct drm_crtc *crtc, bool enable)
 137 {
 138         struct drm_device *dev = crtc->dev;
 139         struct omap_drm_private *priv = dev->dev_private;
 140         struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
 141         enum omap_channel channel = omap_crtc->channel;
 142         struct omap_irq_wait *wait;
 143         u32 framedone_irq, vsync_irq;
 144         int ret;
 145
 146         if (WARN_ON(omap_crtc->enabled == enable))
 147                 return;
 148
 149         if (omap_crtc_output[channel]->output_type == OMAP_DISPLAY_TYPE_HDMI) {
 150                 priv->dispc_ops->mgr_enable(channel, enable);
 151                 omap_crtc->enabled = enable;
 152                 return;
 153         }
 154
 155         if (omap_crtc->channel == OMAP_DSS_CHANNEL_DIGIT) {
 156                 /*
 157                  * Digit output produces some sync lost interrupts during the
 158                  * first frame when enabling, so we need to ignore those.
 159                  */
 160                 omap_crtc->ignore_digit_sync_lost = true;
 161         }
 162
 163         framedone_irq = priv->dispc_ops->mgr_get_framedone_irq(channel);
 164         vsync_irq = priv->dispc_ops->mgr_get_vsync_irq(channel);
 165
 166         if (enable) {
 167                 wait = omap_irq_wait_init(dev, vsync_irq, 1);
 168         } else {
 169                 /*
 170                  * When we disable the digit output, we need to wait for
 171                  * FRAMEDONE to know that DISPC has finished with the output.
 172                  *
 173                  * OMAP2/3 does not have FRAMEDONE irq for digit output, and in
 174                  * that case we need to use vsync interrupt, and wait for both
 175                  * even and odd frames.
 176                  */
 177
 178                 if (framedone_irq)
 179                         wait = omap_irq_wait_init(dev, framedone_irq, 1);
 180                 else
 181                         wait = omap_irq_wait_init(dev, vsync_irq, 2);
 182         }
 183
 184         priv->dispc_ops->mgr_enable(channel, enable);
 185         omap_crtc->enabled = enable;
 186
 187         ret = omap_irq_wait(dev, wait, msecs_to_jiffies(100));
 188         if (ret) {
 189                 dev_err(dev->dev, "%s: timeout waiting for %s\n",
 190                                 omap_crtc->name, enable ? "enable" : "disable");
 191         }
 192
 193         if (omap_crtc->channel == OMAP_DSS_CHANNEL_DIGIT) {
 194                 omap_crtc->ignore_digit_sync_lost = false;
 195                 /* make sure the irq handler sees the value above */
 196                 mb();
 197         }
 198 }
 199
 200
 201 static int omap_crtc_dss_enable(enum omap_channel channel)
 202 {
 203         struct omap_crtc *omap_crtc = omap_crtcs[channel];
 204         struct omap_drm_private *priv = omap_crtc->base.dev->dev_private;
 205
 206         priv->dispc_ops->mgr_set_timings(omap_crtc->channel, &omap_crtc->vm);
 207         omap_crtc_set_enabled(&omap_crtc->base, true);
 208
 209         return 0;
 210 }
 211
 212 static void omap_crtc_dss_disable(enum omap_channel channel)
 213 {
 214         struct omap_crtc *omap_crtc = omap_crtcs[channel];
 215
 216         omap_crtc_set_enabled(&omap_crtc->base, false);
 217 }
 218
 219 static void omap_crtc_dss_set_timings(enum omap_channel channel,
 220                 const struct videomode *vm)
 221 {
 222         struct omap_crtc *omap_crtc = omap_crtcs[channel];
 223         DBG("%s", omap_crtc->name);
 224         omap_crtc->vm = *vm;
 225 }
 226
 227 static void omap_crtc_dss_set_lcd_config(enum omap_channel channel,
 228                 const struct dss_lcd_mgr_config *config)
 229 {
 230         struct omap_crtc *omap_crtc = omap_crtcs[channel];
 231         struct omap_drm_private *priv = omap_crtc->base.dev->dev_private;
 232
 233         DBG("%s", omap_crtc->name);
 234         priv->dispc_ops->mgr_set_lcd_config(omap_crtc->channel, config);
 235 }
 236
 237 static int omap_crtc_dss_register_framedone(
 238                 enum omap_channel channel,
 239                 void (*handler)(void *), void *data)
 240 {
 241         return 0;
 242 }
 243
 244 static void omap_crtc_dss_unregister_framedone(
 245                 enum omap_channel channel,
 246                 void (*handler)(void *), void *data)
 247 {
 248 }
 249
 250 static const struct dss_mgr_ops mgr_ops = {
 251         .connect = omap_crtc_dss_connect,
 252         .disconnect = omap_crtc_dss_disconnect,
 253         .start_update = omap_crtc_dss_start_update,
 254         .enable = omap_crtc_dss_enable,
 255         .disable = omap_crtc_dss_disable,
 256         .set_timings = omap_crtc_dss_set_timings,
 257         .set_lcd_config = omap_crtc_dss_set_lcd_config,
 258         .register_framedone_handler = omap_crtc_dss_register_framedone,
 259         .unregister_framedone_handler = omap_crtc_dss_unregister_framedone,
 260 };
 261
 262 /* -----------------------------------------------------------------------------
 263  * Setup, Flush and Page Flip
 264  */
 265
 266 void omap_crtc_error_irq(struct drm_crtc *crtc, uint32_t irqstatus)
 267 {
 268         struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
 269
 270         if (omap_crtc->ignore_digit_sync_lost) {
 271                 irqstatus &= ~DISPC_IRQ_SYNC_LOST_DIGIT;
 272                 if (!irqstatus)
 273                         return;
 274         }
 275
 276         DRM_ERROR_RATELIMITED("%s: errors: %08x\n", omap_crtc->name, irqstatus);
 277 }
 278
 279 void omap_crtc_vblank_irq(struct drm_crtc *crtc)
 280 {
 281         struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
 282         struct drm_device *dev = omap_crtc->base.dev;
 283         struct omap_drm_private *priv = dev->dev_private;
 284         bool pending;
 285
 286         spin_lock(&crtc->dev->event_lock);
 287         /*
 288          * If the dispc is busy we're racing the flush operation. Try again on
 289          * the next vblank interrupt.
 290          */
 291         if (priv->dispc_ops->mgr_go_busy(omap_crtc->channel)) {
 292                 spin_unlock(&crtc->dev->event_lock);
 293                 return;
 294         }
 295
 296         /* Send the vblank event if one has been requested. */
 297         if (omap_crtc->event) {
 298                 drm_crtc_send_vblank_event(crtc, omap_crtc->event);
 299                 omap_crtc->event = NULL;
 300         }
 301
 302         pending = omap_crtc->pending;
 303         omap_crtc->pending = false;
 304         spin_unlock(&crtc->dev->event_lock);
 305
 306         if (pending)
 307                 drm_crtc_vblank_put(crtc);
 308
 309         /* Wake up omap_atomic_complete. */
 310         wake_up(&omap_crtc->pending_wait);
 311
 312         DBG("%s: apply done", omap_crtc->name);
 313 }
 314
 315 static void omap_crtc_write_crtc_properties(struct drm_crtc *crtc)
 316 {
 317         struct omap_drm_private *priv = crtc->dev->dev_private;
 318         struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
 319         struct omap_overlay_manager_info info;
 320
 321         memset(&info, 0, sizeof(info));
 322
 323         info.default_color = 0x000000;
 324         info.trans_enabled = false;
 325         info.partial_alpha_enabled = false;
 326         info.cpr_enable = false;
 327
 328         priv->dispc_ops->mgr_setup(omap_crtc->channel, &info);
 329 }
 330
 331 /* -----------------------------------------------------------------------------
 332  * CRTC Functions
 333  */
 334
 335 static void omap_crtc_destroy(struct drm_crtc *crtc)
 336 {
 337         struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
 338
 339         DBG("%s", omap_crtc->name);
 340
 341         drm_crtc_cleanup(crtc);
 342
 343         kfree(omap_crtc);
 344 }
 345
 346 static void omap_crtc_enable(struct drm_crtc *crtc)
 347 {
 348         struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
 349         int ret;
 350
 351         DBG("%s", omap_crtc->name);
 352
 353         spin_lock_irq(&crtc->dev->event_lock);
 354         drm_crtc_vblank_on(crtc);
 355         ret = drm_crtc_vblank_get(crtc);
 356         WARN_ON(ret != 0);
 357
 358         WARN_ON(omap_crtc->pending);
 359         omap_crtc->pending = true;
 360         spin_unlock_irq(&crtc->dev->event_lock);
 361 }
 362
 363 static void omap_crtc_disable(struct drm_crtc *crtc)
 364 {
 365         struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
 366
 367         DBG("%s", omap_crtc->name);
 368
 369         drm_crtc_vblank_off(crtc);
 370 }
 371
 372 static void omap_crtc_mode_set_nofb(struct drm_crtc *crtc)
 373 {
 374         struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
 375         struct drm_display_mode *mode = &crtc->state->adjusted_mode;
 376         struct omap_drm_private *priv = crtc->dev->dev_private;
 377         const u32 flags_mask = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_DE_LOW |
 378                 DISPLAY_FLAGS_PIXDATA_POSEDGE | DISPLAY_FLAGS_PIXDATA_NEGEDGE |
 379                 DISPLAY_FLAGS_SYNC_POSEDGE | DISPLAY_FLAGS_SYNC_NEGEDGE;
 380         unsigned int i;
 381
 382         DBG("%s: set mode: %d:\"%s\" %d %d %d %d %d %d %d %d %d %d 0x%x 0x%x",
 383             omap_crtc->name, mode->base.id, mode->name,
 384             mode->vrefresh, mode->clock,
 385             mode->hdisplay, mode->hsync_start, mode->hsync_end, mode->htotal,
 386             mode->vdisplay, mode->vsync_start, mode->vsync_end, mode->vtotal,
 387             mode->type, mode->flags);
 388
 389         drm_display_mode_to_videomode(mode, &omap_crtc->vm);
 390
 391         /*
 392          * HACK: This fixes the vm flags.
 393          * struct drm_display_mode does not contain the VSYNC/HSYNC/DE flags
 394          * and they get lost when converting back and forth between
 395          * struct drm_display_mode and struct videomode. The hack below
 396          * goes and fetches the missing flags from the panel drivers.
 397          *
 398          * Correct solution would be to use DRM's bus-flags, but that's not
 399          * easily possible before the omapdrm's panel/encoder driver model
 400          * has been changed to the DRM model.
 401          */
 402
 403         for (i = 0; i < priv->num_encoders; ++i) {
 404                 struct drm_encoder *encoder = priv->encoders[i];
 405
 406                 if (encoder->crtc == crtc) {
 407                         struct omap_dss_device *dssdev;
 408
 409                         dssdev = omap_encoder_get_dssdev(encoder);
 410
 411                         if (dssdev) {
 412                                 struct videomode vm = {0};
 413
 414                                 dssdev->driver->get_timings(dssdev, &vm);
 415
 416                                 omap_crtc->vm.flags |= vm.flags & flags_mask;
 417                         }
 418
 419                         break;
 420                 }
 421         }
 422 }
 423
 424 static int omap_crtc_atomic_check(struct drm_crtc *crtc,
 425                                 struct drm_crtc_state *state)
 426 {
 427         if (state->color_mgmt_changed && state->gamma_lut) {
 428                 uint length = state->gamma_lut->length /
 429                         sizeof(struct drm_color_lut);
 430
 431                 if (length < 2)
 432                         return -EINVAL;
 433         }
 434
 435         return 0;
 436 }
 437
 438 static void omap_crtc_atomic_begin(struct drm_crtc *crtc,
 439                                    struct drm_crtc_state *old_crtc_state)
 440 {
 441 }
 442
 443 static void omap_crtc_atomic_flush(struct drm_crtc *crtc,
 444                                    struct drm_crtc_state *old_crtc_state)
 445 {
 446         struct omap_drm_private *priv = crtc->dev->dev_private;
 447         struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
 448         int ret;
 449
 450         if (crtc->state->color_mgmt_changed) {
 451                 struct drm_color_lut *lut = NULL;
 452                 uint length = 0;
 453
 454                 if (crtc->state->gamma_lut) {
 455                         lut = (struct drm_color_lut *)
 456                                 crtc->state->gamma_lut->data;
 457                         length = crtc->state->gamma_lut->length /
 458                                 sizeof(*lut);
 459                 }
 460                 priv->dispc_ops->mgr_set_gamma(omap_crtc->channel, lut, length);
 461         }
 462
 463         omap_crtc_write_crtc_properties(crtc);
 464
 465         /* Only flush the CRTC if it is currently enabled. */
 466         if (!omap_crtc->enabled)
 467                 return;
 468
 469         DBG("%s: GO", omap_crtc->name);
 470
 471         ret = drm_crtc_vblank_get(crtc);
 472         WARN_ON(ret != 0);
 473
 474         spin_lock_irq(&crtc->dev->event_lock);
 475         priv->dispc_ops->mgr_go(omap_crtc->channel);
 476
 477         WARN_ON(omap_crtc->pending);
 478         omap_crtc->pending = true;
 479
 480         if (crtc->state->event)
 481                 omap_crtc->event = crtc->state->event;
 482         spin_unlock_irq(&crtc->dev->event_lock);
 483 }
 484
 485 static bool omap_crtc_is_plane_prop(struct drm_crtc *crtc,
 486         struct drm_property *property)
 487 {
 488         struct drm_device *dev = crtc->dev;
 489         struct omap_drm_private *priv = dev->dev_private;
 490
 491         return property == priv->zorder_prop ||
 492                 property == crtc->primary->rotation_property;
 493 }
 494
 495 static int omap_crtc_atomic_set_property(struct drm_crtc *crtc,
 496                                          struct drm_crtc_state *state,
 497                                          struct drm_property *property,
 498                                          uint64_t val)
 499 {
 500         if (omap_crtc_is_plane_prop(crtc, property)) {
 501                 struct drm_plane_state *plane_state;
 502                 struct drm_plane *plane = crtc->primary;
 503
 504                 /*
 505                  * Delegate property set to the primary plane. Get the plane
 506                  * state and set the property directly.
 507                  */
 508
 509                 plane_state = drm_atomic_get_plane_state(state->state, plane);
 510                 if (IS_ERR(plane_state))
 511                         return PTR_ERR(plane_state);
 512
 513                 return drm_atomic_plane_set_property(plane, plane_state,
 514                                 property, val);
 515         }
 516
 517         return -EINVAL;
 518 }
 519
 520 static int omap_crtc_atomic_get_property(struct drm_crtc *crtc,
 521                                          const struct drm_crtc_state *state,
 522                                          struct drm_property *property,
 523                                          uint64_t *val)
 524 {
 525         if (omap_crtc_is_plane_prop(crtc, property)) {
 526                 /*
 527                  * Delegate property get to the primary plane. The
 528                  * drm_atomic_plane_get_property() function isn't exported, but
 529                  * can be called through drm_object_property_get_value() as that
 530                  * will call drm_atomic_get_property() for atomic drivers.
 531                  */
 532                 return drm_object_property_get_value(&crtc->primary->base,
 533                                 property, val);
 534         }
 535
 536         return -EINVAL;
 537 }
 538
 539 static const struct drm_crtc_funcs omap_crtc_funcs = {
 540         .reset = drm_atomic_helper_crtc_reset,
 541         .set_config = drm_atomic_helper_set_config,
 542         .destroy = omap_crtc_destroy,
 543         .page_flip = drm_atomic_helper_page_flip,
 544         .gamma_set = drm_atomic_helper_legacy_gamma_set,
 545         .set_property = drm_atomic_helper_crtc_set_property,
 546         .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
 547         .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
 548         .atomic_set_property = omap_crtc_atomic_set_property,
 549         .atomic_get_property = omap_crtc_atomic_get_property,
 550         .enable_vblank = omap_irq_enable_vblank,
 551         .disable_vblank = omap_irq_disable_vblank,
 552 };
 553
 554 static const struct drm_crtc_helper_funcs omap_crtc_helper_funcs = {
 555         .mode_set_nofb = omap_crtc_mode_set_nofb,
 556         .disable = omap_crtc_disable,
 557         .enable = omap_crtc_enable,
 558         .atomic_check = omap_crtc_atomic_check,
 559         .atomic_begin = omap_crtc_atomic_begin,
 560         .atomic_flush = omap_crtc_atomic_flush,
 561 };
 562
 563 /* -----------------------------------------------------------------------------
 564  * Init and Cleanup
 565  */
 566
 567 static const char *channel_names[] = {
 568         [OMAP_DSS_CHANNEL_LCD] = "lcd",
 569         [OMAP_DSS_CHANNEL_DIGIT] = "tv",
 570         [OMAP_DSS_CHANNEL_LCD2] = "lcd2",
 571         [OMAP_DSS_CHANNEL_LCD3] = "lcd3",
 572 };
 573
 574 void omap_crtc_pre_init(void)
 575 {
 576         memset(omap_crtcs, 0, sizeof(omap_crtcs));
 577
 578         dss_install_mgr_ops(&mgr_ops);
 579 }
 580
 581 void omap_crtc_pre_uninit(void)
 582 {
 583         dss_uninstall_mgr_ops();
 584 }
 585
 586 /* initialize crtc */
 587 struct drm_crtc *omap_crtc_init(struct drm_device *dev,
 588                 struct drm_plane *plane, struct omap_dss_device *dssdev)
 589 {
 590         struct omap_drm_private *priv = dev->dev_private;
 591         struct drm_crtc *crtc = NULL;
 592         struct omap_crtc *omap_crtc;
 593         enum omap_channel channel;
 594         struct omap_dss_device *out;
 595         int ret;
 596
 597         out = omapdss_find_output_from_display(dssdev);
 598         channel = out->dispc_channel;
 599         omap_dss_put_device(out);
 600
 601         DBG("%s", channel_names[channel]);
 602
 603         /* Multiple displays on same channel is not allowed */
 604         if (WARN_ON(omap_crtcs[channel] != NULL))
 605                 return ERR_PTR(-EINVAL);
 606
 607         omap_crtc = kzalloc(sizeof(*omap_crtc), GFP_KERNEL);
 608         if (!omap_crtc)
 609                 return ERR_PTR(-ENOMEM);
 610
 611         crtc = &omap_crtc->base;
 612
 613         init_waitqueue_head(&omap_crtc->pending_wait);
 614
 615         omap_crtc->channel = channel;
 616         omap_crtc->name = channel_names[channel];
 617
 618         ret = drm_crtc_init_with_planes(dev, crtc, plane, NULL,
 619                                         &omap_crtc_funcs, NULL);
 620         if (ret < 0) {
 621                 dev_err(dev->dev, "%s(): could not init crtc for: %s\n",
 622                         __func__, dssdev->name);
 623                 kfree(omap_crtc);
 624                 return ERR_PTR(ret);
 625         }
 626
 627         drm_crtc_helper_add(crtc, &omap_crtc_helper_funcs);
 628
 629         /* The dispc API adapts to what ever size, but the HW supports
 630          * 256 element gamma table for LCDs and 1024 element table for
 631          * OMAP_DSS_CHANNEL_DIGIT. X server assumes 256 element gamma
 632          * tables so lets use that. Size of HW gamma table can be
 633          * extracted with dispc_mgr_gamma_size(). If it returns 0
 634          * gamma table is not supprted.
 635          */
 636         if (priv->dispc_ops->mgr_gamma_size(channel)) {
 637                 uint gamma_lut_size = 256;
 638
 639                 drm_crtc_enable_color_mgmt(crtc, 0, false, gamma_lut_size);
 640                 drm_mode_crtc_set_gamma_size(crtc, gamma_lut_size);
 641         }
 642
 643         omap_plane_install_properties(crtc->primary, &crtc->base);
 644
 645         omap_crtcs[channel] = omap_crtc;
 646
 647         return crtc;
 648 }