2 * DMM IOMMU driver support functions for TI OMAP processors.
4 * Author: Rob Clark <rob@ti.com>
5 * Andy Gross <andy.gross@ti.com>
7 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation version 2.
13 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
14 * kind, whether express or implied; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 #include <linux/init.h>
19 #include <linux/module.h>
20 #include <linux/platform_device.h> /* platform_device() */
21 #include <linux/errno.h>
22 #include <linux/sched.h>
23 #include <linux/wait.h>
24 #include <linux/interrupt.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/slab.h>
27 #include <linux/vmalloc.h>
28 #include <linux/delay.h>
30 #include <linux/time.h>
31 #include <linux/list.h>
33 #include "omap_dmm_tiler.h"
34 #include "omap_dmm_priv.h"
36 #define DMM_DRIVER_NAME "dmm"
38 /* mappings for associating views to luts */
39 static struct tcm *containers[TILFMT_NFORMATS];
40 static struct dmm *omap_dmm;
42 /* global spinlock for protecting lists */
43 static DEFINE_SPINLOCK(list_lock);
46 #define GEOM(xshift, yshift, bytes_per_pixel) { \
49 .cpp = (bytes_per_pixel), \
50 .slot_w = 1 << (SLOT_WIDTH_BITS - (xshift)), \
51 .slot_h = 1 << (SLOT_HEIGHT_BITS - (yshift)), \
55 uint32_t x_shft; /* unused X-bits (as part of bpp) */
56 uint32_t y_shft; /* unused Y-bits (as part of bpp) */
57 uint32_t cpp; /* bytes/chars per pixel */
58 uint32_t slot_w; /* width of each slot (in pixels) */
59 uint32_t slot_h; /* height of each slot (in pixels) */
60 } geom[TILFMT_NFORMATS] = {
61 [TILFMT_8BIT] = GEOM(0, 0, 1),
62 [TILFMT_16BIT] = GEOM(0, 1, 2),
63 [TILFMT_32BIT] = GEOM(1, 1, 4),
64 [TILFMT_PAGE] = GEOM(SLOT_WIDTH_BITS, SLOT_HEIGHT_BITS, 1),
68 /* lookup table for registers w/ per-engine instances */
69 static const uint32_t reg[][4] = {
70 [PAT_STATUS] = {DMM_PAT_STATUS__0, DMM_PAT_STATUS__1,
71 DMM_PAT_STATUS__2, DMM_PAT_STATUS__3},
72 [PAT_DESCR] = {DMM_PAT_DESCR__0, DMM_PAT_DESCR__1,
73 DMM_PAT_DESCR__2, DMM_PAT_DESCR__3},
76 /* simple allocator to grab next 16 byte aligned memory from txn */
77 static void *alloc_dma(struct dmm_txn *txn, size_t sz, dma_addr_t *pa)
80 struct refill_engine *engine = txn->engine_handle;
82 /* dmm programming requires 16 byte aligned addresses */
83 txn->current_pa = round_up(txn->current_pa, 16);
84 txn->current_va = (void *)round_up((long)txn->current_va, 16);
86 ptr = txn->current_va;
87 *pa = txn->current_pa;
89 txn->current_pa += sz;
90 txn->current_va += sz;
92 BUG_ON((txn->current_va - engine->refill_va) > REFILL_BUFFER_SIZE);
97 /* check status and spin until wait_mask comes true */
98 static int wait_status(struct refill_engine *engine, uint32_t wait_mask)
100 struct dmm *dmm = engine->dmm;
101 uint32_t r = 0, err, i;
103 i = DMM_FIXED_RETRY_COUNT;
105 r = readl(dmm->base + reg[PAT_STATUS][engine->id]);
106 err = r & DMM_PATSTATUS_ERR;
110 if ((r & wait_mask) == wait_mask)
122 static void release_engine(struct refill_engine *engine)
126 spin_lock_irqsave(&list_lock, flags);
127 list_add(&engine->idle_node, &omap_dmm->idle_head);
128 spin_unlock_irqrestore(&list_lock, flags);
130 atomic_inc(&omap_dmm->engine_counter);
131 wake_up_interruptible(&omap_dmm->engine_queue);
134 static irqreturn_t omap_dmm_irq_handler(int irq, void *arg)
136 struct dmm *dmm = arg;
137 uint32_t status = readl(dmm->base + DMM_PAT_IRQSTATUS);
141 writel(status, dmm->base + DMM_PAT_IRQSTATUS);
143 for (i = 0; i < dmm->num_engines; i++) {
144 if (status & DMM_IRQSTAT_LST) {
145 wake_up_interruptible(&dmm->engines[i].wait_for_refill);
147 if (dmm->engines[i].async)
148 release_engine(&dmm->engines[i]);
158 * Get a handle for a DMM transaction
160 static struct dmm_txn *dmm_txn_init(struct dmm *dmm, struct tcm *tcm)
162 struct dmm_txn *txn = NULL;
163 struct refill_engine *engine = NULL;
168 /* wait until an engine is available */
169 ret = wait_event_interruptible(omap_dmm->engine_queue,
170 atomic_add_unless(&omap_dmm->engine_counter, -1, 0));
174 /* grab an idle engine */
175 spin_lock_irqsave(&list_lock, flags);
176 if (!list_empty(&dmm->idle_head)) {
177 engine = list_entry(dmm->idle_head.next, struct refill_engine,
179 list_del(&engine->idle_node);
181 spin_unlock_irqrestore(&list_lock, flags);
187 txn->engine_handle = engine;
188 txn->last_pat = NULL;
189 txn->current_va = engine->refill_va;
190 txn->current_pa = engine->refill_pa;
196 * Add region to DMM transaction. If pages or pages[i] is NULL, then the
197 * corresponding slot is cleared (ie. dummy_pa is programmed)
199 static void dmm_txn_append(struct dmm_txn *txn, struct pat_area *area,
200 struct page **pages, uint32_t npages, uint32_t roll)
202 dma_addr_t pat_pa = 0;
205 struct refill_engine *engine = txn->engine_handle;
206 int columns = (1 + area->x1 - area->x0);
207 int rows = (1 + area->y1 - area->y0);
208 int i = columns*rows;
210 pat = alloc_dma(txn, sizeof(struct pat), &pat_pa);
213 txn->last_pat->next_pa = (uint32_t)pat_pa;
217 /* adjust Y coordinates based off of container parameters */
218 pat->area.y0 += engine->tcm->y_offset;
219 pat->area.y1 += engine->tcm->y_offset;
221 pat->ctrl = (struct pat_ctrl){
223 .lut_id = engine->tcm->lut_id,
226 data = alloc_dma(txn, 4*i, &pat->data_pa);
232 data[i] = (pages && pages[n]) ?
233 page_to_phys(pages[n]) : engine->dmm->dummy_pa;
242 * Commit the DMM transaction.
244 static int dmm_txn_commit(struct dmm_txn *txn, bool wait)
247 struct refill_engine *engine = txn->engine_handle;
248 struct dmm *dmm = engine->dmm;
250 if (!txn->last_pat) {
251 dev_err(engine->dmm->dev, "need at least one txn\n");
256 txn->last_pat->next_pa = 0;
258 /* write to PAT_DESCR to clear out any pending transaction */
259 writel(0x0, dmm->base + reg[PAT_DESCR][engine->id]);
261 /* wait for engine ready: */
262 ret = wait_status(engine, DMM_PATSTATUS_READY);
268 /* mark whether it is async to denote list management in IRQ handler */
269 engine->async = wait ? false : true;
272 writel(engine->refill_pa,
273 dmm->base + reg[PAT_DESCR][engine->id]);
276 if (wait_event_interruptible_timeout(engine->wait_for_refill,
277 wait_status(engine, DMM_PATSTATUS_READY) == 0,
278 msecs_to_jiffies(1)) <= 0) {
279 dev_err(dmm->dev, "timed out waiting for done\n");
285 /* only place engine back on list if we are done with it */
287 release_engine(engine);
295 static int fill(struct tcm_area *area, struct page **pages,
296 uint32_t npages, uint32_t roll, bool wait)
299 struct tcm_area slice, area_s;
302 txn = dmm_txn_init(omap_dmm, area->tcm);
303 if (IS_ERR_OR_NULL(txn))
306 tcm_for_each_slice(slice, *area, area_s) {
307 struct pat_area p_area = {
308 .x0 = slice.p0.x, .y0 = slice.p0.y,
309 .x1 = slice.p1.x, .y1 = slice.p1.y,
312 dmm_txn_append(txn, &p_area, pages, npages, roll);
314 roll += tcm_sizeof(slice);
317 ret = dmm_txn_commit(txn, wait);
326 /* note: slots for which pages[i] == NULL are filled w/ dummy page
328 int tiler_pin(struct tiler_block *block, struct page **pages,
329 uint32_t npages, uint32_t roll, bool wait)
333 ret = fill(&block->area, pages, npages, roll, wait);
341 int tiler_unpin(struct tiler_block *block)
343 return fill(&block->area, NULL, 0, 0, false);
349 struct tiler_block *tiler_reserve_2d(enum tiler_fmt fmt, uint16_t w,
350 uint16_t h, uint16_t align)
352 struct tiler_block *block = kzalloc(sizeof(*block), GFP_KERNEL);
357 BUG_ON(!validfmt(fmt));
359 /* convert width/height to slots */
360 w = DIV_ROUND_UP(w, geom[fmt].slot_w);
361 h = DIV_ROUND_UP(h, geom[fmt].slot_h);
363 /* convert alignment to slots */
364 min_align = max(min_align, (geom[fmt].slot_w * geom[fmt].cpp));
365 align = ALIGN(align, min_align);
366 align /= geom[fmt].slot_w * geom[fmt].cpp;
370 ret = tcm_reserve_2d(containers[fmt], w, h, align, &block->area);
373 return ERR_PTR(-ENOMEM);
376 /* add to allocation list */
377 spin_lock_irqsave(&list_lock, flags);
378 list_add(&block->alloc_node, &omap_dmm->alloc_head);
379 spin_unlock_irqrestore(&list_lock, flags);
384 struct tiler_block *tiler_reserve_1d(size_t size)
386 struct tiler_block *block = kzalloc(sizeof(*block), GFP_KERNEL);
387 int num_pages = (size + PAGE_SIZE - 1) >> PAGE_SHIFT;
391 return ERR_PTR(-ENOMEM);
393 block->fmt = TILFMT_PAGE;
395 if (tcm_reserve_1d(containers[TILFMT_PAGE], num_pages,
398 return ERR_PTR(-ENOMEM);
401 spin_lock_irqsave(&list_lock, flags);
402 list_add(&block->alloc_node, &omap_dmm->alloc_head);
403 spin_unlock_irqrestore(&list_lock, flags);
408 /* note: if you have pin'd pages, you should have already unpin'd first! */
409 int tiler_release(struct tiler_block *block)
411 int ret = tcm_free(&block->area);
415 dev_err(omap_dmm->dev, "failed to release block\n");
417 spin_lock_irqsave(&list_lock, flags);
418 list_del(&block->alloc_node);
419 spin_unlock_irqrestore(&list_lock, flags);
429 /* calculate the tiler space address of a pixel in a view orientation...
430 * below description copied from the display subsystem section of TRM:
432 * When the TILER is addressed, the bits:
433 * [28:27] = 0x0 for 8-bit tiled
434 * 0x1 for 16-bit tiled
435 * 0x2 for 32-bit tiled
437 * [31:29] = 0x0 for 0-degree view
438 * 0x1 for 180-degree view + mirroring
439 * 0x2 for 0-degree view + mirroring
440 * 0x3 for 180-degree view
441 * 0x4 for 270-degree view + mirroring
442 * 0x5 for 270-degree view
443 * 0x6 for 90-degree view
444 * 0x7 for 90-degree view + mirroring
445 * Otherwise the bits indicated the corresponding bit address to access
448 static u32 tiler_get_address(enum tiler_fmt fmt, u32 orient, u32 x, u32 y)
450 u32 x_bits, y_bits, tmp, x_mask, y_mask, alignment;
452 x_bits = CONT_WIDTH_BITS - geom[fmt].x_shft;
453 y_bits = CONT_HEIGHT_BITS - geom[fmt].y_shft;
454 alignment = geom[fmt].x_shft + geom[fmt].y_shft;
456 /* validate coordinate */
457 x_mask = MASK(x_bits);
458 y_mask = MASK(y_bits);
460 if (x < 0 || x > x_mask || y < 0 || y > y_mask) {
461 DBG("invalid coords: %u < 0 || %u > %u || %u < 0 || %u > %u",
462 x, x, x_mask, y, y, y_mask);
466 /* account for mirroring */
467 if (orient & MASK_X_INVERT)
469 if (orient & MASK_Y_INVERT)
472 /* get coordinate address */
473 if (orient & MASK_XY_FLIP)
474 tmp = ((x << y_bits) + y);
476 tmp = ((y << x_bits) + x);
478 return TIL_ADDR((tmp << alignment), orient, fmt);
481 dma_addr_t tiler_ssptr(struct tiler_block *block)
483 BUG_ON(!validfmt(block->fmt));
485 return TILVIEW_8BIT + tiler_get_address(block->fmt, 0,
486 block->area.p0.x * geom[block->fmt].slot_w,
487 block->area.p0.y * geom[block->fmt].slot_h);
490 dma_addr_t tiler_tsptr(struct tiler_block *block, uint32_t orient,
491 uint32_t x, uint32_t y)
493 struct tcm_pt *p = &block->area.p0;
494 BUG_ON(!validfmt(block->fmt));
496 return tiler_get_address(block->fmt, orient,
497 (p->x * geom[block->fmt].slot_w) + x,
498 (p->y * geom[block->fmt].slot_h) + y);
501 void tiler_align(enum tiler_fmt fmt, uint16_t *w, uint16_t *h)
503 BUG_ON(!validfmt(fmt));
504 *w = round_up(*w, geom[fmt].slot_w);
505 *h = round_up(*h, geom[fmt].slot_h);
508 uint32_t tiler_stride(enum tiler_fmt fmt, uint32_t orient)
510 BUG_ON(!validfmt(fmt));
512 if (orient & MASK_XY_FLIP)
513 return 1 << (CONT_HEIGHT_BITS + geom[fmt].x_shft);
515 return 1 << (CONT_WIDTH_BITS + geom[fmt].y_shft);
518 size_t tiler_size(enum tiler_fmt fmt, uint16_t w, uint16_t h)
520 tiler_align(fmt, &w, &h);
521 return geom[fmt].cpp * w * h;
524 size_t tiler_vsize(enum tiler_fmt fmt, uint16_t w, uint16_t h)
526 BUG_ON(!validfmt(fmt));
527 return round_up(geom[fmt].cpp * w, PAGE_SIZE) * h;
530 bool dmm_is_available(void)
532 return omap_dmm ? true : false;
535 static int omap_dmm_remove(struct platform_device *dev)
537 struct tiler_block *block, *_block;
542 /* free all area regions */
543 spin_lock_irqsave(&list_lock, flags);
544 list_for_each_entry_safe(block, _block, &omap_dmm->alloc_head,
546 list_del(&block->alloc_node);
549 spin_unlock_irqrestore(&list_lock, flags);
551 for (i = 0; i < omap_dmm->num_lut; i++)
552 if (omap_dmm->tcm && omap_dmm->tcm[i])
553 omap_dmm->tcm[i]->deinit(omap_dmm->tcm[i]);
554 kfree(omap_dmm->tcm);
556 kfree(omap_dmm->engines);
557 if (omap_dmm->refill_va)
558 dma_free_writecombine(omap_dmm->dev,
559 REFILL_BUFFER_SIZE * omap_dmm->num_engines,
561 omap_dmm->refill_pa);
562 if (omap_dmm->dummy_page)
563 __free_page(omap_dmm->dummy_page);
565 if (omap_dmm->irq > 0)
566 free_irq(omap_dmm->irq, omap_dmm);
568 iounmap(omap_dmm->base);
576 static int omap_dmm_probe(struct platform_device *dev)
578 int ret = -EFAULT, i;
579 struct tcm_area area = {0};
580 u32 hwinfo, pat_geom;
581 struct resource *mem;
583 omap_dmm = kzalloc(sizeof(*omap_dmm), GFP_KERNEL);
585 dev_err(&dev->dev, "failed to allocate driver data section\n");
589 /* initialize lists */
590 INIT_LIST_HEAD(&omap_dmm->alloc_head);
591 INIT_LIST_HEAD(&omap_dmm->idle_head);
593 init_waitqueue_head(&omap_dmm->engine_queue);
595 /* lookup hwmod data - base address and irq */
596 mem = platform_get_resource(dev, IORESOURCE_MEM, 0);
598 dev_err(&dev->dev, "failed to get base address resource\n");
602 omap_dmm->base = ioremap(mem->start, SZ_2K);
604 if (!omap_dmm->base) {
605 dev_err(&dev->dev, "failed to get dmm base address\n");
609 omap_dmm->irq = platform_get_irq(dev, 0);
610 if (omap_dmm->irq < 0) {
611 dev_err(&dev->dev, "failed to get IRQ resource\n");
615 omap_dmm->dev = &dev->dev;
617 hwinfo = readl(omap_dmm->base + DMM_PAT_HWINFO);
618 omap_dmm->num_engines = (hwinfo >> 24) & 0x1F;
619 omap_dmm->num_lut = (hwinfo >> 16) & 0x1F;
620 omap_dmm->container_width = 256;
621 omap_dmm->container_height = 128;
623 atomic_set(&omap_dmm->engine_counter, omap_dmm->num_engines);
625 /* read out actual LUT width and height */
626 pat_geom = readl(omap_dmm->base + DMM_PAT_GEOMETRY);
627 omap_dmm->lut_width = ((pat_geom >> 16) & 0xF) << 5;
628 omap_dmm->lut_height = ((pat_geom >> 24) & 0xF) << 5;
630 /* increment LUT by one if on OMAP5 */
631 /* LUT has twice the height, and is split into a separate container */
632 if (omap_dmm->lut_height != omap_dmm->container_height)
635 /* initialize DMM registers */
636 writel(0x88888888, omap_dmm->base + DMM_PAT_VIEW__0);
637 writel(0x88888888, omap_dmm->base + DMM_PAT_VIEW__1);
638 writel(0x80808080, omap_dmm->base + DMM_PAT_VIEW_MAP__0);
639 writel(0x80000000, omap_dmm->base + DMM_PAT_VIEW_MAP_BASE);
640 writel(0x88888888, omap_dmm->base + DMM_TILER_OR__0);
641 writel(0x88888888, omap_dmm->base + DMM_TILER_OR__1);
643 ret = request_irq(omap_dmm->irq, omap_dmm_irq_handler, IRQF_SHARED,
644 "omap_dmm_irq_handler", omap_dmm);
647 dev_err(&dev->dev, "couldn't register IRQ %d, error %d\n",
653 /* Enable all interrupts for each refill engine except
654 * ERR_LUT_MISS<n> (which is just advisory, and we don't care
655 * about because we want to be able to refill live scanout
656 * buffers for accelerated pan/scroll) and FILL_DSC<n> which
657 * we just generally don't care about.
659 writel(0x7e7e7e7e, omap_dmm->base + DMM_PAT_IRQENABLE_SET);
661 omap_dmm->dummy_page = alloc_page(GFP_KERNEL | __GFP_DMA32);
662 if (!omap_dmm->dummy_page) {
663 dev_err(&dev->dev, "could not allocate dummy page\n");
668 /* set dma mask for device */
669 /* NOTE: this is a workaround for the hwmod not initializing properly */
670 dev->dev.coherent_dma_mask = DMA_BIT_MASK(32);
672 omap_dmm->dummy_pa = page_to_phys(omap_dmm->dummy_page);
674 /* alloc refill memory */
675 omap_dmm->refill_va = dma_alloc_writecombine(&dev->dev,
676 REFILL_BUFFER_SIZE * omap_dmm->num_engines,
677 &omap_dmm->refill_pa, GFP_KERNEL);
678 if (!omap_dmm->refill_va) {
679 dev_err(&dev->dev, "could not allocate refill memory\n");
684 omap_dmm->engines = kzalloc(
685 omap_dmm->num_engines * sizeof(struct refill_engine),
687 if (!omap_dmm->engines) {
688 dev_err(&dev->dev, "could not allocate engines\n");
693 for (i = 0; i < omap_dmm->num_engines; i++) {
694 omap_dmm->engines[i].id = i;
695 omap_dmm->engines[i].dmm = omap_dmm;
696 omap_dmm->engines[i].refill_va = omap_dmm->refill_va +
697 (REFILL_BUFFER_SIZE * i);
698 omap_dmm->engines[i].refill_pa = omap_dmm->refill_pa +
699 (REFILL_BUFFER_SIZE * i);
700 init_waitqueue_head(&omap_dmm->engines[i].wait_for_refill);
702 list_add(&omap_dmm->engines[i].idle_node, &omap_dmm->idle_head);
705 omap_dmm->tcm = kzalloc(omap_dmm->num_lut * sizeof(*omap_dmm->tcm),
707 if (!omap_dmm->tcm) {
708 dev_err(&dev->dev, "failed to allocate lut ptrs\n");
713 /* init containers */
714 /* Each LUT is associated with a TCM (container manager). We use the
715 lut_id to denote the lut_id used to identify the correct LUT for
716 programming during reill operations */
717 for (i = 0; i < omap_dmm->num_lut; i++) {
718 omap_dmm->tcm[i] = sita_init(omap_dmm->container_width,
719 omap_dmm->container_height,
722 if (!omap_dmm->tcm[i]) {
723 dev_err(&dev->dev, "failed to allocate container\n");
728 omap_dmm->tcm[i]->lut_id = i;
731 /* assign access mode containers to applicable tcm container */
732 /* OMAP 4 has 1 container for all 4 views */
733 /* OMAP 5 has 2 containers, 1 for 2D and 1 for 1D */
734 containers[TILFMT_8BIT] = omap_dmm->tcm[0];
735 containers[TILFMT_16BIT] = omap_dmm->tcm[0];
736 containers[TILFMT_32BIT] = omap_dmm->tcm[0];
738 if (omap_dmm->container_height != omap_dmm->lut_height) {
739 /* second LUT is used for PAGE mode. Programming must use
740 y offset that is added to all y coordinates. LUT id is still
741 0, because it is the same LUT, just the upper 128 lines */
742 containers[TILFMT_PAGE] = omap_dmm->tcm[1];
743 omap_dmm->tcm[1]->y_offset = OMAP5_LUT_OFFSET;
744 omap_dmm->tcm[1]->lut_id = 0;
746 containers[TILFMT_PAGE] = omap_dmm->tcm[0];
749 area = (struct tcm_area) {
751 .p1.x = omap_dmm->container_width - 1,
752 .p1.y = omap_dmm->container_height - 1,
755 /* initialize all LUTs to dummy page entries */
756 for (i = 0; i < omap_dmm->num_lut; i++) {
757 area.tcm = omap_dmm->tcm[i];
758 if (fill(&area, NULL, 0, 0, true))
759 dev_err(omap_dmm->dev, "refill failed");
762 dev_info(omap_dmm->dev, "initialized all PAT entries\n");
767 if (omap_dmm_remove(dev))
768 dev_err(&dev->dev, "cleanup failed\n");
776 #ifdef CONFIG_DEBUG_FS
778 static const char *alphabet = "abcdefghijklmnopqrstuvwxyz"
779 "ABCDEFGHIJKLMNOPQRSTUVWXYZ0123456789";
780 static const char *special = ".,:;'\"`~!^-+";
782 static void fill_map(char **map, int xdiv, int ydiv, struct tcm_area *a,
786 for (y = a->p0.y / ydiv; y <= a->p1.y / ydiv; y++)
787 for (x = a->p0.x / xdiv; x <= a->p1.x / xdiv; x++)
788 if (map[y][x] == ' ' || ovw)
792 static void fill_map_pt(char **map, int xdiv, int ydiv, struct tcm_pt *p,
795 map[p->y / ydiv][p->x / xdiv] = c;
798 static char read_map_pt(char **map, int xdiv, int ydiv, struct tcm_pt *p)
800 return map[p->y / ydiv][p->x / xdiv];
803 static int map_width(int xdiv, int x0, int x1)
805 return (x1 / xdiv) - (x0 / xdiv) + 1;
808 static void text_map(char **map, int xdiv, char *nice, int yd, int x0, int x1)
810 char *p = map[yd] + (x0 / xdiv);
811 int w = (map_width(xdiv, x0, x1) - strlen(nice)) / 2;
819 static void map_1d_info(char **map, int xdiv, int ydiv, char *nice,
822 sprintf(nice, "%dK", tcm_sizeof(*a) * 4);
823 if (a->p0.y + 1 < a->p1.y) {
824 text_map(map, xdiv, nice, (a->p0.y + a->p1.y) / 2 / ydiv, 0,
826 } else if (a->p0.y < a->p1.y) {
827 if (strlen(nice) < map_width(xdiv, a->p0.x, 256 - 1))
828 text_map(map, xdiv, nice, a->p0.y / ydiv,
829 a->p0.x + xdiv, 256 - 1);
830 else if (strlen(nice) < map_width(xdiv, 0, a->p1.x))
831 text_map(map, xdiv, nice, a->p1.y / ydiv,
833 } else if (strlen(nice) + 1 < map_width(xdiv, a->p0.x, a->p1.x)) {
834 text_map(map, xdiv, nice, a->p0.y / ydiv, a->p0.x, a->p1.x);
838 static void map_2d_info(char **map, int xdiv, int ydiv, char *nice,
841 sprintf(nice, "(%d*%d)", tcm_awidth(*a), tcm_aheight(*a));
842 if (strlen(nice) + 1 < map_width(xdiv, a->p0.x, a->p1.x))
843 text_map(map, xdiv, nice, (a->p0.y + a->p1.y) / 2 / ydiv,
847 int tiler_map_show(struct seq_file *s, void *arg)
849 int xdiv = 2, ydiv = 1;
850 char **map = NULL, *global_map;
851 struct tiler_block *block;
852 struct tcm_area a, p;
854 const char *m2d = alphabet;
855 const char *a2d = special;
856 const char *m2dp = m2d, *a2dp = a2d;
865 /* early return if dmm/tiler device is not initialized */
869 h_adj = omap_dmm->container_height / ydiv;
870 w_adj = omap_dmm->container_width / xdiv;
872 map = kmalloc(h_adj * sizeof(*map), GFP_KERNEL);
873 global_map = kmalloc((w_adj + 1) * h_adj, GFP_KERNEL);
875 if (!map || !global_map)
878 for (lut_idx = 0; lut_idx < omap_dmm->num_lut; lut_idx++) {
879 memset(map, 0, sizeof(h_adj * sizeof(*map)));
880 memset(global_map, ' ', (w_adj + 1) * h_adj);
882 for (i = 0; i < omap_dmm->container_height; i++) {
883 map[i] = global_map + i * (w_adj + 1);
887 spin_lock_irqsave(&list_lock, flags);
889 list_for_each_entry(block, &omap_dmm->alloc_head, alloc_node) {
890 if (block->area.tcm == omap_dmm->tcm[lut_idx]) {
891 if (block->fmt != TILFMT_PAGE) {
892 fill_map(map, xdiv, ydiv, &block->area,
898 map_2d_info(map, xdiv, ydiv, nice,
901 bool start = read_map_pt(map, xdiv,
902 ydiv, &block->area.p0) == ' ';
903 bool end = read_map_pt(map, xdiv, ydiv,
904 &block->area.p1) == ' ';
906 tcm_for_each_slice(a, block->area, p)
907 fill_map(map, xdiv, ydiv, &a,
909 fill_map_pt(map, xdiv, ydiv,
912 fill_map_pt(map, xdiv, ydiv,
915 map_1d_info(map, xdiv, ydiv, nice,
921 spin_unlock_irqrestore(&list_lock, flags);
924 seq_printf(s, "CONTAINER %d DUMP BEGIN\n", lut_idx);
925 for (i = 0; i < 128; i++)
926 seq_printf(s, "%03d:%s\n", i, map[i]);
927 seq_printf(s, "CONTAINER %d DUMP END\n", lut_idx);
929 dev_dbg(omap_dmm->dev, "CONTAINER %d DUMP BEGIN\n",
931 for (i = 0; i < 128; i++)
932 dev_dbg(omap_dmm->dev, "%03d:%s\n", i, map[i]);
933 dev_dbg(omap_dmm->dev, "CONTAINER %d DUMP END\n",
947 static int omap_dmm_resume(struct device *dev)
949 struct tcm_area area;
955 area = (struct tcm_area) {
957 .p1.x = omap_dmm->container_width - 1,
958 .p1.y = omap_dmm->container_height - 1,
961 /* initialize all LUTs to dummy page entries */
962 for (i = 0; i < omap_dmm->num_lut; i++) {
963 area.tcm = omap_dmm->tcm[i];
964 if (fill(&area, NULL, 0, 0, true))
965 dev_err(dev, "refill failed");
971 static const struct dev_pm_ops omap_dmm_pm_ops = {
972 .resume = omap_dmm_resume,
976 struct platform_driver omap_dmm_driver = {
977 .probe = omap_dmm_probe,
978 .remove = omap_dmm_remove,
980 .owner = THIS_MODULE,
981 .name = DMM_DRIVER_NAME,
983 .pm = &omap_dmm_pm_ops,
988 MODULE_LICENSE("GPL v2");
989 MODULE_AUTHOR("Andy Gross <andy.gross@ti.com>");
990 MODULE_DESCRIPTION("OMAP DMM/Tiler Driver");
991 MODULE_ALIAS("platform:" DMM_DRIVER_NAME);