2 * Copyright (C) 2013, NVIDIA Corporation. All rights reserved.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sub license,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the
12 * next paragraph) shall be included in all copies or substantial portions
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 #include <linux/backlight.h>
25 #include <linux/gpio/consumer.h>
26 #include <linux/module.h>
27 #include <linux/of_platform.h>
28 #include <linux/platform_device.h>
29 #include <linux/regulator/consumer.h>
32 #include <drm/drm_crtc.h>
33 #include <drm/drm_mipi_dsi.h>
34 #include <drm/drm_panel.h>
36 #include <video/display_timing.h>
37 #include <video/videomode.h>
40 const struct drm_display_mode *modes;
41 unsigned int num_modes;
42 const struct display_timing *timings;
43 unsigned int num_timings;
48 * @width: width (in millimeters) of the panel's active display area
49 * @height: height (in millimeters) of the panel's active display area
57 * @prepare: the time (in milliseconds) that it takes for the panel to
58 * become ready and start receiving video data
59 * @enable: the time (in milliseconds) that it takes for the panel to
60 * display the first valid frame after starting to receive
62 * @disable: the time (in milliseconds) that it takes for the panel to
63 * turn the display off (no content is visible)
64 * @unprepare: the time (in milliseconds) that it takes for the panel
65 * to power itself down completely
71 unsigned int unprepare;
79 struct drm_panel base;
83 const struct panel_desc *desc;
85 struct backlight_device *backlight;
86 struct regulator *supply;
87 struct i2c_adapter *ddc;
89 struct gpio_desc *enable_gpio;
92 static inline struct panel_simple *to_panel_simple(struct drm_panel *panel)
94 return container_of(panel, struct panel_simple, base);
97 static int panel_simple_get_fixed_modes(struct panel_simple *panel)
99 struct drm_connector *connector = panel->base.connector;
100 struct drm_device *drm = panel->base.drm;
101 struct drm_display_mode *mode;
102 unsigned int i, num = 0;
107 for (i = 0; i < panel->desc->num_timings; i++) {
108 const struct display_timing *dt = &panel->desc->timings[i];
111 videomode_from_timing(dt, &vm);
112 mode = drm_mode_create(drm);
114 dev_err(drm->dev, "failed to add mode %ux%u\n",
115 dt->hactive.typ, dt->vactive.typ);
119 drm_display_mode_from_videomode(&vm, mode);
121 mode->type |= DRM_MODE_TYPE_DRIVER;
123 if (panel->desc->num_timings == 1)
124 mode->type |= DRM_MODE_TYPE_PREFERRED;
126 drm_mode_probed_add(connector, mode);
130 for (i = 0; i < panel->desc->num_modes; i++) {
131 const struct drm_display_mode *m = &panel->desc->modes[i];
133 mode = drm_mode_duplicate(drm, m);
135 dev_err(drm->dev, "failed to add mode %ux%u@%u\n",
136 m->hdisplay, m->vdisplay, m->vrefresh);
140 mode->type |= DRM_MODE_TYPE_DRIVER;
142 if (panel->desc->num_modes == 1)
143 mode->type |= DRM_MODE_TYPE_PREFERRED;
145 drm_mode_set_name(mode);
147 drm_mode_probed_add(connector, mode);
151 connector->display_info.bpc = panel->desc->bpc;
152 connector->display_info.width_mm = panel->desc->size.width;
153 connector->display_info.height_mm = panel->desc->size.height;
154 if (panel->desc->bus_format)
155 drm_display_info_set_bus_formats(&connector->display_info,
156 &panel->desc->bus_format, 1);
157 connector->display_info.bus_flags = panel->desc->bus_flags;
162 static int panel_simple_disable(struct drm_panel *panel)
164 struct panel_simple *p = to_panel_simple(panel);
170 p->backlight->props.power = FB_BLANK_POWERDOWN;
171 p->backlight->props.state |= BL_CORE_FBBLANK;
172 backlight_update_status(p->backlight);
175 if (p->desc->delay.disable)
176 msleep(p->desc->delay.disable);
183 static int panel_simple_unprepare(struct drm_panel *panel)
185 struct panel_simple *p = to_panel_simple(panel);
191 gpiod_set_value_cansleep(p->enable_gpio, 0);
193 regulator_disable(p->supply);
195 if (p->desc->delay.unprepare)
196 msleep(p->desc->delay.unprepare);
203 static int panel_simple_prepare(struct drm_panel *panel)
205 struct panel_simple *p = to_panel_simple(panel);
211 err = regulator_enable(p->supply);
213 dev_err(panel->dev, "failed to enable supply: %d\n", err);
218 gpiod_set_value_cansleep(p->enable_gpio, 1);
220 if (p->desc->delay.prepare)
221 msleep(p->desc->delay.prepare);
228 static int panel_simple_enable(struct drm_panel *panel)
230 struct panel_simple *p = to_panel_simple(panel);
235 if (p->desc->delay.enable)
236 msleep(p->desc->delay.enable);
239 p->backlight->props.state &= ~BL_CORE_FBBLANK;
240 p->backlight->props.power = FB_BLANK_UNBLANK;
241 backlight_update_status(p->backlight);
249 static int panel_simple_get_modes(struct drm_panel *panel)
251 struct panel_simple *p = to_panel_simple(panel);
254 /* probe EDID if a DDC bus is available */
256 struct edid *edid = drm_get_edid(panel->connector, p->ddc);
257 drm_mode_connector_update_edid_property(panel->connector, edid);
259 num += drm_add_edid_modes(panel->connector, edid);
264 /* add hard-coded panel modes */
265 num += panel_simple_get_fixed_modes(p);
270 static int panel_simple_get_timings(struct drm_panel *panel,
271 unsigned int num_timings,
272 struct display_timing *timings)
274 struct panel_simple *p = to_panel_simple(panel);
277 if (p->desc->num_timings < num_timings)
278 num_timings = p->desc->num_timings;
281 for (i = 0; i < num_timings; i++)
282 timings[i] = p->desc->timings[i];
284 return p->desc->num_timings;
287 static const struct drm_panel_funcs panel_simple_funcs = {
288 .disable = panel_simple_disable,
289 .unprepare = panel_simple_unprepare,
290 .prepare = panel_simple_prepare,
291 .enable = panel_simple_enable,
292 .get_modes = panel_simple_get_modes,
293 .get_timings = panel_simple_get_timings,
296 static int panel_simple_probe(struct device *dev, const struct panel_desc *desc)
298 struct device_node *backlight, *ddc;
299 struct panel_simple *panel;
302 panel = devm_kzalloc(dev, sizeof(*panel), GFP_KERNEL);
306 panel->enabled = false;
307 panel->prepared = false;
310 panel->supply = devm_regulator_get(dev, "power");
311 if (IS_ERR(panel->supply))
312 return PTR_ERR(panel->supply);
314 panel->enable_gpio = devm_gpiod_get_optional(dev, "enable",
316 if (IS_ERR(panel->enable_gpio)) {
317 err = PTR_ERR(panel->enable_gpio);
318 dev_err(dev, "failed to request GPIO: %d\n", err);
322 backlight = of_parse_phandle(dev->of_node, "backlight", 0);
324 panel->backlight = of_find_backlight_by_node(backlight);
325 of_node_put(backlight);
327 if (!panel->backlight)
328 return -EPROBE_DEFER;
331 ddc = of_parse_phandle(dev->of_node, "ddc-i2c-bus", 0);
333 panel->ddc = of_find_i2c_adapter_by_node(ddc);
342 drm_panel_init(&panel->base);
343 panel->base.dev = dev;
344 panel->base.funcs = &panel_simple_funcs;
346 err = drm_panel_add(&panel->base);
350 dev_set_drvdata(dev, panel);
356 put_device(&panel->ddc->dev);
358 if (panel->backlight)
359 put_device(&panel->backlight->dev);
364 static int panel_simple_remove(struct device *dev)
366 struct panel_simple *panel = dev_get_drvdata(dev);
368 drm_panel_detach(&panel->base);
369 drm_panel_remove(&panel->base);
371 panel_simple_disable(&panel->base);
374 put_device(&panel->ddc->dev);
376 if (panel->backlight)
377 put_device(&panel->backlight->dev);
382 static void panel_simple_shutdown(struct device *dev)
384 struct panel_simple *panel = dev_get_drvdata(dev);
386 panel_simple_disable(&panel->base);
389 static const struct drm_display_mode ampire_am_480272h3tmqw_t01h_mode = {
392 .hsync_start = 480 + 2,
393 .hsync_end = 480 + 2 + 41,
394 .htotal = 480 + 2 + 41 + 2,
396 .vsync_start = 272 + 2,
397 .vsync_end = 272 + 2 + 10,
398 .vtotal = 272 + 2 + 10 + 2,
400 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
403 static const struct panel_desc ampire_am_480272h3tmqw_t01h = {
404 .modes = &ire_am_480272h3tmqw_t01h_mode,
411 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
414 static const struct drm_display_mode ampire_am800480r3tmqwa1h_mode = {
417 .hsync_start = 800 + 0,
418 .hsync_end = 800 + 0 + 255,
419 .htotal = 800 + 0 + 255 + 0,
421 .vsync_start = 480 + 2,
422 .vsync_end = 480 + 2 + 45,
423 .vtotal = 480 + 2 + 45 + 0,
425 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
428 static const struct panel_desc ampire_am800480r3tmqwa1h = {
429 .modes = &ire_am800480r3tmqwa1h_mode,
436 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
439 static const struct drm_display_mode auo_b101aw03_mode = {
442 .hsync_start = 1024 + 156,
443 .hsync_end = 1024 + 156 + 8,
444 .htotal = 1024 + 156 + 8 + 156,
446 .vsync_start = 600 + 16,
447 .vsync_end = 600 + 16 + 6,
448 .vtotal = 600 + 16 + 6 + 16,
452 static const struct panel_desc auo_b101aw03 = {
453 .modes = &auo_b101aw03_mode,
462 static const struct drm_display_mode auo_b101ean01_mode = {
465 .hsync_start = 1280 + 119,
466 .hsync_end = 1280 + 119 + 32,
467 .htotal = 1280 + 119 + 32 + 21,
469 .vsync_start = 800 + 4,
470 .vsync_end = 800 + 4 + 20,
471 .vtotal = 800 + 4 + 20 + 8,
475 static const struct panel_desc auo_b101ean01 = {
476 .modes = &auo_b101ean01_mode,
485 static const struct drm_display_mode auo_b101xtn01_mode = {
488 .hsync_start = 1366 + 20,
489 .hsync_end = 1366 + 20 + 70,
490 .htotal = 1366 + 20 + 70,
492 .vsync_start = 768 + 14,
493 .vsync_end = 768 + 14 + 42,
494 .vtotal = 768 + 14 + 42,
496 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
499 static const struct panel_desc auo_b101xtn01 = {
500 .modes = &auo_b101xtn01_mode,
509 static const struct drm_display_mode auo_b116xw03_mode = {
512 .hsync_start = 1366 + 40,
513 .hsync_end = 1366 + 40 + 40,
514 .htotal = 1366 + 40 + 40 + 32,
516 .vsync_start = 768 + 10,
517 .vsync_end = 768 + 10 + 12,
518 .vtotal = 768 + 10 + 12 + 6,
522 static const struct panel_desc auo_b116xw03 = {
523 .modes = &auo_b116xw03_mode,
532 static const struct drm_display_mode auo_b133xtn01_mode = {
535 .hsync_start = 1366 + 48,
536 .hsync_end = 1366 + 48 + 32,
537 .htotal = 1366 + 48 + 32 + 20,
539 .vsync_start = 768 + 3,
540 .vsync_end = 768 + 3 + 6,
541 .vtotal = 768 + 3 + 6 + 13,
545 static const struct panel_desc auo_b133xtn01 = {
546 .modes = &auo_b133xtn01_mode,
555 static const struct drm_display_mode auo_b133htn01_mode = {
558 .hsync_start = 1920 + 172,
559 .hsync_end = 1920 + 172 + 80,
560 .htotal = 1920 + 172 + 80 + 60,
562 .vsync_start = 1080 + 25,
563 .vsync_end = 1080 + 25 + 10,
564 .vtotal = 1080 + 25 + 10 + 10,
568 static const struct panel_desc auo_b133htn01 = {
569 .modes = &auo_b133htn01_mode,
583 static const struct display_timing auo_g133han01_timings = {
584 .pixelclock = { 134000000, 141200000, 149000000 },
585 .hactive = { 1920, 1920, 1920 },
586 .hfront_porch = { 39, 58, 77 },
587 .hback_porch = { 59, 88, 117 },
588 .hsync_len = { 28, 42, 56 },
589 .vactive = { 1080, 1080, 1080 },
590 .vfront_porch = { 3, 8, 11 },
591 .vback_porch = { 5, 14, 19 },
592 .vsync_len = { 4, 14, 19 },
595 static const struct panel_desc auo_g133han01 = {
596 .timings = &auo_g133han01_timings,
609 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
612 static const struct display_timing auo_g185han01_timings = {
613 .pixelclock = { 120000000, 144000000, 175000000 },
614 .hactive = { 1920, 1920, 1920 },
615 .hfront_porch = { 18, 60, 74 },
616 .hback_porch = { 12, 44, 54 },
617 .hsync_len = { 10, 24, 32 },
618 .vactive = { 1080, 1080, 1080 },
619 .vfront_porch = { 6, 10, 40 },
620 .vback_porch = { 2, 5, 20 },
621 .vsync_len = { 2, 5, 20 },
624 static const struct panel_desc auo_g185han01 = {
625 .timings = &auo_g185han01_timings,
638 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
641 static const struct drm_display_mode auo_t215hvn01_mode = {
644 .hsync_start = 1920 + 88,
645 .hsync_end = 1920 + 88 + 44,
646 .htotal = 1920 + 88 + 44 + 148,
648 .vsync_start = 1080 + 4,
649 .vsync_end = 1080 + 4 + 5,
650 .vtotal = 1080 + 4 + 5 + 36,
654 static const struct panel_desc auo_t215hvn01 = {
655 .modes = &auo_t215hvn01_mode,
668 static const struct drm_display_mode avic_tm070ddh03_mode = {
671 .hsync_start = 1024 + 160,
672 .hsync_end = 1024 + 160 + 4,
673 .htotal = 1024 + 160 + 4 + 156,
675 .vsync_start = 600 + 17,
676 .vsync_end = 600 + 17 + 1,
677 .vtotal = 600 + 17 + 1 + 17,
681 static const struct panel_desc avic_tm070ddh03 = {
682 .modes = &avic_tm070ddh03_mode,
696 static const struct drm_display_mode boe_nv101wxmn51_modes[] = {
700 .hsync_start = 1280 + 48,
701 .hsync_end = 1280 + 48 + 32,
702 .htotal = 1280 + 48 + 32 + 80,
704 .vsync_start = 800 + 3,
705 .vsync_end = 800 + 3 + 5,
706 .vtotal = 800 + 3 + 5 + 24,
712 .hsync_start = 1280 + 48,
713 .hsync_end = 1280 + 48 + 32,
714 .htotal = 1280 + 48 + 32 + 80,
716 .vsync_start = 800 + 3,
717 .vsync_end = 800 + 3 + 5,
718 .vtotal = 800 + 3 + 5 + 24,
723 static const struct panel_desc boe_nv101wxmn51 = {
724 .modes = boe_nv101wxmn51_modes,
725 .num_modes = ARRAY_SIZE(boe_nv101wxmn51_modes),
738 static const struct drm_display_mode chunghwa_claa070wp03xg_mode = {
741 .hsync_start = 800 + 49,
742 .hsync_end = 800 + 49 + 33,
743 .htotal = 800 + 49 + 33 + 17,
745 .vsync_start = 1280 + 1,
746 .vsync_end = 1280 + 1 + 7,
747 .vtotal = 1280 + 1 + 7 + 15,
749 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
752 static const struct panel_desc chunghwa_claa070wp03xg = {
753 .modes = &chunghwa_claa070wp03xg_mode,
762 static const struct drm_display_mode chunghwa_claa101wa01a_mode = {
765 .hsync_start = 1366 + 58,
766 .hsync_end = 1366 + 58 + 58,
767 .htotal = 1366 + 58 + 58 + 58,
769 .vsync_start = 768 + 4,
770 .vsync_end = 768 + 4 + 4,
771 .vtotal = 768 + 4 + 4 + 4,
775 static const struct panel_desc chunghwa_claa101wa01a = {
776 .modes = &chunghwa_claa101wa01a_mode,
785 static const struct drm_display_mode chunghwa_claa101wb01_mode = {
788 .hsync_start = 1366 + 48,
789 .hsync_end = 1366 + 48 + 32,
790 .htotal = 1366 + 48 + 32 + 20,
792 .vsync_start = 768 + 16,
793 .vsync_end = 768 + 16 + 8,
794 .vtotal = 768 + 16 + 8 + 16,
798 static const struct panel_desc chunghwa_claa101wb01 = {
799 .modes = &chunghwa_claa101wb01_mode,
808 static const struct drm_display_mode edt_et057090dhu_mode = {
811 .hsync_start = 640 + 16,
812 .hsync_end = 640 + 16 + 30,
813 .htotal = 640 + 16 + 30 + 114,
815 .vsync_start = 480 + 10,
816 .vsync_end = 480 + 10 + 3,
817 .vtotal = 480 + 10 + 3 + 32,
819 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
822 static const struct panel_desc edt_et057090dhu = {
823 .modes = &edt_et057090dhu_mode,
830 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
831 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_NEGEDGE,
834 static const struct drm_display_mode edt_etm0700g0dh6_mode = {
837 .hsync_start = 800 + 40,
838 .hsync_end = 800 + 40 + 128,
839 .htotal = 800 + 40 + 128 + 88,
841 .vsync_start = 480 + 10,
842 .vsync_end = 480 + 10 + 2,
843 .vtotal = 480 + 10 + 2 + 33,
845 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
848 static const struct panel_desc edt_etm0700g0dh6 = {
849 .modes = &edt_etm0700g0dh6_mode,
856 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
857 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_NEGEDGE,
860 static const struct drm_display_mode foxlink_fl500wvr00_a0t_mode = {
863 .hsync_start = 800 + 168,
864 .hsync_end = 800 + 168 + 64,
865 .htotal = 800 + 168 + 64 + 88,
867 .vsync_start = 480 + 37,
868 .vsync_end = 480 + 37 + 2,
869 .vtotal = 480 + 37 + 2 + 8,
873 static const struct panel_desc foxlink_fl500wvr00_a0t = {
874 .modes = &foxlink_fl500wvr00_a0t_mode,
881 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
884 static const struct drm_display_mode giantplus_gpg482739qs5_mode = {
887 .hsync_start = 480 + 5,
888 .hsync_end = 480 + 5 + 1,
889 .htotal = 480 + 5 + 1 + 40,
891 .vsync_start = 272 + 8,
892 .vsync_end = 272 + 8 + 1,
893 .vtotal = 272 + 8 + 1 + 8,
897 static const struct panel_desc giantplus_gpg482739qs5 = {
898 .modes = &giantplus_gpg482739qs5_mode,
905 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
908 static const struct display_timing hannstar_hsd070pww1_timing = {
909 .pixelclock = { 64300000, 71100000, 82000000 },
910 .hactive = { 1280, 1280, 1280 },
911 .hfront_porch = { 1, 1, 10 },
912 .hback_porch = { 1, 1, 10 },
914 * According to the data sheet, the minimum horizontal blanking interval
915 * is 54 clocks (1 + 52 + 1), but tests with a Nitrogen6X have shown the
916 * minimum working horizontal blanking interval to be 60 clocks.
918 .hsync_len = { 58, 158, 661 },
919 .vactive = { 800, 800, 800 },
920 .vfront_porch = { 1, 1, 10 },
921 .vback_porch = { 1, 1, 10 },
922 .vsync_len = { 1, 21, 203 },
923 .flags = DISPLAY_FLAGS_DE_HIGH,
926 static const struct panel_desc hannstar_hsd070pww1 = {
927 .timings = &hannstar_hsd070pww1_timing,
934 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
937 static const struct display_timing hannstar_hsd100pxn1_timing = {
938 .pixelclock = { 55000000, 65000000, 75000000 },
939 .hactive = { 1024, 1024, 1024 },
940 .hfront_porch = { 40, 40, 40 },
941 .hback_porch = { 220, 220, 220 },
942 .hsync_len = { 20, 60, 100 },
943 .vactive = { 768, 768, 768 },
944 .vfront_porch = { 7, 7, 7 },
945 .vback_porch = { 21, 21, 21 },
946 .vsync_len = { 10, 10, 10 },
947 .flags = DISPLAY_FLAGS_DE_HIGH,
950 static const struct panel_desc hannstar_hsd100pxn1 = {
951 .timings = &hannstar_hsd100pxn1_timing,
958 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
961 static const struct drm_display_mode hitachi_tx23d38vm0caa_mode = {
964 .hsync_start = 800 + 85,
965 .hsync_end = 800 + 85 + 86,
966 .htotal = 800 + 85 + 86 + 85,
968 .vsync_start = 480 + 16,
969 .vsync_end = 480 + 16 + 13,
970 .vtotal = 480 + 16 + 13 + 16,
974 static const struct panel_desc hitachi_tx23d38vm0caa = {
975 .modes = &hitachi_tx23d38vm0caa_mode,
984 static const struct drm_display_mode innolux_at043tn24_mode = {
987 .hsync_start = 480 + 2,
988 .hsync_end = 480 + 2 + 41,
989 .htotal = 480 + 2 + 41 + 2,
991 .vsync_start = 272 + 2,
992 .vsync_end = 272 + 2 + 11,
993 .vtotal = 272 + 2 + 11 + 2,
995 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
998 static const struct panel_desc innolux_at043tn24 = {
999 .modes = &innolux_at043tn24_mode,
1006 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1009 static const struct drm_display_mode innolux_at070tn92_mode = {
1012 .hsync_start = 800 + 210,
1013 .hsync_end = 800 + 210 + 20,
1014 .htotal = 800 + 210 + 20 + 46,
1016 .vsync_start = 480 + 22,
1017 .vsync_end = 480 + 22 + 10,
1018 .vtotal = 480 + 22 + 23 + 10,
1022 static const struct panel_desc innolux_at070tn92 = {
1023 .modes = &innolux_at070tn92_mode,
1029 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1032 static const struct display_timing innolux_g101ice_l01_timing = {
1033 .pixelclock = { 60400000, 71100000, 74700000 },
1034 .hactive = { 1280, 1280, 1280 },
1035 .hfront_porch = { 41, 80, 100 },
1036 .hback_porch = { 40, 79, 99 },
1037 .hsync_len = { 1, 1, 1 },
1038 .vactive = { 800, 800, 800 },
1039 .vfront_porch = { 5, 11, 14 },
1040 .vback_porch = { 4, 11, 14 },
1041 .vsync_len = { 1, 1, 1 },
1042 .flags = DISPLAY_FLAGS_DE_HIGH,
1045 static const struct panel_desc innolux_g101ice_l01 = {
1046 .timings = &innolux_g101ice_l01_timing,
1057 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1060 static const struct display_timing innolux_g121i1_l01_timing = {
1061 .pixelclock = { 67450000, 71000000, 74550000 },
1062 .hactive = { 1280, 1280, 1280 },
1063 .hfront_porch = { 40, 80, 160 },
1064 .hback_porch = { 39, 79, 159 },
1065 .hsync_len = { 1, 1, 1 },
1066 .vactive = { 800, 800, 800 },
1067 .vfront_porch = { 5, 11, 100 },
1068 .vback_porch = { 4, 11, 99 },
1069 .vsync_len = { 1, 1, 1 },
1072 static const struct panel_desc innolux_g121i1_l01 = {
1073 .timings = &innolux_g121i1_l01_timing,
1084 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1087 static const struct drm_display_mode innolux_g121x1_l03_mode = {
1090 .hsync_start = 1024 + 0,
1091 .hsync_end = 1024 + 1,
1092 .htotal = 1024 + 0 + 1 + 320,
1094 .vsync_start = 768 + 38,
1095 .vsync_end = 768 + 38 + 1,
1096 .vtotal = 768 + 38 + 1 + 0,
1098 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1101 static const struct panel_desc innolux_g121x1_l03 = {
1102 .modes = &innolux_g121x1_l03_mode,
1116 static const struct drm_display_mode innolux_n116bge_mode = {
1119 .hsync_start = 1366 + 136,
1120 .hsync_end = 1366 + 136 + 30,
1121 .htotal = 1366 + 136 + 30 + 60,
1123 .vsync_start = 768 + 8,
1124 .vsync_end = 768 + 8 + 12,
1125 .vtotal = 768 + 8 + 12 + 12,
1127 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1130 static const struct panel_desc innolux_n116bge = {
1131 .modes = &innolux_n116bge_mode,
1140 static const struct drm_display_mode innolux_n156bge_l21_mode = {
1143 .hsync_start = 1366 + 16,
1144 .hsync_end = 1366 + 16 + 34,
1145 .htotal = 1366 + 16 + 34 + 50,
1147 .vsync_start = 768 + 2,
1148 .vsync_end = 768 + 2 + 6,
1149 .vtotal = 768 + 2 + 6 + 12,
1153 static const struct panel_desc innolux_n156bge_l21 = {
1154 .modes = &innolux_n156bge_l21_mode,
1163 static const struct drm_display_mode innolux_zj070na_01p_mode = {
1166 .hsync_start = 1024 + 128,
1167 .hsync_end = 1024 + 128 + 64,
1168 .htotal = 1024 + 128 + 64 + 128,
1170 .vsync_start = 600 + 16,
1171 .vsync_end = 600 + 16 + 4,
1172 .vtotal = 600 + 16 + 4 + 16,
1176 static const struct panel_desc innolux_zj070na_01p = {
1177 .modes = &innolux_zj070na_01p_mode,
1186 static const struct display_timing kyo_tcg121xglp_timing = {
1187 .pixelclock = { 52000000, 65000000, 71000000 },
1188 .hactive = { 1024, 1024, 1024 },
1189 .hfront_porch = { 2, 2, 2 },
1190 .hback_porch = { 2, 2, 2 },
1191 .hsync_len = { 86, 124, 244 },
1192 .vactive = { 768, 768, 768 },
1193 .vfront_porch = { 2, 2, 2 },
1194 .vback_porch = { 2, 2, 2 },
1195 .vsync_len = { 6, 34, 73 },
1196 .flags = DISPLAY_FLAGS_DE_HIGH,
1199 static const struct panel_desc kyo_tcg121xglp = {
1200 .timings = &kyo_tcg121xglp_timing,
1207 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1210 static const struct drm_display_mode lg_lb070wv8_mode = {
1213 .hsync_start = 800 + 88,
1214 .hsync_end = 800 + 88 + 80,
1215 .htotal = 800 + 88 + 80 + 88,
1217 .vsync_start = 480 + 10,
1218 .vsync_end = 480 + 10 + 25,
1219 .vtotal = 480 + 10 + 25 + 10,
1223 static const struct panel_desc lg_lb070wv8 = {
1224 .modes = &lg_lb070wv8_mode,
1231 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1234 static const struct drm_display_mode lg_lp079qx1_sp0v_mode = {
1237 .hsync_start = 1536 + 12,
1238 .hsync_end = 1536 + 12 + 16,
1239 .htotal = 1536 + 12 + 16 + 48,
1241 .vsync_start = 2048 + 8,
1242 .vsync_end = 2048 + 8 + 4,
1243 .vtotal = 2048 + 8 + 4 + 8,
1245 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1248 static const struct panel_desc lg_lp079qx1_sp0v = {
1249 .modes = &lg_lp079qx1_sp0v_mode,
1257 static const struct drm_display_mode lg_lp097qx1_spa1_mode = {
1260 .hsync_start = 2048 + 150,
1261 .hsync_end = 2048 + 150 + 5,
1262 .htotal = 2048 + 150 + 5 + 5,
1264 .vsync_start = 1536 + 3,
1265 .vsync_end = 1536 + 3 + 1,
1266 .vtotal = 1536 + 3 + 1 + 9,
1270 static const struct panel_desc lg_lp097qx1_spa1 = {
1271 .modes = &lg_lp097qx1_spa1_mode,
1279 static const struct drm_display_mode lg_lp120up1_mode = {
1282 .hsync_start = 1920 + 40,
1283 .hsync_end = 1920 + 40 + 40,
1284 .htotal = 1920 + 40 + 40+ 80,
1286 .vsync_start = 1280 + 4,
1287 .vsync_end = 1280 + 4 + 4,
1288 .vtotal = 1280 + 4 + 4 + 12,
1292 static const struct panel_desc lg_lp120up1 = {
1293 .modes = &lg_lp120up1_mode,
1302 static const struct drm_display_mode lg_lp129qe_mode = {
1305 .hsync_start = 2560 + 48,
1306 .hsync_end = 2560 + 48 + 32,
1307 .htotal = 2560 + 48 + 32 + 80,
1309 .vsync_start = 1700 + 3,
1310 .vsync_end = 1700 + 3 + 10,
1311 .vtotal = 1700 + 3 + 10 + 36,
1315 static const struct panel_desc lg_lp129qe = {
1316 .modes = &lg_lp129qe_mode,
1325 static const struct drm_display_mode nec_nl4827hc19_05b_mode = {
1328 .hsync_start = 480 + 2,
1329 .hsync_end = 480 + 2 + 41,
1330 .htotal = 480 + 2 + 41 + 2,
1332 .vsync_start = 272 + 2,
1333 .vsync_end = 272 + 2 + 4,
1334 .vtotal = 272 + 2 + 4 + 2,
1336 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1339 static const struct panel_desc nec_nl4827hc19_05b = {
1340 .modes = &nec_nl4827hc19_05b_mode,
1347 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1348 .bus_flags = DRM_BUS_FLAG_PIXDATA_POSEDGE,
1351 static const struct drm_display_mode netron_dy_e231732_mode = {
1354 .hsync_start = 1024 + 160,
1355 .hsync_end = 1024 + 160 + 70,
1356 .htotal = 1024 + 160 + 70 + 90,
1358 .vsync_start = 600 + 127,
1359 .vsync_end = 600 + 127 + 20,
1360 .vtotal = 600 + 127 + 20 + 3,
1364 static const struct panel_desc netron_dy_e231732 = {
1365 .modes = &netron_dy_e231732_mode,
1371 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1374 static const struct drm_display_mode nvd_9128_mode = {
1377 .hsync_start = 800 + 130,
1378 .hsync_end = 800 + 130 + 98,
1379 .htotal = 800 + 0 + 130 + 98,
1381 .vsync_start = 480 + 10,
1382 .vsync_end = 480 + 10 + 50,
1383 .vtotal = 480 + 0 + 10 + 50,
1386 static const struct panel_desc nvd_9128 = {
1387 .modes = &nvd_9128_mode,
1394 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1397 static const struct display_timing okaya_rs800480t_7x0gp_timing = {
1398 .pixelclock = { 30000000, 30000000, 40000000 },
1399 .hactive = { 800, 800, 800 },
1400 .hfront_porch = { 40, 40, 40 },
1401 .hback_porch = { 40, 40, 40 },
1402 .hsync_len = { 1, 48, 48 },
1403 .vactive = { 480, 480, 480 },
1404 .vfront_porch = { 13, 13, 13 },
1405 .vback_porch = { 29, 29, 29 },
1406 .vsync_len = { 3, 3, 3 },
1407 .flags = DISPLAY_FLAGS_DE_HIGH,
1410 static const struct panel_desc okaya_rs800480t_7x0gp = {
1411 .timings = &okaya_rs800480t_7x0gp_timing,
1424 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1427 static const struct drm_display_mode olimex_lcd_olinuxino_43ts_mode = {
1430 .hsync_start = 480 + 5,
1431 .hsync_end = 480 + 5 + 30,
1432 .htotal = 480 + 5 + 30 + 10,
1434 .vsync_start = 272 + 8,
1435 .vsync_end = 272 + 8 + 5,
1436 .vtotal = 272 + 8 + 5 + 3,
1440 static const struct panel_desc olimex_lcd_olinuxino_43ts = {
1441 .modes = &olimex_lcd_olinuxino_43ts_mode,
1447 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1451 * 800x480 CVT. The panel appears to be quite accepting, at least as far as
1452 * pixel clocks, but this is the timing that was being used in the Adafruit
1453 * installation instructions.
1455 static const struct drm_display_mode ontat_yx700wv03_mode = {
1466 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1471 * https://www.adafruit.com/images/product-files/2406/c3163.pdf
1473 static const struct panel_desc ontat_yx700wv03 = {
1474 .modes = &ontat_yx700wv03_mode,
1481 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1484 static const struct drm_display_mode ortustech_com43h4m85ulc_mode = {
1487 .hsync_start = 480 + 10,
1488 .hsync_end = 480 + 10 + 10,
1489 .htotal = 480 + 10 + 10 + 15,
1491 .vsync_start = 800 + 3,
1492 .vsync_end = 800 + 3 + 3,
1493 .vtotal = 800 + 3 + 3 + 3,
1497 static const struct panel_desc ortustech_com43h4m85ulc = {
1498 .modes = &ortustech_com43h4m85ulc_mode,
1505 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1506 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE,
1509 static const struct drm_display_mode qd43003c0_40_mode = {
1512 .hsync_start = 480 + 8,
1513 .hsync_end = 480 + 8 + 4,
1514 .htotal = 480 + 8 + 4 + 39,
1516 .vsync_start = 272 + 4,
1517 .vsync_end = 272 + 4 + 10,
1518 .vtotal = 272 + 4 + 10 + 2,
1522 static const struct panel_desc qd43003c0_40 = {
1523 .modes = &qd43003c0_40_mode,
1530 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1533 static const struct drm_display_mode samsung_lsn122dl01_c01_mode = {
1536 .hsync_start = 2560 + 48,
1537 .hsync_end = 2560 + 48 + 32,
1538 .htotal = 2560 + 48 + 32 + 80,
1540 .vsync_start = 1600 + 2,
1541 .vsync_end = 1600 + 2 + 5,
1542 .vtotal = 1600 + 2 + 5 + 57,
1546 static const struct panel_desc samsung_lsn122dl01_c01 = {
1547 .modes = &samsung_lsn122dl01_c01_mode,
1555 static const struct drm_display_mode samsung_ltn101nt05_mode = {
1558 .hsync_start = 1024 + 24,
1559 .hsync_end = 1024 + 24 + 136,
1560 .htotal = 1024 + 24 + 136 + 160,
1562 .vsync_start = 600 + 3,
1563 .vsync_end = 600 + 3 + 6,
1564 .vtotal = 600 + 3 + 6 + 61,
1568 static const struct panel_desc samsung_ltn101nt05 = {
1569 .modes = &samsung_ltn101nt05_mode,
1578 static const struct drm_display_mode samsung_ltn140at29_301_mode = {
1581 .hsync_start = 1366 + 64,
1582 .hsync_end = 1366 + 64 + 48,
1583 .htotal = 1366 + 64 + 48 + 128,
1585 .vsync_start = 768 + 2,
1586 .vsync_end = 768 + 2 + 5,
1587 .vtotal = 768 + 2 + 5 + 17,
1591 static const struct panel_desc samsung_ltn140at29_301 = {
1592 .modes = &samsung_ltn140at29_301_mode,
1601 static const struct display_timing sharp_lq101k1ly04_timing = {
1602 .pixelclock = { 60000000, 65000000, 80000000 },
1603 .hactive = { 1280, 1280, 1280 },
1604 .hfront_porch = { 20, 20, 20 },
1605 .hback_porch = { 20, 20, 20 },
1606 .hsync_len = { 10, 10, 10 },
1607 .vactive = { 800, 800, 800 },
1608 .vfront_porch = { 4, 4, 4 },
1609 .vback_porch = { 4, 4, 4 },
1610 .vsync_len = { 4, 4, 4 },
1611 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE,
1614 static const struct panel_desc sharp_lq101k1ly04 = {
1615 .timings = &sharp_lq101k1ly04_timing,
1622 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
1625 static const struct drm_display_mode sharp_lq123p1jx31_mode = {
1628 .hsync_start = 2400 + 48,
1629 .hsync_end = 2400 + 48 + 32,
1630 .htotal = 2400 + 48 + 32 + 80,
1632 .vsync_start = 1600 + 3,
1633 .vsync_end = 1600 + 3 + 10,
1634 .vtotal = 1600 + 3 + 10 + 33,
1636 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1639 static const struct panel_desc sharp_lq123p1jx31 = {
1640 .modes = &sharp_lq123p1jx31_mode,
1654 static const struct drm_display_mode sharp_lq150x1lg11_mode = {
1657 .hsync_start = 1024 + 168,
1658 .hsync_end = 1024 + 168 + 64,
1659 .htotal = 1024 + 168 + 64 + 88,
1661 .vsync_start = 768 + 37,
1662 .vsync_end = 768 + 37 + 2,
1663 .vtotal = 768 + 37 + 2 + 8,
1667 static const struct panel_desc sharp_lq150x1lg11 = {
1668 .modes = &sharp_lq150x1lg11_mode,
1675 .bus_format = MEDIA_BUS_FMT_RGB565_1X16,
1678 static const struct drm_display_mode shelly_sca07010_bfn_lnn_mode = {
1681 .hsync_start = 800 + 1,
1682 .hsync_end = 800 + 1 + 64,
1683 .htotal = 800 + 1 + 64 + 64,
1685 .vsync_start = 480 + 1,
1686 .vsync_end = 480 + 1 + 23,
1687 .vtotal = 480 + 1 + 23 + 22,
1691 static const struct panel_desc shelly_sca07010_bfn_lnn = {
1692 .modes = &shelly_sca07010_bfn_lnn_mode,
1698 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1701 static const struct drm_display_mode starry_kr122ea0sra_mode = {
1704 .hsync_start = 1920 + 16,
1705 .hsync_end = 1920 + 16 + 16,
1706 .htotal = 1920 + 16 + 16 + 32,
1708 .vsync_start = 1200 + 15,
1709 .vsync_end = 1200 + 15 + 2,
1710 .vtotal = 1200 + 15 + 2 + 18,
1712 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1715 static const struct panel_desc starry_kr122ea0sra = {
1716 .modes = &starry_kr122ea0sra_mode,
1723 .prepare = 10 + 200,
1725 .unprepare = 10 + 500,
1729 static const struct display_timing tianma_tm070jdhg30_timing = {
1730 .pixelclock = { 62600000, 68200000, 78100000 },
1731 .hactive = { 1280, 1280, 1280 },
1732 .hfront_porch = { 15, 64, 159 },
1733 .hback_porch = { 5, 5, 5 },
1734 .hsync_len = { 1, 1, 256 },
1735 .vactive = { 800, 800, 800 },
1736 .vfront_porch = { 3, 40, 99 },
1737 .vback_porch = { 2, 2, 2 },
1738 .vsync_len = { 1, 1, 128 },
1739 .flags = DISPLAY_FLAGS_DE_HIGH,
1742 static const struct panel_desc tianma_tm070jdhg30 = {
1743 .timings = &tianma_tm070jdhg30_timing,
1750 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1753 static const struct drm_display_mode tpk_f07a_0102_mode = {
1756 .hsync_start = 800 + 40,
1757 .hsync_end = 800 + 40 + 128,
1758 .htotal = 800 + 40 + 128 + 88,
1760 .vsync_start = 480 + 10,
1761 .vsync_end = 480 + 10 + 2,
1762 .vtotal = 480 + 10 + 2 + 33,
1766 static const struct panel_desc tpk_f07a_0102 = {
1767 .modes = &tpk_f07a_0102_mode,
1773 .bus_flags = DRM_BUS_FLAG_PIXDATA_POSEDGE,
1776 static const struct drm_display_mode tpk_f10a_0102_mode = {
1779 .hsync_start = 1024 + 176,
1780 .hsync_end = 1024 + 176 + 5,
1781 .htotal = 1024 + 176 + 5 + 88,
1783 .vsync_start = 600 + 20,
1784 .vsync_end = 600 + 20 + 5,
1785 .vtotal = 600 + 20 + 5 + 25,
1789 static const struct panel_desc tpk_f10a_0102 = {
1790 .modes = &tpk_f10a_0102_mode,
1798 static const struct display_timing urt_umsh_8596md_timing = {
1799 .pixelclock = { 33260000, 33260000, 33260000 },
1800 .hactive = { 800, 800, 800 },
1801 .hfront_porch = { 41, 41, 41 },
1802 .hback_porch = { 216 - 128, 216 - 128, 216 - 128 },
1803 .hsync_len = { 71, 128, 128 },
1804 .vactive = { 480, 480, 480 },
1805 .vfront_porch = { 10, 10, 10 },
1806 .vback_porch = { 35 - 2, 35 - 2, 35 - 2 },
1807 .vsync_len = { 2, 2, 2 },
1808 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE |
1809 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW,
1812 static const struct panel_desc urt_umsh_8596md_lvds = {
1813 .timings = &urt_umsh_8596md_timing,
1820 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1823 static const struct panel_desc urt_umsh_8596md_parallel = {
1824 .timings = &urt_umsh_8596md_timing,
1831 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1834 static const struct drm_display_mode winstar_wf35ltiacd_mode = {
1837 .hsync_start = 320 + 20,
1838 .hsync_end = 320 + 20 + 30,
1839 .htotal = 320 + 20 + 30 + 38,
1841 .vsync_start = 240 + 4,
1842 .vsync_end = 240 + 4 + 3,
1843 .vtotal = 240 + 4 + 3 + 15,
1845 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1848 static const struct panel_desc winstar_wf35ltiacd = {
1849 .modes = &winstar_wf35ltiacd_mode,
1856 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1859 static const struct of_device_id platform_of_match[] = {
1861 .compatible = "ampire,am-480272h3tmqw-t01h",
1862 .data = &ire_am_480272h3tmqw_t01h,
1864 .compatible = "ampire,am800480r3tmqwa1h",
1865 .data = &ire_am800480r3tmqwa1h,
1867 .compatible = "auo,b101aw03",
1868 .data = &auo_b101aw03,
1870 .compatible = "auo,b101ean01",
1871 .data = &auo_b101ean01,
1873 .compatible = "auo,b101xtn01",
1874 .data = &auo_b101xtn01,
1876 .compatible = "auo,b116xw03",
1877 .data = &auo_b116xw03,
1879 .compatible = "auo,b133htn01",
1880 .data = &auo_b133htn01,
1882 .compatible = "auo,b133xtn01",
1883 .data = &auo_b133xtn01,
1885 .compatible = "auo,g133han01",
1886 .data = &auo_g133han01,
1888 .compatible = "auo,g185han01",
1889 .data = &auo_g185han01,
1891 .compatible = "auo,t215hvn01",
1892 .data = &auo_t215hvn01,
1894 .compatible = "avic,tm070ddh03",
1895 .data = &avic_tm070ddh03,
1897 .compatible = "boe,nv101wxmn51",
1898 .data = &boe_nv101wxmn51,
1900 .compatible = "chunghwa,claa070wp03xg",
1901 .data = &chunghwa_claa070wp03xg,
1903 .compatible = "chunghwa,claa101wa01a",
1904 .data = &chunghwa_claa101wa01a
1906 .compatible = "chunghwa,claa101wb01",
1907 .data = &chunghwa_claa101wb01
1909 .compatible = "edt,et057090dhu",
1910 .data = &edt_et057090dhu,
1912 .compatible = "edt,et070080dh6",
1913 .data = &edt_etm0700g0dh6,
1915 .compatible = "edt,etm0700g0dh6",
1916 .data = &edt_etm0700g0dh6,
1918 .compatible = "foxlink,fl500wvr00-a0t",
1919 .data = &foxlink_fl500wvr00_a0t,
1921 .compatible = "giantplus,gpg482739qs5",
1922 .data = &giantplus_gpg482739qs5
1924 .compatible = "hannstar,hsd070pww1",
1925 .data = &hannstar_hsd070pww1,
1927 .compatible = "hannstar,hsd100pxn1",
1928 .data = &hannstar_hsd100pxn1,
1930 .compatible = "hit,tx23d38vm0caa",
1931 .data = &hitachi_tx23d38vm0caa
1933 .compatible = "innolux,at043tn24",
1934 .data = &innolux_at043tn24,
1936 .compatible = "innolux,at070tn92",
1937 .data = &innolux_at070tn92,
1939 .compatible ="innolux,g101ice-l01",
1940 .data = &innolux_g101ice_l01
1942 .compatible ="innolux,g121i1-l01",
1943 .data = &innolux_g121i1_l01
1945 .compatible = "innolux,g121x1-l03",
1946 .data = &innolux_g121x1_l03,
1948 .compatible = "innolux,n116bge",
1949 .data = &innolux_n116bge,
1951 .compatible = "innolux,n156bge-l21",
1952 .data = &innolux_n156bge_l21,
1954 .compatible = "innolux,zj070na-01p",
1955 .data = &innolux_zj070na_01p,
1957 .compatible = "kyo,tcg121xglp",
1958 .data = &kyo_tcg121xglp,
1960 .compatible = "lg,lb070wv8",
1961 .data = &lg_lb070wv8,
1963 .compatible = "lg,lp079qx1-sp0v",
1964 .data = &lg_lp079qx1_sp0v,
1966 .compatible = "lg,lp097qx1-spa1",
1967 .data = &lg_lp097qx1_spa1,
1969 .compatible = "lg,lp120up1",
1970 .data = &lg_lp120up1,
1972 .compatible = "lg,lp129qe",
1973 .data = &lg_lp129qe,
1975 .compatible = "nec,nl4827hc19-05b",
1976 .data = &nec_nl4827hc19_05b,
1978 .compatible = "netron-dy,e231732",
1979 .data = &netron_dy_e231732,
1981 .compatible = "nvd,9128",
1984 .compatible = "okaya,rs800480t-7x0gp",
1985 .data = &okaya_rs800480t_7x0gp,
1987 .compatible = "olimex,lcd-olinuxino-43-ts",
1988 .data = &olimex_lcd_olinuxino_43ts,
1990 .compatible = "ontat,yx700wv03",
1991 .data = &ontat_yx700wv03,
1993 .compatible = "ortustech,com43h4m85ulc",
1994 .data = &ortustech_com43h4m85ulc,
1996 .compatible = "qiaodian,qd43003c0-40",
1997 .data = &qd43003c0_40,
1999 .compatible = "samsung,lsn122dl01-c01",
2000 .data = &samsung_lsn122dl01_c01,
2002 .compatible = "samsung,ltn101nt05",
2003 .data = &samsung_ltn101nt05,
2005 .compatible = "samsung,ltn140at29-301",
2006 .data = &samsung_ltn140at29_301,
2008 .compatible = "sharp,lq101k1ly04",
2009 .data = &sharp_lq101k1ly04,
2011 .compatible = "sharp,lq123p1jx31",
2012 .data = &sharp_lq123p1jx31,
2014 .compatible = "sharp,lq150x1lg11",
2015 .data = &sharp_lq150x1lg11,
2017 .compatible = "shelly,sca07010-bfn-lnn",
2018 .data = &shelly_sca07010_bfn_lnn,
2020 .compatible = "starry,kr122ea0sra",
2021 .data = &starry_kr122ea0sra,
2023 .compatible = "tianma,tm070jdhg30",
2024 .data = &tianma_tm070jdhg30,
2026 .compatible = "tpk,f07a-0102",
2027 .data = &tpk_f07a_0102,
2029 .compatible = "tpk,f10a-0102",
2030 .data = &tpk_f10a_0102,
2032 .compatible = "urt,umsh-8596md-t",
2033 .data = &urt_umsh_8596md_parallel,
2035 .compatible = "urt,umsh-8596md-1t",
2036 .data = &urt_umsh_8596md_parallel,
2038 .compatible = "urt,umsh-8596md-7t",
2039 .data = &urt_umsh_8596md_parallel,
2041 .compatible = "urt,umsh-8596md-11t",
2042 .data = &urt_umsh_8596md_lvds,
2044 .compatible = "urt,umsh-8596md-19t",
2045 .data = &urt_umsh_8596md_lvds,
2047 .compatible = "urt,umsh-8596md-20t",
2048 .data = &urt_umsh_8596md_parallel,
2050 .compatible = "winstar,wf35ltiacd",
2051 .data = &winstar_wf35ltiacd,
2056 MODULE_DEVICE_TABLE(of, platform_of_match);
2058 static int panel_simple_platform_probe(struct platform_device *pdev)
2060 const struct of_device_id *id;
2062 id = of_match_node(platform_of_match, pdev->dev.of_node);
2066 return panel_simple_probe(&pdev->dev, id->data);
2069 static int panel_simple_platform_remove(struct platform_device *pdev)
2071 return panel_simple_remove(&pdev->dev);
2074 static void panel_simple_platform_shutdown(struct platform_device *pdev)
2076 panel_simple_shutdown(&pdev->dev);
2079 static struct platform_driver panel_simple_platform_driver = {
2081 .name = "panel-simple",
2082 .of_match_table = platform_of_match,
2084 .probe = panel_simple_platform_probe,
2085 .remove = panel_simple_platform_remove,
2086 .shutdown = panel_simple_platform_shutdown,
2089 struct panel_desc_dsi {
2090 struct panel_desc desc;
2092 unsigned long flags;
2093 enum mipi_dsi_pixel_format format;
2097 static const struct drm_display_mode auo_b080uan01_mode = {
2100 .hsync_start = 1200 + 62,
2101 .hsync_end = 1200 + 62 + 4,
2102 .htotal = 1200 + 62 + 4 + 62,
2104 .vsync_start = 1920 + 9,
2105 .vsync_end = 1920 + 9 + 2,
2106 .vtotal = 1920 + 9 + 2 + 8,
2110 static const struct panel_desc_dsi auo_b080uan01 = {
2112 .modes = &auo_b080uan01_mode,
2120 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS,
2121 .format = MIPI_DSI_FMT_RGB888,
2125 static const struct drm_display_mode boe_tv080wum_nl0_mode = {
2128 .hsync_start = 1200 + 120,
2129 .hsync_end = 1200 + 120 + 20,
2130 .htotal = 1200 + 120 + 20 + 21,
2132 .vsync_start = 1920 + 21,
2133 .vsync_end = 1920 + 21 + 3,
2134 .vtotal = 1920 + 21 + 3 + 18,
2136 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2139 static const struct panel_desc_dsi boe_tv080wum_nl0 = {
2141 .modes = &boe_tv080wum_nl0_mode,
2148 .flags = MIPI_DSI_MODE_VIDEO |
2149 MIPI_DSI_MODE_VIDEO_BURST |
2150 MIPI_DSI_MODE_VIDEO_SYNC_PULSE,
2151 .format = MIPI_DSI_FMT_RGB888,
2155 static const struct drm_display_mode lg_ld070wx3_sl01_mode = {
2158 .hsync_start = 800 + 32,
2159 .hsync_end = 800 + 32 + 1,
2160 .htotal = 800 + 32 + 1 + 57,
2162 .vsync_start = 1280 + 28,
2163 .vsync_end = 1280 + 28 + 1,
2164 .vtotal = 1280 + 28 + 1 + 14,
2168 static const struct panel_desc_dsi lg_ld070wx3_sl01 = {
2170 .modes = &lg_ld070wx3_sl01_mode,
2178 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS,
2179 .format = MIPI_DSI_FMT_RGB888,
2183 static const struct drm_display_mode lg_lh500wx1_sd03_mode = {
2186 .hsync_start = 720 + 12,
2187 .hsync_end = 720 + 12 + 4,
2188 .htotal = 720 + 12 + 4 + 112,
2190 .vsync_start = 1280 + 8,
2191 .vsync_end = 1280 + 8 + 4,
2192 .vtotal = 1280 + 8 + 4 + 12,
2196 static const struct panel_desc_dsi lg_lh500wx1_sd03 = {
2198 .modes = &lg_lh500wx1_sd03_mode,
2206 .flags = MIPI_DSI_MODE_VIDEO,
2207 .format = MIPI_DSI_FMT_RGB888,
2211 static const struct drm_display_mode panasonic_vvx10f004b00_mode = {
2214 .hsync_start = 1920 + 154,
2215 .hsync_end = 1920 + 154 + 16,
2216 .htotal = 1920 + 154 + 16 + 32,
2218 .vsync_start = 1200 + 17,
2219 .vsync_end = 1200 + 17 + 2,
2220 .vtotal = 1200 + 17 + 2 + 16,
2224 static const struct panel_desc_dsi panasonic_vvx10f004b00 = {
2226 .modes = &panasonic_vvx10f004b00_mode,
2234 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
2235 MIPI_DSI_CLOCK_NON_CONTINUOUS,
2236 .format = MIPI_DSI_FMT_RGB888,
2240 static const struct of_device_id dsi_of_match[] = {
2242 .compatible = "auo,b080uan01",
2243 .data = &auo_b080uan01
2245 .compatible = "boe,tv080wum-nl0",
2246 .data = &boe_tv080wum_nl0
2248 .compatible = "lg,ld070wx3-sl01",
2249 .data = &lg_ld070wx3_sl01
2251 .compatible = "lg,lh500wx1-sd03",
2252 .data = &lg_lh500wx1_sd03
2254 .compatible = "panasonic,vvx10f004b00",
2255 .data = &panasonic_vvx10f004b00
2260 MODULE_DEVICE_TABLE(of, dsi_of_match);
2262 static int panel_simple_dsi_probe(struct mipi_dsi_device *dsi)
2264 const struct panel_desc_dsi *desc;
2265 const struct of_device_id *id;
2268 id = of_match_node(dsi_of_match, dsi->dev.of_node);
2274 err = panel_simple_probe(&dsi->dev, &desc->desc);
2278 dsi->mode_flags = desc->flags;
2279 dsi->format = desc->format;
2280 dsi->lanes = desc->lanes;
2282 return mipi_dsi_attach(dsi);
2285 static int panel_simple_dsi_remove(struct mipi_dsi_device *dsi)
2289 err = mipi_dsi_detach(dsi);
2291 dev_err(&dsi->dev, "failed to detach from DSI host: %d\n", err);
2293 return panel_simple_remove(&dsi->dev);
2296 static void panel_simple_dsi_shutdown(struct mipi_dsi_device *dsi)
2298 panel_simple_shutdown(&dsi->dev);
2301 static struct mipi_dsi_driver panel_simple_dsi_driver = {
2303 .name = "panel-simple-dsi",
2304 .of_match_table = dsi_of_match,
2306 .probe = panel_simple_dsi_probe,
2307 .remove = panel_simple_dsi_remove,
2308 .shutdown = panel_simple_dsi_shutdown,
2311 static int __init panel_simple_init(void)
2315 err = platform_driver_register(&panel_simple_platform_driver);
2319 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) {
2320 err = mipi_dsi_driver_register(&panel_simple_dsi_driver);
2327 module_init(panel_simple_init);
2329 static void __exit panel_simple_exit(void)
2331 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI))
2332 mipi_dsi_driver_unregister(&panel_simple_dsi_driver);
2334 platform_driver_unregister(&panel_simple_platform_driver);
2336 module_exit(panel_simple_exit);
2338 MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>");
2339 MODULE_DESCRIPTION("DRM Driver for Simple Panels");
2340 MODULE_LICENSE("GPL and additional rights");