2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
23 * Authors: Dave Airlie
27 #include <drm/drm_crtc_helper.h>
28 #include <drm/radeon_drm.h>
29 #include <drm/drm_fixed.h>
32 #include "atom-bits.h"
34 static void atombios_overscan_setup(struct drm_crtc *crtc,
35 struct drm_display_mode *mode,
36 struct drm_display_mode *adjusted_mode)
38 struct drm_device *dev = crtc->dev;
39 struct radeon_device *rdev = dev->dev_private;
40 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
41 SET_CRTC_OVERSCAN_PS_ALLOCATION args;
42 int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_OverScan);
45 memset(&args, 0, sizeof(args));
47 args.ucCRTC = radeon_crtc->crtc_id;
49 switch (radeon_crtc->rmx_type) {
51 args.usOverscanTop = (adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2;
52 args.usOverscanBottom = (adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2;
53 args.usOverscanLeft = (adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2;
54 args.usOverscanRight = (adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2;
57 a1 = mode->crtc_vdisplay * adjusted_mode->crtc_hdisplay;
58 a2 = adjusted_mode->crtc_vdisplay * mode->crtc_hdisplay;
61 args.usOverscanLeft = (adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2;
62 args.usOverscanRight = (adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2;
64 args.usOverscanLeft = (adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2;
65 args.usOverscanRight = (adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2;
70 args.usOverscanRight = radeon_crtc->h_border;
71 args.usOverscanLeft = radeon_crtc->h_border;
72 args.usOverscanBottom = radeon_crtc->v_border;
73 args.usOverscanTop = radeon_crtc->v_border;
76 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
79 static void atombios_scaler_setup(struct drm_crtc *crtc)
81 struct drm_device *dev = crtc->dev;
82 struct radeon_device *rdev = dev->dev_private;
83 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
84 ENABLE_SCALER_PS_ALLOCATION args;
85 int index = GetIndexIntoMasterTable(COMMAND, EnableScaler);
87 /* fixme - fill in enc_priv for atom dac */
88 enum radeon_tv_std tv_std = TV_STD_NTSC;
89 bool is_tv = false, is_cv = false;
90 struct drm_encoder *encoder;
92 if (!ASIC_IS_AVIVO(rdev) && radeon_crtc->crtc_id)
95 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
97 if (encoder->crtc == crtc) {
98 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
99 if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) {
100 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv;
101 tv_std = tv_dac->tv_std;
107 memset(&args, 0, sizeof(args));
109 args.ucScaler = radeon_crtc->crtc_id;
115 args.ucTVStandard = ATOM_TV_NTSC;
118 args.ucTVStandard = ATOM_TV_PAL;
121 args.ucTVStandard = ATOM_TV_PALM;
124 args.ucTVStandard = ATOM_TV_PAL60;
127 args.ucTVStandard = ATOM_TV_NTSCJ;
129 case TV_STD_SCART_PAL:
130 args.ucTVStandard = ATOM_TV_PAL; /* ??? */
133 args.ucTVStandard = ATOM_TV_SECAM;
136 args.ucTVStandard = ATOM_TV_PALCN;
139 args.ucEnable = SCALER_ENABLE_MULTITAP_MODE;
141 args.ucTVStandard = ATOM_TV_CV;
142 args.ucEnable = SCALER_ENABLE_MULTITAP_MODE;
144 switch (radeon_crtc->rmx_type) {
146 args.ucEnable = ATOM_SCALER_EXPANSION;
149 args.ucEnable = ATOM_SCALER_CENTER;
152 args.ucEnable = ATOM_SCALER_EXPANSION;
155 if (ASIC_IS_AVIVO(rdev))
156 args.ucEnable = ATOM_SCALER_DISABLE;
158 args.ucEnable = ATOM_SCALER_CENTER;
162 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
164 && rdev->family >= CHIP_RV515 && rdev->family <= CHIP_R580) {
165 atom_rv515_force_tv_scaler(rdev, radeon_crtc);
169 static void atombios_lock_crtc(struct drm_crtc *crtc, int lock)
171 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
172 struct drm_device *dev = crtc->dev;
173 struct radeon_device *rdev = dev->dev_private;
175 GetIndexIntoMasterTable(COMMAND, UpdateCRTC_DoubleBufferRegisters);
176 ENABLE_CRTC_PS_ALLOCATION args;
178 memset(&args, 0, sizeof(args));
180 args.ucCRTC = radeon_crtc->crtc_id;
181 args.ucEnable = lock;
183 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
186 static void atombios_enable_crtc(struct drm_crtc *crtc, int state)
188 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
189 struct drm_device *dev = crtc->dev;
190 struct radeon_device *rdev = dev->dev_private;
191 int index = GetIndexIntoMasterTable(COMMAND, EnableCRTC);
192 ENABLE_CRTC_PS_ALLOCATION args;
194 memset(&args, 0, sizeof(args));
196 args.ucCRTC = radeon_crtc->crtc_id;
197 args.ucEnable = state;
199 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
202 static void atombios_enable_crtc_memreq(struct drm_crtc *crtc, int state)
204 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
205 struct drm_device *dev = crtc->dev;
206 struct radeon_device *rdev = dev->dev_private;
207 int index = GetIndexIntoMasterTable(COMMAND, EnableCRTCMemReq);
208 ENABLE_CRTC_PS_ALLOCATION args;
210 memset(&args, 0, sizeof(args));
212 args.ucCRTC = radeon_crtc->crtc_id;
213 args.ucEnable = state;
215 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
218 static void atombios_blank_crtc(struct drm_crtc *crtc, int state)
220 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
221 struct drm_device *dev = crtc->dev;
222 struct radeon_device *rdev = dev->dev_private;
223 int index = GetIndexIntoMasterTable(COMMAND, BlankCRTC);
224 BLANK_CRTC_PS_ALLOCATION args;
226 memset(&args, 0, sizeof(args));
228 args.ucCRTC = radeon_crtc->crtc_id;
229 args.ucBlanking = state;
231 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
234 void atombios_crtc_dpms(struct drm_crtc *crtc, int mode)
236 struct drm_device *dev = crtc->dev;
237 struct radeon_device *rdev = dev->dev_private;
238 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
241 case DRM_MODE_DPMS_ON:
242 radeon_crtc->enabled = true;
243 /* adjust pm to dpms changes BEFORE enabling crtcs */
244 radeon_pm_compute_clocks(rdev);
245 atombios_enable_crtc(crtc, ATOM_ENABLE);
246 if (ASIC_IS_DCE3(rdev))
247 atombios_enable_crtc_memreq(crtc, ATOM_ENABLE);
248 atombios_blank_crtc(crtc, ATOM_DISABLE);
249 drm_vblank_post_modeset(dev, radeon_crtc->crtc_id);
250 radeon_crtc_load_lut(crtc);
252 case DRM_MODE_DPMS_STANDBY:
253 case DRM_MODE_DPMS_SUSPEND:
254 case DRM_MODE_DPMS_OFF:
255 drm_vblank_pre_modeset(dev, radeon_crtc->crtc_id);
256 atombios_blank_crtc(crtc, ATOM_ENABLE);
257 if (ASIC_IS_DCE3(rdev))
258 atombios_enable_crtc_memreq(crtc, ATOM_DISABLE);
259 atombios_enable_crtc(crtc, ATOM_DISABLE);
260 radeon_crtc->enabled = false;
261 /* adjust pm to dpms changes AFTER disabling crtcs */
262 radeon_pm_compute_clocks(rdev);
268 atombios_set_crtc_dtd_timing(struct drm_crtc *crtc,
269 struct drm_display_mode *mode)
271 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
272 struct drm_device *dev = crtc->dev;
273 struct radeon_device *rdev = dev->dev_private;
274 SET_CRTC_USING_DTD_TIMING_PARAMETERS args;
275 int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_UsingDTDTiming);
278 memset(&args, 0, sizeof(args));
279 args.usH_Size = cpu_to_le16(mode->crtc_hdisplay - (radeon_crtc->h_border * 2));
280 args.usH_Blanking_Time =
281 cpu_to_le16(mode->crtc_hblank_end - mode->crtc_hdisplay + (radeon_crtc->h_border * 2));
282 args.usV_Size = cpu_to_le16(mode->crtc_vdisplay - (radeon_crtc->v_border * 2));
283 args.usV_Blanking_Time =
284 cpu_to_le16(mode->crtc_vblank_end - mode->crtc_vdisplay + (radeon_crtc->v_border * 2));
285 args.usH_SyncOffset =
286 cpu_to_le16(mode->crtc_hsync_start - mode->crtc_hdisplay + radeon_crtc->h_border);
288 cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start);
289 args.usV_SyncOffset =
290 cpu_to_le16(mode->crtc_vsync_start - mode->crtc_vdisplay + radeon_crtc->v_border);
292 cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start);
293 args.ucH_Border = radeon_crtc->h_border;
294 args.ucV_Border = radeon_crtc->v_border;
296 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
297 misc |= ATOM_VSYNC_POLARITY;
298 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
299 misc |= ATOM_HSYNC_POLARITY;
300 if (mode->flags & DRM_MODE_FLAG_CSYNC)
301 misc |= ATOM_COMPOSITESYNC;
302 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
303 misc |= ATOM_INTERLACE;
304 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
305 misc |= ATOM_DOUBLE_CLOCK_MODE;
307 args.susModeMiscInfo.usAccess = cpu_to_le16(misc);
308 args.ucCRTC = radeon_crtc->crtc_id;
310 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
313 static void atombios_crtc_set_timing(struct drm_crtc *crtc,
314 struct drm_display_mode *mode)
316 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
317 struct drm_device *dev = crtc->dev;
318 struct radeon_device *rdev = dev->dev_private;
319 SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION args;
320 int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_Timing);
323 memset(&args, 0, sizeof(args));
324 args.usH_Total = cpu_to_le16(mode->crtc_htotal);
325 args.usH_Disp = cpu_to_le16(mode->crtc_hdisplay);
326 args.usH_SyncStart = cpu_to_le16(mode->crtc_hsync_start);
328 cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start);
329 args.usV_Total = cpu_to_le16(mode->crtc_vtotal);
330 args.usV_Disp = cpu_to_le16(mode->crtc_vdisplay);
331 args.usV_SyncStart = cpu_to_le16(mode->crtc_vsync_start);
333 cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start);
335 args.ucOverscanRight = radeon_crtc->h_border;
336 args.ucOverscanLeft = radeon_crtc->h_border;
337 args.ucOverscanBottom = radeon_crtc->v_border;
338 args.ucOverscanTop = radeon_crtc->v_border;
340 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
341 misc |= ATOM_VSYNC_POLARITY;
342 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
343 misc |= ATOM_HSYNC_POLARITY;
344 if (mode->flags & DRM_MODE_FLAG_CSYNC)
345 misc |= ATOM_COMPOSITESYNC;
346 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
347 misc |= ATOM_INTERLACE;
348 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
349 misc |= ATOM_DOUBLE_CLOCK_MODE;
351 args.susModeMiscInfo.usAccess = cpu_to_le16(misc);
352 args.ucCRTC = radeon_crtc->crtc_id;
354 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
357 static void atombios_disable_ss(struct drm_crtc *crtc)
359 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
360 struct drm_device *dev = crtc->dev;
361 struct radeon_device *rdev = dev->dev_private;
364 if (ASIC_IS_DCE4(rdev)) {
365 switch (radeon_crtc->pll_id) {
367 ss_cntl = RREG32(EVERGREEN_P1PLL_SS_CNTL);
368 ss_cntl &= ~EVERGREEN_PxPLL_SS_EN;
369 WREG32(EVERGREEN_P1PLL_SS_CNTL, ss_cntl);
372 ss_cntl = RREG32(EVERGREEN_P2PLL_SS_CNTL);
373 ss_cntl &= ~EVERGREEN_PxPLL_SS_EN;
374 WREG32(EVERGREEN_P2PLL_SS_CNTL, ss_cntl);
377 case ATOM_PPLL_INVALID:
380 } else if (ASIC_IS_AVIVO(rdev)) {
381 switch (radeon_crtc->pll_id) {
383 ss_cntl = RREG32(AVIVO_P1PLL_INT_SS_CNTL);
385 WREG32(AVIVO_P1PLL_INT_SS_CNTL, ss_cntl);
388 ss_cntl = RREG32(AVIVO_P2PLL_INT_SS_CNTL);
390 WREG32(AVIVO_P2PLL_INT_SS_CNTL, ss_cntl);
393 case ATOM_PPLL_INVALID:
400 union atom_enable_ss {
401 ENABLE_LVDS_SS_PARAMETERS lvds_ss;
402 ENABLE_LVDS_SS_PARAMETERS_V2 lvds_ss_2;
403 ENABLE_SPREAD_SPECTRUM_ON_PPLL_PS_ALLOCATION v1;
404 ENABLE_SPREAD_SPECTRUM_ON_PPLL_V2 v2;
407 static void atombios_crtc_program_ss(struct drm_crtc *crtc,
410 struct radeon_atom_ss *ss)
412 struct drm_device *dev = crtc->dev;
413 struct radeon_device *rdev = dev->dev_private;
414 int index = GetIndexIntoMasterTable(COMMAND, EnableSpreadSpectrumOnPPLL);
415 union atom_enable_ss args;
417 memset(&args, 0, sizeof(args));
419 if (ASIC_IS_DCE4(rdev)) {
420 args.v2.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
421 args.v2.ucSpreadSpectrumType = ss->type;
424 args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_P1PLL;
425 args.v2.usSpreadSpectrumAmount = ss->amount;
426 args.v2.usSpreadSpectrumStep = ss->step;
429 args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_P2PLL;
430 args.v2.usSpreadSpectrumAmount = ss->amount;
431 args.v2.usSpreadSpectrumStep = ss->step;
434 args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_DCPLL;
435 args.v2.usSpreadSpectrumAmount = 0;
436 args.v2.usSpreadSpectrumStep = 0;
438 case ATOM_PPLL_INVALID:
441 args.v2.ucEnable = enable;
442 } else if (ASIC_IS_DCE3(rdev)) {
443 args.v1.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
444 args.v1.ucSpreadSpectrumType = ss->type;
445 args.v1.ucSpreadSpectrumStep = ss->step;
446 args.v1.ucSpreadSpectrumDelay = ss->delay;
447 args.v1.ucSpreadSpectrumRange = ss->range;
448 args.v1.ucPpll = pll_id;
449 args.v1.ucEnable = enable;
450 } else if (ASIC_IS_AVIVO(rdev)) {
451 if (enable == ATOM_DISABLE) {
452 atombios_disable_ss(crtc);
455 args.lvds_ss_2.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
456 args.lvds_ss_2.ucSpreadSpectrumType = ss->type;
457 args.lvds_ss_2.ucSpreadSpectrumStep = ss->step;
458 args.lvds_ss_2.ucSpreadSpectrumDelay = ss->delay;
459 args.lvds_ss_2.ucSpreadSpectrumRange = ss->range;
460 args.lvds_ss_2.ucEnable = enable;
462 if (enable == ATOM_DISABLE) {
463 atombios_disable_ss(crtc);
466 args.lvds_ss.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
467 args.lvds_ss.ucSpreadSpectrumType = ss->type;
468 args.lvds_ss.ucSpreadSpectrumStepSize_Delay = (ss->step & 3) << 2;
469 args.lvds_ss.ucSpreadSpectrumStepSize_Delay |= (ss->delay & 7) << 4;
470 args.lvds_ss.ucEnable = enable;
472 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
475 union adjust_pixel_clock {
476 ADJUST_DISPLAY_PLL_PS_ALLOCATION v1;
477 ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3 v3;
480 static u32 atombios_adjust_pll(struct drm_crtc *crtc,
481 struct drm_display_mode *mode,
482 struct radeon_pll *pll,
484 struct radeon_atom_ss *ss)
486 struct drm_device *dev = crtc->dev;
487 struct radeon_device *rdev = dev->dev_private;
488 struct drm_encoder *encoder = NULL;
489 struct radeon_encoder *radeon_encoder = NULL;
490 u32 adjusted_clock = mode->clock;
491 int encoder_mode = 0;
492 u32 dp_clock = mode->clock;
495 /* reset the pll flags */
498 if (ASIC_IS_AVIVO(rdev)) {
499 if ((rdev->family == CHIP_RS600) ||
500 (rdev->family == CHIP_RS690) ||
501 (rdev->family == CHIP_RS740))
502 pll->flags |= (/*RADEON_PLL_USE_FRAC_FB_DIV |*/
503 RADEON_PLL_PREFER_CLOSEST_LOWER);
505 pll->flags |= RADEON_PLL_LEGACY;
507 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
508 if (encoder->crtc == crtc) {
509 radeon_encoder = to_radeon_encoder(encoder);
510 encoder_mode = atombios_get_encoder_mode(encoder);
511 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) {
512 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
514 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
515 struct radeon_connector_atom_dig *dig_connector =
516 radeon_connector->con_priv;
518 dp_clock = dig_connector->dp_clock;
522 /* use recommended ref_div for ss */
523 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
526 pll->flags |= RADEON_PLL_USE_REF_DIV;
527 pll->reference_div = ss->refdiv;
532 if (ASIC_IS_AVIVO(rdev)) {
533 /* DVO wants 2x pixel clock if the DVO chip is in 12 bit mode */
534 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1)
535 adjusted_clock = mode->clock * 2;
536 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
537 pll->flags |= RADEON_PLL_PREFER_CLOSEST_LOWER;
539 if (encoder->encoder_type != DRM_MODE_ENCODER_DAC)
540 pll->flags |= RADEON_PLL_NO_ODD_POST_DIV;
541 if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS)
542 pll->flags |= RADEON_PLL_USE_REF_DIV;
548 /* DCE3+ has an AdjustDisplayPll that will adjust the pixel clock
549 * accordingly based on the encoder/transmitter to work around
550 * special hw requirements.
552 if (ASIC_IS_DCE3(rdev)) {
553 union adjust_pixel_clock args;
557 index = GetIndexIntoMasterTable(COMMAND, AdjustDisplayPll);
558 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
560 return adjusted_clock;
562 memset(&args, 0, sizeof(args));
569 args.v1.usPixelClock = cpu_to_le16(mode->clock / 10);
570 args.v1.ucTransmitterID = radeon_encoder->encoder_id;
571 args.v1.ucEncodeMode = encoder_mode;
572 if (encoder_mode == ATOM_ENCODER_MODE_DP) {
575 ADJUST_DISPLAY_CONFIG_SS_ENABLE;
576 } else if (encoder_mode == ATOM_ENCODER_MODE_LVDS) {
578 ADJUST_DISPLAY_CONFIG_SS_ENABLE;
581 atom_execute_table(rdev->mode_info.atom_context,
582 index, (uint32_t *)&args);
583 adjusted_clock = le16_to_cpu(args.v1.usPixelClock) * 10;
586 args.v3.sInput.usPixelClock = cpu_to_le16(mode->clock / 10);
587 args.v3.sInput.ucTransmitterID = radeon_encoder->encoder_id;
588 args.v3.sInput.ucEncodeMode = encoder_mode;
589 args.v3.sInput.ucDispPllConfig = 0;
590 if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
591 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
592 if (encoder_mode == ATOM_ENCODER_MODE_DP) {
594 args.v3.sInput.ucDispPllConfig |=
595 DISPPLL_CONFIG_SS_ENABLE;
596 args.v3.sInput.ucDispPllConfig |=
597 DISPPLL_CONFIG_COHERENT_MODE;
599 args.v3.sInput.usPixelClock = cpu_to_le16(dp_clock / 10);
601 if (encoder_mode == ATOM_ENCODER_MODE_HDMI) {
602 /* deep color support */
603 args.v3.sInput.usPixelClock =
604 cpu_to_le16((mode->clock * bpc / 8) / 10);
606 if (dig->coherent_mode)
607 args.v3.sInput.ucDispPllConfig |=
608 DISPPLL_CONFIG_COHERENT_MODE;
609 if (mode->clock > 165000)
610 args.v3.sInput.ucDispPllConfig |=
611 DISPPLL_CONFIG_DUAL_LINK;
613 } else if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
614 if (encoder_mode == ATOM_ENCODER_MODE_DP) {
616 args.v3.sInput.ucDispPllConfig |=
617 DISPPLL_CONFIG_SS_ENABLE;
618 args.v3.sInput.ucDispPllConfig |=
619 DISPPLL_CONFIG_COHERENT_MODE;
621 args.v3.sInput.usPixelClock = cpu_to_le16(dp_clock / 10);
622 } else if (encoder_mode == ATOM_ENCODER_MODE_LVDS) {
624 args.v3.sInput.ucDispPllConfig |=
625 DISPPLL_CONFIG_SS_ENABLE;
627 if (mode->clock > 165000)
628 args.v3.sInput.ucDispPllConfig |=
629 DISPPLL_CONFIG_DUAL_LINK;
632 atom_execute_table(rdev->mode_info.atom_context,
633 index, (uint32_t *)&args);
634 adjusted_clock = le32_to_cpu(args.v3.sOutput.ulDispPllFreq) * 10;
635 if (args.v3.sOutput.ucRefDiv) {
636 pll->flags |= RADEON_PLL_USE_REF_DIV;
637 pll->reference_div = args.v3.sOutput.ucRefDiv;
639 if (args.v3.sOutput.ucPostDiv) {
640 pll->flags |= RADEON_PLL_USE_POST_DIV;
641 pll->post_div = args.v3.sOutput.ucPostDiv;
645 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
646 return adjusted_clock;
650 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
651 return adjusted_clock;
654 return adjusted_clock;
657 union set_pixel_clock {
658 SET_PIXEL_CLOCK_PS_ALLOCATION base;
659 PIXEL_CLOCK_PARAMETERS v1;
660 PIXEL_CLOCK_PARAMETERS_V2 v2;
661 PIXEL_CLOCK_PARAMETERS_V3 v3;
662 PIXEL_CLOCK_PARAMETERS_V5 v5;
665 static void atombios_crtc_set_dcpll(struct drm_crtc *crtc)
667 struct drm_device *dev = crtc->dev;
668 struct radeon_device *rdev = dev->dev_private;
671 union set_pixel_clock args;
673 memset(&args, 0, sizeof(args));
675 index = GetIndexIntoMasterTable(COMMAND, SetPixelClock);
676 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
684 /* if the default dcpll clock is specified,
685 * SetPixelClock provides the dividers
687 args.v5.ucCRTC = ATOM_CRTC_INVALID;
688 args.v5.usPixelClock = rdev->clock.default_dispclk;
689 args.v5.ucPpll = ATOM_DCPLL;
692 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
697 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
700 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
703 static void atombios_crtc_program_pll(struct drm_crtc *crtc,
714 struct drm_device *dev = crtc->dev;
715 struct radeon_device *rdev = dev->dev_private;
717 int index = GetIndexIntoMasterTable(COMMAND, SetPixelClock);
718 union set_pixel_clock args;
720 memset(&args, 0, sizeof(args));
722 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
730 if (clock == ATOM_DISABLE)
732 args.v1.usPixelClock = cpu_to_le16(clock / 10);
733 args.v1.usRefDiv = cpu_to_le16(ref_div);
734 args.v1.usFbDiv = cpu_to_le16(fb_div);
735 args.v1.ucFracFbDiv = frac_fb_div;
736 args.v1.ucPostDiv = post_div;
737 args.v1.ucPpll = pll_id;
738 args.v1.ucCRTC = crtc_id;
739 args.v1.ucRefDivSrc = 1;
742 args.v2.usPixelClock = cpu_to_le16(clock / 10);
743 args.v2.usRefDiv = cpu_to_le16(ref_div);
744 args.v2.usFbDiv = cpu_to_le16(fb_div);
745 args.v2.ucFracFbDiv = frac_fb_div;
746 args.v2.ucPostDiv = post_div;
747 args.v2.ucPpll = pll_id;
748 args.v2.ucCRTC = crtc_id;
749 args.v2.ucRefDivSrc = 1;
752 args.v3.usPixelClock = cpu_to_le16(clock / 10);
753 args.v3.usRefDiv = cpu_to_le16(ref_div);
754 args.v3.usFbDiv = cpu_to_le16(fb_div);
755 args.v3.ucFracFbDiv = frac_fb_div;
756 args.v3.ucPostDiv = post_div;
757 args.v3.ucPpll = pll_id;
758 args.v3.ucMiscInfo = (pll_id << 2);
759 args.v3.ucTransmitterId = encoder_id;
760 args.v3.ucEncoderMode = encoder_mode;
763 args.v5.ucCRTC = crtc_id;
764 args.v5.usPixelClock = cpu_to_le16(clock / 10);
765 args.v5.ucRefDiv = ref_div;
766 args.v5.usFbDiv = cpu_to_le16(fb_div);
767 args.v5.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000);
768 args.v5.ucPostDiv = post_div;
769 args.v5.ucMiscInfo = 0; /* HDMI depth, etc. */
770 args.v5.ucTransmitterID = encoder_id;
771 args.v5.ucEncoderMode = encoder_mode;
772 args.v5.ucPpll = pll_id;
775 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
780 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
784 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
787 static void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
789 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
790 struct drm_device *dev = crtc->dev;
791 struct radeon_device *rdev = dev->dev_private;
792 struct drm_encoder *encoder = NULL;
793 struct radeon_encoder *radeon_encoder = NULL;
794 u32 pll_clock = mode->clock;
795 u32 ref_div = 0, fb_div = 0, frac_fb_div = 0, post_div = 0;
796 struct radeon_pll *pll;
798 int encoder_mode = 0;
799 struct radeon_atom_ss ss;
800 bool ss_enabled = false;
802 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
803 if (encoder->crtc == crtc) {
804 radeon_encoder = to_radeon_encoder(encoder);
805 encoder_mode = atombios_get_encoder_mode(encoder);
813 switch (radeon_crtc->pll_id) {
815 pll = &rdev->clock.p1pll;
818 pll = &rdev->clock.p2pll;
821 case ATOM_PPLL_INVALID:
823 pll = &rdev->clock.dcpll;
827 if (radeon_encoder->active_device &
828 (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) {
829 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
830 struct drm_connector *connector =
831 radeon_get_connector_for_encoder(encoder);
832 struct radeon_connector *radeon_connector =
833 to_radeon_connector(connector);
834 struct radeon_connector_atom_dig *dig_connector =
835 radeon_connector->con_priv;
838 switch (encoder_mode) {
839 case ATOM_ENCODER_MODE_DP:
841 dp_clock = dig_connector->dp_clock / 10;
842 if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT)) {
843 if (ASIC_IS_DCE4(rdev))
845 radeon_atombios_get_asic_ss_info(rdev, &ss,
850 radeon_atombios_get_ppll_ss_info(rdev, &ss,
853 if (ASIC_IS_DCE4(rdev))
855 radeon_atombios_get_asic_ss_info(rdev, &ss,
856 ASIC_INTERNAL_SS_ON_DP,
859 if (dp_clock == 16200) {
861 radeon_atombios_get_ppll_ss_info(rdev, &ss,
865 radeon_atombios_get_ppll_ss_info(rdev, &ss,
869 radeon_atombios_get_ppll_ss_info(rdev, &ss,
874 case ATOM_ENCODER_MODE_LVDS:
875 if (ASIC_IS_DCE4(rdev))
876 ss_enabled = radeon_atombios_get_asic_ss_info(rdev, &ss,
880 ss_enabled = radeon_atombios_get_ppll_ss_info(rdev, &ss,
883 case ATOM_ENCODER_MODE_DVI:
884 if (ASIC_IS_DCE4(rdev))
886 radeon_atombios_get_asic_ss_info(rdev, &ss,
887 ASIC_INTERNAL_SS_ON_TMDS,
890 case ATOM_ENCODER_MODE_HDMI:
891 if (ASIC_IS_DCE4(rdev))
893 radeon_atombios_get_asic_ss_info(rdev, &ss,
894 ASIC_INTERNAL_SS_ON_HDMI,
902 /* adjust pixel clock as needed */
903 adjusted_clock = atombios_adjust_pll(crtc, mode, pll, ss_enabled, &ss);
905 radeon_compute_pll(pll, adjusted_clock, &pll_clock, &fb_div, &frac_fb_div,
906 &ref_div, &post_div);
908 atombios_crtc_program_ss(crtc, ATOM_DISABLE, radeon_crtc->pll_id, &ss);
910 atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id,
911 encoder_mode, radeon_encoder->encoder_id, mode->clock,
912 ref_div, fb_div, frac_fb_div, post_div);
915 /* calculate ss amount and step size */
916 if (ASIC_IS_DCE4(rdev)) {
918 u32 amount = (((fb_div * 10) + frac_fb_div) * ss.percentage) / 10000;
919 ss.amount = (amount / 10) & ATOM_PPLL_SS_AMOUNT_V2_FBDIV_MASK;
920 ss.amount |= ((amount - (ss.amount * 10)) << ATOM_PPLL_SS_AMOUNT_V2_NFRAC_SHIFT) &
921 ATOM_PPLL_SS_AMOUNT_V2_NFRAC_MASK;
922 if (ss.type & ATOM_PPLL_SS_TYPE_V2_CENTRE_SPREAD)
923 step_size = (4 * amount * ref_div * (ss.rate * 2048)) /
924 (125 * 25 * pll->reference_freq / 100);
926 step_size = (2 * amount * ref_div * (ss.rate * 2048)) /
927 (125 * 25 * pll->reference_freq / 100);
931 atombios_crtc_program_ss(crtc, ATOM_ENABLE, radeon_crtc->pll_id, &ss);
935 static int evergreen_crtc_do_set_base(struct drm_crtc *crtc,
936 struct drm_framebuffer *fb,
937 int x, int y, int atomic)
939 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
940 struct drm_device *dev = crtc->dev;
941 struct radeon_device *rdev = dev->dev_private;
942 struct radeon_framebuffer *radeon_fb;
943 struct drm_framebuffer *target_fb;
944 struct drm_gem_object *obj;
945 struct radeon_bo *rbo;
946 uint64_t fb_location;
947 uint32_t fb_format, fb_pitch_pixels, tiling_flags;
951 if (!atomic && !crtc->fb) {
952 DRM_DEBUG_KMS("No FB bound\n");
957 radeon_fb = to_radeon_framebuffer(fb);
961 radeon_fb = to_radeon_framebuffer(crtc->fb);
962 target_fb = crtc->fb;
965 /* If atomic, assume fb object is pinned & idle & fenced and
966 * just update base pointers
968 obj = radeon_fb->obj;
969 rbo = obj->driver_private;
970 r = radeon_bo_reserve(rbo, false);
971 if (unlikely(r != 0))
975 fb_location = radeon_bo_gpu_offset(rbo);
977 r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location);
978 if (unlikely(r != 0)) {
979 radeon_bo_unreserve(rbo);
984 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
985 radeon_bo_unreserve(rbo);
987 switch (target_fb->bits_per_pixel) {
989 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_8BPP) |
990 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_INDEXED));
993 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) |
994 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB1555));
997 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) |
998 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB565));
1002 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) |
1003 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB8888));
1006 DRM_ERROR("Unsupported screen depth %d\n",
1007 target_fb->bits_per_pixel);
1011 if (tiling_flags & RADEON_TILING_MACRO)
1012 fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_2D_TILED_THIN1);
1013 else if (tiling_flags & RADEON_TILING_MICRO)
1014 fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_1D_TILED_THIN1);
1016 switch (radeon_crtc->crtc_id) {
1018 WREG32(AVIVO_D1VGA_CONTROL, 0);
1021 WREG32(AVIVO_D2VGA_CONTROL, 0);
1024 WREG32(EVERGREEN_D3VGA_CONTROL, 0);
1027 WREG32(EVERGREEN_D4VGA_CONTROL, 0);
1030 WREG32(EVERGREEN_D5VGA_CONTROL, 0);
1033 WREG32(EVERGREEN_D6VGA_CONTROL, 0);
1039 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
1040 upper_32_bits(fb_location));
1041 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
1042 upper_32_bits(fb_location));
1043 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
1044 (u32)fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK);
1045 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
1046 (u32) fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK);
1047 WREG32(EVERGREEN_GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format);
1049 WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0);
1050 WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0);
1051 WREG32(EVERGREEN_GRPH_X_START + radeon_crtc->crtc_offset, 0);
1052 WREG32(EVERGREEN_GRPH_Y_START + radeon_crtc->crtc_offset, 0);
1053 WREG32(EVERGREEN_GRPH_X_END + radeon_crtc->crtc_offset, target_fb->width);
1054 WREG32(EVERGREEN_GRPH_Y_END + radeon_crtc->crtc_offset, target_fb->height);
1056 fb_pitch_pixels = target_fb->pitch / (target_fb->bits_per_pixel / 8);
1057 WREG32(EVERGREEN_GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels);
1058 WREG32(EVERGREEN_GRPH_ENABLE + radeon_crtc->crtc_offset, 1);
1060 WREG32(EVERGREEN_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,
1061 crtc->mode.vdisplay);
1064 WREG32(EVERGREEN_VIEWPORT_START + radeon_crtc->crtc_offset,
1066 WREG32(EVERGREEN_VIEWPORT_SIZE + radeon_crtc->crtc_offset,
1067 (crtc->mode.hdisplay << 16) | crtc->mode.vdisplay);
1069 if (crtc->mode.flags & DRM_MODE_FLAG_INTERLACE)
1070 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset,
1071 EVERGREEN_INTERLEAVE_EN);
1073 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
1075 if (!atomic && fb && fb != crtc->fb) {
1076 radeon_fb = to_radeon_framebuffer(fb);
1077 rbo = radeon_fb->obj->driver_private;
1078 r = radeon_bo_reserve(rbo, false);
1079 if (unlikely(r != 0))
1081 radeon_bo_unpin(rbo);
1082 radeon_bo_unreserve(rbo);
1085 /* Bytes per pixel may have changed */
1086 radeon_bandwidth_update(rdev);
1091 static int avivo_crtc_do_set_base(struct drm_crtc *crtc,
1092 struct drm_framebuffer *fb,
1093 int x, int y, int atomic)
1095 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1096 struct drm_device *dev = crtc->dev;
1097 struct radeon_device *rdev = dev->dev_private;
1098 struct radeon_framebuffer *radeon_fb;
1099 struct drm_gem_object *obj;
1100 struct radeon_bo *rbo;
1101 struct drm_framebuffer *target_fb;
1102 uint64_t fb_location;
1103 uint32_t fb_format, fb_pitch_pixels, tiling_flags;
1107 if (!atomic && !crtc->fb) {
1108 DRM_DEBUG_KMS("No FB bound\n");
1113 radeon_fb = to_radeon_framebuffer(fb);
1117 radeon_fb = to_radeon_framebuffer(crtc->fb);
1118 target_fb = crtc->fb;
1121 obj = radeon_fb->obj;
1122 rbo = obj->driver_private;
1123 r = radeon_bo_reserve(rbo, false);
1124 if (unlikely(r != 0))
1127 /* If atomic, assume fb object is pinned & idle & fenced and
1128 * just update base pointers
1131 fb_location = radeon_bo_gpu_offset(rbo);
1133 r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location);
1134 if (unlikely(r != 0)) {
1135 radeon_bo_unreserve(rbo);
1139 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
1140 radeon_bo_unreserve(rbo);
1142 switch (target_fb->bits_per_pixel) {
1145 AVIVO_D1GRPH_CONTROL_DEPTH_8BPP |
1146 AVIVO_D1GRPH_CONTROL_8BPP_INDEXED;
1150 AVIVO_D1GRPH_CONTROL_DEPTH_16BPP |
1151 AVIVO_D1GRPH_CONTROL_16BPP_ARGB1555;
1155 AVIVO_D1GRPH_CONTROL_DEPTH_16BPP |
1156 AVIVO_D1GRPH_CONTROL_16BPP_RGB565;
1161 AVIVO_D1GRPH_CONTROL_DEPTH_32BPP |
1162 AVIVO_D1GRPH_CONTROL_32BPP_ARGB8888;
1165 DRM_ERROR("Unsupported screen depth %d\n",
1166 target_fb->bits_per_pixel);
1170 if (rdev->family >= CHIP_R600) {
1171 if (tiling_flags & RADEON_TILING_MACRO)
1172 fb_format |= R600_D1GRPH_ARRAY_MODE_2D_TILED_THIN1;
1173 else if (tiling_flags & RADEON_TILING_MICRO)
1174 fb_format |= R600_D1GRPH_ARRAY_MODE_1D_TILED_THIN1;
1176 if (tiling_flags & RADEON_TILING_MACRO)
1177 fb_format |= AVIVO_D1GRPH_MACRO_ADDRESS_MODE;
1179 if (tiling_flags & RADEON_TILING_MICRO)
1180 fb_format |= AVIVO_D1GRPH_TILED;
1183 if (radeon_crtc->crtc_id == 0)
1184 WREG32(AVIVO_D1VGA_CONTROL, 0);
1186 WREG32(AVIVO_D2VGA_CONTROL, 0);
1188 if (rdev->family >= CHIP_RV770) {
1189 if (radeon_crtc->crtc_id) {
1190 WREG32(R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
1191 WREG32(R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
1193 WREG32(R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
1194 WREG32(R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
1197 WREG32(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
1199 WREG32(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS +
1200 radeon_crtc->crtc_offset, (u32) fb_location);
1201 WREG32(AVIVO_D1GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format);
1203 WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0);
1204 WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0);
1205 WREG32(AVIVO_D1GRPH_X_START + radeon_crtc->crtc_offset, 0);
1206 WREG32(AVIVO_D1GRPH_Y_START + radeon_crtc->crtc_offset, 0);
1207 WREG32(AVIVO_D1GRPH_X_END + radeon_crtc->crtc_offset, target_fb->width);
1208 WREG32(AVIVO_D1GRPH_Y_END + radeon_crtc->crtc_offset, target_fb->height);
1210 fb_pitch_pixels = target_fb->pitch / (target_fb->bits_per_pixel / 8);
1211 WREG32(AVIVO_D1GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels);
1212 WREG32(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 1);
1214 WREG32(AVIVO_D1MODE_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,
1215 crtc->mode.vdisplay);
1218 WREG32(AVIVO_D1MODE_VIEWPORT_START + radeon_crtc->crtc_offset,
1220 WREG32(AVIVO_D1MODE_VIEWPORT_SIZE + radeon_crtc->crtc_offset,
1221 (crtc->mode.hdisplay << 16) | crtc->mode.vdisplay);
1223 if (crtc->mode.flags & DRM_MODE_FLAG_INTERLACE)
1224 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset,
1225 AVIVO_D1MODE_INTERLEAVE_EN);
1227 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
1229 if (!atomic && fb && fb != crtc->fb) {
1230 radeon_fb = to_radeon_framebuffer(fb);
1231 rbo = radeon_fb->obj->driver_private;
1232 r = radeon_bo_reserve(rbo, false);
1233 if (unlikely(r != 0))
1235 radeon_bo_unpin(rbo);
1236 radeon_bo_unreserve(rbo);
1239 /* Bytes per pixel may have changed */
1240 radeon_bandwidth_update(rdev);
1245 int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y,
1246 struct drm_framebuffer *old_fb)
1248 struct drm_device *dev = crtc->dev;
1249 struct radeon_device *rdev = dev->dev_private;
1251 if (ASIC_IS_DCE4(rdev))
1252 return evergreen_crtc_do_set_base(crtc, old_fb, x, y, 0);
1253 else if (ASIC_IS_AVIVO(rdev))
1254 return avivo_crtc_do_set_base(crtc, old_fb, x, y, 0);
1256 return radeon_crtc_do_set_base(crtc, old_fb, x, y, 0);
1259 int atombios_crtc_set_base_atomic(struct drm_crtc *crtc,
1260 struct drm_framebuffer *fb,
1261 int x, int y, int enter)
1263 struct drm_device *dev = crtc->dev;
1264 struct radeon_device *rdev = dev->dev_private;
1266 if (ASIC_IS_DCE4(rdev))
1267 return evergreen_crtc_do_set_base(crtc, fb, x, y, 1);
1268 else if (ASIC_IS_AVIVO(rdev))
1269 return avivo_crtc_do_set_base(crtc, fb, x, y, 1);
1271 return radeon_crtc_do_set_base(crtc, fb, x, y, 1);
1274 /* properly set additional regs when using atombios */
1275 static void radeon_legacy_atom_fixup(struct drm_crtc *crtc)
1277 struct drm_device *dev = crtc->dev;
1278 struct radeon_device *rdev = dev->dev_private;
1279 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1280 u32 disp_merge_cntl;
1282 switch (radeon_crtc->crtc_id) {
1284 disp_merge_cntl = RREG32(RADEON_DISP_MERGE_CNTL);
1285 disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN;
1286 WREG32(RADEON_DISP_MERGE_CNTL, disp_merge_cntl);
1289 disp_merge_cntl = RREG32(RADEON_DISP2_MERGE_CNTL);
1290 disp_merge_cntl &= ~RADEON_DISP2_RGB_OFFSET_EN;
1291 WREG32(RADEON_DISP2_MERGE_CNTL, disp_merge_cntl);
1292 WREG32(RADEON_FP_H2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_H_SYNC_STRT_WID));
1293 WREG32(RADEON_FP_V2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_V_SYNC_STRT_WID));
1298 static int radeon_atom_pick_pll(struct drm_crtc *crtc)
1300 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1301 struct drm_device *dev = crtc->dev;
1302 struct radeon_device *rdev = dev->dev_private;
1303 struct drm_encoder *test_encoder;
1304 struct drm_crtc *test_crtc;
1305 uint32_t pll_in_use = 0;
1307 if (ASIC_IS_DCE4(rdev)) {
1308 /* if crtc is driving DP and we have an ext clock, use that */
1309 list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) {
1310 if (test_encoder->crtc && (test_encoder->crtc == crtc)) {
1311 if (atombios_get_encoder_mode(test_encoder) == ATOM_ENCODER_MODE_DP) {
1312 if (rdev->clock.dp_extclk)
1313 return ATOM_PPLL_INVALID;
1318 /* otherwise, pick one of the plls */
1319 list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) {
1320 struct radeon_crtc *radeon_test_crtc;
1322 if (crtc == test_crtc)
1325 radeon_test_crtc = to_radeon_crtc(test_crtc);
1326 if ((radeon_test_crtc->pll_id >= ATOM_PPLL1) &&
1327 (radeon_test_crtc->pll_id <= ATOM_PPLL2))
1328 pll_in_use |= (1 << radeon_test_crtc->pll_id);
1330 if (!(pll_in_use & 1))
1334 return radeon_crtc->crtc_id;
1338 int atombios_crtc_mode_set(struct drm_crtc *crtc,
1339 struct drm_display_mode *mode,
1340 struct drm_display_mode *adjusted_mode,
1341 int x, int y, struct drm_framebuffer *old_fb)
1343 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1344 struct drm_device *dev = crtc->dev;
1345 struct radeon_device *rdev = dev->dev_private;
1346 struct drm_encoder *encoder;
1347 bool is_tvcv = false;
1349 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1351 if (encoder->crtc == crtc) {
1352 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1353 if (radeon_encoder->active_device &
1354 (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
1359 /* always set DCPLL */
1360 if (ASIC_IS_DCE4(rdev)) {
1361 struct radeon_atom_ss ss;
1362 bool ss_enabled = radeon_atombios_get_asic_ss_info(rdev, &ss,
1363 ASIC_INTERNAL_SS_ON_DCPLL,
1364 rdev->clock.default_dispclk);
1366 atombios_crtc_program_ss(crtc, ATOM_DISABLE, ATOM_DCPLL, &ss);
1367 atombios_crtc_set_dcpll(crtc);
1369 atombios_crtc_program_ss(crtc, ATOM_ENABLE, ATOM_DCPLL, &ss);
1371 atombios_crtc_set_pll(crtc, adjusted_mode);
1373 if (ASIC_IS_DCE4(rdev))
1374 atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
1375 else if (ASIC_IS_AVIVO(rdev)) {
1377 atombios_crtc_set_timing(crtc, adjusted_mode);
1379 atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
1381 atombios_crtc_set_timing(crtc, adjusted_mode);
1382 if (radeon_crtc->crtc_id == 0)
1383 atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
1384 radeon_legacy_atom_fixup(crtc);
1386 atombios_crtc_set_base(crtc, x, y, old_fb);
1387 atombios_overscan_setup(crtc, mode, adjusted_mode);
1388 atombios_scaler_setup(crtc);
1392 static bool atombios_crtc_mode_fixup(struct drm_crtc *crtc,
1393 struct drm_display_mode *mode,
1394 struct drm_display_mode *adjusted_mode)
1396 struct drm_device *dev = crtc->dev;
1397 struct radeon_device *rdev = dev->dev_private;
1399 /* adjust pm to upcoming mode change */
1400 radeon_pm_compute_clocks(rdev);
1402 if (!radeon_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
1407 static void atombios_crtc_prepare(struct drm_crtc *crtc)
1409 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1412 radeon_crtc->pll_id = radeon_atom_pick_pll(crtc);
1414 atombios_lock_crtc(crtc, ATOM_ENABLE);
1415 atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
1418 static void atombios_crtc_commit(struct drm_crtc *crtc)
1420 atombios_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
1421 atombios_lock_crtc(crtc, ATOM_DISABLE);
1424 static void atombios_crtc_disable(struct drm_crtc *crtc)
1426 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1427 atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
1429 switch (radeon_crtc->pll_id) {
1432 /* disable the ppll */
1433 atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id,
1434 0, 0, ATOM_DISABLE, 0, 0, 0, 0);
1439 radeon_crtc->pll_id = -1;
1442 static const struct drm_crtc_helper_funcs atombios_helper_funcs = {
1443 .dpms = atombios_crtc_dpms,
1444 .mode_fixup = atombios_crtc_mode_fixup,
1445 .mode_set = atombios_crtc_mode_set,
1446 .mode_set_base = atombios_crtc_set_base,
1447 .mode_set_base_atomic = atombios_crtc_set_base_atomic,
1448 .prepare = atombios_crtc_prepare,
1449 .commit = atombios_crtc_commit,
1450 .load_lut = radeon_crtc_load_lut,
1451 .disable = atombios_crtc_disable,
1454 void radeon_atombios_init_crtc(struct drm_device *dev,
1455 struct radeon_crtc *radeon_crtc)
1457 struct radeon_device *rdev = dev->dev_private;
1459 if (ASIC_IS_DCE4(rdev)) {
1460 switch (radeon_crtc->crtc_id) {
1463 radeon_crtc->crtc_offset = EVERGREEN_CRTC0_REGISTER_OFFSET;
1466 radeon_crtc->crtc_offset = EVERGREEN_CRTC1_REGISTER_OFFSET;
1469 radeon_crtc->crtc_offset = EVERGREEN_CRTC2_REGISTER_OFFSET;
1472 radeon_crtc->crtc_offset = EVERGREEN_CRTC3_REGISTER_OFFSET;
1475 radeon_crtc->crtc_offset = EVERGREEN_CRTC4_REGISTER_OFFSET;
1478 radeon_crtc->crtc_offset = EVERGREEN_CRTC5_REGISTER_OFFSET;
1482 if (radeon_crtc->crtc_id == 1)
1483 radeon_crtc->crtc_offset =
1484 AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL;
1486 radeon_crtc->crtc_offset = 0;
1488 radeon_crtc->pll_id = -1;
1489 drm_crtc_helper_add(&radeon_crtc->base, &atombios_helper_funcs);