drivers/gpu/drm/radeon/atombios_crtc.c

   1 /*
   2  * Copyright 2007-8 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Dave Airlie
  24  *          Alex Deucher
  25  */
  26 #include <drm/drmP.h>
  27 #include <drm/drm_crtc_helper.h>
  28 #include <drm/radeon_drm.h>
  29 #include "radeon_fixed.h"
  30 #include "radeon.h"
  31 #include "atom.h"
  32 #include "atom-bits.h"
  33
  34 static void atombios_overscan_setup(struct drm_crtc *crtc,
  35                                     struct drm_display_mode *mode,
  36                                     struct drm_display_mode *adjusted_mode)
  37 {
  38         struct drm_device *dev = crtc->dev;
  39         struct radeon_device *rdev = dev->dev_private;
  40         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
  41         SET_CRTC_OVERSCAN_PS_ALLOCATION args;
  42         int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_OverScan);
  43         int a1, a2;
  44
  45         memset(&args, 0, sizeof(args));
  46
  47         args.usOverscanRight = 0;
  48         args.usOverscanLeft = 0;
  49         args.usOverscanBottom = 0;
  50         args.usOverscanTop = 0;
  51         args.ucCRTC = radeon_crtc->crtc_id;
  52
  53         switch (radeon_crtc->rmx_type) {
  54         case RMX_CENTER:
  55                 args.usOverscanTop = (adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2;
  56                 args.usOverscanBottom = (adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2;
  57                 args.usOverscanLeft = (adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2;
  58                 args.usOverscanRight = (adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2;
  59                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
  60                 break;
  61         case RMX_ASPECT:
  62                 a1 = mode->crtc_vdisplay * adjusted_mode->crtc_hdisplay;
  63                 a2 = adjusted_mode->crtc_vdisplay * mode->crtc_hdisplay;
  64
  65                 if (a1 > a2) {
  66                         args.usOverscanLeft = (adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2;
  67                         args.usOverscanRight = (adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2;
  68                 } else if (a2 > a1) {
  69                         args.usOverscanLeft = (adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2;
  70                         args.usOverscanRight = (adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2;
  71                 }
  72                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
  73                 break;
  74         case RMX_FULL:
  75         default:
  76                 args.usOverscanRight = 0;
  77                 args.usOverscanLeft = 0;
  78                 args.usOverscanBottom = 0;
  79                 args.usOverscanTop = 0;
  80                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
  81                 break;
  82         }
  83 }
  84
  85 static void atombios_scaler_setup(struct drm_crtc *crtc)
  86 {
  87         struct drm_device *dev = crtc->dev;
  88         struct radeon_device *rdev = dev->dev_private;
  89         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
  90         ENABLE_SCALER_PS_ALLOCATION args;
  91         int index = GetIndexIntoMasterTable(COMMAND, EnableScaler);
  92
  93         /* fixme - fill in enc_priv for atom dac */
  94         enum radeon_tv_std tv_std = TV_STD_NTSC;
  95         bool is_tv = false, is_cv = false;
  96         struct drm_encoder *encoder;
  97
  98         if (!ASIC_IS_AVIVO(rdev) && radeon_crtc->crtc_id)
  99                 return;
 100
 101         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 102                 /* find tv std */
 103                 if (encoder->crtc == crtc) {
 104                         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 105                         if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) {
 106                                 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv;
 107                                 tv_std = tv_dac->tv_std;
 108                                 is_tv = true;
 109                         }
 110                 }
 111         }
 112
 113         memset(&args, 0, sizeof(args));
 114
 115         args.ucScaler = radeon_crtc->crtc_id;
 116
 117         if (is_tv) {
 118                 switch (tv_std) {
 119                 case TV_STD_NTSC:
 120                 default:
 121                         args.ucTVStandard = ATOM_TV_NTSC;
 122                         break;
 123                 case TV_STD_PAL:
 124                         args.ucTVStandard = ATOM_TV_PAL;
 125                         break;
 126                 case TV_STD_PAL_M:
 127                         args.ucTVStandard = ATOM_TV_PALM;
 128                         break;
 129                 case TV_STD_PAL_60:
 130                         args.ucTVStandard = ATOM_TV_PAL60;
 131                         break;
 132                 case TV_STD_NTSC_J:
 133                         args.ucTVStandard = ATOM_TV_NTSCJ;
 134                         break;
 135                 case TV_STD_SCART_PAL:
 136                         args.ucTVStandard = ATOM_TV_PAL; /* ??? */
 137                         break;
 138                 case TV_STD_SECAM:
 139                         args.ucTVStandard = ATOM_TV_SECAM;
 140                         break;
 141                 case TV_STD_PAL_CN:
 142                         args.ucTVStandard = ATOM_TV_PALCN;
 143                         break;
 144                 }
 145                 args.ucEnable = SCALER_ENABLE_MULTITAP_MODE;
 146         } else if (is_cv) {
 147                 args.ucTVStandard = ATOM_TV_CV;
 148                 args.ucEnable = SCALER_ENABLE_MULTITAP_MODE;
 149         } else {
 150                 switch (radeon_crtc->rmx_type) {
 151                 case RMX_FULL:
 152                         args.ucEnable = ATOM_SCALER_EXPANSION;
 153                         break;
 154                 case RMX_CENTER:
 155                         args.ucEnable = ATOM_SCALER_CENTER;
 156                         break;
 157                 case RMX_ASPECT:
 158                         args.ucEnable = ATOM_SCALER_EXPANSION;
 159                         break;
 160                 default:
 161                         if (ASIC_IS_AVIVO(rdev))
 162                                 args.ucEnable = ATOM_SCALER_DISABLE;
 163                         else
 164                                 args.ucEnable = ATOM_SCALER_CENTER;
 165                         break;
 166                 }
 167         }
 168         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 169         if ((is_tv || is_cv)
 170             && rdev->family >= CHIP_RV515 && rdev->family <= CHIP_R580) {
 171                 atom_rv515_force_tv_scaler(rdev, radeon_crtc);
 172         }
 173 }
 174
 175 static void atombios_lock_crtc(struct drm_crtc *crtc, int lock)
 176 {
 177         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 178         struct drm_device *dev = crtc->dev;
 179         struct radeon_device *rdev = dev->dev_private;
 180         int index =
 181             GetIndexIntoMasterTable(COMMAND, UpdateCRTC_DoubleBufferRegisters);
 182         ENABLE_CRTC_PS_ALLOCATION args;
 183
 184         memset(&args, 0, sizeof(args));
 185
 186         args.ucCRTC = radeon_crtc->crtc_id;
 187         args.ucEnable = lock;
 188
 189         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 190 }
 191
 192 static void atombios_enable_crtc(struct drm_crtc *crtc, int state)
 193 {
 194         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 195         struct drm_device *dev = crtc->dev;
 196         struct radeon_device *rdev = dev->dev_private;
 197         int index = GetIndexIntoMasterTable(COMMAND, EnableCRTC);
 198         ENABLE_CRTC_PS_ALLOCATION args;
 199
 200         memset(&args, 0, sizeof(args));
 201
 202         args.ucCRTC = radeon_crtc->crtc_id;
 203         args.ucEnable = state;
 204
 205         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 206 }
 207
 208 static void atombios_enable_crtc_memreq(struct drm_crtc *crtc, int state)
 209 {
 210         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 211         struct drm_device *dev = crtc->dev;
 212         struct radeon_device *rdev = dev->dev_private;
 213         int index = GetIndexIntoMasterTable(COMMAND, EnableCRTCMemReq);
 214         ENABLE_CRTC_PS_ALLOCATION args;
 215
 216         memset(&args, 0, sizeof(args));
 217
 218         args.ucCRTC = radeon_crtc->crtc_id;
 219         args.ucEnable = state;
 220
 221         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 222 }
 223
 224 static void atombios_blank_crtc(struct drm_crtc *crtc, int state)
 225 {
 226         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 227         struct drm_device *dev = crtc->dev;
 228         struct radeon_device *rdev = dev->dev_private;
 229         int index = GetIndexIntoMasterTable(COMMAND, BlankCRTC);
 230         BLANK_CRTC_PS_ALLOCATION args;
 231
 232         memset(&args, 0, sizeof(args));
 233
 234         args.ucCRTC = radeon_crtc->crtc_id;
 235         args.ucBlanking = state;
 236
 237         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 238 }
 239
 240 void atombios_crtc_dpms(struct drm_crtc *crtc, int mode)
 241 {
 242         struct drm_device *dev = crtc->dev;
 243         struct radeon_device *rdev = dev->dev_private;
 244
 245         switch (mode) {
 246         case DRM_MODE_DPMS_ON:
 247                 atombios_enable_crtc(crtc, 1);
 248                 if (ASIC_IS_DCE3(rdev))
 249                         atombios_enable_crtc_memreq(crtc, 1);
 250                 atombios_blank_crtc(crtc, 0);
 251                 break;
 252         case DRM_MODE_DPMS_STANDBY:
 253         case DRM_MODE_DPMS_SUSPEND:
 254         case DRM_MODE_DPMS_OFF:
 255                 atombios_blank_crtc(crtc, 1);
 256                 if (ASIC_IS_DCE3(rdev))
 257                         atombios_enable_crtc_memreq(crtc, 0);
 258                 atombios_enable_crtc(crtc, 0);
 259                 break;
 260         }
 261
 262         if (mode != DRM_MODE_DPMS_OFF) {
 263                 radeon_crtc_load_lut(crtc);
 264         }
 265 }
 266
 267 static void
 268 atombios_set_crtc_dtd_timing(struct drm_crtc *crtc,
 269                              struct drm_display_mode *mode)
 270 {
 271         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 272         struct drm_device *dev = crtc->dev;
 273         struct radeon_device *rdev = dev->dev_private;
 274         SET_CRTC_USING_DTD_TIMING_PARAMETERS args;
 275         int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_UsingDTDTiming);
 276         u16 misc = 0;
 277
 278         memset(&args, 0, sizeof(args));
 279         args.usH_Size = cpu_to_le16(mode->crtc_hdisplay);
 280         args.usH_Blanking_Time =
 281                 cpu_to_le16(mode->crtc_hblank_end - mode->crtc_hdisplay);
 282         args.usV_Size = cpu_to_le16(mode->crtc_vdisplay);
 283         args.usV_Blanking_Time =
 284             cpu_to_le16(mode->crtc_vblank_end - mode->crtc_vdisplay);
 285         args.usH_SyncOffset =
 286                 cpu_to_le16(mode->crtc_hsync_start - mode->crtc_hdisplay);
 287         args.usH_SyncWidth =
 288                 cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start);
 289         args.usV_SyncOffset =
 290                 cpu_to_le16(mode->crtc_vsync_start - mode->crtc_vdisplay);
 291         args.usV_SyncWidth =
 292                 cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start);
 293         /*args.ucH_Border = mode->hborder;*/
 294         /*args.ucV_Border = mode->vborder;*/
 295
 296         if (mode->flags & DRM_MODE_FLAG_NVSYNC)
 297                 misc |= ATOM_VSYNC_POLARITY;
 298         if (mode->flags & DRM_MODE_FLAG_NHSYNC)
 299                 misc |= ATOM_HSYNC_POLARITY;
 300         if (mode->flags & DRM_MODE_FLAG_CSYNC)
 301                 misc |= ATOM_COMPOSITESYNC;
 302         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
 303                 misc |= ATOM_INTERLACE;
 304         if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
 305                 misc |= ATOM_DOUBLE_CLOCK_MODE;
 306
 307         args.susModeMiscInfo.usAccess = cpu_to_le16(misc);
 308         args.ucCRTC = radeon_crtc->crtc_id;
 309
 310         printk("executing set crtc dtd timing\n");
 311         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 312 }
 313
 314 static void atombios_crtc_set_timing(struct drm_crtc *crtc,
 315                                      struct drm_display_mode *mode)
 316 {
 317         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 318         struct drm_device *dev = crtc->dev;
 319         struct radeon_device *rdev = dev->dev_private;
 320         SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION args;
 321         int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_Timing);
 322         u16 misc = 0;
 323
 324         memset(&args, 0, sizeof(args));
 325         args.usH_Total = cpu_to_le16(mode->crtc_htotal);
 326         args.usH_Disp = cpu_to_le16(mode->crtc_hdisplay);
 327         args.usH_SyncStart = cpu_to_le16(mode->crtc_hsync_start);
 328         args.usH_SyncWidth =
 329                 cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start);
 330         args.usV_Total = cpu_to_le16(mode->crtc_vtotal);
 331         args.usV_Disp = cpu_to_le16(mode->crtc_vdisplay);
 332         args.usV_SyncStart = cpu_to_le16(mode->crtc_vsync_start);
 333         args.usV_SyncWidth =
 334                 cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start);
 335
 336         if (mode->flags & DRM_MODE_FLAG_NVSYNC)
 337                 misc |= ATOM_VSYNC_POLARITY;
 338         if (mode->flags & DRM_MODE_FLAG_NHSYNC)
 339                 misc |= ATOM_HSYNC_POLARITY;
 340         if (mode->flags & DRM_MODE_FLAG_CSYNC)
 341                 misc |= ATOM_COMPOSITESYNC;
 342         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
 343                 misc |= ATOM_INTERLACE;
 344         if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
 345                 misc |= ATOM_DOUBLE_CLOCK_MODE;
 346
 347         args.susModeMiscInfo.usAccess = cpu_to_le16(misc);
 348         args.ucCRTC = radeon_crtc->crtc_id;
 349
 350         printk("executing set crtc timing\n");
 351         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 352 }
 353
 354 void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
 355 {
 356         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 357         struct drm_device *dev = crtc->dev;
 358         struct radeon_device *rdev = dev->dev_private;
 359         struct drm_encoder *encoder = NULL;
 360         struct radeon_encoder *radeon_encoder = NULL;
 361         uint8_t frev, crev;
 362         int index;
 363         SET_PIXEL_CLOCK_PS_ALLOCATION args;
 364         PIXEL_CLOCK_PARAMETERS *spc1_ptr;
 365         PIXEL_CLOCK_PARAMETERS_V2 *spc2_ptr;
 366         PIXEL_CLOCK_PARAMETERS_V3 *spc3_ptr;
 367         uint32_t pll_clock = mode->clock;
 368         uint32_t adjusted_clock;
 369         uint32_t ref_div = 0, fb_div = 0, frac_fb_div = 0, post_div = 0;
 370         struct radeon_pll *pll;
 371         int pll_flags = 0;
 372
 373         memset(&args, 0, sizeof(args));
 374
 375         if (ASIC_IS_AVIVO(rdev)) {
 376                 uint32_t ss_cntl;
 377
 378                 if ((rdev->family == CHIP_RS600) ||
 379                     (rdev->family == CHIP_RS690) ||
 380                     (rdev->family == CHIP_RS740))
 381                         pll_flags |= (RADEON_PLL_USE_FRAC_FB_DIV |
 382                                       RADEON_PLL_PREFER_CLOSEST_LOWER);
 383
 384                 if (ASIC_IS_DCE32(rdev) && mode->clock > 200000)        /* range limits??? */
 385                         pll_flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
 386                 else
 387                         pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
 388
 389                 /* disable spread spectrum clocking for now -- thanks Hedy Lamarr */
 390                 if (radeon_crtc->crtc_id == 0) {
 391                         ss_cntl = RREG32(AVIVO_P1PLL_INT_SS_CNTL);
 392                         WREG32(AVIVO_P1PLL_INT_SS_CNTL, ss_cntl & ~1);
 393                 } else {
 394                         ss_cntl = RREG32(AVIVO_P2PLL_INT_SS_CNTL);
 395                         WREG32(AVIVO_P2PLL_INT_SS_CNTL, ss_cntl & ~1);
 396                 }
 397         } else {
 398                 pll_flags |= RADEON_PLL_LEGACY;
 399
 400                 if (mode->clock > 200000)       /* range limits??? */
 401                         pll_flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
 402                 else
 403                         pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
 404
 405         }
 406
 407         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 408                 if (encoder->crtc == crtc) {
 409                         if (!ASIC_IS_AVIVO(rdev)) {
 410                                 if (encoder->encoder_type !=
 411                                     DRM_MODE_ENCODER_DAC)
 412                                         pll_flags |= RADEON_PLL_NO_ODD_POST_DIV;
 413                                 if (!ASIC_IS_AVIVO(rdev)
 414                                     && (encoder->encoder_type ==
 415                                         DRM_MODE_ENCODER_LVDS))
 416                                         pll_flags |= RADEON_PLL_USE_REF_DIV;
 417                         }
 418                         radeon_encoder = to_radeon_encoder(encoder);
 419                         break;
 420                 }
 421         }
 422
 423         /* DCE3+ has an AdjustDisplayPll that will adjust the pixel clock
 424          * accordingly based on the encoder/transmitter to work around
 425          * special hw requirements.
 426          */
 427         if (ASIC_IS_DCE3(rdev)) {
 428                 ADJUST_DISPLAY_PLL_PS_ALLOCATION adjust_pll_args;
 429
 430                 if (!encoder)
 431                         return;
 432
 433                 memset(&adjust_pll_args, 0, sizeof(adjust_pll_args));
 434                 adjust_pll_args.usPixelClock = cpu_to_le16(mode->clock / 10);
 435                 adjust_pll_args.ucTransmitterID = radeon_encoder->encoder_id;
 436                 adjust_pll_args.ucEncodeMode = atombios_get_encoder_mode(encoder);
 437
 438                 index = GetIndexIntoMasterTable(COMMAND, AdjustDisplayPll);
 439                 atom_execute_table(rdev->mode_info.atom_context,
 440                                    index, (uint32_t *)&adjust_pll_args);
 441                 adjusted_clock = le16_to_cpu(adjust_pll_args.usPixelClock) * 10;
 442         } else
 443                 adjusted_clock = mode->clock;
 444
 445         if (radeon_crtc->crtc_id == 0)
 446                 pll = &rdev->clock.p1pll;
 447         else
 448                 pll = &rdev->clock.p2pll;
 449
 450         radeon_compute_pll(pll, adjusted_clock, &pll_clock, &fb_div, &frac_fb_div,
 451                            &ref_div, &post_div, pll_flags);
 452
 453         index = GetIndexIntoMasterTable(COMMAND, SetPixelClock);
 454         atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
 455                               &crev);
 456
 457         switch (frev) {
 458         case 1:
 459                 switch (crev) {
 460                 case 1:
 461                         spc1_ptr = (PIXEL_CLOCK_PARAMETERS *) & args.sPCLKInput;
 462                         spc1_ptr->usPixelClock = cpu_to_le16(mode->clock / 10);
 463                         spc1_ptr->usRefDiv = cpu_to_le16(ref_div);
 464                         spc1_ptr->usFbDiv = cpu_to_le16(fb_div);
 465                         spc1_ptr->ucFracFbDiv = frac_fb_div;
 466                         spc1_ptr->ucPostDiv = post_div;
 467                         spc1_ptr->ucPpll =
 468                             radeon_crtc->crtc_id ? ATOM_PPLL2 : ATOM_PPLL1;
 469                         spc1_ptr->ucCRTC = radeon_crtc->crtc_id;
 470                         spc1_ptr->ucRefDivSrc = 1;
 471                         break;
 472                 case 2:
 473                         spc2_ptr =
 474                             (PIXEL_CLOCK_PARAMETERS_V2 *) & args.sPCLKInput;
 475                         spc2_ptr->usPixelClock = cpu_to_le16(mode->clock / 10);
 476                         spc2_ptr->usRefDiv = cpu_to_le16(ref_div);
 477                         spc2_ptr->usFbDiv = cpu_to_le16(fb_div);
 478                         spc2_ptr->ucFracFbDiv = frac_fb_div;
 479                         spc2_ptr->ucPostDiv = post_div;
 480                         spc2_ptr->ucPpll =
 481                             radeon_crtc->crtc_id ? ATOM_PPLL2 : ATOM_PPLL1;
 482                         spc2_ptr->ucCRTC = radeon_crtc->crtc_id;
 483                         spc2_ptr->ucRefDivSrc = 1;
 484                         break;
 485                 case 3:
 486                         if (!encoder)
 487                                 return;
 488                         spc3_ptr =
 489                             (PIXEL_CLOCK_PARAMETERS_V3 *) & args.sPCLKInput;
 490                         spc3_ptr->usPixelClock = cpu_to_le16(mode->clock / 10);
 491                         spc3_ptr->usRefDiv = cpu_to_le16(ref_div);
 492                         spc3_ptr->usFbDiv = cpu_to_le16(fb_div);
 493                         spc3_ptr->ucFracFbDiv = frac_fb_div;
 494                         spc3_ptr->ucPostDiv = post_div;
 495                         spc3_ptr->ucPpll =
 496                             radeon_crtc->crtc_id ? ATOM_PPLL2 : ATOM_PPLL1;
 497                         spc3_ptr->ucMiscInfo = (radeon_crtc->crtc_id << 2);
 498                         spc3_ptr->ucTransmitterId = radeon_encoder->encoder_id;
 499                         spc3_ptr->ucEncoderMode =
 500                             atombios_get_encoder_mode(encoder);
 501                         break;
 502                 default:
 503                         DRM_ERROR("Unknown table version %d %d\n", frev, crev);
 504                         return;
 505                 }
 506                 break;
 507         default:
 508                 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
 509                 return;
 510         }
 511
 512         printk("executing set pll\n");
 513         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 514 }
 515
 516 int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y,
 517                            struct drm_framebuffer *old_fb)
 518 {
 519         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 520         struct drm_device *dev = crtc->dev;
 521         struct radeon_device *rdev = dev->dev_private;
 522         struct radeon_framebuffer *radeon_fb;
 523         struct drm_gem_object *obj;
 524         struct drm_radeon_gem_object *obj_priv;
 525         uint64_t fb_location;
 526         uint32_t fb_format, fb_pitch_pixels, tiling_flags;
 527
 528         if (!crtc->fb)
 529                 return -EINVAL;
 530
 531         radeon_fb = to_radeon_framebuffer(crtc->fb);
 532
 533         obj = radeon_fb->obj;
 534         obj_priv = obj->driver_private;
 535
 536         if (radeon_gem_object_pin(obj, RADEON_GEM_DOMAIN_VRAM, &fb_location)) {
 537                 return -EINVAL;
 538         }
 539
 540         switch (crtc->fb->bits_per_pixel) {
 541         case 8:
 542                 fb_format =
 543                     AVIVO_D1GRPH_CONTROL_DEPTH_8BPP |
 544                     AVIVO_D1GRPH_CONTROL_8BPP_INDEXED;
 545                 break;
 546         case 15:
 547                 fb_format =
 548                     AVIVO_D1GRPH_CONTROL_DEPTH_16BPP |
 549                     AVIVO_D1GRPH_CONTROL_16BPP_ARGB1555;
 550                 break;
 551         case 16:
 552                 fb_format =
 553                     AVIVO_D1GRPH_CONTROL_DEPTH_16BPP |
 554                     AVIVO_D1GRPH_CONTROL_16BPP_RGB565;
 555                 break;
 556         case 24:
 557         case 32:
 558                 fb_format =
 559                     AVIVO_D1GRPH_CONTROL_DEPTH_32BPP |
 560                     AVIVO_D1GRPH_CONTROL_32BPP_ARGB8888;
 561                 break;
 562         default:
 563                 DRM_ERROR("Unsupported screen depth %d\n",
 564                           crtc->fb->bits_per_pixel);
 565                 return -EINVAL;
 566         }
 567
 568         radeon_object_get_tiling_flags(obj->driver_private,
 569                                        &tiling_flags, NULL);
 570         if (tiling_flags & RADEON_TILING_MACRO)
 571                 fb_format |= AVIVO_D1GRPH_MACRO_ADDRESS_MODE;
 572
 573         if (tiling_flags & RADEON_TILING_MICRO)
 574                 fb_format |= AVIVO_D1GRPH_TILED;
 575
 576         if (radeon_crtc->crtc_id == 0)
 577                 WREG32(AVIVO_D1VGA_CONTROL, 0);
 578         else
 579                 WREG32(AVIVO_D2VGA_CONTROL, 0);
 580
 581         if (rdev->family >= CHIP_RV770) {
 582                 if (radeon_crtc->crtc_id) {
 583                         WREG32(R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, 0);
 584                         WREG32(R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, 0);
 585                 } else {
 586                         WREG32(R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, 0);
 587                         WREG32(R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, 0);
 588                 }
 589         }
 590         WREG32(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
 591                (u32) fb_location);
 592         WREG32(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS +
 593                radeon_crtc->crtc_offset, (u32) fb_location);
 594         WREG32(AVIVO_D1GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format);
 595
 596         WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0);
 597         WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0);
 598         WREG32(AVIVO_D1GRPH_X_START + radeon_crtc->crtc_offset, 0);
 599         WREG32(AVIVO_D1GRPH_Y_START + radeon_crtc->crtc_offset, 0);
 600         WREG32(AVIVO_D1GRPH_X_END + radeon_crtc->crtc_offset, crtc->fb->width);
 601         WREG32(AVIVO_D1GRPH_Y_END + radeon_crtc->crtc_offset, crtc->fb->height);
 602
 603         fb_pitch_pixels = crtc->fb->pitch / (crtc->fb->bits_per_pixel / 8);
 604         WREG32(AVIVO_D1GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels);
 605         WREG32(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 1);
 606
 607         WREG32(AVIVO_D1MODE_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,
 608                crtc->mode.vdisplay);
 609         x &= ~3;
 610         y &= ~1;
 611         WREG32(AVIVO_D1MODE_VIEWPORT_START + radeon_crtc->crtc_offset,
 612                (x << 16) | y);
 613         WREG32(AVIVO_D1MODE_VIEWPORT_SIZE + radeon_crtc->crtc_offset,
 614                (crtc->mode.hdisplay << 16) | crtc->mode.vdisplay);
 615
 616         if (crtc->mode.flags & DRM_MODE_FLAG_INTERLACE)
 617                 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset,
 618                        AVIVO_D1MODE_INTERLEAVE_EN);
 619         else
 620                 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
 621
 622         if (old_fb && old_fb != crtc->fb) {
 623                 radeon_fb = to_radeon_framebuffer(old_fb);
 624                 radeon_gem_object_unpin(radeon_fb->obj);
 625         }
 626
 627         /* Bytes per pixel may have changed */
 628         radeon_bandwidth_update(rdev);
 629
 630         return 0;
 631 }
 632
 633 int atombios_crtc_mode_set(struct drm_crtc *crtc,
 634                            struct drm_display_mode *mode,
 635                            struct drm_display_mode *adjusted_mode,
 636                            int x, int y, struct drm_framebuffer *old_fb)
 637 {
 638         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 639         struct drm_device *dev = crtc->dev;
 640         struct radeon_device *rdev = dev->dev_private;
 641
 642         /* TODO color tiling */
 643
 644         atombios_crtc_set_pll(crtc, adjusted_mode);
 645         atombios_crtc_set_timing(crtc, adjusted_mode);
 646
 647         if (ASIC_IS_AVIVO(rdev))
 648                 atombios_crtc_set_base(crtc, x, y, old_fb);
 649         else {
 650                 if (radeon_crtc->crtc_id == 0)
 651                         atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
 652                 radeon_crtc_set_base(crtc, x, y, old_fb);
 653                 radeon_legacy_atom_set_surface(crtc);
 654         }
 655         atombios_overscan_setup(crtc, mode, adjusted_mode);
 656         atombios_scaler_setup(crtc);
 657         return 0;
 658 }
 659
 660 static bool atombios_crtc_mode_fixup(struct drm_crtc *crtc,
 661                                      struct drm_display_mode *mode,
 662                                      struct drm_display_mode *adjusted_mode)
 663 {
 664         if (!radeon_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
 665                 return false;
 666         return true;
 667 }
 668
 669 static void atombios_crtc_prepare(struct drm_crtc *crtc)
 670 {
 671         atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
 672         atombios_lock_crtc(crtc, 1);
 673 }
 674
 675 static void atombios_crtc_commit(struct drm_crtc *crtc)
 676 {
 677         atombios_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
 678         atombios_lock_crtc(crtc, 0);
 679 }
 680
 681 static const struct drm_crtc_helper_funcs atombios_helper_funcs = {
 682         .dpms = atombios_crtc_dpms,
 683         .mode_fixup = atombios_crtc_mode_fixup,
 684         .mode_set = atombios_crtc_mode_set,
 685         .mode_set_base = atombios_crtc_set_base,
 686         .prepare = atombios_crtc_prepare,
 687         .commit = atombios_crtc_commit,
 688         .load_lut = radeon_crtc_load_lut,
 689 };
 690
 691 void radeon_atombios_init_crtc(struct drm_device *dev,
 692                                struct radeon_crtc *radeon_crtc)
 693 {
 694         if (radeon_crtc->crtc_id == 1)
 695                 radeon_crtc->crtc_offset =
 696                     AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL;
 697         drm_crtc_helper_add(&radeon_crtc->base, &atombios_helper_funcs);
 698 }