2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
23 * Authors: Dave Airlie
27 #include <drm/drm_crtc_helper.h>
28 #include <drm/radeon_drm.h>
29 #include <drm/drm_fixed.h>
32 #include "atom-bits.h"
34 static void atombios_overscan_setup(struct drm_crtc *crtc,
35 struct drm_display_mode *mode,
36 struct drm_display_mode *adjusted_mode)
38 struct drm_device *dev = crtc->dev;
39 struct radeon_device *rdev = dev->dev_private;
40 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
41 SET_CRTC_OVERSCAN_PS_ALLOCATION args;
42 int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_OverScan);
45 memset(&args, 0, sizeof(args));
47 args.ucCRTC = radeon_crtc->crtc_id;
49 switch (radeon_crtc->rmx_type) {
51 args.usOverscanTop = cpu_to_le16((adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2);
52 args.usOverscanBottom = cpu_to_le16((adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2);
53 args.usOverscanLeft = cpu_to_le16((adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2);
54 args.usOverscanRight = cpu_to_le16((adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2);
57 a1 = mode->crtc_vdisplay * adjusted_mode->crtc_hdisplay;
58 a2 = adjusted_mode->crtc_vdisplay * mode->crtc_hdisplay;
61 args.usOverscanLeft = cpu_to_le16((adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2);
62 args.usOverscanRight = cpu_to_le16((adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2);
64 args.usOverscanTop = cpu_to_le16((adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2);
65 args.usOverscanBottom = cpu_to_le16((adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2);
70 args.usOverscanRight = cpu_to_le16(radeon_crtc->h_border);
71 args.usOverscanLeft = cpu_to_le16(radeon_crtc->h_border);
72 args.usOverscanBottom = cpu_to_le16(radeon_crtc->v_border);
73 args.usOverscanTop = cpu_to_le16(radeon_crtc->v_border);
76 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
79 static void atombios_scaler_setup(struct drm_crtc *crtc)
81 struct drm_device *dev = crtc->dev;
82 struct radeon_device *rdev = dev->dev_private;
83 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
84 ENABLE_SCALER_PS_ALLOCATION args;
85 int index = GetIndexIntoMasterTable(COMMAND, EnableScaler);
87 /* fixme - fill in enc_priv for atom dac */
88 enum radeon_tv_std tv_std = TV_STD_NTSC;
89 bool is_tv = false, is_cv = false;
90 struct drm_encoder *encoder;
92 if (!ASIC_IS_AVIVO(rdev) && radeon_crtc->crtc_id)
95 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
97 if (encoder->crtc == crtc) {
98 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
99 if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) {
100 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv;
101 tv_std = tv_dac->tv_std;
107 memset(&args, 0, sizeof(args));
109 args.ucScaler = radeon_crtc->crtc_id;
115 args.ucTVStandard = ATOM_TV_NTSC;
118 args.ucTVStandard = ATOM_TV_PAL;
121 args.ucTVStandard = ATOM_TV_PALM;
124 args.ucTVStandard = ATOM_TV_PAL60;
127 args.ucTVStandard = ATOM_TV_NTSCJ;
129 case TV_STD_SCART_PAL:
130 args.ucTVStandard = ATOM_TV_PAL; /* ??? */
133 args.ucTVStandard = ATOM_TV_SECAM;
136 args.ucTVStandard = ATOM_TV_PALCN;
139 args.ucEnable = SCALER_ENABLE_MULTITAP_MODE;
141 args.ucTVStandard = ATOM_TV_CV;
142 args.ucEnable = SCALER_ENABLE_MULTITAP_MODE;
144 switch (radeon_crtc->rmx_type) {
146 args.ucEnable = ATOM_SCALER_EXPANSION;
149 args.ucEnable = ATOM_SCALER_CENTER;
152 args.ucEnable = ATOM_SCALER_EXPANSION;
155 if (ASIC_IS_AVIVO(rdev))
156 args.ucEnable = ATOM_SCALER_DISABLE;
158 args.ucEnable = ATOM_SCALER_CENTER;
162 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
164 && rdev->family >= CHIP_RV515 && rdev->family <= CHIP_R580) {
165 atom_rv515_force_tv_scaler(rdev, radeon_crtc);
169 static void atombios_lock_crtc(struct drm_crtc *crtc, int lock)
171 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
172 struct drm_device *dev = crtc->dev;
173 struct radeon_device *rdev = dev->dev_private;
175 GetIndexIntoMasterTable(COMMAND, UpdateCRTC_DoubleBufferRegisters);
176 ENABLE_CRTC_PS_ALLOCATION args;
178 memset(&args, 0, sizeof(args));
180 args.ucCRTC = radeon_crtc->crtc_id;
181 args.ucEnable = lock;
183 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
186 static void atombios_enable_crtc(struct drm_crtc *crtc, int state)
188 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
189 struct drm_device *dev = crtc->dev;
190 struct radeon_device *rdev = dev->dev_private;
191 int index = GetIndexIntoMasterTable(COMMAND, EnableCRTC);
192 ENABLE_CRTC_PS_ALLOCATION args;
194 memset(&args, 0, sizeof(args));
196 args.ucCRTC = radeon_crtc->crtc_id;
197 args.ucEnable = state;
199 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
202 static void atombios_enable_crtc_memreq(struct drm_crtc *crtc, int state)
204 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
205 struct drm_device *dev = crtc->dev;
206 struct radeon_device *rdev = dev->dev_private;
207 int index = GetIndexIntoMasterTable(COMMAND, EnableCRTCMemReq);
208 ENABLE_CRTC_PS_ALLOCATION args;
210 memset(&args, 0, sizeof(args));
212 args.ucCRTC = radeon_crtc->crtc_id;
213 args.ucEnable = state;
215 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
218 static void atombios_blank_crtc(struct drm_crtc *crtc, int state)
220 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
221 struct drm_device *dev = crtc->dev;
222 struct radeon_device *rdev = dev->dev_private;
223 int index = GetIndexIntoMasterTable(COMMAND, BlankCRTC);
224 BLANK_CRTC_PS_ALLOCATION args;
226 memset(&args, 0, sizeof(args));
228 args.ucCRTC = radeon_crtc->crtc_id;
229 args.ucBlanking = state;
231 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
234 void atombios_crtc_dpms(struct drm_crtc *crtc, int mode)
236 struct drm_device *dev = crtc->dev;
237 struct radeon_device *rdev = dev->dev_private;
238 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
241 case DRM_MODE_DPMS_ON:
242 radeon_crtc->enabled = true;
243 /* adjust pm to dpms changes BEFORE enabling crtcs */
244 radeon_pm_compute_clocks(rdev);
245 atombios_enable_crtc(crtc, ATOM_ENABLE);
246 if (ASIC_IS_DCE3(rdev))
247 atombios_enable_crtc_memreq(crtc, ATOM_ENABLE);
248 atombios_blank_crtc(crtc, ATOM_DISABLE);
249 drm_vblank_post_modeset(dev, radeon_crtc->crtc_id);
250 radeon_crtc_load_lut(crtc);
252 case DRM_MODE_DPMS_STANDBY:
253 case DRM_MODE_DPMS_SUSPEND:
254 case DRM_MODE_DPMS_OFF:
255 drm_vblank_pre_modeset(dev, radeon_crtc->crtc_id);
256 if (radeon_crtc->enabled)
257 atombios_blank_crtc(crtc, ATOM_ENABLE);
258 if (ASIC_IS_DCE3(rdev))
259 atombios_enable_crtc_memreq(crtc, ATOM_DISABLE);
260 atombios_enable_crtc(crtc, ATOM_DISABLE);
261 radeon_crtc->enabled = false;
262 /* adjust pm to dpms changes AFTER disabling crtcs */
263 radeon_pm_compute_clocks(rdev);
269 atombios_set_crtc_dtd_timing(struct drm_crtc *crtc,
270 struct drm_display_mode *mode)
272 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
273 struct drm_device *dev = crtc->dev;
274 struct radeon_device *rdev = dev->dev_private;
275 SET_CRTC_USING_DTD_TIMING_PARAMETERS args;
276 int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_UsingDTDTiming);
279 memset(&args, 0, sizeof(args));
280 args.usH_Size = cpu_to_le16(mode->crtc_hdisplay - (radeon_crtc->h_border * 2));
281 args.usH_Blanking_Time =
282 cpu_to_le16(mode->crtc_hblank_end - mode->crtc_hdisplay + (radeon_crtc->h_border * 2));
283 args.usV_Size = cpu_to_le16(mode->crtc_vdisplay - (radeon_crtc->v_border * 2));
284 args.usV_Blanking_Time =
285 cpu_to_le16(mode->crtc_vblank_end - mode->crtc_vdisplay + (radeon_crtc->v_border * 2));
286 args.usH_SyncOffset =
287 cpu_to_le16(mode->crtc_hsync_start - mode->crtc_hdisplay + radeon_crtc->h_border);
289 cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start);
290 args.usV_SyncOffset =
291 cpu_to_le16(mode->crtc_vsync_start - mode->crtc_vdisplay + radeon_crtc->v_border);
293 cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start);
294 args.ucH_Border = radeon_crtc->h_border;
295 args.ucV_Border = radeon_crtc->v_border;
297 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
298 misc |= ATOM_VSYNC_POLARITY;
299 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
300 misc |= ATOM_HSYNC_POLARITY;
301 if (mode->flags & DRM_MODE_FLAG_CSYNC)
302 misc |= ATOM_COMPOSITESYNC;
303 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
304 misc |= ATOM_INTERLACE;
305 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
306 misc |= ATOM_DOUBLE_CLOCK_MODE;
308 args.susModeMiscInfo.usAccess = cpu_to_le16(misc);
309 args.ucCRTC = radeon_crtc->crtc_id;
311 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
314 static void atombios_crtc_set_timing(struct drm_crtc *crtc,
315 struct drm_display_mode *mode)
317 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
318 struct drm_device *dev = crtc->dev;
319 struct radeon_device *rdev = dev->dev_private;
320 SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION args;
321 int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_Timing);
324 memset(&args, 0, sizeof(args));
325 args.usH_Total = cpu_to_le16(mode->crtc_htotal);
326 args.usH_Disp = cpu_to_le16(mode->crtc_hdisplay);
327 args.usH_SyncStart = cpu_to_le16(mode->crtc_hsync_start);
329 cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start);
330 args.usV_Total = cpu_to_le16(mode->crtc_vtotal);
331 args.usV_Disp = cpu_to_le16(mode->crtc_vdisplay);
332 args.usV_SyncStart = cpu_to_le16(mode->crtc_vsync_start);
334 cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start);
336 args.ucOverscanRight = radeon_crtc->h_border;
337 args.ucOverscanLeft = radeon_crtc->h_border;
338 args.ucOverscanBottom = radeon_crtc->v_border;
339 args.ucOverscanTop = radeon_crtc->v_border;
341 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
342 misc |= ATOM_VSYNC_POLARITY;
343 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
344 misc |= ATOM_HSYNC_POLARITY;
345 if (mode->flags & DRM_MODE_FLAG_CSYNC)
346 misc |= ATOM_COMPOSITESYNC;
347 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
348 misc |= ATOM_INTERLACE;
349 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
350 misc |= ATOM_DOUBLE_CLOCK_MODE;
352 args.susModeMiscInfo.usAccess = cpu_to_le16(misc);
353 args.ucCRTC = radeon_crtc->crtc_id;
355 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
358 static void atombios_disable_ss(struct drm_crtc *crtc)
360 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
361 struct drm_device *dev = crtc->dev;
362 struct radeon_device *rdev = dev->dev_private;
365 if (ASIC_IS_DCE4(rdev)) {
366 switch (radeon_crtc->pll_id) {
368 ss_cntl = RREG32(EVERGREEN_P1PLL_SS_CNTL);
369 ss_cntl &= ~EVERGREEN_PxPLL_SS_EN;
370 WREG32(EVERGREEN_P1PLL_SS_CNTL, ss_cntl);
373 ss_cntl = RREG32(EVERGREEN_P2PLL_SS_CNTL);
374 ss_cntl &= ~EVERGREEN_PxPLL_SS_EN;
375 WREG32(EVERGREEN_P2PLL_SS_CNTL, ss_cntl);
378 case ATOM_PPLL_INVALID:
381 } else if (ASIC_IS_AVIVO(rdev)) {
382 switch (radeon_crtc->pll_id) {
384 ss_cntl = RREG32(AVIVO_P1PLL_INT_SS_CNTL);
386 WREG32(AVIVO_P1PLL_INT_SS_CNTL, ss_cntl);
389 ss_cntl = RREG32(AVIVO_P2PLL_INT_SS_CNTL);
391 WREG32(AVIVO_P2PLL_INT_SS_CNTL, ss_cntl);
394 case ATOM_PPLL_INVALID:
401 union atom_enable_ss {
402 ENABLE_LVDS_SS_PARAMETERS lvds_ss;
403 ENABLE_LVDS_SS_PARAMETERS_V2 lvds_ss_2;
404 ENABLE_SPREAD_SPECTRUM_ON_PPLL_PS_ALLOCATION v1;
405 ENABLE_SPREAD_SPECTRUM_ON_PPLL_V2 v2;
406 ENABLE_SPREAD_SPECTRUM_ON_PPLL_V3 v3;
409 static void atombios_crtc_program_ss(struct drm_crtc *crtc,
412 struct radeon_atom_ss *ss)
414 struct drm_device *dev = crtc->dev;
415 struct radeon_device *rdev = dev->dev_private;
416 int index = GetIndexIntoMasterTable(COMMAND, EnableSpreadSpectrumOnPPLL);
417 union atom_enable_ss args;
419 memset(&args, 0, sizeof(args));
421 if (ASIC_IS_DCE5(rdev)) {
422 args.v3.usSpreadSpectrumAmountFrac = cpu_to_le16(0);
423 args.v3.ucSpreadSpectrumType = ss->type;
426 args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_P1PLL;
427 args.v3.usSpreadSpectrumAmount = cpu_to_le16(ss->amount);
428 args.v3.usSpreadSpectrumStep = cpu_to_le16(ss->step);
431 args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_P2PLL;
432 args.v3.usSpreadSpectrumAmount = cpu_to_le16(ss->amount);
433 args.v3.usSpreadSpectrumStep = cpu_to_le16(ss->step);
436 args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_DCPLL;
437 args.v3.usSpreadSpectrumAmount = cpu_to_le16(0);
438 args.v3.usSpreadSpectrumStep = cpu_to_le16(0);
440 case ATOM_PPLL_INVALID:
443 args.v2.ucEnable = enable;
444 } else if (ASIC_IS_DCE4(rdev)) {
445 args.v2.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
446 args.v2.ucSpreadSpectrumType = ss->type;
449 args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_P1PLL;
450 args.v2.usSpreadSpectrumAmount = cpu_to_le16(ss->amount);
451 args.v2.usSpreadSpectrumStep = cpu_to_le16(ss->step);
454 args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_P2PLL;
455 args.v2.usSpreadSpectrumAmount = cpu_to_le16(ss->amount);
456 args.v2.usSpreadSpectrumStep = cpu_to_le16(ss->step);
459 args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_DCPLL;
460 args.v2.usSpreadSpectrumAmount = cpu_to_le16(0);
461 args.v2.usSpreadSpectrumStep = cpu_to_le16(0);
463 case ATOM_PPLL_INVALID:
466 args.v2.ucEnable = enable;
467 } else if (ASIC_IS_DCE3(rdev)) {
468 args.v1.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
469 args.v1.ucSpreadSpectrumType = ss->type;
470 args.v1.ucSpreadSpectrumStep = ss->step;
471 args.v1.ucSpreadSpectrumDelay = ss->delay;
472 args.v1.ucSpreadSpectrumRange = ss->range;
473 args.v1.ucPpll = pll_id;
474 args.v1.ucEnable = enable;
475 } else if (ASIC_IS_AVIVO(rdev)) {
476 if (enable == ATOM_DISABLE) {
477 atombios_disable_ss(crtc);
480 args.lvds_ss_2.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
481 args.lvds_ss_2.ucSpreadSpectrumType = ss->type;
482 args.lvds_ss_2.ucSpreadSpectrumStep = ss->step;
483 args.lvds_ss_2.ucSpreadSpectrumDelay = ss->delay;
484 args.lvds_ss_2.ucSpreadSpectrumRange = ss->range;
485 args.lvds_ss_2.ucEnable = enable;
487 if (enable == ATOM_DISABLE) {
488 atombios_disable_ss(crtc);
491 args.lvds_ss.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
492 args.lvds_ss.ucSpreadSpectrumType = ss->type;
493 args.lvds_ss.ucSpreadSpectrumStepSize_Delay = (ss->step & 3) << 2;
494 args.lvds_ss.ucSpreadSpectrumStepSize_Delay |= (ss->delay & 7) << 4;
495 args.lvds_ss.ucEnable = enable;
497 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
500 union adjust_pixel_clock {
501 ADJUST_DISPLAY_PLL_PS_ALLOCATION v1;
502 ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3 v3;
505 static u32 atombios_adjust_pll(struct drm_crtc *crtc,
506 struct drm_display_mode *mode,
507 struct radeon_pll *pll,
509 struct radeon_atom_ss *ss)
511 struct drm_device *dev = crtc->dev;
512 struct radeon_device *rdev = dev->dev_private;
513 struct drm_encoder *encoder = NULL;
514 struct radeon_encoder *radeon_encoder = NULL;
515 u32 adjusted_clock = mode->clock;
516 int encoder_mode = 0;
517 u32 dp_clock = mode->clock;
520 /* reset the pll flags */
523 if (ASIC_IS_AVIVO(rdev)) {
524 if ((rdev->family == CHIP_RS600) ||
525 (rdev->family == CHIP_RS690) ||
526 (rdev->family == CHIP_RS740))
527 pll->flags |= (/*RADEON_PLL_USE_FRAC_FB_DIV |*/
528 RADEON_PLL_PREFER_CLOSEST_LOWER);
530 if (ASIC_IS_DCE32(rdev) && mode->clock > 200000) /* range limits??? */
531 pll->flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
533 pll->flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
535 pll->flags |= RADEON_PLL_LEGACY;
537 if (mode->clock > 200000) /* range limits??? */
538 pll->flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
540 pll->flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
543 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
544 if (encoder->crtc == crtc) {
545 radeon_encoder = to_radeon_encoder(encoder);
546 encoder_mode = atombios_get_encoder_mode(encoder);
547 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) {
548 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
550 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
551 struct radeon_connector_atom_dig *dig_connector =
552 radeon_connector->con_priv;
554 dp_clock = dig_connector->dp_clock;
558 /* use recommended ref_div for ss */
559 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
562 pll->flags |= RADEON_PLL_PREFER_MINM_OVER_MAXP;
563 pll->flags |= RADEON_PLL_USE_REF_DIV;
564 pll->reference_div = ss->refdiv;
565 if (ASIC_IS_AVIVO(rdev))
566 pll->flags |= RADEON_PLL_USE_FRAC_FB_DIV;
571 if (ASIC_IS_AVIVO(rdev)) {
572 /* DVO wants 2x pixel clock if the DVO chip is in 12 bit mode */
573 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1)
574 adjusted_clock = mode->clock * 2;
575 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
576 pll->flags |= RADEON_PLL_PREFER_CLOSEST_LOWER;
577 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
578 pll->flags |= RADEON_PLL_IS_LCD;
580 if (encoder->encoder_type != DRM_MODE_ENCODER_DAC)
581 pll->flags |= RADEON_PLL_NO_ODD_POST_DIV;
582 if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS)
583 pll->flags |= RADEON_PLL_USE_REF_DIV;
589 /* DCE3+ has an AdjustDisplayPll that will adjust the pixel clock
590 * accordingly based on the encoder/transmitter to work around
591 * special hw requirements.
593 if (ASIC_IS_DCE3(rdev)) {
594 union adjust_pixel_clock args;
598 index = GetIndexIntoMasterTable(COMMAND, AdjustDisplayPll);
599 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
601 return adjusted_clock;
603 memset(&args, 0, sizeof(args));
610 args.v1.usPixelClock = cpu_to_le16(mode->clock / 10);
611 args.v1.ucTransmitterID = radeon_encoder->encoder_id;
612 args.v1.ucEncodeMode = encoder_mode;
615 ADJUST_DISPLAY_CONFIG_SS_ENABLE;
617 atom_execute_table(rdev->mode_info.atom_context,
618 index, (uint32_t *)&args);
619 adjusted_clock = le16_to_cpu(args.v1.usPixelClock) * 10;
622 args.v3.sInput.usPixelClock = cpu_to_le16(mode->clock / 10);
623 args.v3.sInput.ucTransmitterID = radeon_encoder->encoder_id;
624 args.v3.sInput.ucEncodeMode = encoder_mode;
625 args.v3.sInput.ucDispPllConfig = 0;
627 args.v3.sInput.ucDispPllConfig |=
628 DISPPLL_CONFIG_SS_ENABLE;
629 if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
630 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
631 if (encoder_mode == ATOM_ENCODER_MODE_DP) {
632 args.v3.sInput.ucDispPllConfig |=
633 DISPPLL_CONFIG_COHERENT_MODE;
635 args.v3.sInput.usPixelClock = cpu_to_le16(dp_clock / 10);
637 if (encoder_mode == ATOM_ENCODER_MODE_HDMI) {
638 /* deep color support */
639 args.v3.sInput.usPixelClock =
640 cpu_to_le16((mode->clock * bpc / 8) / 10);
642 if (dig->coherent_mode)
643 args.v3.sInput.ucDispPllConfig |=
644 DISPPLL_CONFIG_COHERENT_MODE;
645 if (mode->clock > 165000)
646 args.v3.sInput.ucDispPllConfig |=
647 DISPPLL_CONFIG_DUAL_LINK;
649 } else if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
650 if (encoder_mode == ATOM_ENCODER_MODE_DP) {
651 args.v3.sInput.ucDispPllConfig |=
652 DISPPLL_CONFIG_COHERENT_MODE;
654 args.v3.sInput.usPixelClock = cpu_to_le16(dp_clock / 10);
655 } else if (encoder_mode != ATOM_ENCODER_MODE_LVDS) {
656 if (mode->clock > 165000)
657 args.v3.sInput.ucDispPllConfig |=
658 DISPPLL_CONFIG_DUAL_LINK;
661 atom_execute_table(rdev->mode_info.atom_context,
662 index, (uint32_t *)&args);
663 adjusted_clock = le32_to_cpu(args.v3.sOutput.ulDispPllFreq) * 10;
664 if (args.v3.sOutput.ucRefDiv) {
665 pll->flags |= RADEON_PLL_USE_FRAC_FB_DIV;
666 pll->flags |= RADEON_PLL_USE_REF_DIV;
667 pll->reference_div = args.v3.sOutput.ucRefDiv;
669 if (args.v3.sOutput.ucPostDiv) {
670 pll->flags |= RADEON_PLL_USE_FRAC_FB_DIV;
671 pll->flags |= RADEON_PLL_USE_POST_DIV;
672 pll->post_div = args.v3.sOutput.ucPostDiv;
676 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
677 return adjusted_clock;
681 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
682 return adjusted_clock;
685 return adjusted_clock;
688 union set_pixel_clock {
689 SET_PIXEL_CLOCK_PS_ALLOCATION base;
690 PIXEL_CLOCK_PARAMETERS v1;
691 PIXEL_CLOCK_PARAMETERS_V2 v2;
692 PIXEL_CLOCK_PARAMETERS_V3 v3;
693 PIXEL_CLOCK_PARAMETERS_V5 v5;
694 PIXEL_CLOCK_PARAMETERS_V6 v6;
697 /* on DCE5, make sure the voltage is high enough to support the
700 static void atombios_crtc_set_dcpll(struct drm_crtc *crtc,
703 struct drm_device *dev = crtc->dev;
704 struct radeon_device *rdev = dev->dev_private;
707 union set_pixel_clock args;
709 memset(&args, 0, sizeof(args));
711 index = GetIndexIntoMasterTable(COMMAND, SetPixelClock);
712 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
720 /* if the default dcpll clock is specified,
721 * SetPixelClock provides the dividers
723 args.v5.ucCRTC = ATOM_CRTC_INVALID;
724 args.v5.usPixelClock = cpu_to_le16(dispclk);
725 args.v5.ucPpll = ATOM_DCPLL;
728 /* if the default dcpll clock is specified,
729 * SetPixelClock provides the dividers
731 args.v6.ulDispEngClkFreq = cpu_to_le32(dispclk);
732 args.v6.ucPpll = ATOM_DCPLL;
735 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
740 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
743 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
746 static void atombios_crtc_program_pll(struct drm_crtc *crtc,
757 struct drm_device *dev = crtc->dev;
758 struct radeon_device *rdev = dev->dev_private;
760 int index = GetIndexIntoMasterTable(COMMAND, SetPixelClock);
761 union set_pixel_clock args;
763 memset(&args, 0, sizeof(args));
765 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
773 if (clock == ATOM_DISABLE)
775 args.v1.usPixelClock = cpu_to_le16(clock / 10);
776 args.v1.usRefDiv = cpu_to_le16(ref_div);
777 args.v1.usFbDiv = cpu_to_le16(fb_div);
778 args.v1.ucFracFbDiv = frac_fb_div;
779 args.v1.ucPostDiv = post_div;
780 args.v1.ucPpll = pll_id;
781 args.v1.ucCRTC = crtc_id;
782 args.v1.ucRefDivSrc = 1;
785 args.v2.usPixelClock = cpu_to_le16(clock / 10);
786 args.v2.usRefDiv = cpu_to_le16(ref_div);
787 args.v2.usFbDiv = cpu_to_le16(fb_div);
788 args.v2.ucFracFbDiv = frac_fb_div;
789 args.v2.ucPostDiv = post_div;
790 args.v2.ucPpll = pll_id;
791 args.v2.ucCRTC = crtc_id;
792 args.v2.ucRefDivSrc = 1;
795 args.v3.usPixelClock = cpu_to_le16(clock / 10);
796 args.v3.usRefDiv = cpu_to_le16(ref_div);
797 args.v3.usFbDiv = cpu_to_le16(fb_div);
798 args.v3.ucFracFbDiv = frac_fb_div;
799 args.v3.ucPostDiv = post_div;
800 args.v3.ucPpll = pll_id;
801 args.v3.ucMiscInfo = (pll_id << 2);
802 args.v3.ucTransmitterId = encoder_id;
803 args.v3.ucEncoderMode = encoder_mode;
806 args.v5.ucCRTC = crtc_id;
807 args.v5.usPixelClock = cpu_to_le16(clock / 10);
808 args.v5.ucRefDiv = ref_div;
809 args.v5.usFbDiv = cpu_to_le16(fb_div);
810 args.v5.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000);
811 args.v5.ucPostDiv = post_div;
812 args.v5.ucMiscInfo = 0; /* HDMI depth, etc. */
813 args.v5.ucTransmitterID = encoder_id;
814 args.v5.ucEncoderMode = encoder_mode;
815 args.v5.ucPpll = pll_id;
818 args.v6.ulCrtcPclkFreq.ucCRTC = crtc_id;
819 args.v6.ulCrtcPclkFreq.ulPixelClock = cpu_to_le32(clock / 10);
820 args.v6.ucRefDiv = ref_div;
821 args.v6.usFbDiv = cpu_to_le16(fb_div);
822 args.v6.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000);
823 args.v6.ucPostDiv = post_div;
824 args.v6.ucMiscInfo = 0; /* HDMI depth, etc. */
825 args.v6.ucTransmitterID = encoder_id;
826 args.v6.ucEncoderMode = encoder_mode;
827 args.v6.ucPpll = pll_id;
830 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
835 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
839 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
842 static void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
844 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
845 struct drm_device *dev = crtc->dev;
846 struct radeon_device *rdev = dev->dev_private;
847 struct drm_encoder *encoder = NULL;
848 struct radeon_encoder *radeon_encoder = NULL;
849 u32 pll_clock = mode->clock;
850 u32 ref_div = 0, fb_div = 0, frac_fb_div = 0, post_div = 0;
851 struct radeon_pll *pll;
853 int encoder_mode = 0;
854 struct radeon_atom_ss ss;
855 bool ss_enabled = false;
857 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
858 if (encoder->crtc == crtc) {
859 radeon_encoder = to_radeon_encoder(encoder);
860 encoder_mode = atombios_get_encoder_mode(encoder);
868 switch (radeon_crtc->pll_id) {
870 pll = &rdev->clock.p1pll;
873 pll = &rdev->clock.p2pll;
876 case ATOM_PPLL_INVALID:
878 pll = &rdev->clock.dcpll;
882 if (radeon_encoder->active_device &
883 (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) {
884 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
885 struct drm_connector *connector =
886 radeon_get_connector_for_encoder(encoder);
887 struct radeon_connector *radeon_connector =
888 to_radeon_connector(connector);
889 struct radeon_connector_atom_dig *dig_connector =
890 radeon_connector->con_priv;
893 switch (encoder_mode) {
894 case ATOM_ENCODER_MODE_DP:
896 dp_clock = dig_connector->dp_clock / 10;
897 if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT)) {
898 if (ASIC_IS_DCE4(rdev))
900 radeon_atombios_get_asic_ss_info(rdev, &ss,
905 radeon_atombios_get_ppll_ss_info(rdev, &ss,
908 if (ASIC_IS_DCE4(rdev))
910 radeon_atombios_get_asic_ss_info(rdev, &ss,
911 ASIC_INTERNAL_SS_ON_DP,
914 if (dp_clock == 16200) {
916 radeon_atombios_get_ppll_ss_info(rdev, &ss,
920 radeon_atombios_get_ppll_ss_info(rdev, &ss,
924 radeon_atombios_get_ppll_ss_info(rdev, &ss,
929 case ATOM_ENCODER_MODE_LVDS:
930 if (ASIC_IS_DCE4(rdev))
931 ss_enabled = radeon_atombios_get_asic_ss_info(rdev, &ss,
935 ss_enabled = radeon_atombios_get_ppll_ss_info(rdev, &ss,
938 case ATOM_ENCODER_MODE_DVI:
939 if (ASIC_IS_DCE4(rdev))
941 radeon_atombios_get_asic_ss_info(rdev, &ss,
942 ASIC_INTERNAL_SS_ON_TMDS,
945 case ATOM_ENCODER_MODE_HDMI:
946 if (ASIC_IS_DCE4(rdev))
948 radeon_atombios_get_asic_ss_info(rdev, &ss,
949 ASIC_INTERNAL_SS_ON_HDMI,
957 /* adjust pixel clock as needed */
958 adjusted_clock = atombios_adjust_pll(crtc, mode, pll, ss_enabled, &ss);
960 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
961 /* TV seems to prefer the legacy algo on some boards */
962 radeon_compute_pll_legacy(pll, adjusted_clock, &pll_clock, &fb_div, &frac_fb_div,
963 &ref_div, &post_div);
964 else if (ASIC_IS_AVIVO(rdev))
965 radeon_compute_pll_avivo(pll, adjusted_clock, &pll_clock, &fb_div, &frac_fb_div,
966 &ref_div, &post_div);
968 radeon_compute_pll_legacy(pll, adjusted_clock, &pll_clock, &fb_div, &frac_fb_div,
969 &ref_div, &post_div);
971 atombios_crtc_program_ss(crtc, ATOM_DISABLE, radeon_crtc->pll_id, &ss);
973 atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id,
974 encoder_mode, radeon_encoder->encoder_id, mode->clock,
975 ref_div, fb_div, frac_fb_div, post_div);
978 /* calculate ss amount and step size */
979 if (ASIC_IS_DCE4(rdev)) {
981 u32 amount = (((fb_div * 10) + frac_fb_div) * ss.percentage) / 10000;
982 ss.amount = (amount / 10) & ATOM_PPLL_SS_AMOUNT_V2_FBDIV_MASK;
983 ss.amount |= ((amount - (ss.amount * 10)) << ATOM_PPLL_SS_AMOUNT_V2_NFRAC_SHIFT) &
984 ATOM_PPLL_SS_AMOUNT_V2_NFRAC_MASK;
985 if (ss.type & ATOM_PPLL_SS_TYPE_V2_CENTRE_SPREAD)
986 step_size = (4 * amount * ref_div * (ss.rate * 2048)) /
987 (125 * 25 * pll->reference_freq / 100);
989 step_size = (2 * amount * ref_div * (ss.rate * 2048)) /
990 (125 * 25 * pll->reference_freq / 100);
994 atombios_crtc_program_ss(crtc, ATOM_ENABLE, radeon_crtc->pll_id, &ss);
998 static int dce4_crtc_do_set_base(struct drm_crtc *crtc,
999 struct drm_framebuffer *fb,
1000 int x, int y, int atomic)
1002 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1003 struct drm_device *dev = crtc->dev;
1004 struct radeon_device *rdev = dev->dev_private;
1005 struct radeon_framebuffer *radeon_fb;
1006 struct drm_framebuffer *target_fb;
1007 struct drm_gem_object *obj;
1008 struct radeon_bo *rbo;
1009 uint64_t fb_location;
1010 uint32_t fb_format, fb_pitch_pixels, tiling_flags;
1011 u32 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_NONE);
1016 if (!atomic && !crtc->fb) {
1017 DRM_DEBUG_KMS("No FB bound\n");
1022 radeon_fb = to_radeon_framebuffer(fb);
1026 radeon_fb = to_radeon_framebuffer(crtc->fb);
1027 target_fb = crtc->fb;
1030 /* If atomic, assume fb object is pinned & idle & fenced and
1031 * just update base pointers
1033 obj = radeon_fb->obj;
1034 rbo = gem_to_radeon_bo(obj);
1035 r = radeon_bo_reserve(rbo, false);
1036 if (unlikely(r != 0))
1040 fb_location = radeon_bo_gpu_offset(rbo);
1042 r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location);
1043 if (unlikely(r != 0)) {
1044 radeon_bo_unreserve(rbo);
1049 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
1050 radeon_bo_unreserve(rbo);
1052 switch (target_fb->bits_per_pixel) {
1054 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_8BPP) |
1055 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_INDEXED));
1058 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) |
1059 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB1555));
1062 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) |
1063 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB565));
1065 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16);
1070 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) |
1071 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB8888));
1073 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN32);
1077 DRM_ERROR("Unsupported screen depth %d\n",
1078 target_fb->bits_per_pixel);
1082 if (tiling_flags & RADEON_TILING_MACRO)
1083 fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_2D_TILED_THIN1);
1084 else if (tiling_flags & RADEON_TILING_MICRO)
1085 fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_1D_TILED_THIN1);
1087 switch (radeon_crtc->crtc_id) {
1089 WREG32(AVIVO_D1VGA_CONTROL, 0);
1092 WREG32(AVIVO_D2VGA_CONTROL, 0);
1095 WREG32(EVERGREEN_D3VGA_CONTROL, 0);
1098 WREG32(EVERGREEN_D4VGA_CONTROL, 0);
1101 WREG32(EVERGREEN_D5VGA_CONTROL, 0);
1104 WREG32(EVERGREEN_D6VGA_CONTROL, 0);
1110 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
1111 upper_32_bits(fb_location));
1112 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
1113 upper_32_bits(fb_location));
1114 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
1115 (u32)fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK);
1116 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
1117 (u32) fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK);
1118 WREG32(EVERGREEN_GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format);
1119 WREG32(EVERGREEN_GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap);
1121 WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0);
1122 WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0);
1123 WREG32(EVERGREEN_GRPH_X_START + radeon_crtc->crtc_offset, 0);
1124 WREG32(EVERGREEN_GRPH_Y_START + radeon_crtc->crtc_offset, 0);
1125 WREG32(EVERGREEN_GRPH_X_END + radeon_crtc->crtc_offset, target_fb->width);
1126 WREG32(EVERGREEN_GRPH_Y_END + radeon_crtc->crtc_offset, target_fb->height);
1128 fb_pitch_pixels = target_fb->pitch / (target_fb->bits_per_pixel / 8);
1129 WREG32(EVERGREEN_GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels);
1130 WREG32(EVERGREEN_GRPH_ENABLE + radeon_crtc->crtc_offset, 1);
1132 WREG32(EVERGREEN_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,
1133 crtc->mode.vdisplay);
1136 WREG32(EVERGREEN_VIEWPORT_START + radeon_crtc->crtc_offset,
1138 WREG32(EVERGREEN_VIEWPORT_SIZE + radeon_crtc->crtc_offset,
1139 (crtc->mode.hdisplay << 16) | crtc->mode.vdisplay);
1141 /* pageflip setup */
1142 /* make sure flip is at vb rather than hb */
1143 tmp = RREG32(EVERGREEN_GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset);
1144 tmp &= ~EVERGREEN_GRPH_SURFACE_UPDATE_H_RETRACE_EN;
1145 WREG32(EVERGREEN_GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, tmp);
1147 /* set pageflip to happen anywhere in vblank interval */
1148 WREG32(EVERGREEN_MASTER_UPDATE_MODE + radeon_crtc->crtc_offset, 0);
1150 if (!atomic && fb && fb != crtc->fb) {
1151 radeon_fb = to_radeon_framebuffer(fb);
1152 rbo = gem_to_radeon_bo(radeon_fb->obj);
1153 r = radeon_bo_reserve(rbo, false);
1154 if (unlikely(r != 0))
1156 radeon_bo_unpin(rbo);
1157 radeon_bo_unreserve(rbo);
1160 /* Bytes per pixel may have changed */
1161 radeon_bandwidth_update(rdev);
1166 static int avivo_crtc_do_set_base(struct drm_crtc *crtc,
1167 struct drm_framebuffer *fb,
1168 int x, int y, int atomic)
1170 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1171 struct drm_device *dev = crtc->dev;
1172 struct radeon_device *rdev = dev->dev_private;
1173 struct radeon_framebuffer *radeon_fb;
1174 struct drm_gem_object *obj;
1175 struct radeon_bo *rbo;
1176 struct drm_framebuffer *target_fb;
1177 uint64_t fb_location;
1178 uint32_t fb_format, fb_pitch_pixels, tiling_flags;
1179 u32 fb_swap = R600_D1GRPH_SWAP_ENDIAN_NONE;
1184 if (!atomic && !crtc->fb) {
1185 DRM_DEBUG_KMS("No FB bound\n");
1190 radeon_fb = to_radeon_framebuffer(fb);
1194 radeon_fb = to_radeon_framebuffer(crtc->fb);
1195 target_fb = crtc->fb;
1198 obj = radeon_fb->obj;
1199 rbo = gem_to_radeon_bo(obj);
1200 r = radeon_bo_reserve(rbo, false);
1201 if (unlikely(r != 0))
1204 /* If atomic, assume fb object is pinned & idle & fenced and
1205 * just update base pointers
1208 fb_location = radeon_bo_gpu_offset(rbo);
1210 r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location);
1211 if (unlikely(r != 0)) {
1212 radeon_bo_unreserve(rbo);
1216 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
1217 radeon_bo_unreserve(rbo);
1219 switch (target_fb->bits_per_pixel) {
1222 AVIVO_D1GRPH_CONTROL_DEPTH_8BPP |
1223 AVIVO_D1GRPH_CONTROL_8BPP_INDEXED;
1227 AVIVO_D1GRPH_CONTROL_DEPTH_16BPP |
1228 AVIVO_D1GRPH_CONTROL_16BPP_ARGB1555;
1232 AVIVO_D1GRPH_CONTROL_DEPTH_16BPP |
1233 AVIVO_D1GRPH_CONTROL_16BPP_RGB565;
1235 fb_swap = R600_D1GRPH_SWAP_ENDIAN_16BIT;
1241 AVIVO_D1GRPH_CONTROL_DEPTH_32BPP |
1242 AVIVO_D1GRPH_CONTROL_32BPP_ARGB8888;
1244 fb_swap = R600_D1GRPH_SWAP_ENDIAN_32BIT;
1248 DRM_ERROR("Unsupported screen depth %d\n",
1249 target_fb->bits_per_pixel);
1253 if (rdev->family >= CHIP_R600) {
1254 if (tiling_flags & RADEON_TILING_MACRO)
1255 fb_format |= R600_D1GRPH_ARRAY_MODE_2D_TILED_THIN1;
1256 else if (tiling_flags & RADEON_TILING_MICRO)
1257 fb_format |= R600_D1GRPH_ARRAY_MODE_1D_TILED_THIN1;
1259 if (tiling_flags & RADEON_TILING_MACRO)
1260 fb_format |= AVIVO_D1GRPH_MACRO_ADDRESS_MODE;
1262 if (tiling_flags & RADEON_TILING_MICRO)
1263 fb_format |= AVIVO_D1GRPH_TILED;
1266 if (radeon_crtc->crtc_id == 0)
1267 WREG32(AVIVO_D1VGA_CONTROL, 0);
1269 WREG32(AVIVO_D2VGA_CONTROL, 0);
1271 if (rdev->family >= CHIP_RV770) {
1272 if (radeon_crtc->crtc_id) {
1273 WREG32(R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
1274 WREG32(R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
1276 WREG32(R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
1277 WREG32(R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
1280 WREG32(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
1282 WREG32(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS +
1283 radeon_crtc->crtc_offset, (u32) fb_location);
1284 WREG32(AVIVO_D1GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format);
1285 if (rdev->family >= CHIP_R600)
1286 WREG32(R600_D1GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap);
1288 WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0);
1289 WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0);
1290 WREG32(AVIVO_D1GRPH_X_START + radeon_crtc->crtc_offset, 0);
1291 WREG32(AVIVO_D1GRPH_Y_START + radeon_crtc->crtc_offset, 0);
1292 WREG32(AVIVO_D1GRPH_X_END + radeon_crtc->crtc_offset, target_fb->width);
1293 WREG32(AVIVO_D1GRPH_Y_END + radeon_crtc->crtc_offset, target_fb->height);
1295 fb_pitch_pixels = target_fb->pitch / (target_fb->bits_per_pixel / 8);
1296 WREG32(AVIVO_D1GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels);
1297 WREG32(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 1);
1299 WREG32(AVIVO_D1MODE_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,
1300 crtc->mode.vdisplay);
1303 WREG32(AVIVO_D1MODE_VIEWPORT_START + radeon_crtc->crtc_offset,
1305 WREG32(AVIVO_D1MODE_VIEWPORT_SIZE + radeon_crtc->crtc_offset,
1306 (crtc->mode.hdisplay << 16) | crtc->mode.vdisplay);
1308 /* pageflip setup */
1309 /* make sure flip is at vb rather than hb */
1310 tmp = RREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset);
1311 tmp &= ~AVIVO_D1GRPH_SURFACE_UPDATE_H_RETRACE_EN;
1312 WREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, tmp);
1314 /* set pageflip to happen anywhere in vblank interval */
1315 WREG32(AVIVO_D1MODE_MASTER_UPDATE_MODE + radeon_crtc->crtc_offset, 0);
1317 if (!atomic && fb && fb != crtc->fb) {
1318 radeon_fb = to_radeon_framebuffer(fb);
1319 rbo = gem_to_radeon_bo(radeon_fb->obj);
1320 r = radeon_bo_reserve(rbo, false);
1321 if (unlikely(r != 0))
1323 radeon_bo_unpin(rbo);
1324 radeon_bo_unreserve(rbo);
1327 /* Bytes per pixel may have changed */
1328 radeon_bandwidth_update(rdev);
1333 int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y,
1334 struct drm_framebuffer *old_fb)
1336 struct drm_device *dev = crtc->dev;
1337 struct radeon_device *rdev = dev->dev_private;
1339 if (ASIC_IS_DCE4(rdev))
1340 return dce4_crtc_do_set_base(crtc, old_fb, x, y, 0);
1341 else if (ASIC_IS_AVIVO(rdev))
1342 return avivo_crtc_do_set_base(crtc, old_fb, x, y, 0);
1344 return radeon_crtc_do_set_base(crtc, old_fb, x, y, 0);
1347 int atombios_crtc_set_base_atomic(struct drm_crtc *crtc,
1348 struct drm_framebuffer *fb,
1349 int x, int y, enum mode_set_atomic state)
1351 struct drm_device *dev = crtc->dev;
1352 struct radeon_device *rdev = dev->dev_private;
1354 if (ASIC_IS_DCE4(rdev))
1355 return dce4_crtc_do_set_base(crtc, fb, x, y, 1);
1356 else if (ASIC_IS_AVIVO(rdev))
1357 return avivo_crtc_do_set_base(crtc, fb, x, y, 1);
1359 return radeon_crtc_do_set_base(crtc, fb, x, y, 1);
1362 /* properly set additional regs when using atombios */
1363 static void radeon_legacy_atom_fixup(struct drm_crtc *crtc)
1365 struct drm_device *dev = crtc->dev;
1366 struct radeon_device *rdev = dev->dev_private;
1367 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1368 u32 disp_merge_cntl;
1370 switch (radeon_crtc->crtc_id) {
1372 disp_merge_cntl = RREG32(RADEON_DISP_MERGE_CNTL);
1373 disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN;
1374 WREG32(RADEON_DISP_MERGE_CNTL, disp_merge_cntl);
1377 disp_merge_cntl = RREG32(RADEON_DISP2_MERGE_CNTL);
1378 disp_merge_cntl &= ~RADEON_DISP2_RGB_OFFSET_EN;
1379 WREG32(RADEON_DISP2_MERGE_CNTL, disp_merge_cntl);
1380 WREG32(RADEON_FP_H2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_H_SYNC_STRT_WID));
1381 WREG32(RADEON_FP_V2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_V_SYNC_STRT_WID));
1386 static int radeon_atom_pick_pll(struct drm_crtc *crtc)
1388 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1389 struct drm_device *dev = crtc->dev;
1390 struct radeon_device *rdev = dev->dev_private;
1391 struct drm_encoder *test_encoder;
1392 struct drm_crtc *test_crtc;
1393 uint32_t pll_in_use = 0;
1395 if (ASIC_IS_DCE4(rdev)) {
1396 /* if crtc is driving DP and we have an ext clock, use that */
1397 list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) {
1398 if (test_encoder->crtc && (test_encoder->crtc == crtc)) {
1399 if (atombios_get_encoder_mode(test_encoder) == ATOM_ENCODER_MODE_DP) {
1400 if (rdev->clock.dp_extclk)
1401 return ATOM_PPLL_INVALID;
1406 /* otherwise, pick one of the plls */
1407 list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) {
1408 struct radeon_crtc *radeon_test_crtc;
1410 if (crtc == test_crtc)
1413 radeon_test_crtc = to_radeon_crtc(test_crtc);
1414 if ((radeon_test_crtc->pll_id >= ATOM_PPLL1) &&
1415 (radeon_test_crtc->pll_id <= ATOM_PPLL2))
1416 pll_in_use |= (1 << radeon_test_crtc->pll_id);
1418 if (!(pll_in_use & 1))
1422 return radeon_crtc->crtc_id;
1426 int atombios_crtc_mode_set(struct drm_crtc *crtc,
1427 struct drm_display_mode *mode,
1428 struct drm_display_mode *adjusted_mode,
1429 int x, int y, struct drm_framebuffer *old_fb)
1431 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1432 struct drm_device *dev = crtc->dev;
1433 struct radeon_device *rdev = dev->dev_private;
1434 struct drm_encoder *encoder;
1435 bool is_tvcv = false;
1437 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1439 if (encoder->crtc == crtc) {
1440 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1441 if (radeon_encoder->active_device &
1442 (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
1447 /* always set DCPLL */
1448 if (ASIC_IS_DCE4(rdev)) {
1449 struct radeon_atom_ss ss;
1450 bool ss_enabled = radeon_atombios_get_asic_ss_info(rdev, &ss,
1451 ASIC_INTERNAL_SS_ON_DCPLL,
1452 rdev->clock.default_dispclk);
1454 atombios_crtc_program_ss(crtc, ATOM_DISABLE, ATOM_DCPLL, &ss);
1455 /* XXX: DCE5, make sure voltage, dispclk is high enough */
1456 atombios_crtc_set_dcpll(crtc, rdev->clock.default_dispclk);
1458 atombios_crtc_program_ss(crtc, ATOM_ENABLE, ATOM_DCPLL, &ss);
1460 atombios_crtc_set_pll(crtc, adjusted_mode);
1462 if (ASIC_IS_DCE4(rdev))
1463 atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
1464 else if (ASIC_IS_AVIVO(rdev)) {
1466 atombios_crtc_set_timing(crtc, adjusted_mode);
1468 atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
1470 atombios_crtc_set_timing(crtc, adjusted_mode);
1471 if (radeon_crtc->crtc_id == 0)
1472 atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
1473 radeon_legacy_atom_fixup(crtc);
1475 atombios_crtc_set_base(crtc, x, y, old_fb);
1476 atombios_overscan_setup(crtc, mode, adjusted_mode);
1477 atombios_scaler_setup(crtc);
1481 static bool atombios_crtc_mode_fixup(struct drm_crtc *crtc,
1482 struct drm_display_mode *mode,
1483 struct drm_display_mode *adjusted_mode)
1485 struct drm_device *dev = crtc->dev;
1486 struct radeon_device *rdev = dev->dev_private;
1488 /* adjust pm to upcoming mode change */
1489 radeon_pm_compute_clocks(rdev);
1491 if (!radeon_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
1496 static void atombios_crtc_prepare(struct drm_crtc *crtc)
1498 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1501 radeon_crtc->pll_id = radeon_atom_pick_pll(crtc);
1503 atombios_lock_crtc(crtc, ATOM_ENABLE);
1504 atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
1507 static void atombios_crtc_commit(struct drm_crtc *crtc)
1509 atombios_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
1510 atombios_lock_crtc(crtc, ATOM_DISABLE);
1513 static void atombios_crtc_disable(struct drm_crtc *crtc)
1515 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1516 atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
1518 switch (radeon_crtc->pll_id) {
1521 /* disable the ppll */
1522 atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id,
1523 0, 0, ATOM_DISABLE, 0, 0, 0, 0);
1528 radeon_crtc->pll_id = -1;
1531 static const struct drm_crtc_helper_funcs atombios_helper_funcs = {
1532 .dpms = atombios_crtc_dpms,
1533 .mode_fixup = atombios_crtc_mode_fixup,
1534 .mode_set = atombios_crtc_mode_set,
1535 .mode_set_base = atombios_crtc_set_base,
1536 .mode_set_base_atomic = atombios_crtc_set_base_atomic,
1537 .prepare = atombios_crtc_prepare,
1538 .commit = atombios_crtc_commit,
1539 .load_lut = radeon_crtc_load_lut,
1540 .disable = atombios_crtc_disable,
1543 void radeon_atombios_init_crtc(struct drm_device *dev,
1544 struct radeon_crtc *radeon_crtc)
1546 struct radeon_device *rdev = dev->dev_private;
1548 if (ASIC_IS_DCE4(rdev)) {
1549 switch (radeon_crtc->crtc_id) {
1552 radeon_crtc->crtc_offset = EVERGREEN_CRTC0_REGISTER_OFFSET;
1555 radeon_crtc->crtc_offset = EVERGREEN_CRTC1_REGISTER_OFFSET;
1558 radeon_crtc->crtc_offset = EVERGREEN_CRTC2_REGISTER_OFFSET;
1561 radeon_crtc->crtc_offset = EVERGREEN_CRTC3_REGISTER_OFFSET;
1564 radeon_crtc->crtc_offset = EVERGREEN_CRTC4_REGISTER_OFFSET;
1567 radeon_crtc->crtc_offset = EVERGREEN_CRTC5_REGISTER_OFFSET;
1571 if (radeon_crtc->crtc_id == 1)
1572 radeon_crtc->crtc_offset =
1573 AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL;
1575 radeon_crtc->crtc_offset = 0;
1577 radeon_crtc->pll_id = -1;
1578 drm_crtc_helper_add(&radeon_crtc->base, &atombios_helper_funcs);