2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
23 * Authors: Dave Airlie
27 #include <drm/drm_crtc_helper.h>
28 #include <drm/drm_fb_helper.h>
29 #include <drm/radeon_drm.h>
30 #include <drm/drm_fixed.h>
33 #include "atom-bits.h"
35 static void atombios_overscan_setup(struct drm_crtc *crtc,
36 struct drm_display_mode *mode,
37 struct drm_display_mode *adjusted_mode)
39 struct drm_device *dev = crtc->dev;
40 struct radeon_device *rdev = dev->dev_private;
41 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
42 SET_CRTC_OVERSCAN_PS_ALLOCATION args;
43 int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_OverScan);
46 memset(&args, 0, sizeof(args));
48 args.ucCRTC = radeon_crtc->crtc_id;
50 switch (radeon_crtc->rmx_type) {
52 args.usOverscanTop = cpu_to_le16((adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2);
53 args.usOverscanBottom = cpu_to_le16((adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2);
54 args.usOverscanLeft = cpu_to_le16((adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2);
55 args.usOverscanRight = cpu_to_le16((adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2);
58 a1 = mode->crtc_vdisplay * adjusted_mode->crtc_hdisplay;
59 a2 = adjusted_mode->crtc_vdisplay * mode->crtc_hdisplay;
62 args.usOverscanLeft = cpu_to_le16((adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2);
63 args.usOverscanRight = cpu_to_le16((adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2);
65 args.usOverscanTop = cpu_to_le16((adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2);
66 args.usOverscanBottom = cpu_to_le16((adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2);
71 args.usOverscanRight = cpu_to_le16(radeon_crtc->h_border);
72 args.usOverscanLeft = cpu_to_le16(radeon_crtc->h_border);
73 args.usOverscanBottom = cpu_to_le16(radeon_crtc->v_border);
74 args.usOverscanTop = cpu_to_le16(radeon_crtc->v_border);
77 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
80 static void atombios_scaler_setup(struct drm_crtc *crtc)
82 struct drm_device *dev = crtc->dev;
83 struct radeon_device *rdev = dev->dev_private;
84 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
85 ENABLE_SCALER_PS_ALLOCATION args;
86 int index = GetIndexIntoMasterTable(COMMAND, EnableScaler);
87 struct radeon_encoder *radeon_encoder =
88 to_radeon_encoder(radeon_crtc->encoder);
89 /* fixme - fill in enc_priv for atom dac */
90 enum radeon_tv_std tv_std = TV_STD_NTSC;
91 bool is_tv = false, is_cv = false;
93 if (!ASIC_IS_AVIVO(rdev) && radeon_crtc->crtc_id)
96 if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) {
97 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv;
98 tv_std = tv_dac->tv_std;
102 memset(&args, 0, sizeof(args));
104 args.ucScaler = radeon_crtc->crtc_id;
110 args.ucTVStandard = ATOM_TV_NTSC;
113 args.ucTVStandard = ATOM_TV_PAL;
116 args.ucTVStandard = ATOM_TV_PALM;
119 args.ucTVStandard = ATOM_TV_PAL60;
122 args.ucTVStandard = ATOM_TV_NTSCJ;
124 case TV_STD_SCART_PAL:
125 args.ucTVStandard = ATOM_TV_PAL; /* ??? */
128 args.ucTVStandard = ATOM_TV_SECAM;
131 args.ucTVStandard = ATOM_TV_PALCN;
134 args.ucEnable = SCALER_ENABLE_MULTITAP_MODE;
136 args.ucTVStandard = ATOM_TV_CV;
137 args.ucEnable = SCALER_ENABLE_MULTITAP_MODE;
139 switch (radeon_crtc->rmx_type) {
141 args.ucEnable = ATOM_SCALER_EXPANSION;
144 args.ucEnable = ATOM_SCALER_CENTER;
147 args.ucEnable = ATOM_SCALER_EXPANSION;
150 if (ASIC_IS_AVIVO(rdev))
151 args.ucEnable = ATOM_SCALER_DISABLE;
153 args.ucEnable = ATOM_SCALER_CENTER;
157 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
159 && rdev->family >= CHIP_RV515 && rdev->family <= CHIP_R580) {
160 atom_rv515_force_tv_scaler(rdev, radeon_crtc);
164 static void atombios_lock_crtc(struct drm_crtc *crtc, int lock)
166 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
167 struct drm_device *dev = crtc->dev;
168 struct radeon_device *rdev = dev->dev_private;
170 GetIndexIntoMasterTable(COMMAND, UpdateCRTC_DoubleBufferRegisters);
171 ENABLE_CRTC_PS_ALLOCATION args;
173 memset(&args, 0, sizeof(args));
175 args.ucCRTC = radeon_crtc->crtc_id;
176 args.ucEnable = lock;
178 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
181 static void atombios_enable_crtc(struct drm_crtc *crtc, int state)
183 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
184 struct drm_device *dev = crtc->dev;
185 struct radeon_device *rdev = dev->dev_private;
186 int index = GetIndexIntoMasterTable(COMMAND, EnableCRTC);
187 ENABLE_CRTC_PS_ALLOCATION args;
189 memset(&args, 0, sizeof(args));
191 args.ucCRTC = radeon_crtc->crtc_id;
192 args.ucEnable = state;
194 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
197 static void atombios_enable_crtc_memreq(struct drm_crtc *crtc, int state)
199 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
200 struct drm_device *dev = crtc->dev;
201 struct radeon_device *rdev = dev->dev_private;
202 int index = GetIndexIntoMasterTable(COMMAND, EnableCRTCMemReq);
203 ENABLE_CRTC_PS_ALLOCATION args;
205 memset(&args, 0, sizeof(args));
207 args.ucCRTC = radeon_crtc->crtc_id;
208 args.ucEnable = state;
210 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
213 static const u32 vga_control_regs[6] =
217 EVERGREEN_D3VGA_CONTROL,
218 EVERGREEN_D4VGA_CONTROL,
219 EVERGREEN_D5VGA_CONTROL,
220 EVERGREEN_D6VGA_CONTROL,
223 static void atombios_blank_crtc(struct drm_crtc *crtc, int state)
225 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
226 struct drm_device *dev = crtc->dev;
227 struct radeon_device *rdev = dev->dev_private;
228 int index = GetIndexIntoMasterTable(COMMAND, BlankCRTC);
229 BLANK_CRTC_PS_ALLOCATION args;
232 memset(&args, 0, sizeof(args));
234 if (ASIC_IS_DCE8(rdev)) {
235 vga_control = RREG32(vga_control_regs[radeon_crtc->crtc_id]);
236 WREG32(vga_control_regs[radeon_crtc->crtc_id], vga_control | 1);
239 args.ucCRTC = radeon_crtc->crtc_id;
240 args.ucBlanking = state;
242 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
244 if (ASIC_IS_DCE8(rdev)) {
245 WREG32(vga_control_regs[radeon_crtc->crtc_id], vga_control);
249 static void atombios_powergate_crtc(struct drm_crtc *crtc, int state)
251 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
252 struct drm_device *dev = crtc->dev;
253 struct radeon_device *rdev = dev->dev_private;
254 int index = GetIndexIntoMasterTable(COMMAND, EnableDispPowerGating);
255 ENABLE_DISP_POWER_GATING_PARAMETERS_V2_1 args;
257 memset(&args, 0, sizeof(args));
259 args.ucDispPipeId = radeon_crtc->crtc_id;
260 args.ucEnable = state;
262 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
265 void atombios_crtc_dpms(struct drm_crtc *crtc, int mode)
267 struct drm_device *dev = crtc->dev;
268 struct radeon_device *rdev = dev->dev_private;
269 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
272 case DRM_MODE_DPMS_ON:
273 radeon_crtc->enabled = true;
274 atombios_enable_crtc(crtc, ATOM_ENABLE);
275 if (ASIC_IS_DCE3(rdev) && !ASIC_IS_DCE6(rdev))
276 atombios_enable_crtc_memreq(crtc, ATOM_ENABLE);
277 atombios_blank_crtc(crtc, ATOM_DISABLE);
278 if (dev->num_crtcs > radeon_crtc->crtc_id)
279 drm_crtc_vblank_on(crtc);
280 radeon_crtc_load_lut(crtc);
282 case DRM_MODE_DPMS_STANDBY:
283 case DRM_MODE_DPMS_SUSPEND:
284 case DRM_MODE_DPMS_OFF:
285 if (dev->num_crtcs > radeon_crtc->crtc_id)
286 drm_crtc_vblank_off(crtc);
287 if (radeon_crtc->enabled)
288 atombios_blank_crtc(crtc, ATOM_ENABLE);
289 if (ASIC_IS_DCE3(rdev) && !ASIC_IS_DCE6(rdev))
290 atombios_enable_crtc_memreq(crtc, ATOM_DISABLE);
291 atombios_enable_crtc(crtc, ATOM_DISABLE);
292 radeon_crtc->enabled = false;
295 /* adjust pm to dpms */
296 radeon_pm_compute_clocks(rdev);
300 atombios_set_crtc_dtd_timing(struct drm_crtc *crtc,
301 struct drm_display_mode *mode)
303 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
304 struct drm_device *dev = crtc->dev;
305 struct radeon_device *rdev = dev->dev_private;
306 SET_CRTC_USING_DTD_TIMING_PARAMETERS args;
307 int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_UsingDTDTiming);
310 memset(&args, 0, sizeof(args));
311 args.usH_Size = cpu_to_le16(mode->crtc_hdisplay - (radeon_crtc->h_border * 2));
312 args.usH_Blanking_Time =
313 cpu_to_le16(mode->crtc_hblank_end - mode->crtc_hdisplay + (radeon_crtc->h_border * 2));
314 args.usV_Size = cpu_to_le16(mode->crtc_vdisplay - (radeon_crtc->v_border * 2));
315 args.usV_Blanking_Time =
316 cpu_to_le16(mode->crtc_vblank_end - mode->crtc_vdisplay + (radeon_crtc->v_border * 2));
317 args.usH_SyncOffset =
318 cpu_to_le16(mode->crtc_hsync_start - mode->crtc_hdisplay + radeon_crtc->h_border);
320 cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start);
321 args.usV_SyncOffset =
322 cpu_to_le16(mode->crtc_vsync_start - mode->crtc_vdisplay + radeon_crtc->v_border);
324 cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start);
325 args.ucH_Border = radeon_crtc->h_border;
326 args.ucV_Border = radeon_crtc->v_border;
328 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
329 misc |= ATOM_VSYNC_POLARITY;
330 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
331 misc |= ATOM_HSYNC_POLARITY;
332 if (mode->flags & DRM_MODE_FLAG_CSYNC)
333 misc |= ATOM_COMPOSITESYNC;
334 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
335 misc |= ATOM_INTERLACE;
336 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
337 misc |= ATOM_DOUBLE_CLOCK_MODE;
338 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
339 misc |= ATOM_H_REPLICATIONBY2 | ATOM_V_REPLICATIONBY2;
341 args.susModeMiscInfo.usAccess = cpu_to_le16(misc);
342 args.ucCRTC = radeon_crtc->crtc_id;
344 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
347 static void atombios_crtc_set_timing(struct drm_crtc *crtc,
348 struct drm_display_mode *mode)
350 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
351 struct drm_device *dev = crtc->dev;
352 struct radeon_device *rdev = dev->dev_private;
353 SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION args;
354 int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_Timing);
357 memset(&args, 0, sizeof(args));
358 args.usH_Total = cpu_to_le16(mode->crtc_htotal);
359 args.usH_Disp = cpu_to_le16(mode->crtc_hdisplay);
360 args.usH_SyncStart = cpu_to_le16(mode->crtc_hsync_start);
362 cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start);
363 args.usV_Total = cpu_to_le16(mode->crtc_vtotal);
364 args.usV_Disp = cpu_to_le16(mode->crtc_vdisplay);
365 args.usV_SyncStart = cpu_to_le16(mode->crtc_vsync_start);
367 cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start);
369 args.ucOverscanRight = radeon_crtc->h_border;
370 args.ucOverscanLeft = radeon_crtc->h_border;
371 args.ucOverscanBottom = radeon_crtc->v_border;
372 args.ucOverscanTop = radeon_crtc->v_border;
374 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
375 misc |= ATOM_VSYNC_POLARITY;
376 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
377 misc |= ATOM_HSYNC_POLARITY;
378 if (mode->flags & DRM_MODE_FLAG_CSYNC)
379 misc |= ATOM_COMPOSITESYNC;
380 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
381 misc |= ATOM_INTERLACE;
382 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
383 misc |= ATOM_DOUBLE_CLOCK_MODE;
384 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
385 misc |= ATOM_H_REPLICATIONBY2 | ATOM_V_REPLICATIONBY2;
387 args.susModeMiscInfo.usAccess = cpu_to_le16(misc);
388 args.ucCRTC = radeon_crtc->crtc_id;
390 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
393 static void atombios_disable_ss(struct radeon_device *rdev, int pll_id)
397 if (ASIC_IS_DCE4(rdev)) {
400 ss_cntl = RREG32(EVERGREEN_P1PLL_SS_CNTL);
401 ss_cntl &= ~EVERGREEN_PxPLL_SS_EN;
402 WREG32(EVERGREEN_P1PLL_SS_CNTL, ss_cntl);
405 ss_cntl = RREG32(EVERGREEN_P2PLL_SS_CNTL);
406 ss_cntl &= ~EVERGREEN_PxPLL_SS_EN;
407 WREG32(EVERGREEN_P2PLL_SS_CNTL, ss_cntl);
410 case ATOM_PPLL_INVALID:
413 } else if (ASIC_IS_AVIVO(rdev)) {
416 ss_cntl = RREG32(AVIVO_P1PLL_INT_SS_CNTL);
418 WREG32(AVIVO_P1PLL_INT_SS_CNTL, ss_cntl);
421 ss_cntl = RREG32(AVIVO_P2PLL_INT_SS_CNTL);
423 WREG32(AVIVO_P2PLL_INT_SS_CNTL, ss_cntl);
426 case ATOM_PPLL_INVALID:
433 union atom_enable_ss {
434 ENABLE_LVDS_SS_PARAMETERS lvds_ss;
435 ENABLE_LVDS_SS_PARAMETERS_V2 lvds_ss_2;
436 ENABLE_SPREAD_SPECTRUM_ON_PPLL_PS_ALLOCATION v1;
437 ENABLE_SPREAD_SPECTRUM_ON_PPLL_V2 v2;
438 ENABLE_SPREAD_SPECTRUM_ON_PPLL_V3 v3;
441 static void atombios_crtc_program_ss(struct radeon_device *rdev,
445 struct radeon_atom_ss *ss)
448 int index = GetIndexIntoMasterTable(COMMAND, EnableSpreadSpectrumOnPPLL);
449 union atom_enable_ss args;
452 /* Don't mess with SS if percentage is 0 or external ss.
453 * SS is already disabled previously, and disabling it
454 * again can cause display problems if the pll is already
457 if (ss->percentage == 0)
459 if (ss->type & ATOM_EXTERNAL_SS_MASK)
462 for (i = 0; i < rdev->num_crtc; i++) {
463 if (rdev->mode_info.crtcs[i] &&
464 rdev->mode_info.crtcs[i]->enabled &&
466 pll_id == rdev->mode_info.crtcs[i]->pll_id) {
467 /* one other crtc is using this pll don't turn
468 * off spread spectrum as it might turn off
469 * display on active crtc
476 memset(&args, 0, sizeof(args));
478 if (ASIC_IS_DCE5(rdev)) {
479 args.v3.usSpreadSpectrumAmountFrac = cpu_to_le16(0);
480 args.v3.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
483 args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_P1PLL;
486 args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_P2PLL;
489 args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_DCPLL;
491 case ATOM_PPLL_INVALID:
494 args.v3.usSpreadSpectrumAmount = cpu_to_le16(ss->amount);
495 args.v3.usSpreadSpectrumStep = cpu_to_le16(ss->step);
496 args.v3.ucEnable = enable;
497 } else if (ASIC_IS_DCE4(rdev)) {
498 args.v2.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
499 args.v2.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
502 args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_P1PLL;
505 args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_P2PLL;
508 args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_DCPLL;
510 case ATOM_PPLL_INVALID:
513 args.v2.usSpreadSpectrumAmount = cpu_to_le16(ss->amount);
514 args.v2.usSpreadSpectrumStep = cpu_to_le16(ss->step);
515 args.v2.ucEnable = enable;
516 } else if (ASIC_IS_DCE3(rdev)) {
517 args.v1.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
518 args.v1.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
519 args.v1.ucSpreadSpectrumStep = ss->step;
520 args.v1.ucSpreadSpectrumDelay = ss->delay;
521 args.v1.ucSpreadSpectrumRange = ss->range;
522 args.v1.ucPpll = pll_id;
523 args.v1.ucEnable = enable;
524 } else if (ASIC_IS_AVIVO(rdev)) {
525 if ((enable == ATOM_DISABLE) || (ss->percentage == 0) ||
526 (ss->type & ATOM_EXTERNAL_SS_MASK)) {
527 atombios_disable_ss(rdev, pll_id);
530 args.lvds_ss_2.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
531 args.lvds_ss_2.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
532 args.lvds_ss_2.ucSpreadSpectrumStep = ss->step;
533 args.lvds_ss_2.ucSpreadSpectrumDelay = ss->delay;
534 args.lvds_ss_2.ucSpreadSpectrumRange = ss->range;
535 args.lvds_ss_2.ucEnable = enable;
537 if (enable == ATOM_DISABLE) {
538 atombios_disable_ss(rdev, pll_id);
541 args.lvds_ss.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
542 args.lvds_ss.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
543 args.lvds_ss.ucSpreadSpectrumStepSize_Delay = (ss->step & 3) << 2;
544 args.lvds_ss.ucSpreadSpectrumStepSize_Delay |= (ss->delay & 7) << 4;
545 args.lvds_ss.ucEnable = enable;
547 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
550 union adjust_pixel_clock {
551 ADJUST_DISPLAY_PLL_PS_ALLOCATION v1;
552 ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3 v3;
555 static u32 atombios_adjust_pll(struct drm_crtc *crtc,
556 struct drm_display_mode *mode)
558 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
559 struct drm_device *dev = crtc->dev;
560 struct radeon_device *rdev = dev->dev_private;
561 struct drm_encoder *encoder = radeon_crtc->encoder;
562 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
563 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
564 u32 adjusted_clock = mode->clock;
565 int encoder_mode = atombios_get_encoder_mode(encoder);
566 u32 dp_clock = mode->clock;
567 u32 clock = mode->clock;
568 int bpc = radeon_crtc->bpc;
569 bool is_duallink = radeon_dig_monitor_is_duallink(encoder, mode->clock);
571 /* reset the pll flags */
572 radeon_crtc->pll_flags = 0;
574 if (ASIC_IS_AVIVO(rdev)) {
575 if ((rdev->family == CHIP_RS600) ||
576 (rdev->family == CHIP_RS690) ||
577 (rdev->family == CHIP_RS740))
578 radeon_crtc->pll_flags |= (/*RADEON_PLL_USE_FRAC_FB_DIV |*/
579 RADEON_PLL_PREFER_CLOSEST_LOWER);
581 if (ASIC_IS_DCE32(rdev) && mode->clock > 200000) /* range limits??? */
582 radeon_crtc->pll_flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
584 radeon_crtc->pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
586 if (rdev->family < CHIP_RV770)
587 radeon_crtc->pll_flags |= RADEON_PLL_PREFER_MINM_OVER_MAXP;
588 /* use frac fb div on APUs */
589 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev) || ASIC_IS_DCE8(rdev))
590 radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;
591 /* use frac fb div on RS780/RS880 */
592 if (((rdev->family == CHIP_RS780) || (rdev->family == CHIP_RS880))
593 && !radeon_crtc->ss_enabled)
594 radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;
595 if (ASIC_IS_DCE32(rdev) && mode->clock > 165000)
596 radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;
598 radeon_crtc->pll_flags |= RADEON_PLL_LEGACY;
600 if (mode->clock > 200000) /* range limits??? */
601 radeon_crtc->pll_flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
603 radeon_crtc->pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
606 if ((radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) ||
607 (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE)) {
609 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
610 struct radeon_connector_atom_dig *dig_connector =
611 radeon_connector->con_priv;
613 dp_clock = dig_connector->dp_clock;
617 if (radeon_encoder->is_mst_encoder) {
618 struct radeon_encoder_mst *mst_enc = radeon_encoder->enc_priv;
619 struct radeon_connector_atom_dig *dig_connector = mst_enc->connector->con_priv;
621 dp_clock = dig_connector->dp_clock;
624 /* use recommended ref_div for ss */
625 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
626 if (radeon_crtc->ss_enabled) {
627 if (radeon_crtc->ss.refdiv) {
628 radeon_crtc->pll_flags |= RADEON_PLL_USE_REF_DIV;
629 radeon_crtc->pll_reference_div = radeon_crtc->ss.refdiv;
630 if (ASIC_IS_AVIVO(rdev) &&
631 rdev->family != CHIP_RS780 &&
632 rdev->family != CHIP_RS880)
633 radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;
638 if (ASIC_IS_AVIVO(rdev)) {
639 /* DVO wants 2x pixel clock if the DVO chip is in 12 bit mode */
640 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1)
641 adjusted_clock = mode->clock * 2;
642 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
643 radeon_crtc->pll_flags |= RADEON_PLL_PREFER_CLOSEST_LOWER;
644 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
645 radeon_crtc->pll_flags |= RADEON_PLL_IS_LCD;
647 if (encoder->encoder_type != DRM_MODE_ENCODER_DAC)
648 radeon_crtc->pll_flags |= RADEON_PLL_NO_ODD_POST_DIV;
649 if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS)
650 radeon_crtc->pll_flags |= RADEON_PLL_USE_REF_DIV;
653 /* adjust pll for deep color modes */
654 if (encoder_mode == ATOM_ENCODER_MODE_HDMI) {
660 clock = (clock * 5) / 4;
663 clock = (clock * 3) / 2;
671 /* DCE3+ has an AdjustDisplayPll that will adjust the pixel clock
672 * accordingly based on the encoder/transmitter to work around
673 * special hw requirements.
675 if (ASIC_IS_DCE3(rdev)) {
676 union adjust_pixel_clock args;
680 index = GetIndexIntoMasterTable(COMMAND, AdjustDisplayPll);
681 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
683 return adjusted_clock;
685 memset(&args, 0, sizeof(args));
692 args.v1.usPixelClock = cpu_to_le16(clock / 10);
693 args.v1.ucTransmitterID = radeon_encoder->encoder_id;
694 args.v1.ucEncodeMode = encoder_mode;
695 if (radeon_crtc->ss_enabled && radeon_crtc->ss.percentage)
697 ADJUST_DISPLAY_CONFIG_SS_ENABLE;
699 atom_execute_table(rdev->mode_info.atom_context,
700 index, (uint32_t *)&args);
701 adjusted_clock = le16_to_cpu(args.v1.usPixelClock) * 10;
704 args.v3.sInput.usPixelClock = cpu_to_le16(clock / 10);
705 args.v3.sInput.ucTransmitterID = radeon_encoder->encoder_id;
706 args.v3.sInput.ucEncodeMode = encoder_mode;
707 args.v3.sInput.ucDispPllConfig = 0;
708 if (radeon_crtc->ss_enabled && radeon_crtc->ss.percentage)
709 args.v3.sInput.ucDispPllConfig |=
710 DISPPLL_CONFIG_SS_ENABLE;
711 if (ENCODER_MODE_IS_DP(encoder_mode)) {
712 args.v3.sInput.ucDispPllConfig |=
713 DISPPLL_CONFIG_COHERENT_MODE;
715 args.v3.sInput.usPixelClock = cpu_to_le16(dp_clock / 10);
716 } else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
717 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
718 if (dig->coherent_mode)
719 args.v3.sInput.ucDispPllConfig |=
720 DISPPLL_CONFIG_COHERENT_MODE;
722 args.v3.sInput.ucDispPllConfig |=
723 DISPPLL_CONFIG_DUAL_LINK;
725 if (radeon_encoder_get_dp_bridge_encoder_id(encoder) !=
726 ENCODER_OBJECT_ID_NONE)
727 args.v3.sInput.ucExtTransmitterID =
728 radeon_encoder_get_dp_bridge_encoder_id(encoder);
730 args.v3.sInput.ucExtTransmitterID = 0;
732 atom_execute_table(rdev->mode_info.atom_context,
733 index, (uint32_t *)&args);
734 adjusted_clock = le32_to_cpu(args.v3.sOutput.ulDispPllFreq) * 10;
735 if (args.v3.sOutput.ucRefDiv) {
736 radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;
737 radeon_crtc->pll_flags |= RADEON_PLL_USE_REF_DIV;
738 radeon_crtc->pll_reference_div = args.v3.sOutput.ucRefDiv;
740 if (args.v3.sOutput.ucPostDiv) {
741 radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;
742 radeon_crtc->pll_flags |= RADEON_PLL_USE_POST_DIV;
743 radeon_crtc->pll_post_div = args.v3.sOutput.ucPostDiv;
747 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
748 return adjusted_clock;
752 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
753 return adjusted_clock;
756 return adjusted_clock;
759 union set_pixel_clock {
760 SET_PIXEL_CLOCK_PS_ALLOCATION base;
761 PIXEL_CLOCK_PARAMETERS v1;
762 PIXEL_CLOCK_PARAMETERS_V2 v2;
763 PIXEL_CLOCK_PARAMETERS_V3 v3;
764 PIXEL_CLOCK_PARAMETERS_V5 v5;
765 PIXEL_CLOCK_PARAMETERS_V6 v6;
768 /* on DCE5, make sure the voltage is high enough to support the
771 static void atombios_crtc_set_disp_eng_pll(struct radeon_device *rdev,
776 union set_pixel_clock args;
778 memset(&args, 0, sizeof(args));
780 index = GetIndexIntoMasterTable(COMMAND, SetPixelClock);
781 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
789 /* if the default dcpll clock is specified,
790 * SetPixelClock provides the dividers
792 args.v5.ucCRTC = ATOM_CRTC_INVALID;
793 args.v5.usPixelClock = cpu_to_le16(dispclk);
794 args.v5.ucPpll = ATOM_DCPLL;
797 /* if the default dcpll clock is specified,
798 * SetPixelClock provides the dividers
800 args.v6.ulDispEngClkFreq = cpu_to_le32(dispclk);
801 if (ASIC_IS_DCE61(rdev) || ASIC_IS_DCE8(rdev))
802 args.v6.ucPpll = ATOM_EXT_PLL1;
803 else if (ASIC_IS_DCE6(rdev))
804 args.v6.ucPpll = ATOM_PPLL0;
806 args.v6.ucPpll = ATOM_DCPLL;
809 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
814 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
817 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
820 static void atombios_crtc_program_pll(struct drm_crtc *crtc,
832 struct radeon_atom_ss *ss)
834 struct drm_device *dev = crtc->dev;
835 struct radeon_device *rdev = dev->dev_private;
837 int index = GetIndexIntoMasterTable(COMMAND, SetPixelClock);
838 union set_pixel_clock args;
840 memset(&args, 0, sizeof(args));
842 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
850 if (clock == ATOM_DISABLE)
852 args.v1.usPixelClock = cpu_to_le16(clock / 10);
853 args.v1.usRefDiv = cpu_to_le16(ref_div);
854 args.v1.usFbDiv = cpu_to_le16(fb_div);
855 args.v1.ucFracFbDiv = frac_fb_div;
856 args.v1.ucPostDiv = post_div;
857 args.v1.ucPpll = pll_id;
858 args.v1.ucCRTC = crtc_id;
859 args.v1.ucRefDivSrc = 1;
862 args.v2.usPixelClock = cpu_to_le16(clock / 10);
863 args.v2.usRefDiv = cpu_to_le16(ref_div);
864 args.v2.usFbDiv = cpu_to_le16(fb_div);
865 args.v2.ucFracFbDiv = frac_fb_div;
866 args.v2.ucPostDiv = post_div;
867 args.v2.ucPpll = pll_id;
868 args.v2.ucCRTC = crtc_id;
869 args.v2.ucRefDivSrc = 1;
872 args.v3.usPixelClock = cpu_to_le16(clock / 10);
873 args.v3.usRefDiv = cpu_to_le16(ref_div);
874 args.v3.usFbDiv = cpu_to_le16(fb_div);
875 args.v3.ucFracFbDiv = frac_fb_div;
876 args.v3.ucPostDiv = post_div;
877 args.v3.ucPpll = pll_id;
878 if (crtc_id == ATOM_CRTC2)
879 args.v3.ucMiscInfo = PIXEL_CLOCK_MISC_CRTC_SEL_CRTC2;
881 args.v3.ucMiscInfo = PIXEL_CLOCK_MISC_CRTC_SEL_CRTC1;
882 if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK))
883 args.v3.ucMiscInfo |= PIXEL_CLOCK_MISC_REF_DIV_SRC;
884 args.v3.ucTransmitterId = encoder_id;
885 args.v3.ucEncoderMode = encoder_mode;
888 args.v5.ucCRTC = crtc_id;
889 args.v5.usPixelClock = cpu_to_le16(clock / 10);
890 args.v5.ucRefDiv = ref_div;
891 args.v5.usFbDiv = cpu_to_le16(fb_div);
892 args.v5.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000);
893 args.v5.ucPostDiv = post_div;
894 args.v5.ucMiscInfo = 0; /* HDMI depth, etc. */
895 if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK))
896 args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_REF_DIV_SRC;
897 if (encoder_mode == ATOM_ENCODER_MODE_HDMI) {
901 args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_24BPP;
904 /* yes this is correct, the atom define is wrong */
905 args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_32BPP;
908 /* yes this is correct, the atom define is wrong */
909 args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_30BPP;
913 args.v5.ucTransmitterID = encoder_id;
914 args.v5.ucEncoderMode = encoder_mode;
915 args.v5.ucPpll = pll_id;
918 args.v6.ulDispEngClkFreq = cpu_to_le32(crtc_id << 24 | clock / 10);
919 args.v6.ucRefDiv = ref_div;
920 args.v6.usFbDiv = cpu_to_le16(fb_div);
921 args.v6.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000);
922 args.v6.ucPostDiv = post_div;
923 args.v6.ucMiscInfo = 0; /* HDMI depth, etc. */
924 if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK))
925 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_REF_DIV_SRC;
926 if (encoder_mode == ATOM_ENCODER_MODE_HDMI) {
930 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_24BPP;
933 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_30BPP_V6;
936 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_36BPP_V6;
939 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_48BPP;
943 args.v6.ucTransmitterID = encoder_id;
944 args.v6.ucEncoderMode = encoder_mode;
945 args.v6.ucPpll = pll_id;
948 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
953 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
957 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
960 static bool atombios_crtc_prepare_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
962 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
963 struct drm_device *dev = crtc->dev;
964 struct radeon_device *rdev = dev->dev_private;
965 struct radeon_encoder *radeon_encoder =
966 to_radeon_encoder(radeon_crtc->encoder);
967 int encoder_mode = atombios_get_encoder_mode(radeon_crtc->encoder);
969 radeon_crtc->bpc = 8;
970 radeon_crtc->ss_enabled = false;
972 if (radeon_encoder->is_mst_encoder) {
973 radeon_dp_mst_prepare_pll(crtc, mode);
974 } else if ((radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) ||
975 (radeon_encoder_get_dp_bridge_encoder_id(radeon_crtc->encoder) != ENCODER_OBJECT_ID_NONE)) {
976 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
977 struct drm_connector *connector =
978 radeon_get_connector_for_encoder(radeon_crtc->encoder);
979 struct radeon_connector *radeon_connector =
980 to_radeon_connector(connector);
981 struct radeon_connector_atom_dig *dig_connector =
982 radeon_connector->con_priv;
985 /* Assign mode clock for hdmi deep color max clock limit check */
986 radeon_connector->pixelclock_for_modeset = mode->clock;
987 radeon_crtc->bpc = radeon_get_monitor_bpc(connector);
989 switch (encoder_mode) {
990 case ATOM_ENCODER_MODE_DP_MST:
991 case ATOM_ENCODER_MODE_DP:
993 dp_clock = dig_connector->dp_clock / 10;
994 if (ASIC_IS_DCE4(rdev))
995 radeon_crtc->ss_enabled =
996 radeon_atombios_get_asic_ss_info(rdev, &radeon_crtc->ss,
997 ASIC_INTERNAL_SS_ON_DP,
1000 if (dp_clock == 16200) {
1001 radeon_crtc->ss_enabled =
1002 radeon_atombios_get_ppll_ss_info(rdev,
1005 if (!radeon_crtc->ss_enabled)
1006 radeon_crtc->ss_enabled =
1007 radeon_atombios_get_ppll_ss_info(rdev,
1011 radeon_crtc->ss_enabled =
1012 radeon_atombios_get_ppll_ss_info(rdev,
1016 /* disable spread spectrum on DCE3 DP */
1017 radeon_crtc->ss_enabled = false;
1020 case ATOM_ENCODER_MODE_LVDS:
1021 if (ASIC_IS_DCE4(rdev))
1022 radeon_crtc->ss_enabled =
1023 radeon_atombios_get_asic_ss_info(rdev,
1028 radeon_crtc->ss_enabled =
1029 radeon_atombios_get_ppll_ss_info(rdev,
1033 case ATOM_ENCODER_MODE_DVI:
1034 if (ASIC_IS_DCE4(rdev))
1035 radeon_crtc->ss_enabled =
1036 radeon_atombios_get_asic_ss_info(rdev,
1038 ASIC_INTERNAL_SS_ON_TMDS,
1041 case ATOM_ENCODER_MODE_HDMI:
1042 if (ASIC_IS_DCE4(rdev))
1043 radeon_crtc->ss_enabled =
1044 radeon_atombios_get_asic_ss_info(rdev,
1046 ASIC_INTERNAL_SS_ON_HDMI,
1054 /* adjust pixel clock as needed */
1055 radeon_crtc->adjusted_clock = atombios_adjust_pll(crtc, mode);
1060 static void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
1062 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1063 struct drm_device *dev = crtc->dev;
1064 struct radeon_device *rdev = dev->dev_private;
1065 struct radeon_encoder *radeon_encoder =
1066 to_radeon_encoder(radeon_crtc->encoder);
1067 u32 pll_clock = mode->clock;
1068 u32 clock = mode->clock;
1069 u32 ref_div = 0, fb_div = 0, frac_fb_div = 0, post_div = 0;
1070 struct radeon_pll *pll;
1071 int encoder_mode = atombios_get_encoder_mode(radeon_crtc->encoder);
1073 /* pass the actual clock to atombios_crtc_program_pll for DCE5,6 for HDMI */
1074 if (ASIC_IS_DCE5(rdev) &&
1075 (encoder_mode == ATOM_ENCODER_MODE_HDMI) &&
1076 (radeon_crtc->bpc > 8))
1077 clock = radeon_crtc->adjusted_clock;
1079 switch (radeon_crtc->pll_id) {
1081 pll = &rdev->clock.p1pll;
1084 pll = &rdev->clock.p2pll;
1087 case ATOM_PPLL_INVALID:
1089 pll = &rdev->clock.dcpll;
1093 /* update pll params */
1094 pll->flags = radeon_crtc->pll_flags;
1095 pll->reference_div = radeon_crtc->pll_reference_div;
1096 pll->post_div = radeon_crtc->pll_post_div;
1098 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1099 /* TV seems to prefer the legacy algo on some boards */
1100 radeon_compute_pll_legacy(pll, radeon_crtc->adjusted_clock, &pll_clock,
1101 &fb_div, &frac_fb_div, &ref_div, &post_div);
1102 else if (ASIC_IS_AVIVO(rdev))
1103 radeon_compute_pll_avivo(pll, radeon_crtc->adjusted_clock, &pll_clock,
1104 &fb_div, &frac_fb_div, &ref_div, &post_div);
1106 radeon_compute_pll_legacy(pll, radeon_crtc->adjusted_clock, &pll_clock,
1107 &fb_div, &frac_fb_div, &ref_div, &post_div);
1109 atombios_crtc_program_ss(rdev, ATOM_DISABLE, radeon_crtc->pll_id,
1110 radeon_crtc->crtc_id, &radeon_crtc->ss);
1112 atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id,
1113 encoder_mode, radeon_encoder->encoder_id, clock,
1114 ref_div, fb_div, frac_fb_div, post_div,
1115 radeon_crtc->bpc, radeon_crtc->ss_enabled, &radeon_crtc->ss);
1117 if (radeon_crtc->ss_enabled) {
1118 /* calculate ss amount and step size */
1119 if (ASIC_IS_DCE4(rdev)) {
1121 u32 amount = (((fb_div * 10) + frac_fb_div) *
1122 (u32)radeon_crtc->ss.percentage) /
1123 (100 * (u32)radeon_crtc->ss.percentage_divider);
1124 radeon_crtc->ss.amount = (amount / 10) & ATOM_PPLL_SS_AMOUNT_V2_FBDIV_MASK;
1125 radeon_crtc->ss.amount |= ((amount - (amount / 10)) << ATOM_PPLL_SS_AMOUNT_V2_NFRAC_SHIFT) &
1126 ATOM_PPLL_SS_AMOUNT_V2_NFRAC_MASK;
1127 if (radeon_crtc->ss.type & ATOM_PPLL_SS_TYPE_V2_CENTRE_SPREAD)
1128 step_size = (4 * amount * ref_div * ((u32)radeon_crtc->ss.rate * 2048)) /
1129 (125 * 25 * pll->reference_freq / 100);
1131 step_size = (2 * amount * ref_div * ((u32)radeon_crtc->ss.rate * 2048)) /
1132 (125 * 25 * pll->reference_freq / 100);
1133 radeon_crtc->ss.step = step_size;
1136 atombios_crtc_program_ss(rdev, ATOM_ENABLE, radeon_crtc->pll_id,
1137 radeon_crtc->crtc_id, &radeon_crtc->ss);
1141 static int dce4_crtc_do_set_base(struct drm_crtc *crtc,
1142 struct drm_framebuffer *fb,
1143 int x, int y, int atomic)
1145 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1146 struct drm_device *dev = crtc->dev;
1147 struct radeon_device *rdev = dev->dev_private;
1148 struct radeon_framebuffer *radeon_fb;
1149 struct drm_framebuffer *target_fb;
1150 struct drm_gem_object *obj;
1151 struct radeon_bo *rbo;
1152 uint64_t fb_location;
1153 uint32_t fb_format, fb_pitch_pixels, tiling_flags;
1154 unsigned bankw, bankh, mtaspect, tile_split;
1155 u32 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_NONE);
1156 u32 tmp, viewport_w, viewport_h;
1158 bool bypass_lut = false;
1159 struct drm_format_name_buf format_name;
1162 if (!atomic && !crtc->primary->fb) {
1163 DRM_DEBUG_KMS("No FB bound\n");
1168 radeon_fb = to_radeon_framebuffer(fb);
1172 radeon_fb = to_radeon_framebuffer(crtc->primary->fb);
1173 target_fb = crtc->primary->fb;
1176 /* If atomic, assume fb object is pinned & idle & fenced and
1177 * just update base pointers
1179 obj = radeon_fb->obj;
1180 rbo = gem_to_radeon_bo(obj);
1181 r = radeon_bo_reserve(rbo, false);
1182 if (unlikely(r != 0))
1186 fb_location = radeon_bo_gpu_offset(rbo);
1188 r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location);
1189 if (unlikely(r != 0)) {
1190 radeon_bo_unreserve(rbo);
1195 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
1196 radeon_bo_unreserve(rbo);
1198 switch (target_fb->pixel_format) {
1200 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_8BPP) |
1201 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_INDEXED));
1203 case DRM_FORMAT_XRGB4444:
1204 case DRM_FORMAT_ARGB4444:
1205 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) |
1206 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB4444));
1208 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16);
1211 case DRM_FORMAT_XRGB1555:
1212 case DRM_FORMAT_ARGB1555:
1213 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) |
1214 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB1555));
1216 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16);
1219 case DRM_FORMAT_BGRX5551:
1220 case DRM_FORMAT_BGRA5551:
1221 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) |
1222 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_BGRA5551));
1224 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16);
1227 case DRM_FORMAT_RGB565:
1228 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) |
1229 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB565));
1231 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16);
1234 case DRM_FORMAT_XRGB8888:
1235 case DRM_FORMAT_ARGB8888:
1236 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) |
1237 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB8888));
1239 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN32);
1242 case DRM_FORMAT_XRGB2101010:
1243 case DRM_FORMAT_ARGB2101010:
1244 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) |
1245 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB2101010));
1247 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN32);
1249 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
1252 case DRM_FORMAT_BGRX1010102:
1253 case DRM_FORMAT_BGRA1010102:
1254 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) |
1255 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_BGRA1010102));
1257 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN32);
1259 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
1263 DRM_ERROR("Unsupported screen format %s\n",
1264 drm_get_format_name(target_fb->pixel_format, &format_name));
1268 if (tiling_flags & RADEON_TILING_MACRO) {
1269 evergreen_tiling_fields(tiling_flags, &bankw, &bankh, &mtaspect, &tile_split);
1271 /* Set NUM_BANKS. */
1272 if (rdev->family >= CHIP_TAHITI) {
1273 unsigned index, num_banks;
1275 if (rdev->family >= CHIP_BONAIRE) {
1276 unsigned tileb, tile_split_bytes;
1278 /* Calculate the macrotile mode index. */
1279 tile_split_bytes = 64 << tile_split;
1280 tileb = 8 * 8 * target_fb->bits_per_pixel / 8;
1281 tileb = min(tile_split_bytes, tileb);
1283 for (index = 0; tileb > 64; index++)
1287 DRM_ERROR("Wrong screen bpp (%u) or tile split (%u)\n",
1288 target_fb->bits_per_pixel, tile_split);
1292 num_banks = (rdev->config.cik.macrotile_mode_array[index] >> 6) & 0x3;
1294 switch (target_fb->bits_per_pixel) {
1299 index = SI_TILE_MODE_COLOR_2D_SCANOUT_16BPP;
1303 index = SI_TILE_MODE_COLOR_2D_SCANOUT_32BPP;
1307 num_banks = (rdev->config.si.tile_mode_array[index] >> 20) & 0x3;
1310 fb_format |= EVERGREEN_GRPH_NUM_BANKS(num_banks);
1313 if (rdev->family >= CHIP_CAYMAN)
1314 tmp = rdev->config.cayman.tile_config;
1316 tmp = rdev->config.evergreen.tile_config;
1318 switch ((tmp & 0xf0) >> 4) {
1319 case 0: /* 4 banks */
1320 fb_format |= EVERGREEN_GRPH_NUM_BANKS(EVERGREEN_ADDR_SURF_4_BANK);
1322 case 1: /* 8 banks */
1324 fb_format |= EVERGREEN_GRPH_NUM_BANKS(EVERGREEN_ADDR_SURF_8_BANK);
1326 case 2: /* 16 banks */
1327 fb_format |= EVERGREEN_GRPH_NUM_BANKS(EVERGREEN_ADDR_SURF_16_BANK);
1332 fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_2D_TILED_THIN1);
1333 fb_format |= EVERGREEN_GRPH_TILE_SPLIT(tile_split);
1334 fb_format |= EVERGREEN_GRPH_BANK_WIDTH(bankw);
1335 fb_format |= EVERGREEN_GRPH_BANK_HEIGHT(bankh);
1336 fb_format |= EVERGREEN_GRPH_MACRO_TILE_ASPECT(mtaspect);
1337 if (rdev->family >= CHIP_BONAIRE) {
1338 /* XXX need to know more about the surface tiling mode */
1339 fb_format |= CIK_GRPH_MICRO_TILE_MODE(CIK_DISPLAY_MICRO_TILING);
1341 } else if (tiling_flags & RADEON_TILING_MICRO)
1342 fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_1D_TILED_THIN1);
1344 if (rdev->family >= CHIP_BONAIRE) {
1345 /* Read the pipe config from the 2D TILED SCANOUT mode.
1346 * It should be the same for the other modes too, but not all
1347 * modes set the pipe config field. */
1348 u32 pipe_config = (rdev->config.cik.tile_mode_array[10] >> 6) & 0x1f;
1350 fb_format |= CIK_GRPH_PIPE_CONFIG(pipe_config);
1351 } else if ((rdev->family == CHIP_TAHITI) ||
1352 (rdev->family == CHIP_PITCAIRN))
1353 fb_format |= SI_GRPH_PIPE_CONFIG(SI_ADDR_SURF_P8_32x32_8x16);
1354 else if ((rdev->family == CHIP_VERDE) ||
1355 (rdev->family == CHIP_OLAND) ||
1356 (rdev->family == CHIP_HAINAN)) /* for completeness. HAINAN has no display hw */
1357 fb_format |= SI_GRPH_PIPE_CONFIG(SI_ADDR_SURF_P4_8x16);
1359 switch (radeon_crtc->crtc_id) {
1361 WREG32(AVIVO_D1VGA_CONTROL, 0);
1364 WREG32(AVIVO_D2VGA_CONTROL, 0);
1367 WREG32(EVERGREEN_D3VGA_CONTROL, 0);
1370 WREG32(EVERGREEN_D4VGA_CONTROL, 0);
1373 WREG32(EVERGREEN_D5VGA_CONTROL, 0);
1376 WREG32(EVERGREEN_D6VGA_CONTROL, 0);
1382 /* Make sure surface address is updated at vertical blank rather than
1385 WREG32(EVERGREEN_GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, 0);
1387 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
1388 upper_32_bits(fb_location));
1389 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
1390 upper_32_bits(fb_location));
1391 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
1392 (u32)fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK);
1393 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
1394 (u32) fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK);
1395 WREG32(EVERGREEN_GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format);
1396 WREG32(EVERGREEN_GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap);
1399 * The LUT only has 256 slots for indexing by a 8 bpc fb. Bypass the LUT
1400 * for > 8 bpc scanout to avoid truncation of fb indices to 8 msb's, to
1401 * retain the full precision throughout the pipeline.
1403 WREG32_P(EVERGREEN_GRPH_LUT_10BIT_BYPASS_CONTROL + radeon_crtc->crtc_offset,
1404 (bypass_lut ? EVERGREEN_LUT_10BIT_BYPASS_EN : 0),
1405 ~EVERGREEN_LUT_10BIT_BYPASS_EN);
1408 DRM_DEBUG_KMS("Bypassing hardware LUT due to 10 bit fb scanout.\n");
1410 WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0);
1411 WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0);
1412 WREG32(EVERGREEN_GRPH_X_START + radeon_crtc->crtc_offset, 0);
1413 WREG32(EVERGREEN_GRPH_Y_START + radeon_crtc->crtc_offset, 0);
1414 WREG32(EVERGREEN_GRPH_X_END + radeon_crtc->crtc_offset, target_fb->width);
1415 WREG32(EVERGREEN_GRPH_Y_END + radeon_crtc->crtc_offset, target_fb->height);
1417 fb_pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8);
1418 WREG32(EVERGREEN_GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels);
1419 WREG32(EVERGREEN_GRPH_ENABLE + radeon_crtc->crtc_offset, 1);
1421 if (rdev->family >= CHIP_BONAIRE)
1422 WREG32(CIK_LB_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,
1425 WREG32(EVERGREEN_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,
1429 WREG32(EVERGREEN_VIEWPORT_START + radeon_crtc->crtc_offset,
1431 viewport_w = crtc->mode.hdisplay;
1432 viewport_h = (crtc->mode.vdisplay + 1) & ~1;
1433 if ((rdev->family >= CHIP_BONAIRE) &&
1434 (crtc->mode.flags & DRM_MODE_FLAG_INTERLACE))
1436 WREG32(EVERGREEN_VIEWPORT_SIZE + radeon_crtc->crtc_offset,
1437 (viewport_w << 16) | viewport_h);
1439 /* set pageflip to happen anywhere in vblank interval */
1440 WREG32(EVERGREEN_MASTER_UPDATE_MODE + radeon_crtc->crtc_offset, 0);
1442 if (!atomic && fb && fb != crtc->primary->fb) {
1443 radeon_fb = to_radeon_framebuffer(fb);
1444 rbo = gem_to_radeon_bo(radeon_fb->obj);
1445 r = radeon_bo_reserve(rbo, false);
1446 if (unlikely(r != 0))
1448 radeon_bo_unpin(rbo);
1449 radeon_bo_unreserve(rbo);
1452 /* Bytes per pixel may have changed */
1453 radeon_bandwidth_update(rdev);
1458 static int avivo_crtc_do_set_base(struct drm_crtc *crtc,
1459 struct drm_framebuffer *fb,
1460 int x, int y, int atomic)
1462 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1463 struct drm_device *dev = crtc->dev;
1464 struct radeon_device *rdev = dev->dev_private;
1465 struct radeon_framebuffer *radeon_fb;
1466 struct drm_gem_object *obj;
1467 struct radeon_bo *rbo;
1468 struct drm_framebuffer *target_fb;
1469 uint64_t fb_location;
1470 uint32_t fb_format, fb_pitch_pixels, tiling_flags;
1471 u32 fb_swap = R600_D1GRPH_SWAP_ENDIAN_NONE;
1472 u32 viewport_w, viewport_h;
1474 bool bypass_lut = false;
1475 struct drm_format_name_buf format_name;
1478 if (!atomic && !crtc->primary->fb) {
1479 DRM_DEBUG_KMS("No FB bound\n");
1484 radeon_fb = to_radeon_framebuffer(fb);
1488 radeon_fb = to_radeon_framebuffer(crtc->primary->fb);
1489 target_fb = crtc->primary->fb;
1492 obj = radeon_fb->obj;
1493 rbo = gem_to_radeon_bo(obj);
1494 r = radeon_bo_reserve(rbo, false);
1495 if (unlikely(r != 0))
1498 /* If atomic, assume fb object is pinned & idle & fenced and
1499 * just update base pointers
1502 fb_location = radeon_bo_gpu_offset(rbo);
1504 r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location);
1505 if (unlikely(r != 0)) {
1506 radeon_bo_unreserve(rbo);
1510 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
1511 radeon_bo_unreserve(rbo);
1513 switch (target_fb->pixel_format) {
1516 AVIVO_D1GRPH_CONTROL_DEPTH_8BPP |
1517 AVIVO_D1GRPH_CONTROL_8BPP_INDEXED;
1519 case DRM_FORMAT_XRGB4444:
1520 case DRM_FORMAT_ARGB4444:
1522 AVIVO_D1GRPH_CONTROL_DEPTH_16BPP |
1523 AVIVO_D1GRPH_CONTROL_16BPP_ARGB4444;
1525 fb_swap = R600_D1GRPH_SWAP_ENDIAN_16BIT;
1528 case DRM_FORMAT_XRGB1555:
1530 AVIVO_D1GRPH_CONTROL_DEPTH_16BPP |
1531 AVIVO_D1GRPH_CONTROL_16BPP_ARGB1555;
1533 fb_swap = R600_D1GRPH_SWAP_ENDIAN_16BIT;
1536 case DRM_FORMAT_RGB565:
1538 AVIVO_D1GRPH_CONTROL_DEPTH_16BPP |
1539 AVIVO_D1GRPH_CONTROL_16BPP_RGB565;
1541 fb_swap = R600_D1GRPH_SWAP_ENDIAN_16BIT;
1544 case DRM_FORMAT_XRGB8888:
1545 case DRM_FORMAT_ARGB8888:
1547 AVIVO_D1GRPH_CONTROL_DEPTH_32BPP |
1548 AVIVO_D1GRPH_CONTROL_32BPP_ARGB8888;
1550 fb_swap = R600_D1GRPH_SWAP_ENDIAN_32BIT;
1553 case DRM_FORMAT_XRGB2101010:
1554 case DRM_FORMAT_ARGB2101010:
1556 AVIVO_D1GRPH_CONTROL_DEPTH_32BPP |
1557 AVIVO_D1GRPH_CONTROL_32BPP_ARGB2101010;
1559 fb_swap = R600_D1GRPH_SWAP_ENDIAN_32BIT;
1561 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
1565 DRM_ERROR("Unsupported screen format %s\n",
1566 drm_get_format_name(target_fb->pixel_format, &format_name));
1570 if (rdev->family >= CHIP_R600) {
1571 if (tiling_flags & RADEON_TILING_MACRO)
1572 fb_format |= R600_D1GRPH_ARRAY_MODE_2D_TILED_THIN1;
1573 else if (tiling_flags & RADEON_TILING_MICRO)
1574 fb_format |= R600_D1GRPH_ARRAY_MODE_1D_TILED_THIN1;
1576 if (tiling_flags & RADEON_TILING_MACRO)
1577 fb_format |= AVIVO_D1GRPH_MACRO_ADDRESS_MODE;
1579 if (tiling_flags & RADEON_TILING_MICRO)
1580 fb_format |= AVIVO_D1GRPH_TILED;
1583 if (radeon_crtc->crtc_id == 0)
1584 WREG32(AVIVO_D1VGA_CONTROL, 0);
1586 WREG32(AVIVO_D2VGA_CONTROL, 0);
1588 /* Make sure surface address is update at vertical blank rather than
1591 WREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, 0);
1593 if (rdev->family >= CHIP_RV770) {
1594 if (radeon_crtc->crtc_id) {
1595 WREG32(R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
1596 WREG32(R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
1598 WREG32(R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
1599 WREG32(R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
1602 WREG32(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
1604 WREG32(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS +
1605 radeon_crtc->crtc_offset, (u32) fb_location);
1606 WREG32(AVIVO_D1GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format);
1607 if (rdev->family >= CHIP_R600)
1608 WREG32(R600_D1GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap);
1610 /* LUT only has 256 slots for 8 bpc fb. Bypass for > 8 bpc scanout for precision */
1611 WREG32_P(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset,
1612 (bypass_lut ? AVIVO_LUT_10BIT_BYPASS_EN : 0), ~AVIVO_LUT_10BIT_BYPASS_EN);
1615 DRM_DEBUG_KMS("Bypassing hardware LUT due to 10 bit fb scanout.\n");
1617 WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0);
1618 WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0);
1619 WREG32(AVIVO_D1GRPH_X_START + radeon_crtc->crtc_offset, 0);
1620 WREG32(AVIVO_D1GRPH_Y_START + radeon_crtc->crtc_offset, 0);
1621 WREG32(AVIVO_D1GRPH_X_END + radeon_crtc->crtc_offset, target_fb->width);
1622 WREG32(AVIVO_D1GRPH_Y_END + radeon_crtc->crtc_offset, target_fb->height);
1624 fb_pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8);
1625 WREG32(AVIVO_D1GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels);
1626 WREG32(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 1);
1628 WREG32(AVIVO_D1MODE_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,
1632 WREG32(AVIVO_D1MODE_VIEWPORT_START + radeon_crtc->crtc_offset,
1634 viewport_w = crtc->mode.hdisplay;
1635 viewport_h = (crtc->mode.vdisplay + 1) & ~1;
1636 WREG32(AVIVO_D1MODE_VIEWPORT_SIZE + radeon_crtc->crtc_offset,
1637 (viewport_w << 16) | viewport_h);
1639 /* set pageflip to happen only at start of vblank interval (front porch) */
1640 WREG32(AVIVO_D1MODE_MASTER_UPDATE_MODE + radeon_crtc->crtc_offset, 3);
1642 if (!atomic && fb && fb != crtc->primary->fb) {
1643 radeon_fb = to_radeon_framebuffer(fb);
1644 rbo = gem_to_radeon_bo(radeon_fb->obj);
1645 r = radeon_bo_reserve(rbo, false);
1646 if (unlikely(r != 0))
1648 radeon_bo_unpin(rbo);
1649 radeon_bo_unreserve(rbo);
1652 /* Bytes per pixel may have changed */
1653 radeon_bandwidth_update(rdev);
1658 int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y,
1659 struct drm_framebuffer *old_fb)
1661 struct drm_device *dev = crtc->dev;
1662 struct radeon_device *rdev = dev->dev_private;
1664 if (ASIC_IS_DCE4(rdev))
1665 return dce4_crtc_do_set_base(crtc, old_fb, x, y, 0);
1666 else if (ASIC_IS_AVIVO(rdev))
1667 return avivo_crtc_do_set_base(crtc, old_fb, x, y, 0);
1669 return radeon_crtc_do_set_base(crtc, old_fb, x, y, 0);
1672 int atombios_crtc_set_base_atomic(struct drm_crtc *crtc,
1673 struct drm_framebuffer *fb,
1674 int x, int y, enum mode_set_atomic state)
1676 struct drm_device *dev = crtc->dev;
1677 struct radeon_device *rdev = dev->dev_private;
1679 if (ASIC_IS_DCE4(rdev))
1680 return dce4_crtc_do_set_base(crtc, fb, x, y, 1);
1681 else if (ASIC_IS_AVIVO(rdev))
1682 return avivo_crtc_do_set_base(crtc, fb, x, y, 1);
1684 return radeon_crtc_do_set_base(crtc, fb, x, y, 1);
1687 /* properly set additional regs when using atombios */
1688 static void radeon_legacy_atom_fixup(struct drm_crtc *crtc)
1690 struct drm_device *dev = crtc->dev;
1691 struct radeon_device *rdev = dev->dev_private;
1692 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1693 u32 disp_merge_cntl;
1695 switch (radeon_crtc->crtc_id) {
1697 disp_merge_cntl = RREG32(RADEON_DISP_MERGE_CNTL);
1698 disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN;
1699 WREG32(RADEON_DISP_MERGE_CNTL, disp_merge_cntl);
1702 disp_merge_cntl = RREG32(RADEON_DISP2_MERGE_CNTL);
1703 disp_merge_cntl &= ~RADEON_DISP2_RGB_OFFSET_EN;
1704 WREG32(RADEON_DISP2_MERGE_CNTL, disp_merge_cntl);
1705 WREG32(RADEON_FP_H2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_H_SYNC_STRT_WID));
1706 WREG32(RADEON_FP_V2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_V_SYNC_STRT_WID));
1712 * radeon_get_pll_use_mask - look up a mask of which pplls are in use
1716 * Returns the mask of which PPLLs (Pixel PLLs) are in use.
1718 static u32 radeon_get_pll_use_mask(struct drm_crtc *crtc)
1720 struct drm_device *dev = crtc->dev;
1721 struct drm_crtc *test_crtc;
1722 struct radeon_crtc *test_radeon_crtc;
1725 list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) {
1726 if (crtc == test_crtc)
1729 test_radeon_crtc = to_radeon_crtc(test_crtc);
1730 if (test_radeon_crtc->pll_id != ATOM_PPLL_INVALID)
1731 pll_in_use |= (1 << test_radeon_crtc->pll_id);
1737 * radeon_get_shared_dp_ppll - return the PPLL used by another crtc for DP
1741 * Returns the PPLL (Pixel PLL) used by another crtc/encoder which is
1742 * also in DP mode. For DP, a single PPLL can be used for all DP
1745 static int radeon_get_shared_dp_ppll(struct drm_crtc *crtc)
1747 struct drm_device *dev = crtc->dev;
1748 struct radeon_device *rdev = dev->dev_private;
1749 struct drm_crtc *test_crtc;
1750 struct radeon_crtc *test_radeon_crtc;
1752 list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) {
1753 if (crtc == test_crtc)
1755 test_radeon_crtc = to_radeon_crtc(test_crtc);
1756 if (test_radeon_crtc->encoder &&
1757 ENCODER_MODE_IS_DP(atombios_get_encoder_mode(test_radeon_crtc->encoder))) {
1758 /* PPLL2 is exclusive to UNIPHYA on DCE61 */
1759 if (ASIC_IS_DCE61(rdev) && !ASIC_IS_DCE8(rdev) &&
1760 test_radeon_crtc->pll_id == ATOM_PPLL2)
1762 /* for DP use the same PLL for all */
1763 if (test_radeon_crtc->pll_id != ATOM_PPLL_INVALID)
1764 return test_radeon_crtc->pll_id;
1767 return ATOM_PPLL_INVALID;
1771 * radeon_get_shared_nondp_ppll - return the PPLL used by another non-DP crtc
1774 * @encoder: drm encoder
1776 * Returns the PPLL (Pixel PLL) used by another non-DP crtc/encoder which can
1777 * be shared (i.e., same clock).
1779 static int radeon_get_shared_nondp_ppll(struct drm_crtc *crtc)
1781 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1782 struct drm_device *dev = crtc->dev;
1783 struct radeon_device *rdev = dev->dev_private;
1784 struct drm_crtc *test_crtc;
1785 struct radeon_crtc *test_radeon_crtc;
1786 u32 adjusted_clock, test_adjusted_clock;
1788 adjusted_clock = radeon_crtc->adjusted_clock;
1790 if (adjusted_clock == 0)
1791 return ATOM_PPLL_INVALID;
1793 list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) {
1794 if (crtc == test_crtc)
1796 test_radeon_crtc = to_radeon_crtc(test_crtc);
1797 if (test_radeon_crtc->encoder &&
1798 !ENCODER_MODE_IS_DP(atombios_get_encoder_mode(test_radeon_crtc->encoder))) {
1799 /* PPLL2 is exclusive to UNIPHYA on DCE61 */
1800 if (ASIC_IS_DCE61(rdev) && !ASIC_IS_DCE8(rdev) &&
1801 test_radeon_crtc->pll_id == ATOM_PPLL2)
1803 /* check if we are already driving this connector with another crtc */
1804 if (test_radeon_crtc->connector == radeon_crtc->connector) {
1805 /* if we are, return that pll */
1806 if (test_radeon_crtc->pll_id != ATOM_PPLL_INVALID)
1807 return test_radeon_crtc->pll_id;
1809 /* for non-DP check the clock */
1810 test_adjusted_clock = test_radeon_crtc->adjusted_clock;
1811 if ((crtc->mode.clock == test_crtc->mode.clock) &&
1812 (adjusted_clock == test_adjusted_clock) &&
1813 (radeon_crtc->ss_enabled == test_radeon_crtc->ss_enabled) &&
1814 (test_radeon_crtc->pll_id != ATOM_PPLL_INVALID))
1815 return test_radeon_crtc->pll_id;
1818 return ATOM_PPLL_INVALID;
1822 * radeon_atom_pick_pll - Allocate a PPLL for use by the crtc.
1826 * Returns the PPLL (Pixel PLL) to be used by the crtc. For DP monitors
1827 * a single PPLL can be used for all DP crtcs/encoders. For non-DP
1828 * monitors a dedicated PPLL must be used. If a particular board has
1829 * an external DP PLL, return ATOM_PPLL_INVALID to skip PLL programming
1830 * as there is no need to program the PLL itself. If we are not able to
1831 * allocate a PLL, return ATOM_PPLL_INVALID to skip PLL programming to
1832 * avoid messing up an existing monitor.
1834 * Asic specific PLL information
1838 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP)
1840 * - PPLL0, PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
1843 * - PPLL2 is only available to UNIPHYA (both DP and non-DP)
1844 * - PPLL0, PPLL1 are available for UNIPHYB/C/D/E/F (both DP and non-DP)
1847 * - PPLL0 is available to all UNIPHY (DP only)
1848 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
1851 * - DCPLL is available to all UNIPHY (DP only)
1852 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
1855 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
1858 static int radeon_atom_pick_pll(struct drm_crtc *crtc)
1860 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1861 struct drm_device *dev = crtc->dev;
1862 struct radeon_device *rdev = dev->dev_private;
1863 struct radeon_encoder *radeon_encoder =
1864 to_radeon_encoder(radeon_crtc->encoder);
1868 if (ASIC_IS_DCE8(rdev)) {
1869 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) {
1870 if (rdev->clock.dp_extclk)
1871 /* skip PPLL programming if using ext clock */
1872 return ATOM_PPLL_INVALID;
1874 /* use the same PPLL for all DP monitors */
1875 pll = radeon_get_shared_dp_ppll(crtc);
1876 if (pll != ATOM_PPLL_INVALID)
1880 /* use the same PPLL for all monitors with the same clock */
1881 pll = radeon_get_shared_nondp_ppll(crtc);
1882 if (pll != ATOM_PPLL_INVALID)
1885 /* otherwise, pick one of the plls */
1886 if ((rdev->family == CHIP_KABINI) ||
1887 (rdev->family == CHIP_MULLINS)) {
1888 /* KB/ML has PPLL1 and PPLL2 */
1889 pll_in_use = radeon_get_pll_use_mask(crtc);
1890 if (!(pll_in_use & (1 << ATOM_PPLL2)))
1892 if (!(pll_in_use & (1 << ATOM_PPLL1)))
1894 DRM_ERROR("unable to allocate a PPLL\n");
1895 return ATOM_PPLL_INVALID;
1897 /* CI/KV has PPLL0, PPLL1, and PPLL2 */
1898 pll_in_use = radeon_get_pll_use_mask(crtc);
1899 if (!(pll_in_use & (1 << ATOM_PPLL2)))
1901 if (!(pll_in_use & (1 << ATOM_PPLL1)))
1903 if (!(pll_in_use & (1 << ATOM_PPLL0)))
1905 DRM_ERROR("unable to allocate a PPLL\n");
1906 return ATOM_PPLL_INVALID;
1908 } else if (ASIC_IS_DCE61(rdev)) {
1909 struct radeon_encoder_atom_dig *dig =
1910 radeon_encoder->enc_priv;
1912 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY) &&
1913 (dig->linkb == false))
1914 /* UNIPHY A uses PPLL2 */
1916 else if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) {
1917 /* UNIPHY B/C/D/E/F */
1918 if (rdev->clock.dp_extclk)
1919 /* skip PPLL programming if using ext clock */
1920 return ATOM_PPLL_INVALID;
1922 /* use the same PPLL for all DP monitors */
1923 pll = radeon_get_shared_dp_ppll(crtc);
1924 if (pll != ATOM_PPLL_INVALID)
1928 /* use the same PPLL for all monitors with the same clock */
1929 pll = radeon_get_shared_nondp_ppll(crtc);
1930 if (pll != ATOM_PPLL_INVALID)
1933 /* UNIPHY B/C/D/E/F */
1934 pll_in_use = radeon_get_pll_use_mask(crtc);
1935 if (!(pll_in_use & (1 << ATOM_PPLL0)))
1937 if (!(pll_in_use & (1 << ATOM_PPLL1)))
1939 DRM_ERROR("unable to allocate a PPLL\n");
1940 return ATOM_PPLL_INVALID;
1941 } else if (ASIC_IS_DCE41(rdev)) {
1942 /* Don't share PLLs on DCE4.1 chips */
1943 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) {
1944 if (rdev->clock.dp_extclk)
1945 /* skip PPLL programming if using ext clock */
1946 return ATOM_PPLL_INVALID;
1948 pll_in_use = radeon_get_pll_use_mask(crtc);
1949 if (!(pll_in_use & (1 << ATOM_PPLL1)))
1951 if (!(pll_in_use & (1 << ATOM_PPLL2)))
1953 DRM_ERROR("unable to allocate a PPLL\n");
1954 return ATOM_PPLL_INVALID;
1955 } else if (ASIC_IS_DCE4(rdev)) {
1956 /* in DP mode, the DP ref clock can come from PPLL, DCPLL, or ext clock,
1957 * depending on the asic:
1958 * DCE4: PPLL or ext clock
1959 * DCE5: PPLL, DCPLL, or ext clock
1960 * DCE6: PPLL, PPLL0, or ext clock
1962 * Setting ATOM_PPLL_INVALID will cause SetPixelClock to skip
1963 * PPLL/DCPLL programming and only program the DP DTO for the
1964 * crtc virtual pixel clock.
1966 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) {
1967 if (rdev->clock.dp_extclk)
1968 /* skip PPLL programming if using ext clock */
1969 return ATOM_PPLL_INVALID;
1970 else if (ASIC_IS_DCE6(rdev))
1971 /* use PPLL0 for all DP */
1973 else if (ASIC_IS_DCE5(rdev))
1974 /* use DCPLL for all DP */
1977 /* use the same PPLL for all DP monitors */
1978 pll = radeon_get_shared_dp_ppll(crtc);
1979 if (pll != ATOM_PPLL_INVALID)
1983 /* use the same PPLL for all monitors with the same clock */
1984 pll = radeon_get_shared_nondp_ppll(crtc);
1985 if (pll != ATOM_PPLL_INVALID)
1988 /* all other cases */
1989 pll_in_use = radeon_get_pll_use_mask(crtc);
1990 if (!(pll_in_use & (1 << ATOM_PPLL1)))
1992 if (!(pll_in_use & (1 << ATOM_PPLL2)))
1994 DRM_ERROR("unable to allocate a PPLL\n");
1995 return ATOM_PPLL_INVALID;
1997 /* on pre-R5xx asics, the crtc to pll mapping is hardcoded */
1998 /* some atombios (observed in some DCE2/DCE3) code have a bug,
1999 * the matching btw pll and crtc is done through
2000 * PCLK_CRTC[1|2]_CNTL (0x480/0x484) but atombios code use the
2001 * pll (1 or 2) to select which register to write. ie if using
2002 * pll1 it will use PCLK_CRTC1_CNTL (0x480) and if using pll2
2003 * it will use PCLK_CRTC2_CNTL (0x484), it then use crtc id to
2004 * choose which value to write. Which is reverse order from
2005 * register logic. So only case that works is when pllid is
2006 * same as crtcid or when both pll and crtc are enabled and
2007 * both use same clock.
2009 * So just return crtc id as if crtc and pll were hard linked
2010 * together even if they aren't
2012 return radeon_crtc->crtc_id;
2016 void radeon_atom_disp_eng_pll_init(struct radeon_device *rdev)
2018 /* always set DCPLL */
2019 if (ASIC_IS_DCE6(rdev))
2020 atombios_crtc_set_disp_eng_pll(rdev, rdev->clock.default_dispclk);
2021 else if (ASIC_IS_DCE4(rdev)) {
2022 struct radeon_atom_ss ss;
2023 bool ss_enabled = radeon_atombios_get_asic_ss_info(rdev, &ss,
2024 ASIC_INTERNAL_SS_ON_DCPLL,
2025 rdev->clock.default_dispclk);
2027 atombios_crtc_program_ss(rdev, ATOM_DISABLE, ATOM_DCPLL, -1, &ss);
2028 /* XXX: DCE5, make sure voltage, dispclk is high enough */
2029 atombios_crtc_set_disp_eng_pll(rdev, rdev->clock.default_dispclk);
2031 atombios_crtc_program_ss(rdev, ATOM_ENABLE, ATOM_DCPLL, -1, &ss);
2036 int atombios_crtc_mode_set(struct drm_crtc *crtc,
2037 struct drm_display_mode *mode,
2038 struct drm_display_mode *adjusted_mode,
2039 int x, int y, struct drm_framebuffer *old_fb)
2041 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
2042 struct drm_device *dev = crtc->dev;
2043 struct radeon_device *rdev = dev->dev_private;
2044 struct radeon_encoder *radeon_encoder =
2045 to_radeon_encoder(radeon_crtc->encoder);
2046 bool is_tvcv = false;
2048 if (radeon_encoder->active_device &
2049 (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
2052 if (!radeon_crtc->adjusted_clock)
2055 atombios_crtc_set_pll(crtc, adjusted_mode);
2057 if (ASIC_IS_DCE4(rdev))
2058 atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
2059 else if (ASIC_IS_AVIVO(rdev)) {
2061 atombios_crtc_set_timing(crtc, adjusted_mode);
2063 atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
2065 atombios_crtc_set_timing(crtc, adjusted_mode);
2066 if (radeon_crtc->crtc_id == 0)
2067 atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
2068 radeon_legacy_atom_fixup(crtc);
2070 atombios_crtc_set_base(crtc, x, y, old_fb);
2071 atombios_overscan_setup(crtc, mode, adjusted_mode);
2072 atombios_scaler_setup(crtc);
2073 radeon_cursor_reset(crtc);
2074 /* update the hw version fpr dpm */
2075 radeon_crtc->hw_mode = *adjusted_mode;
2080 static bool atombios_crtc_mode_fixup(struct drm_crtc *crtc,
2081 const struct drm_display_mode *mode,
2082 struct drm_display_mode *adjusted_mode)
2084 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
2085 struct drm_device *dev = crtc->dev;
2086 struct drm_encoder *encoder;
2088 /* assign the encoder to the radeon crtc to avoid repeated lookups later */
2089 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2090 if (encoder->crtc == crtc) {
2091 radeon_crtc->encoder = encoder;
2092 radeon_crtc->connector = radeon_get_connector_for_encoder(encoder);
2096 if ((radeon_crtc->encoder == NULL) || (radeon_crtc->connector == NULL)) {
2097 radeon_crtc->encoder = NULL;
2098 radeon_crtc->connector = NULL;
2101 if (radeon_crtc->encoder) {
2102 struct radeon_encoder *radeon_encoder =
2103 to_radeon_encoder(radeon_crtc->encoder);
2105 radeon_crtc->output_csc = radeon_encoder->output_csc;
2107 if (!radeon_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
2109 if (!atombios_crtc_prepare_pll(crtc, adjusted_mode))
2112 radeon_crtc->pll_id = radeon_atom_pick_pll(crtc);
2113 /* if we can't get a PPLL for a non-DP encoder, fail */
2114 if ((radeon_crtc->pll_id == ATOM_PPLL_INVALID) &&
2115 !ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder)))
2121 static void atombios_crtc_prepare(struct drm_crtc *crtc)
2123 struct drm_device *dev = crtc->dev;
2124 struct radeon_device *rdev = dev->dev_private;
2126 /* disable crtc pair power gating before programming */
2127 if (ASIC_IS_DCE6(rdev))
2128 atombios_powergate_crtc(crtc, ATOM_DISABLE);
2130 atombios_lock_crtc(crtc, ATOM_ENABLE);
2131 atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
2134 static void atombios_crtc_commit(struct drm_crtc *crtc)
2136 atombios_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
2137 atombios_lock_crtc(crtc, ATOM_DISABLE);
2140 static void atombios_crtc_disable(struct drm_crtc *crtc)
2142 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
2143 struct drm_device *dev = crtc->dev;
2144 struct radeon_device *rdev = dev->dev_private;
2145 struct radeon_atom_ss ss;
2148 atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
2149 if (crtc->primary->fb) {
2151 struct radeon_framebuffer *radeon_fb;
2152 struct radeon_bo *rbo;
2154 radeon_fb = to_radeon_framebuffer(crtc->primary->fb);
2155 rbo = gem_to_radeon_bo(radeon_fb->obj);
2156 r = radeon_bo_reserve(rbo, false);
2158 DRM_ERROR("failed to reserve rbo before unpin\n");
2160 radeon_bo_unpin(rbo);
2161 radeon_bo_unreserve(rbo);
2164 /* disable the GRPH */
2165 if (ASIC_IS_DCE4(rdev))
2166 WREG32(EVERGREEN_GRPH_ENABLE + radeon_crtc->crtc_offset, 0);
2167 else if (ASIC_IS_AVIVO(rdev))
2168 WREG32(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 0);
2170 if (ASIC_IS_DCE6(rdev))
2171 atombios_powergate_crtc(crtc, ATOM_ENABLE);
2173 for (i = 0; i < rdev->num_crtc; i++) {
2174 if (rdev->mode_info.crtcs[i] &&
2175 rdev->mode_info.crtcs[i]->enabled &&
2176 i != radeon_crtc->crtc_id &&
2177 radeon_crtc->pll_id == rdev->mode_info.crtcs[i]->pll_id) {
2178 /* one other crtc is using this pll don't turn
2185 switch (radeon_crtc->pll_id) {
2188 /* disable the ppll */
2189 atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id,
2190 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
2193 /* disable the ppll */
2194 if ((rdev->family == CHIP_ARUBA) ||
2195 (rdev->family == CHIP_KAVERI) ||
2196 (rdev->family == CHIP_BONAIRE) ||
2197 (rdev->family == CHIP_HAWAII))
2198 atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id,
2199 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
2205 radeon_crtc->pll_id = ATOM_PPLL_INVALID;
2206 radeon_crtc->adjusted_clock = 0;
2207 radeon_crtc->encoder = NULL;
2208 radeon_crtc->connector = NULL;
2211 static const struct drm_crtc_helper_funcs atombios_helper_funcs = {
2212 .dpms = atombios_crtc_dpms,
2213 .mode_fixup = atombios_crtc_mode_fixup,
2214 .mode_set = atombios_crtc_mode_set,
2215 .mode_set_base = atombios_crtc_set_base,
2216 .mode_set_base_atomic = atombios_crtc_set_base_atomic,
2217 .prepare = atombios_crtc_prepare,
2218 .commit = atombios_crtc_commit,
2219 .load_lut = radeon_crtc_load_lut,
2220 .disable = atombios_crtc_disable,
2223 void radeon_atombios_init_crtc(struct drm_device *dev,
2224 struct radeon_crtc *radeon_crtc)
2226 struct radeon_device *rdev = dev->dev_private;
2228 if (ASIC_IS_DCE4(rdev)) {
2229 switch (radeon_crtc->crtc_id) {
2232 radeon_crtc->crtc_offset = EVERGREEN_CRTC0_REGISTER_OFFSET;
2235 radeon_crtc->crtc_offset = EVERGREEN_CRTC1_REGISTER_OFFSET;
2238 radeon_crtc->crtc_offset = EVERGREEN_CRTC2_REGISTER_OFFSET;
2241 radeon_crtc->crtc_offset = EVERGREEN_CRTC3_REGISTER_OFFSET;
2244 radeon_crtc->crtc_offset = EVERGREEN_CRTC4_REGISTER_OFFSET;
2247 radeon_crtc->crtc_offset = EVERGREEN_CRTC5_REGISTER_OFFSET;
2251 if (radeon_crtc->crtc_id == 1)
2252 radeon_crtc->crtc_offset =
2253 AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL;
2255 radeon_crtc->crtc_offset = 0;
2257 radeon_crtc->pll_id = ATOM_PPLL_INVALID;
2258 radeon_crtc->adjusted_clock = 0;
2259 radeon_crtc->encoder = NULL;
2260 radeon_crtc->connector = NULL;
2261 drm_crtc_helper_add(&radeon_crtc->base, &atombios_helper_funcs);