2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
23 * Authors: Dave Airlie
28 #include <drm/radeon_drm.h>
32 #include "atom-bits.h"
33 #include <drm/drm_dp_helper.h>
35 /* move these to drm_dp_helper.c/h */
36 #define DP_LINK_CONFIGURATION_SIZE 9
37 #define DP_DPCD_SIZE DP_RECEIVER_CAP_SIZE
39 static char *voltage_names[] = {
40 "0.4V", "0.6V", "0.8V", "1.2V"
42 static char *pre_emph_names[] = {
43 "0dB", "3.5dB", "6dB", "9.5dB"
46 /***** radeon AUX functions *****/
48 /* Atom needs data in little endian format
49 * so swap as appropriate when copying data to
50 * or from atom. Note that atom operates on
53 void radeon_atom_copy_swap(u8 *dst, u8 *src, u8 num_bytes, bool to_le)
56 u8 src_tmp[20], dst_tmp[20]; /* used for byteswapping */
60 memcpy(src_tmp, src, num_bytes);
61 src32 = (u32 *)src_tmp;
62 dst32 = (u32 *)dst_tmp;
64 for (i = 0; i < ((num_bytes + 3) / 4); i++)
65 dst32[i] = cpu_to_le32(src32[i]);
66 memcpy(dst, dst_tmp, num_bytes);
68 u8 dws = num_bytes & ~3;
69 for (i = 0; i < ((num_bytes + 3) / 4); i++)
70 dst32[i] = le32_to_cpu(src32[i]);
71 memcpy(dst, dst_tmp, dws);
73 for (i = 0; i < (num_bytes % 4); i++)
74 dst[dws+i] = dst_tmp[dws+i];
78 memcpy(dst, src, num_bytes);
82 union aux_channel_transaction {
83 PROCESS_AUX_CHANNEL_TRANSACTION_PS_ALLOCATION v1;
84 PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS_V2 v2;
87 static int radeon_process_aux_ch(struct radeon_i2c_chan *chan,
88 u8 *send, int send_bytes,
89 u8 *recv, int recv_size,
92 struct drm_device *dev = chan->dev;
93 struct radeon_device *rdev = dev->dev_private;
94 union aux_channel_transaction args;
95 int index = GetIndexIntoMasterTable(COMMAND, ProcessAuxChannelTransaction);
100 memset(&args, 0, sizeof(args));
102 mutex_lock(&chan->mutex);
103 mutex_lock(&rdev->mode_info.atom_context->scratch_mutex);
105 base = (unsigned char *)(rdev->mode_info.atom_context->scratch + 1);
107 radeon_atom_copy_swap(base, send, send_bytes, true);
109 args.v1.lpAuxRequest = cpu_to_le16((u16)(0 + 4));
110 args.v1.lpDataOut = cpu_to_le16((u16)(16 + 4));
111 args.v1.ucDataOutLen = 0;
112 args.v1.ucChannelID = chan->rec.i2c_id;
113 args.v1.ucDelay = delay / 10;
114 if (ASIC_IS_DCE4(rdev))
115 args.v2.ucHPD_ID = chan->rec.hpd;
117 atom_execute_table_scratch_unlocked(rdev->mode_info.atom_context, index, (uint32_t *)&args);
119 *ack = args.v1.ucReplyStatus;
122 if (args.v1.ucReplyStatus == 1) {
123 DRM_DEBUG_KMS("dp_aux_ch timeout\n");
129 if (args.v1.ucReplyStatus == 2) {
130 DRM_DEBUG_KMS("dp_aux_ch flags not zero\n");
136 if (args.v1.ucReplyStatus == 3) {
137 DRM_DEBUG_KMS("dp_aux_ch error\n");
142 recv_bytes = args.v1.ucDataOutLen;
143 if (recv_bytes > recv_size)
144 recv_bytes = recv_size;
146 if (recv && recv_size)
147 radeon_atom_copy_swap(recv, base + 16, recv_bytes, false);
151 mutex_unlock(&rdev->mode_info.atom_context->scratch_mutex);
152 mutex_unlock(&chan->mutex);
157 #define BARE_ADDRESS_SIZE 3
158 #define HEADER_SIZE (BARE_ADDRESS_SIZE + 1)
161 radeon_dp_aux_transfer_atom(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
163 struct radeon_i2c_chan *chan =
164 container_of(aux, struct radeon_i2c_chan, aux);
170 if (WARN_ON(msg->size > 16))
173 tx_buf[0] = msg->address & 0xff;
174 tx_buf[1] = (msg->address >> 8) & 0xff;
175 tx_buf[2] = (msg->request << 4) |
176 ((msg->address >> 16) & 0xf);
177 tx_buf[3] = msg->size ? (msg->size - 1) : 0;
179 switch (msg->request & ~DP_AUX_I2C_MOT) {
180 case DP_AUX_NATIVE_WRITE:
181 case DP_AUX_I2C_WRITE:
182 /* The atom implementation only supports writes with a max payload of
183 * 12 bytes since it uses 4 bits for the total count (header + payload)
184 * in the parameter space. The atom interface supports 16 byte
185 * payloads for reads. The hw itself supports up to 16 bytes of payload.
187 if (WARN_ON_ONCE(msg->size > 12))
189 /* tx_size needs to be 4 even for bare address packets since the atom
190 * table needs the info in tx_buf[3].
192 tx_size = HEADER_SIZE + msg->size;
194 tx_buf[3] |= BARE_ADDRESS_SIZE << 4;
196 tx_buf[3] |= tx_size << 4;
197 memcpy(tx_buf + HEADER_SIZE, msg->buffer, msg->size);
198 ret = radeon_process_aux_ch(chan,
199 tx_buf, tx_size, NULL, 0, delay, &ack);
201 /* Return payload size. */
204 case DP_AUX_NATIVE_READ:
205 case DP_AUX_I2C_READ:
206 /* tx_size needs to be 4 even for bare address packets since the atom
207 * table needs the info in tx_buf[3].
209 tx_size = HEADER_SIZE;
211 tx_buf[3] |= BARE_ADDRESS_SIZE << 4;
213 tx_buf[3] |= tx_size << 4;
214 ret = radeon_process_aux_ch(chan,
215 tx_buf, tx_size, msg->buffer, msg->size, delay, &ack);
223 msg->reply = ack >> 4;
228 void radeon_dp_aux_init(struct radeon_connector *radeon_connector)
230 struct drm_device *dev = radeon_connector->base.dev;
231 struct radeon_device *rdev = dev->dev_private;
234 radeon_connector->ddc_bus->rec.hpd = radeon_connector->hpd.hpd;
235 radeon_connector->ddc_bus->aux.dev = radeon_connector->base.kdev;
236 if (ASIC_IS_DCE5(rdev)) {
238 radeon_connector->ddc_bus->aux.transfer = radeon_dp_aux_transfer_native;
240 radeon_connector->ddc_bus->aux.transfer = radeon_dp_aux_transfer_atom;
242 radeon_connector->ddc_bus->aux.transfer = radeon_dp_aux_transfer_atom;
245 ret = drm_dp_aux_register(&radeon_connector->ddc_bus->aux);
247 radeon_connector->ddc_bus->has_aux = true;
249 WARN(ret, "drm_dp_aux_register() failed with error %d\n", ret);
252 /***** general DP utility functions *****/
254 #define DP_VOLTAGE_MAX DP_TRAIN_VOLTAGE_SWING_LEVEL_3
255 #define DP_PRE_EMPHASIS_MAX DP_TRAIN_PRE_EMPH_LEVEL_3
257 static void dp_get_adjust_train(const u8 link_status[DP_LINK_STATUS_SIZE],
265 for (lane = 0; lane < lane_count; lane++) {
266 u8 this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
267 u8 this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
269 DRM_DEBUG_KMS("requested signal parameters: lane %d voltage %s pre_emph %s\n",
271 voltage_names[this_v >> DP_TRAIN_VOLTAGE_SWING_SHIFT],
272 pre_emph_names[this_p >> DP_TRAIN_PRE_EMPHASIS_SHIFT]);
280 if (v >= DP_VOLTAGE_MAX)
281 v |= DP_TRAIN_MAX_SWING_REACHED;
283 if (p >= DP_PRE_EMPHASIS_MAX)
284 p |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
286 DRM_DEBUG_KMS("using signal parameters: voltage %s pre_emph %s\n",
287 voltage_names[(v & DP_TRAIN_VOLTAGE_SWING_MASK) >> DP_TRAIN_VOLTAGE_SWING_SHIFT],
288 pre_emph_names[(p & DP_TRAIN_PRE_EMPHASIS_MASK) >> DP_TRAIN_PRE_EMPHASIS_SHIFT]);
290 for (lane = 0; lane < 4; lane++)
291 train_set[lane] = v | p;
294 /* convert bits per color to bits per pixel */
295 /* get bpc from the EDID */
296 static int convert_bpc_to_bpp(int bpc)
304 /* get the max pix clock supported by the link rate and lane num */
305 static int dp_get_max_dp_pix_clock(int link_rate,
309 return (link_rate * lane_num * 8) / bpp;
312 /***** radeon specific DP functions *****/
314 int radeon_dp_get_max_link_rate(struct drm_connector *connector,
315 const u8 dpcd[DP_DPCD_SIZE])
319 if (radeon_connector_is_dp12_capable(connector))
320 max_link_rate = min(drm_dp_max_link_rate(dpcd), 540000);
322 max_link_rate = min(drm_dp_max_link_rate(dpcd), 270000);
324 return max_link_rate;
327 /* First get the min lane# when low rate is used according to pixel clock
328 * (prefer low rate), second check max lane# supported by DP panel,
329 * if the max lane# < low rate lane# then use max lane# instead.
331 static int radeon_dp_get_dp_lane_number(struct drm_connector *connector,
332 const u8 dpcd[DP_DPCD_SIZE],
335 int bpp = convert_bpc_to_bpp(radeon_get_monitor_bpc(connector));
336 int max_link_rate = radeon_dp_get_max_link_rate(connector, dpcd);
337 int max_lane_num = drm_dp_max_lane_count(dpcd);
339 int max_dp_pix_clock;
341 for (lane_num = 1; lane_num < max_lane_num; lane_num <<= 1) {
342 max_dp_pix_clock = dp_get_max_dp_pix_clock(max_link_rate, lane_num, bpp);
343 if (pix_clock <= max_dp_pix_clock)
350 static int radeon_dp_get_dp_link_clock(struct drm_connector *connector,
351 const u8 dpcd[DP_DPCD_SIZE],
354 int bpp = convert_bpc_to_bpp(radeon_get_monitor_bpc(connector));
355 int lane_num, max_pix_clock;
357 if (radeon_connector_encoder_get_dp_bridge_encoder_id(connector) ==
358 ENCODER_OBJECT_ID_NUTMEG)
361 lane_num = radeon_dp_get_dp_lane_number(connector, dpcd, pix_clock);
362 max_pix_clock = dp_get_max_dp_pix_clock(162000, lane_num, bpp);
363 if (pix_clock <= max_pix_clock)
365 max_pix_clock = dp_get_max_dp_pix_clock(270000, lane_num, bpp);
366 if (pix_clock <= max_pix_clock)
368 if (radeon_connector_is_dp12_capable(connector)) {
369 max_pix_clock = dp_get_max_dp_pix_clock(540000, lane_num, bpp);
370 if (pix_clock <= max_pix_clock)
374 return radeon_dp_get_max_link_rate(connector, dpcd);
377 static u8 radeon_dp_encoder_service(struct radeon_device *rdev,
378 int action, int dp_clock,
379 u8 ucconfig, u8 lane_num)
381 DP_ENCODER_SERVICE_PARAMETERS args;
382 int index = GetIndexIntoMasterTable(COMMAND, DPEncoderService);
384 memset(&args, 0, sizeof(args));
385 args.ucLinkClock = dp_clock / 10;
386 args.ucConfig = ucconfig;
387 args.ucAction = action;
388 args.ucLaneNum = lane_num;
391 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
392 return args.ucStatus;
395 u8 radeon_dp_getsinktype(struct radeon_connector *radeon_connector)
397 struct drm_device *dev = radeon_connector->base.dev;
398 struct radeon_device *rdev = dev->dev_private;
400 return radeon_dp_encoder_service(rdev, ATOM_DP_ACTION_GET_SINK_TYPE, 0,
401 radeon_connector->ddc_bus->rec.i2c_id, 0);
404 static void radeon_dp_probe_oui(struct radeon_connector *radeon_connector)
406 struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
409 if (!(dig_connector->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
412 if (drm_dp_dpcd_read(&radeon_connector->ddc_bus->aux, DP_SINK_OUI, buf, 3) == 3)
413 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
414 buf[0], buf[1], buf[2]);
416 if (drm_dp_dpcd_read(&radeon_connector->ddc_bus->aux, DP_BRANCH_OUI, buf, 3) == 3)
417 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
418 buf[0], buf[1], buf[2]);
421 bool radeon_dp_getdpcd(struct radeon_connector *radeon_connector)
423 struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
424 u8 msg[DP_DPCD_SIZE];
427 for (i = 0; i < 7; i++) {
428 ret = drm_dp_dpcd_read(&radeon_connector->ddc_bus->aux, DP_DPCD_REV, msg,
430 if (ret == DP_DPCD_SIZE) {
431 memcpy(dig_connector->dpcd, msg, DP_DPCD_SIZE);
433 DRM_DEBUG_KMS("DPCD: %*ph\n", (int)sizeof(dig_connector->dpcd),
434 dig_connector->dpcd);
436 radeon_dp_probe_oui(radeon_connector);
441 dig_connector->dpcd[0] = 0;
445 int radeon_dp_get_panel_mode(struct drm_encoder *encoder,
446 struct drm_connector *connector)
448 struct drm_device *dev = encoder->dev;
449 struct radeon_device *rdev = dev->dev_private;
450 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
451 struct radeon_connector_atom_dig *dig_connector;
452 int panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE;
453 u16 dp_bridge = radeon_connector_encoder_get_dp_bridge_encoder_id(connector);
456 if (!ASIC_IS_DCE4(rdev))
459 if (!radeon_connector->con_priv)
462 dig_connector = radeon_connector->con_priv;
464 if (dp_bridge != ENCODER_OBJECT_ID_NONE) {
465 /* DP bridge chips */
466 if (drm_dp_dpcd_readb(&radeon_connector->ddc_bus->aux,
467 DP_EDP_CONFIGURATION_CAP, &tmp) == 1) {
469 panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE;
470 else if ((dp_bridge == ENCODER_OBJECT_ID_NUTMEG) ||
471 (dp_bridge == ENCODER_OBJECT_ID_TRAVIS))
472 panel_mode = DP_PANEL_MODE_INTERNAL_DP1_MODE;
474 panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE;
476 } else if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
478 if (drm_dp_dpcd_readb(&radeon_connector->ddc_bus->aux,
479 DP_EDP_CONFIGURATION_CAP, &tmp) == 1) {
481 panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE;
488 void radeon_dp_set_link_config(struct drm_connector *connector,
489 const struct drm_display_mode *mode)
491 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
492 struct radeon_connector_atom_dig *dig_connector;
494 if (!radeon_connector->con_priv)
496 dig_connector = radeon_connector->con_priv;
498 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
499 (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) {
500 dig_connector->dp_clock =
501 radeon_dp_get_dp_link_clock(connector, dig_connector->dpcd, mode->clock);
502 dig_connector->dp_lane_count =
503 radeon_dp_get_dp_lane_number(connector, dig_connector->dpcd, mode->clock);
507 int radeon_dp_mode_valid_helper(struct drm_connector *connector,
508 struct drm_display_mode *mode)
510 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
511 struct radeon_connector_atom_dig *dig_connector;
514 if ((mode->clock > 340000) &&
515 (!radeon_connector_is_dp12_capable(connector)))
516 return MODE_CLOCK_HIGH;
518 if (!radeon_connector->con_priv)
519 return MODE_CLOCK_HIGH;
520 dig_connector = radeon_connector->con_priv;
523 radeon_dp_get_dp_link_clock(connector, dig_connector->dpcd, mode->clock);
525 if ((dp_clock == 540000) &&
526 (!radeon_connector_is_dp12_capable(connector)))
527 return MODE_CLOCK_HIGH;
532 bool radeon_dp_needs_link_train(struct radeon_connector *radeon_connector)
534 u8 link_status[DP_LINK_STATUS_SIZE];
535 struct radeon_connector_atom_dig *dig = radeon_connector->con_priv;
537 if (drm_dp_dpcd_read_link_status(&radeon_connector->ddc_bus->aux, link_status)
540 if (drm_dp_channel_eq_ok(link_status, dig->dp_lane_count))
545 void radeon_dp_set_rx_power_state(struct drm_connector *connector,
548 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
549 struct radeon_connector_atom_dig *dig_connector;
551 if (!radeon_connector->con_priv)
554 dig_connector = radeon_connector->con_priv;
556 /* power up/down the sink */
557 if (dig_connector->dpcd[0] >= 0x11) {
558 drm_dp_dpcd_writeb(&radeon_connector->ddc_bus->aux,
559 DP_SET_POWER, power_state);
560 usleep_range(1000, 2000);
565 struct radeon_dp_link_train_info {
566 struct radeon_device *rdev;
567 struct drm_encoder *encoder;
568 struct drm_connector *connector;
573 u8 dpcd[DP_RECEIVER_CAP_SIZE];
575 u8 link_status[DP_LINK_STATUS_SIZE];
578 struct drm_dp_aux *aux;
581 static void radeon_dp_update_vs_emph(struct radeon_dp_link_train_info *dp_info)
583 /* set the initial vs/emph on the source */
584 atombios_dig_transmitter_setup(dp_info->encoder,
585 ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH,
586 0, dp_info->train_set[0]); /* sets all lanes at once */
588 /* set the vs/emph on the sink */
589 drm_dp_dpcd_write(dp_info->aux, DP_TRAINING_LANE0_SET,
590 dp_info->train_set, dp_info->dp_lane_count);
593 static void radeon_dp_set_tp(struct radeon_dp_link_train_info *dp_info, int tp)
597 /* set training pattern on the source */
598 if (ASIC_IS_DCE4(dp_info->rdev) || !dp_info->use_dpencoder) {
600 case DP_TRAINING_PATTERN_1:
601 rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN1;
603 case DP_TRAINING_PATTERN_2:
604 rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN2;
606 case DP_TRAINING_PATTERN_3:
607 rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN3;
610 atombios_dig_encoder_setup(dp_info->encoder, rtp, 0);
613 case DP_TRAINING_PATTERN_1:
616 case DP_TRAINING_PATTERN_2:
620 radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_PATTERN_SEL,
621 dp_info->dp_clock, dp_info->enc_id, rtp);
624 /* enable training pattern on the sink */
625 drm_dp_dpcd_writeb(dp_info->aux, DP_TRAINING_PATTERN_SET, tp);
628 static int radeon_dp_link_train_init(struct radeon_dp_link_train_info *dp_info)
630 struct radeon_encoder *radeon_encoder = to_radeon_encoder(dp_info->encoder);
631 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
634 /* power up the sink */
635 radeon_dp_set_rx_power_state(dp_info->connector, DP_SET_POWER_D0);
637 /* possibly enable downspread on the sink */
638 if (dp_info->dpcd[3] & 0x1)
639 drm_dp_dpcd_writeb(dp_info->aux,
640 DP_DOWNSPREAD_CTRL, DP_SPREAD_AMP_0_5);
642 drm_dp_dpcd_writeb(dp_info->aux,
643 DP_DOWNSPREAD_CTRL, 0);
645 if (dig->panel_mode == DP_PANEL_MODE_INTERNAL_DP2_MODE)
646 drm_dp_dpcd_writeb(dp_info->aux, DP_EDP_CONFIGURATION_SET, 1);
648 /* set the lane count on the sink */
649 tmp = dp_info->dp_lane_count;
650 if (drm_dp_enhanced_frame_cap(dp_info->dpcd))
651 tmp |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
652 drm_dp_dpcd_writeb(dp_info->aux, DP_LANE_COUNT_SET, tmp);
654 /* set the link rate on the sink */
655 tmp = drm_dp_link_rate_to_bw_code(dp_info->dp_clock);
656 drm_dp_dpcd_writeb(dp_info->aux, DP_LINK_BW_SET, tmp);
658 /* start training on the source */
659 if (ASIC_IS_DCE4(dp_info->rdev) || !dp_info->use_dpencoder)
660 atombios_dig_encoder_setup(dp_info->encoder,
661 ATOM_ENCODER_CMD_DP_LINK_TRAINING_START, 0);
663 radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_START,
664 dp_info->dp_clock, dp_info->enc_id, 0);
666 /* disable the training pattern on the sink */
667 drm_dp_dpcd_writeb(dp_info->aux,
668 DP_TRAINING_PATTERN_SET,
669 DP_TRAINING_PATTERN_DISABLE);
674 static int radeon_dp_link_train_finish(struct radeon_dp_link_train_info *dp_info)
678 /* disable the training pattern on the sink */
679 drm_dp_dpcd_writeb(dp_info->aux,
680 DP_TRAINING_PATTERN_SET,
681 DP_TRAINING_PATTERN_DISABLE);
683 /* disable the training pattern on the source */
684 if (ASIC_IS_DCE4(dp_info->rdev) || !dp_info->use_dpencoder)
685 atombios_dig_encoder_setup(dp_info->encoder,
686 ATOM_ENCODER_CMD_DP_LINK_TRAINING_COMPLETE, 0);
688 radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_COMPLETE,
689 dp_info->dp_clock, dp_info->enc_id, 0);
694 static int radeon_dp_link_train_cr(struct radeon_dp_link_train_info *dp_info)
700 radeon_dp_set_tp(dp_info, DP_TRAINING_PATTERN_1);
701 memset(dp_info->train_set, 0, 4);
702 radeon_dp_update_vs_emph(dp_info);
706 /* clock recovery loop */
707 clock_recovery = false;
711 drm_dp_link_train_clock_recovery_delay(dp_info->dpcd);
713 if (drm_dp_dpcd_read_link_status(dp_info->aux,
714 dp_info->link_status) <= 0) {
715 DRM_ERROR("displayport link status failed\n");
719 if (drm_dp_clock_recovery_ok(dp_info->link_status, dp_info->dp_lane_count)) {
720 clock_recovery = true;
724 for (i = 0; i < dp_info->dp_lane_count; i++) {
725 if ((dp_info->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
728 if (i == dp_info->dp_lane_count) {
729 DRM_ERROR("clock recovery reached max voltage\n");
733 if ((dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
735 if (dp_info->tries == 5) {
736 DRM_ERROR("clock recovery tried 5 times\n");
742 voltage = dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
744 /* Compute new train_set as requested by sink */
745 dp_get_adjust_train(dp_info->link_status, dp_info->dp_lane_count, dp_info->train_set);
747 radeon_dp_update_vs_emph(dp_info);
749 if (!clock_recovery) {
750 DRM_ERROR("clock recovery failed\n");
753 DRM_DEBUG_KMS("clock recovery at voltage %d pre-emphasis %d\n",
754 dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK,
755 (dp_info->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK) >>
756 DP_TRAIN_PRE_EMPHASIS_SHIFT);
761 static int radeon_dp_link_train_ce(struct radeon_dp_link_train_info *dp_info)
765 if (dp_info->tp3_supported)
766 radeon_dp_set_tp(dp_info, DP_TRAINING_PATTERN_3);
768 radeon_dp_set_tp(dp_info, DP_TRAINING_PATTERN_2);
770 /* channel equalization loop */
774 drm_dp_link_train_channel_eq_delay(dp_info->dpcd);
776 if (drm_dp_dpcd_read_link_status(dp_info->aux,
777 dp_info->link_status) <= 0) {
778 DRM_ERROR("displayport link status failed\n");
782 if (drm_dp_channel_eq_ok(dp_info->link_status, dp_info->dp_lane_count)) {
788 if (dp_info->tries > 5) {
789 DRM_ERROR("channel eq failed: 5 tries\n");
793 /* Compute new train_set as requested by sink */
794 dp_get_adjust_train(dp_info->link_status, dp_info->dp_lane_count, dp_info->train_set);
796 radeon_dp_update_vs_emph(dp_info);
801 DRM_ERROR("channel eq failed\n");
804 DRM_DEBUG_KMS("channel eq at voltage %d pre-emphasis %d\n",
805 dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK,
806 (dp_info->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK)
807 >> DP_TRAIN_PRE_EMPHASIS_SHIFT);
812 void radeon_dp_link_train(struct drm_encoder *encoder,
813 struct drm_connector *connector)
815 struct drm_device *dev = encoder->dev;
816 struct radeon_device *rdev = dev->dev_private;
817 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
818 struct radeon_encoder_atom_dig *dig;
819 struct radeon_connector *radeon_connector;
820 struct radeon_connector_atom_dig *dig_connector;
821 struct radeon_dp_link_train_info dp_info;
825 if (!radeon_encoder->enc_priv)
827 dig = radeon_encoder->enc_priv;
829 radeon_connector = to_radeon_connector(connector);
830 if (!radeon_connector->con_priv)
832 dig_connector = radeon_connector->con_priv;
834 if ((dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_DISPLAYPORT) &&
835 (dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_eDP))
838 /* DPEncoderService newer than 1.1 can't program properly the
839 * training pattern. When facing such version use the
840 * DIGXEncoderControl (X== 1 | 2)
842 dp_info.use_dpencoder = true;
843 index = GetIndexIntoMasterTable(COMMAND, DPEncoderService);
844 if (atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) {
846 dp_info.use_dpencoder = false;
851 if (dig->dig_encoder)
852 dp_info.enc_id |= ATOM_DP_CONFIG_DIG2_ENCODER;
854 dp_info.enc_id |= ATOM_DP_CONFIG_DIG1_ENCODER;
856 dp_info.enc_id |= ATOM_DP_CONFIG_LINK_B;
858 dp_info.enc_id |= ATOM_DP_CONFIG_LINK_A;
860 if (drm_dp_dpcd_readb(&radeon_connector->ddc_bus->aux, DP_MAX_LANE_COUNT, &tmp)
862 if (ASIC_IS_DCE5(rdev) && (tmp & DP_TPS3_SUPPORTED))
863 dp_info.tp3_supported = true;
865 dp_info.tp3_supported = false;
867 dp_info.tp3_supported = false;
870 memcpy(dp_info.dpcd, dig_connector->dpcd, DP_RECEIVER_CAP_SIZE);
872 dp_info.encoder = encoder;
873 dp_info.connector = connector;
874 dp_info.dp_lane_count = dig_connector->dp_lane_count;
875 dp_info.dp_clock = dig_connector->dp_clock;
876 dp_info.aux = &radeon_connector->ddc_bus->aux;
878 if (radeon_dp_link_train_init(&dp_info))
880 if (radeon_dp_link_train_cr(&dp_info))
882 if (radeon_dp_link_train_ce(&dp_info))
885 if (radeon_dp_link_train_finish(&dp_info))