2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
23 * Authors: Dave Airlie
28 #include <drm/radeon_drm.h>
32 #include "atom-bits.h"
33 #include <drm/drm_dp_helper.h>
35 /* move these to drm_dp_helper.c/h */
36 #define DP_LINK_CONFIGURATION_SIZE 9
37 #define DP_DPCD_SIZE DP_RECEIVER_CAP_SIZE
39 static char *voltage_names[] = {
40 "0.4V", "0.6V", "0.8V", "1.2V"
42 static char *pre_emph_names[] = {
43 "0dB", "3.5dB", "6dB", "9.5dB"
46 /***** radeon AUX functions *****/
48 /* Atom needs data in little endian format
49 * so swap as appropriate when copying data to
50 * or from atom. Note that atom operates on
53 void radeon_atom_copy_swap(u8 *dst, u8 *src, u8 num_bytes, bool to_le)
56 u8 src_tmp[20], dst_tmp[20]; /* used for byteswapping */
60 memcpy(src_tmp, src, num_bytes);
61 src32 = (u32 *)src_tmp;
62 dst32 = (u32 *)dst_tmp;
64 for (i = 0; i < ((num_bytes + 3) / 4); i++)
65 dst32[i] = cpu_to_le32(src32[i]);
66 memcpy(dst, dst_tmp, num_bytes);
68 u8 dws = num_bytes & ~3;
69 for (i = 0; i < ((num_bytes + 3) / 4); i++)
70 dst32[i] = le32_to_cpu(src32[i]);
71 memcpy(dst, dst_tmp, dws);
73 for (i = 0; i < (num_bytes % 4); i++)
74 dst[dws+i] = dst_tmp[dws+i];
78 memcpy(dst, src, num_bytes);
82 union aux_channel_transaction {
83 PROCESS_AUX_CHANNEL_TRANSACTION_PS_ALLOCATION v1;
84 PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS_V2 v2;
87 static int radeon_process_aux_ch(struct radeon_i2c_chan *chan,
88 u8 *send, int send_bytes,
89 u8 *recv, int recv_size,
92 struct drm_device *dev = chan->dev;
93 struct radeon_device *rdev = dev->dev_private;
94 union aux_channel_transaction args;
95 int index = GetIndexIntoMasterTable(COMMAND, ProcessAuxChannelTransaction);
99 memset(&args, 0, sizeof(args));
101 base = (unsigned char *)(rdev->mode_info.atom_context->scratch + 1);
103 radeon_atom_copy_swap(base, send, send_bytes, true);
105 args.v1.lpAuxRequest = cpu_to_le16((u16)(0 + 4));
106 args.v1.lpDataOut = cpu_to_le16((u16)(16 + 4));
107 args.v1.ucDataOutLen = 0;
108 args.v1.ucChannelID = chan->rec.i2c_id;
109 args.v1.ucDelay = delay / 10;
110 if (ASIC_IS_DCE4(rdev))
111 args.v2.ucHPD_ID = chan->rec.hpd;
113 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
115 *ack = args.v1.ucReplyStatus;
118 if (args.v1.ucReplyStatus == 1) {
119 DRM_DEBUG_KMS("dp_aux_ch timeout\n");
124 if (args.v1.ucReplyStatus == 2) {
125 DRM_DEBUG_KMS("dp_aux_ch flags not zero\n");
130 if (args.v1.ucReplyStatus == 3) {
131 DRM_DEBUG_KMS("dp_aux_ch error\n");
135 recv_bytes = args.v1.ucDataOutLen;
136 if (recv_bytes > recv_size)
137 recv_bytes = recv_size;
139 if (recv && recv_size)
140 radeon_atom_copy_swap(recv, base + 16, recv_bytes, false);
145 #define BARE_ADDRESS_SIZE 3
146 #define HEADER_SIZE (BARE_ADDRESS_SIZE + 1)
149 radeon_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
151 struct radeon_i2c_chan *chan =
152 container_of(aux, struct radeon_i2c_chan, aux);
158 if (WARN_ON(msg->size > 16))
161 tx_buf[0] = msg->address & 0xff;
162 tx_buf[1] = msg->address >> 8;
163 tx_buf[2] = msg->request << 4;
164 tx_buf[3] = msg->size ? (msg->size - 1) : 0;
166 switch (msg->request & ~DP_AUX_I2C_MOT) {
167 case DP_AUX_NATIVE_WRITE:
168 case DP_AUX_I2C_WRITE:
169 /* tx_size needs to be 4 even for bare address packets since the atom
170 * table needs the info in tx_buf[3].
172 tx_size = HEADER_SIZE + msg->size;
174 tx_buf[3] |= BARE_ADDRESS_SIZE << 4;
176 tx_buf[3] |= tx_size << 4;
177 memcpy(tx_buf + HEADER_SIZE, msg->buffer, msg->size);
178 ret = radeon_process_aux_ch(chan,
179 tx_buf, tx_size, NULL, 0, delay, &ack);
181 /* Return payload size. */
184 case DP_AUX_NATIVE_READ:
185 case DP_AUX_I2C_READ:
186 /* tx_size needs to be 4 even for bare address packets since the atom
187 * table needs the info in tx_buf[3].
189 tx_size = HEADER_SIZE;
191 tx_buf[3] |= BARE_ADDRESS_SIZE << 4;
193 tx_buf[3] |= tx_size << 4;
194 ret = radeon_process_aux_ch(chan,
195 tx_buf, tx_size, msg->buffer, msg->size, delay, &ack);
203 msg->reply = ack >> 4;
208 void radeon_dp_aux_init(struct radeon_connector *radeon_connector)
212 radeon_connector->ddc_bus->rec.hpd = radeon_connector->hpd.hpd;
213 radeon_connector->ddc_bus->aux.dev = radeon_connector->base.kdev;
214 radeon_connector->ddc_bus->aux.transfer = radeon_dp_aux_transfer;
215 ret = drm_dp_aux_register_i2c_bus(&radeon_connector->ddc_bus->aux);
217 radeon_connector->ddc_bus->has_aux = true;
219 WARN(ret, "drm_dp_aux_register_i2c_bus() failed with error %d\n", ret);
222 /***** general DP utility functions *****/
224 #define DP_VOLTAGE_MAX DP_TRAIN_VOLTAGE_SWING_1200
225 #define DP_PRE_EMPHASIS_MAX DP_TRAIN_PRE_EMPHASIS_9_5
227 static void dp_get_adjust_train(u8 link_status[DP_LINK_STATUS_SIZE],
235 for (lane = 0; lane < lane_count; lane++) {
236 u8 this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
237 u8 this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
239 DRM_DEBUG_KMS("requested signal parameters: lane %d voltage %s pre_emph %s\n",
241 voltage_names[this_v >> DP_TRAIN_VOLTAGE_SWING_SHIFT],
242 pre_emph_names[this_p >> DP_TRAIN_PRE_EMPHASIS_SHIFT]);
250 if (v >= DP_VOLTAGE_MAX)
251 v |= DP_TRAIN_MAX_SWING_REACHED;
253 if (p >= DP_PRE_EMPHASIS_MAX)
254 p |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
256 DRM_DEBUG_KMS("using signal parameters: voltage %s pre_emph %s\n",
257 voltage_names[(v & DP_TRAIN_VOLTAGE_SWING_MASK) >> DP_TRAIN_VOLTAGE_SWING_SHIFT],
258 pre_emph_names[(p & DP_TRAIN_PRE_EMPHASIS_MASK) >> DP_TRAIN_PRE_EMPHASIS_SHIFT]);
260 for (lane = 0; lane < 4; lane++)
261 train_set[lane] = v | p;
264 /* convert bits per color to bits per pixel */
265 /* get bpc from the EDID */
266 static int convert_bpc_to_bpp(int bpc)
274 /* get the max pix clock supported by the link rate and lane num */
275 static int dp_get_max_dp_pix_clock(int link_rate,
279 return (link_rate * lane_num * 8) / bpp;
282 /***** radeon specific DP functions *****/
284 /* First get the min lane# when low rate is used according to pixel clock
285 * (prefer low rate), second check max lane# supported by DP panel,
286 * if the max lane# < low rate lane# then use max lane# instead.
288 static int radeon_dp_get_dp_lane_number(struct drm_connector *connector,
289 u8 dpcd[DP_DPCD_SIZE],
292 int bpp = convert_bpc_to_bpp(radeon_get_monitor_bpc(connector));
293 int max_link_rate = drm_dp_max_link_rate(dpcd);
294 int max_lane_num = drm_dp_max_lane_count(dpcd);
296 int max_dp_pix_clock;
298 for (lane_num = 1; lane_num < max_lane_num; lane_num <<= 1) {
299 max_dp_pix_clock = dp_get_max_dp_pix_clock(max_link_rate, lane_num, bpp);
300 if (pix_clock <= max_dp_pix_clock)
307 static int radeon_dp_get_dp_link_clock(struct drm_connector *connector,
308 u8 dpcd[DP_DPCD_SIZE],
311 int bpp = convert_bpc_to_bpp(radeon_get_monitor_bpc(connector));
312 int lane_num, max_pix_clock;
314 if (radeon_connector_encoder_get_dp_bridge_encoder_id(connector) ==
315 ENCODER_OBJECT_ID_NUTMEG)
318 lane_num = radeon_dp_get_dp_lane_number(connector, dpcd, pix_clock);
319 max_pix_clock = dp_get_max_dp_pix_clock(162000, lane_num, bpp);
320 if (pix_clock <= max_pix_clock)
322 max_pix_clock = dp_get_max_dp_pix_clock(270000, lane_num, bpp);
323 if (pix_clock <= max_pix_clock)
325 if (radeon_connector_is_dp12_capable(connector)) {
326 max_pix_clock = dp_get_max_dp_pix_clock(540000, lane_num, bpp);
327 if (pix_clock <= max_pix_clock)
331 return drm_dp_max_link_rate(dpcd);
334 static u8 radeon_dp_encoder_service(struct radeon_device *rdev,
335 int action, int dp_clock,
336 u8 ucconfig, u8 lane_num)
338 DP_ENCODER_SERVICE_PARAMETERS args;
339 int index = GetIndexIntoMasterTable(COMMAND, DPEncoderService);
341 memset(&args, 0, sizeof(args));
342 args.ucLinkClock = dp_clock / 10;
343 args.ucConfig = ucconfig;
344 args.ucAction = action;
345 args.ucLaneNum = lane_num;
348 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
349 return args.ucStatus;
352 u8 radeon_dp_getsinktype(struct radeon_connector *radeon_connector)
354 struct drm_device *dev = radeon_connector->base.dev;
355 struct radeon_device *rdev = dev->dev_private;
357 return radeon_dp_encoder_service(rdev, ATOM_DP_ACTION_GET_SINK_TYPE, 0,
358 radeon_connector->ddc_bus->rec.i2c_id, 0);
361 static void radeon_dp_probe_oui(struct radeon_connector *radeon_connector)
363 struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
366 if (!(dig_connector->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
369 if (drm_dp_dpcd_read(&radeon_connector->ddc_bus->aux, DP_SINK_OUI, buf, 3))
370 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
371 buf[0], buf[1], buf[2]);
373 if (drm_dp_dpcd_read(&radeon_connector->ddc_bus->aux, DP_BRANCH_OUI, buf, 3))
374 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
375 buf[0], buf[1], buf[2]);
378 bool radeon_dp_getdpcd(struct radeon_connector *radeon_connector)
380 struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
381 u8 msg[DP_DPCD_SIZE];
384 ret = drm_dp_dpcd_read(&radeon_connector->ddc_bus->aux, DP_DPCD_REV, msg,
387 memcpy(dig_connector->dpcd, msg, DP_DPCD_SIZE);
388 DRM_DEBUG_KMS("DPCD: ");
389 for (i = 0; i < DP_DPCD_SIZE; i++)
390 DRM_DEBUG_KMS("%02x ", msg[i]);
393 radeon_dp_probe_oui(radeon_connector);
397 dig_connector->dpcd[0] = 0;
401 int radeon_dp_get_panel_mode(struct drm_encoder *encoder,
402 struct drm_connector *connector)
404 struct drm_device *dev = encoder->dev;
405 struct radeon_device *rdev = dev->dev_private;
406 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
407 struct radeon_connector_atom_dig *dig_connector;
408 int panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE;
409 u16 dp_bridge = radeon_connector_encoder_get_dp_bridge_encoder_id(connector);
412 if (!ASIC_IS_DCE4(rdev))
415 if (!radeon_connector->con_priv)
418 dig_connector = radeon_connector->con_priv;
420 if (dp_bridge != ENCODER_OBJECT_ID_NONE) {
421 /* DP bridge chips */
422 drm_dp_dpcd_readb(&radeon_connector->ddc_bus->aux,
423 DP_EDP_CONFIGURATION_CAP, &tmp);
425 panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE;
426 else if ((dp_bridge == ENCODER_OBJECT_ID_NUTMEG) ||
427 (dp_bridge == ENCODER_OBJECT_ID_TRAVIS))
428 panel_mode = DP_PANEL_MODE_INTERNAL_DP1_MODE;
430 panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE;
431 } else if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
433 drm_dp_dpcd_readb(&radeon_connector->ddc_bus->aux,
434 DP_EDP_CONFIGURATION_CAP, &tmp);
436 panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE;
442 void radeon_dp_set_link_config(struct drm_connector *connector,
443 const struct drm_display_mode *mode)
445 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
446 struct radeon_connector_atom_dig *dig_connector;
448 if (!radeon_connector->con_priv)
450 dig_connector = radeon_connector->con_priv;
452 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
453 (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) {
454 dig_connector->dp_clock =
455 radeon_dp_get_dp_link_clock(connector, dig_connector->dpcd, mode->clock);
456 dig_connector->dp_lane_count =
457 radeon_dp_get_dp_lane_number(connector, dig_connector->dpcd, mode->clock);
461 int radeon_dp_mode_valid_helper(struct drm_connector *connector,
462 struct drm_display_mode *mode)
464 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
465 struct radeon_connector_atom_dig *dig_connector;
468 if (!radeon_connector->con_priv)
469 return MODE_CLOCK_HIGH;
470 dig_connector = radeon_connector->con_priv;
473 radeon_dp_get_dp_link_clock(connector, dig_connector->dpcd, mode->clock);
475 if ((dp_clock == 540000) &&
476 (!radeon_connector_is_dp12_capable(connector)))
477 return MODE_CLOCK_HIGH;
482 bool radeon_dp_needs_link_train(struct radeon_connector *radeon_connector)
484 u8 link_status[DP_LINK_STATUS_SIZE];
485 struct radeon_connector_atom_dig *dig = radeon_connector->con_priv;
487 if (drm_dp_dpcd_read_link_status(&radeon_connector->ddc_bus->aux, link_status)
490 if (drm_dp_channel_eq_ok(link_status, dig->dp_lane_count))
495 void radeon_dp_set_rx_power_state(struct drm_connector *connector,
498 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
499 struct radeon_connector_atom_dig *dig_connector;
501 if (!radeon_connector->con_priv)
504 dig_connector = radeon_connector->con_priv;
506 /* power up/down the sink */
507 if (dig_connector->dpcd[0] >= 0x11) {
508 drm_dp_dpcd_writeb(&radeon_connector->ddc_bus->aux,
509 DP_SET_POWER, power_state);
510 usleep_range(1000, 2000);
515 struct radeon_dp_link_train_info {
516 struct radeon_device *rdev;
517 struct drm_encoder *encoder;
518 struct drm_connector *connector;
523 u8 dpcd[DP_RECEIVER_CAP_SIZE];
525 u8 link_status[DP_LINK_STATUS_SIZE];
528 struct drm_dp_aux *aux;
531 static void radeon_dp_update_vs_emph(struct radeon_dp_link_train_info *dp_info)
533 /* set the initial vs/emph on the source */
534 atombios_dig_transmitter_setup(dp_info->encoder,
535 ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH,
536 0, dp_info->train_set[0]); /* sets all lanes at once */
538 /* set the vs/emph on the sink */
539 drm_dp_dpcd_write(dp_info->aux, DP_TRAINING_LANE0_SET,
540 dp_info->train_set, dp_info->dp_lane_count);
543 static void radeon_dp_set_tp(struct radeon_dp_link_train_info *dp_info, int tp)
547 /* set training pattern on the source */
548 if (ASIC_IS_DCE4(dp_info->rdev) || !dp_info->use_dpencoder) {
550 case DP_TRAINING_PATTERN_1:
551 rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN1;
553 case DP_TRAINING_PATTERN_2:
554 rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN2;
556 case DP_TRAINING_PATTERN_3:
557 rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN3;
560 atombios_dig_encoder_setup(dp_info->encoder, rtp, 0);
563 case DP_TRAINING_PATTERN_1:
566 case DP_TRAINING_PATTERN_2:
570 radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_PATTERN_SEL,
571 dp_info->dp_clock, dp_info->enc_id, rtp);
574 /* enable training pattern on the sink */
575 drm_dp_dpcd_writeb(dp_info->aux, DP_TRAINING_PATTERN_SET, tp);
578 static int radeon_dp_link_train_init(struct radeon_dp_link_train_info *dp_info)
580 struct radeon_encoder *radeon_encoder = to_radeon_encoder(dp_info->encoder);
581 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
584 /* power up the sink */
585 radeon_dp_set_rx_power_state(dp_info->connector, DP_SET_POWER_D0);
587 /* possibly enable downspread on the sink */
588 if (dp_info->dpcd[3] & 0x1)
589 drm_dp_dpcd_writeb(dp_info->aux,
590 DP_DOWNSPREAD_CTRL, DP_SPREAD_AMP_0_5);
592 drm_dp_dpcd_writeb(dp_info->aux,
593 DP_DOWNSPREAD_CTRL, 0);
595 if ((dp_info->connector->connector_type == DRM_MODE_CONNECTOR_eDP) &&
596 (dig->panel_mode == DP_PANEL_MODE_INTERNAL_DP2_MODE)) {
597 drm_dp_dpcd_writeb(dp_info->aux, DP_EDP_CONFIGURATION_SET, 1);
600 /* set the lane count on the sink */
601 tmp = dp_info->dp_lane_count;
602 if (drm_dp_enhanced_frame_cap(dp_info->dpcd))
603 tmp |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
604 drm_dp_dpcd_writeb(dp_info->aux, DP_LANE_COUNT_SET, tmp);
606 /* set the link rate on the sink */
607 tmp = drm_dp_link_rate_to_bw_code(dp_info->dp_clock);
608 drm_dp_dpcd_writeb(dp_info->aux, DP_LINK_BW_SET, tmp);
610 /* start training on the source */
611 if (ASIC_IS_DCE4(dp_info->rdev) || !dp_info->use_dpencoder)
612 atombios_dig_encoder_setup(dp_info->encoder,
613 ATOM_ENCODER_CMD_DP_LINK_TRAINING_START, 0);
615 radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_START,
616 dp_info->dp_clock, dp_info->enc_id, 0);
618 /* disable the training pattern on the sink */
619 drm_dp_dpcd_writeb(dp_info->aux,
620 DP_TRAINING_PATTERN_SET,
621 DP_TRAINING_PATTERN_DISABLE);
626 static int radeon_dp_link_train_finish(struct radeon_dp_link_train_info *dp_info)
630 /* disable the training pattern on the sink */
631 drm_dp_dpcd_writeb(dp_info->aux,
632 DP_TRAINING_PATTERN_SET,
633 DP_TRAINING_PATTERN_DISABLE);
635 /* disable the training pattern on the source */
636 if (ASIC_IS_DCE4(dp_info->rdev) || !dp_info->use_dpencoder)
637 atombios_dig_encoder_setup(dp_info->encoder,
638 ATOM_ENCODER_CMD_DP_LINK_TRAINING_COMPLETE, 0);
640 radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_COMPLETE,
641 dp_info->dp_clock, dp_info->enc_id, 0);
646 static int radeon_dp_link_train_cr(struct radeon_dp_link_train_info *dp_info)
652 radeon_dp_set_tp(dp_info, DP_TRAINING_PATTERN_1);
653 memset(dp_info->train_set, 0, 4);
654 radeon_dp_update_vs_emph(dp_info);
658 /* clock recovery loop */
659 clock_recovery = false;
663 drm_dp_link_train_clock_recovery_delay(dp_info->dpcd);
665 if (drm_dp_dpcd_read_link_status(dp_info->aux,
666 dp_info->link_status) <= 0) {
667 DRM_ERROR("displayport link status failed\n");
671 if (drm_dp_clock_recovery_ok(dp_info->link_status, dp_info->dp_lane_count)) {
672 clock_recovery = true;
676 for (i = 0; i < dp_info->dp_lane_count; i++) {
677 if ((dp_info->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
680 if (i == dp_info->dp_lane_count) {
681 DRM_ERROR("clock recovery reached max voltage\n");
685 if ((dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
687 if (dp_info->tries == 5) {
688 DRM_ERROR("clock recovery tried 5 times\n");
694 voltage = dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
696 /* Compute new train_set as requested by sink */
697 dp_get_adjust_train(dp_info->link_status, dp_info->dp_lane_count, dp_info->train_set);
699 radeon_dp_update_vs_emph(dp_info);
701 if (!clock_recovery) {
702 DRM_ERROR("clock recovery failed\n");
705 DRM_DEBUG_KMS("clock recovery at voltage %d pre-emphasis %d\n",
706 dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK,
707 (dp_info->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK) >>
708 DP_TRAIN_PRE_EMPHASIS_SHIFT);
713 static int radeon_dp_link_train_ce(struct radeon_dp_link_train_info *dp_info)
717 if (dp_info->tp3_supported)
718 radeon_dp_set_tp(dp_info, DP_TRAINING_PATTERN_3);
720 radeon_dp_set_tp(dp_info, DP_TRAINING_PATTERN_2);
722 /* channel equalization loop */
726 drm_dp_link_train_channel_eq_delay(dp_info->dpcd);
728 if (drm_dp_dpcd_read_link_status(dp_info->aux,
729 dp_info->link_status) <= 0) {
730 DRM_ERROR("displayport link status failed\n");
734 if (drm_dp_channel_eq_ok(dp_info->link_status, dp_info->dp_lane_count)) {
740 if (dp_info->tries > 5) {
741 DRM_ERROR("channel eq failed: 5 tries\n");
745 /* Compute new train_set as requested by sink */
746 dp_get_adjust_train(dp_info->link_status, dp_info->dp_lane_count, dp_info->train_set);
748 radeon_dp_update_vs_emph(dp_info);
753 DRM_ERROR("channel eq failed\n");
756 DRM_DEBUG_KMS("channel eq at voltage %d pre-emphasis %d\n",
757 dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK,
758 (dp_info->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK)
759 >> DP_TRAIN_PRE_EMPHASIS_SHIFT);
764 void radeon_dp_link_train(struct drm_encoder *encoder,
765 struct drm_connector *connector)
767 struct drm_device *dev = encoder->dev;
768 struct radeon_device *rdev = dev->dev_private;
769 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
770 struct radeon_encoder_atom_dig *dig;
771 struct radeon_connector *radeon_connector;
772 struct radeon_connector_atom_dig *dig_connector;
773 struct radeon_dp_link_train_info dp_info;
777 if (!radeon_encoder->enc_priv)
779 dig = radeon_encoder->enc_priv;
781 radeon_connector = to_radeon_connector(connector);
782 if (!radeon_connector->con_priv)
784 dig_connector = radeon_connector->con_priv;
786 if ((dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_DISPLAYPORT) &&
787 (dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_eDP))
790 /* DPEncoderService newer than 1.1 can't program properly the
791 * training pattern. When facing such version use the
792 * DIGXEncoderControl (X== 1 | 2)
794 dp_info.use_dpencoder = true;
795 index = GetIndexIntoMasterTable(COMMAND, DPEncoderService);
796 if (atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) {
798 dp_info.use_dpencoder = false;
803 if (dig->dig_encoder)
804 dp_info.enc_id |= ATOM_DP_CONFIG_DIG2_ENCODER;
806 dp_info.enc_id |= ATOM_DP_CONFIG_DIG1_ENCODER;
808 dp_info.enc_id |= ATOM_DP_CONFIG_LINK_B;
810 dp_info.enc_id |= ATOM_DP_CONFIG_LINK_A;
812 drm_dp_dpcd_readb(&radeon_connector->ddc_bus->aux, DP_MAX_LANE_COUNT, &tmp);
813 if (ASIC_IS_DCE5(rdev) && (tmp & DP_TPS3_SUPPORTED))
814 dp_info.tp3_supported = true;
816 dp_info.tp3_supported = false;
818 memcpy(dp_info.dpcd, dig_connector->dpcd, DP_RECEIVER_CAP_SIZE);
820 dp_info.encoder = encoder;
821 dp_info.connector = connector;
822 dp_info.dp_lane_count = dig_connector->dp_lane_count;
823 dp_info.dp_clock = dig_connector->dp_clock;
824 dp_info.aux = &radeon_connector->ddc_bus->aux;
826 if (radeon_dp_link_train_init(&dp_info))
828 if (radeon_dp_link_train_cr(&dp_info))
830 if (radeon_dp_link_train_ce(&dp_info))
833 if (radeon_dp_link_train_finish(&dp_info))