2 * Copyright 2007-11 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
23 * Authors: Dave Airlie
27 #include <drm/drm_crtc_helper.h>
28 #include <drm/radeon_drm.h>
30 #include "radeon_audio.h"
32 #include <linux/backlight.h>
34 extern int atom_debug;
37 radeon_atom_get_backlight_level_from_reg(struct radeon_device *rdev)
42 if (rdev->family >= CHIP_R600)
43 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
45 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
47 backlight_level = ((bios_2_scratch & ATOM_S2_CURRENT_BL_LEVEL_MASK) >>
48 ATOM_S2_CURRENT_BL_LEVEL_SHIFT);
50 return backlight_level;
54 radeon_atom_set_backlight_level_to_reg(struct radeon_device *rdev,
59 if (rdev->family >= CHIP_R600)
60 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
62 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
64 bios_2_scratch &= ~ATOM_S2_CURRENT_BL_LEVEL_MASK;
65 bios_2_scratch |= ((backlight_level << ATOM_S2_CURRENT_BL_LEVEL_SHIFT) &
66 ATOM_S2_CURRENT_BL_LEVEL_MASK);
68 if (rdev->family >= CHIP_R600)
69 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
71 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
75 atombios_get_backlight_level(struct radeon_encoder *radeon_encoder)
77 struct drm_device *dev = radeon_encoder->base.dev;
78 struct radeon_device *rdev = dev->dev_private;
80 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU))
83 return radeon_atom_get_backlight_level_from_reg(rdev);
87 atombios_set_backlight_level(struct radeon_encoder *radeon_encoder, u8 level)
89 struct drm_encoder *encoder = &radeon_encoder->base;
90 struct drm_device *dev = radeon_encoder->base.dev;
91 struct radeon_device *rdev = dev->dev_private;
92 struct radeon_encoder_atom_dig *dig;
93 DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args;
96 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU))
99 if ((radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) &&
100 radeon_encoder->enc_priv) {
101 dig = radeon_encoder->enc_priv;
102 dig->backlight_level = level;
103 radeon_atom_set_backlight_level_to_reg(rdev, dig->backlight_level);
105 switch (radeon_encoder->encoder_id) {
106 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
107 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
108 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
109 if (dig->backlight_level == 0) {
110 args.ucAction = ATOM_LCD_BLOFF;
111 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
113 args.ucAction = ATOM_LCD_BL_BRIGHTNESS_CONTROL;
114 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
115 args.ucAction = ATOM_LCD_BLON;
116 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
119 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
120 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
121 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
122 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
123 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
124 if (dig->backlight_level == 0)
125 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0);
127 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_BL_BRIGHTNESS_CONTROL, 0, 0);
128 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLON, 0, 0);
137 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
139 static u8 radeon_atom_bl_level(struct backlight_device *bd)
143 /* Convert brightness to hardware level */
144 if (bd->props.brightness < 0)
146 else if (bd->props.brightness > RADEON_MAX_BL_LEVEL)
147 level = RADEON_MAX_BL_LEVEL;
149 level = bd->props.brightness;
154 static int radeon_atom_backlight_update_status(struct backlight_device *bd)
156 struct radeon_backlight_privdata *pdata = bl_get_data(bd);
157 struct radeon_encoder *radeon_encoder = pdata->encoder;
159 atombios_set_backlight_level(radeon_encoder, radeon_atom_bl_level(bd));
164 static int radeon_atom_backlight_get_brightness(struct backlight_device *bd)
166 struct radeon_backlight_privdata *pdata = bl_get_data(bd);
167 struct radeon_encoder *radeon_encoder = pdata->encoder;
168 struct drm_device *dev = radeon_encoder->base.dev;
169 struct radeon_device *rdev = dev->dev_private;
171 return radeon_atom_get_backlight_level_from_reg(rdev);
174 static const struct backlight_ops radeon_atom_backlight_ops = {
175 .get_brightness = radeon_atom_backlight_get_brightness,
176 .update_status = radeon_atom_backlight_update_status,
179 void radeon_atom_backlight_init(struct radeon_encoder *radeon_encoder,
180 struct drm_connector *drm_connector)
182 struct drm_device *dev = radeon_encoder->base.dev;
183 struct radeon_device *rdev = dev->dev_private;
184 struct backlight_device *bd;
185 struct backlight_properties props;
186 struct radeon_backlight_privdata *pdata;
187 struct radeon_encoder_atom_dig *dig;
190 /* Mac laptops with multiple GPUs use the gmux driver for backlight
191 * so don't register a backlight device
193 if ((rdev->pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE) &&
194 (rdev->pdev->device == 0x6741))
197 if (!radeon_encoder->enc_priv)
200 if (!rdev->is_atom_bios)
203 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU))
206 pdata = kmalloc(sizeof(struct radeon_backlight_privdata), GFP_KERNEL);
208 DRM_ERROR("Memory allocation failed\n");
212 memset(&props, 0, sizeof(props));
213 props.max_brightness = RADEON_MAX_BL_LEVEL;
214 props.type = BACKLIGHT_RAW;
215 snprintf(bl_name, sizeof(bl_name),
216 "radeon_bl%d", dev->primary->index);
217 bd = backlight_device_register(bl_name, drm_connector->kdev,
218 pdata, &radeon_atom_backlight_ops, &props);
220 DRM_ERROR("Backlight registration failed\n");
224 pdata->encoder = radeon_encoder;
226 dig = radeon_encoder->enc_priv;
229 bd->props.brightness = radeon_atom_backlight_get_brightness(bd);
230 /* Set a reasonable default here if the level is 0 otherwise
231 * fbdev will attempt to turn the backlight on after console
232 * unblanking and it will try and restore 0 which turns the backlight
235 if (bd->props.brightness == 0)
236 bd->props.brightness = RADEON_MAX_BL_LEVEL;
237 bd->props.power = FB_BLANK_UNBLANK;
238 backlight_update_status(bd);
240 DRM_INFO("radeon atom DIG backlight initialized\n");
241 rdev->mode_info.bl_encoder = radeon_encoder;
250 static void radeon_atom_backlight_exit(struct radeon_encoder *radeon_encoder)
252 struct drm_device *dev = radeon_encoder->base.dev;
253 struct radeon_device *rdev = dev->dev_private;
254 struct backlight_device *bd = NULL;
255 struct radeon_encoder_atom_dig *dig;
257 if (!radeon_encoder->enc_priv)
260 if (!rdev->is_atom_bios)
263 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU))
266 dig = radeon_encoder->enc_priv;
271 struct radeon_legacy_backlight_privdata *pdata;
273 pdata = bl_get_data(bd);
274 backlight_device_unregister(bd);
277 DRM_INFO("radeon atom LVDS backlight unloaded\n");
281 #else /* !CONFIG_BACKLIGHT_CLASS_DEVICE */
283 void radeon_atom_backlight_init(struct radeon_encoder *encoder)
287 static void radeon_atom_backlight_exit(struct radeon_encoder *encoder)
293 /* evil but including atombios.h is much worse */
294 bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
295 struct drm_display_mode *mode);
297 static bool radeon_atom_mode_fixup(struct drm_encoder *encoder,
298 const struct drm_display_mode *mode,
299 struct drm_display_mode *adjusted_mode)
301 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
302 struct drm_device *dev = encoder->dev;
303 struct radeon_device *rdev = dev->dev_private;
305 /* set the active encoder to connector routing */
306 radeon_encoder_set_active_device(encoder);
307 drm_mode_set_crtcinfo(adjusted_mode, 0);
310 if ((mode->flags & DRM_MODE_FLAG_INTERLACE)
311 && (mode->crtc_vsync_start < (mode->crtc_vdisplay + 2)))
312 adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + 2;
314 /* vertical FP must be at least 1 */
315 if (mode->crtc_vsync_start == mode->crtc_vdisplay)
316 adjusted_mode->crtc_vsync_start++;
318 /* get the native mode for scaling */
319 if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT)) {
320 radeon_panel_mode_fixup(encoder, adjusted_mode);
321 } else if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) {
322 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv;
324 if (tv_dac->tv_std == TV_STD_NTSC ||
325 tv_dac->tv_std == TV_STD_NTSC_J ||
326 tv_dac->tv_std == TV_STD_PAL_M)
327 radeon_atom_get_tv_timings(rdev, 0, adjusted_mode);
329 radeon_atom_get_tv_timings(rdev, 1, adjusted_mode);
331 } else if (radeon_encoder->rmx_type != RMX_OFF) {
332 radeon_panel_mode_fixup(encoder, adjusted_mode);
335 if (ASIC_IS_DCE3(rdev) &&
336 ((radeon_encoder->active_device & (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
337 (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE))) {
338 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
339 radeon_dp_set_link_config(connector, adjusted_mode);
346 atombios_dac_setup(struct drm_encoder *encoder, int action)
348 struct drm_device *dev = encoder->dev;
349 struct radeon_device *rdev = dev->dev_private;
350 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
351 DAC_ENCODER_CONTROL_PS_ALLOCATION args;
353 struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
355 memset(&args, 0, sizeof(args));
357 switch (radeon_encoder->encoder_id) {
358 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
359 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
360 index = GetIndexIntoMasterTable(COMMAND, DAC1EncoderControl);
362 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
363 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
364 index = GetIndexIntoMasterTable(COMMAND, DAC2EncoderControl);
368 args.ucAction = action;
370 if (radeon_encoder->active_device & (ATOM_DEVICE_CRT_SUPPORT))
371 args.ucDacStandard = ATOM_DAC1_PS2;
372 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
373 args.ucDacStandard = ATOM_DAC1_CV;
375 switch (dac_info->tv_std) {
378 case TV_STD_SCART_PAL:
381 args.ucDacStandard = ATOM_DAC1_PAL;
387 args.ucDacStandard = ATOM_DAC1_NTSC;
391 args.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
393 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
398 atombios_tv_setup(struct drm_encoder *encoder, int action)
400 struct drm_device *dev = encoder->dev;
401 struct radeon_device *rdev = dev->dev_private;
402 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
403 TV_ENCODER_CONTROL_PS_ALLOCATION args;
405 struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
407 memset(&args, 0, sizeof(args));
409 index = GetIndexIntoMasterTable(COMMAND, TVEncoderControl);
411 args.sTVEncoder.ucAction = action;
413 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
414 args.sTVEncoder.ucTvStandard = ATOM_TV_CV;
416 switch (dac_info->tv_std) {
418 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
421 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL;
424 args.sTVEncoder.ucTvStandard = ATOM_TV_PALM;
427 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL60;
430 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSCJ;
432 case TV_STD_SCART_PAL:
433 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL; /* ??? */
436 args.sTVEncoder.ucTvStandard = ATOM_TV_SECAM;
439 args.sTVEncoder.ucTvStandard = ATOM_TV_PALCN;
442 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
447 args.sTVEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
449 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
453 static u8 radeon_atom_get_bpc(struct drm_encoder *encoder)
458 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
459 bpc = radeon_crtc->bpc;
464 return PANEL_BPC_UNDEFINE;
466 return PANEL_6BIT_PER_COLOR;
469 return PANEL_8BIT_PER_COLOR;
471 return PANEL_10BIT_PER_COLOR;
473 return PANEL_12BIT_PER_COLOR;
475 return PANEL_16BIT_PER_COLOR;
479 union dvo_encoder_control {
480 ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION ext_tmds;
481 DVO_ENCODER_CONTROL_PS_ALLOCATION dvo;
482 DVO_ENCODER_CONTROL_PS_ALLOCATION_V3 dvo_v3;
483 DVO_ENCODER_CONTROL_PS_ALLOCATION_V1_4 dvo_v4;
487 atombios_dvo_setup(struct drm_encoder *encoder, int action)
489 struct drm_device *dev = encoder->dev;
490 struct radeon_device *rdev = dev->dev_private;
491 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
492 union dvo_encoder_control args;
493 int index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl);
496 memset(&args, 0, sizeof(args));
498 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
501 /* some R4xx chips have the wrong frev */
502 if (rdev->family <= CHIP_RV410)
510 args.ext_tmds.sXTmdsEncoder.ucEnable = action;
512 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
513 args.ext_tmds.sXTmdsEncoder.ucMisc |= PANEL_ENCODER_MISC_DUAL;
515 args.ext_tmds.sXTmdsEncoder.ucMisc |= ATOM_PANEL_MISC_888RGB;
519 args.dvo.sDVOEncoder.ucAction = action;
520 args.dvo.sDVOEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
521 /* DFP1, CRT1, TV1 depending on the type of port */
522 args.dvo.sDVOEncoder.ucDeviceType = ATOM_DEVICE_DFP1_INDEX;
524 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
525 args.dvo.sDVOEncoder.usDevAttr.sDigAttrib.ucAttribute |= PANEL_ENCODER_MISC_DUAL;
529 args.dvo_v3.ucAction = action;
530 args.dvo_v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
531 args.dvo_v3.ucDVOConfig = 0; /* XXX */
535 args.dvo_v4.ucAction = action;
536 args.dvo_v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
537 args.dvo_v4.ucDVOConfig = 0; /* XXX */
538 args.dvo_v4.ucBitPerColor = radeon_atom_get_bpc(encoder);
541 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
546 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
550 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
553 union lvds_encoder_control {
554 LVDS_ENCODER_CONTROL_PS_ALLOCATION v1;
555 LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 v2;
559 atombios_digital_setup(struct drm_encoder *encoder, int action)
561 struct drm_device *dev = encoder->dev;
562 struct radeon_device *rdev = dev->dev_private;
563 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
564 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
565 union lvds_encoder_control args;
567 int hdmi_detected = 0;
573 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
576 memset(&args, 0, sizeof(args));
578 switch (radeon_encoder->encoder_id) {
579 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
580 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
582 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
583 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
584 index = GetIndexIntoMasterTable(COMMAND, TMDS1EncoderControl);
586 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
587 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
588 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
590 index = GetIndexIntoMasterTable(COMMAND, TMDS2EncoderControl);
594 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
603 args.v1.ucAction = action;
605 args.v1.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
606 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
607 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
608 if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL)
609 args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
610 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
611 args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB;
614 args.v1.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
615 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
616 args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
617 /*if (pScrn->rgbBits == 8) */
618 args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB;
624 args.v2.ucAction = action;
626 if (dig->coherent_mode)
627 args.v2.ucMisc |= PANEL_ENCODER_MISC_COHERENT;
630 args.v2.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
631 args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
632 args.v2.ucTruncate = 0;
633 args.v2.ucSpatial = 0;
634 args.v2.ucTemporal = 0;
636 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
637 if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL)
638 args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
639 if (dig->lcd_misc & ATOM_PANEL_MISC_SPATIAL) {
640 args.v2.ucSpatial = PANEL_ENCODER_SPATIAL_DITHER_EN;
641 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
642 args.v2.ucSpatial |= PANEL_ENCODER_SPATIAL_DITHER_DEPTH;
644 if (dig->lcd_misc & ATOM_PANEL_MISC_TEMPORAL) {
645 args.v2.ucTemporal = PANEL_ENCODER_TEMPORAL_DITHER_EN;
646 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
647 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_DITHER_DEPTH;
648 if (((dig->lcd_misc >> ATOM_PANEL_MISC_GREY_LEVEL_SHIFT) & 0x3) == 2)
649 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_LEVEL_4;
653 args.v2.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
654 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
655 args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
659 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
664 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
668 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
672 atombios_get_encoder_mode(struct drm_encoder *encoder)
674 struct drm_device *dev = encoder->dev;
675 struct radeon_device *rdev = dev->dev_private;
676 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
677 struct drm_connector *connector;
678 struct radeon_connector *radeon_connector;
679 struct radeon_connector_atom_dig *dig_connector;
680 struct radeon_encoder_atom_dig *dig_enc;
682 if (radeon_encoder_is_digital(encoder)) {
683 dig_enc = radeon_encoder->enc_priv;
684 if (dig_enc->active_mst_links)
685 return ATOM_ENCODER_MODE_DP_MST;
687 if (radeon_encoder->is_mst_encoder || radeon_encoder->offset)
688 return ATOM_ENCODER_MODE_DP_MST;
689 /* dp bridges are always DP */
690 if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE)
691 return ATOM_ENCODER_MODE_DP;
693 /* DVO is always DVO */
694 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DVO1) ||
695 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1))
696 return ATOM_ENCODER_MODE_DVO;
698 connector = radeon_get_connector_for_encoder(encoder);
699 /* if we don't have an active device yet, just use one of
700 * the connectors tied to the encoder.
703 connector = radeon_get_connector_for_encoder_init(encoder);
704 radeon_connector = to_radeon_connector(connector);
706 switch (connector->connector_type) {
707 case DRM_MODE_CONNECTOR_DVII:
708 case DRM_MODE_CONNECTOR_HDMIB: /* HDMI-B is basically DL-DVI; analog works fine */
709 if (radeon_audio != 0) {
710 if (radeon_connector->use_digital &&
711 (radeon_connector->audio == RADEON_AUDIO_ENABLE))
712 return ATOM_ENCODER_MODE_HDMI;
713 else if (drm_detect_hdmi_monitor(radeon_connector_edid(connector)) &&
714 (radeon_connector->audio == RADEON_AUDIO_AUTO))
715 return ATOM_ENCODER_MODE_HDMI;
716 else if (radeon_connector->use_digital)
717 return ATOM_ENCODER_MODE_DVI;
719 return ATOM_ENCODER_MODE_CRT;
720 } else if (radeon_connector->use_digital) {
721 return ATOM_ENCODER_MODE_DVI;
723 return ATOM_ENCODER_MODE_CRT;
726 case DRM_MODE_CONNECTOR_DVID:
727 case DRM_MODE_CONNECTOR_HDMIA:
729 if (radeon_audio != 0) {
730 if (radeon_connector->audio == RADEON_AUDIO_ENABLE)
731 return ATOM_ENCODER_MODE_HDMI;
732 else if (drm_detect_hdmi_monitor(radeon_connector_edid(connector)) &&
733 (radeon_connector->audio == RADEON_AUDIO_AUTO))
734 return ATOM_ENCODER_MODE_HDMI;
736 return ATOM_ENCODER_MODE_DVI;
738 return ATOM_ENCODER_MODE_DVI;
741 case DRM_MODE_CONNECTOR_LVDS:
742 return ATOM_ENCODER_MODE_LVDS;
744 case DRM_MODE_CONNECTOR_DisplayPort:
745 dig_connector = radeon_connector->con_priv;
746 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
747 (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) {
748 if (radeon_audio != 0 &&
749 drm_detect_monitor_audio(radeon_connector_edid(connector)) &&
750 ASIC_IS_DCE4(rdev) && !ASIC_IS_DCE5(rdev))
751 return ATOM_ENCODER_MODE_DP_AUDIO;
752 return ATOM_ENCODER_MODE_DP;
753 } else if (radeon_audio != 0) {
754 if (radeon_connector->audio == RADEON_AUDIO_ENABLE)
755 return ATOM_ENCODER_MODE_HDMI;
756 else if (drm_detect_hdmi_monitor(radeon_connector_edid(connector)) &&
757 (radeon_connector->audio == RADEON_AUDIO_AUTO))
758 return ATOM_ENCODER_MODE_HDMI;
760 return ATOM_ENCODER_MODE_DVI;
762 return ATOM_ENCODER_MODE_DVI;
765 case DRM_MODE_CONNECTOR_eDP:
766 if (radeon_audio != 0 &&
767 drm_detect_monitor_audio(radeon_connector_edid(connector)) &&
768 ASIC_IS_DCE4(rdev) && !ASIC_IS_DCE5(rdev))
769 return ATOM_ENCODER_MODE_DP_AUDIO;
770 return ATOM_ENCODER_MODE_DP;
771 case DRM_MODE_CONNECTOR_DVIA:
772 case DRM_MODE_CONNECTOR_VGA:
773 return ATOM_ENCODER_MODE_CRT;
775 case DRM_MODE_CONNECTOR_Composite:
776 case DRM_MODE_CONNECTOR_SVIDEO:
777 case DRM_MODE_CONNECTOR_9PinDIN:
779 return ATOM_ENCODER_MODE_TV;
780 /*return ATOM_ENCODER_MODE_CV;*/
786 * DIG Encoder/Transmitter Setup
789 * - 2 DIG transmitter blocks. UNIPHY (links A and B) and LVTMA.
790 * Supports up to 3 digital outputs
791 * - 2 DIG encoder blocks.
792 * DIG1 can drive UNIPHY link A or link B
793 * DIG2 can drive UNIPHY link B or LVTMA
796 * - 3 DIG transmitter blocks. UNIPHY0/1/2 (links A and B).
797 * Supports up to 5 digital outputs
798 * - 2 DIG encoder blocks.
799 * DIG1/2 can drive UNIPHY0/1/2 link A or link B
802 * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B).
803 * Supports up to 6 digital outputs
804 * - 6 DIG encoder blocks.
805 * - DIG to PHY mapping is hardcoded
806 * DIG1 drives UNIPHY0 link A, A+B
807 * DIG2 drives UNIPHY0 link B
808 * DIG3 drives UNIPHY1 link A, A+B
809 * DIG4 drives UNIPHY1 link B
810 * DIG5 drives UNIPHY2 link A, A+B
811 * DIG6 drives UNIPHY2 link B
814 * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B).
815 * Supports up to 6 digital outputs
816 * - 2 DIG encoder blocks.
818 * DIG1/2 can drive UNIPHY0/1/2 link A or link B
820 * DIG1 drives UNIPHY0/1/2 link A
821 * DIG2 drives UNIPHY0/1/2 link B
824 * crtc -> dig encoder -> UNIPHY/LVTMA (1 or 2 links)
826 * crtc0 -> dig2 -> LVTMA links A+B -> TMDS/HDMI
827 * crtc1 -> dig1 -> UNIPHY0 link B -> DP
828 * crtc0 -> dig1 -> UNIPHY2 link A -> LVDS
829 * crtc1 -> dig2 -> UNIPHY1 link B+A -> TMDS/HDMI
832 union dig_encoder_control {
833 DIG_ENCODER_CONTROL_PS_ALLOCATION v1;
834 DIG_ENCODER_CONTROL_PARAMETERS_V2 v2;
835 DIG_ENCODER_CONTROL_PARAMETERS_V3 v3;
836 DIG_ENCODER_CONTROL_PARAMETERS_V4 v4;
840 atombios_dig_encoder_setup2(struct drm_encoder *encoder, int action, int panel_mode, int enc_override)
842 struct drm_device *dev = encoder->dev;
843 struct radeon_device *rdev = dev->dev_private;
844 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
845 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
846 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
847 union dig_encoder_control args;
851 int dp_lane_count = 0;
852 int hpd_id = RADEON_HPD_NONE;
855 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
856 struct radeon_connector_atom_dig *dig_connector =
857 radeon_connector->con_priv;
859 dp_clock = dig_connector->dp_clock;
860 dp_lane_count = dig_connector->dp_lane_count;
861 hpd_id = radeon_connector->hpd.hpd;
864 /* no dig encoder assigned */
865 if (dig->dig_encoder == -1)
868 memset(&args, 0, sizeof(args));
870 if (ASIC_IS_DCE4(rdev))
871 index = GetIndexIntoMasterTable(COMMAND, DIGxEncoderControl);
873 if (dig->dig_encoder)
874 index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl);
876 index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl);
879 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
886 args.v1.ucAction = action;
887 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
888 if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE)
889 args.v3.ucPanelMode = panel_mode;
891 args.v1.ucEncoderMode = atombios_get_encoder_mode(encoder);
893 if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode))
894 args.v1.ucLaneNum = dp_lane_count;
895 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
896 args.v1.ucLaneNum = 8;
898 args.v1.ucLaneNum = 4;
900 switch (radeon_encoder->encoder_id) {
901 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
902 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER1;
904 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
905 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
906 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER2;
908 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
909 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER3;
913 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKB;
915 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKA;
917 if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode) && (dp_clock == 270000))
918 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
923 args.v3.ucAction = action;
924 args.v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
925 if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE)
926 args.v3.ucPanelMode = panel_mode;
928 args.v3.ucEncoderMode = atombios_get_encoder_mode(encoder);
930 if (ENCODER_MODE_IS_DP(args.v3.ucEncoderMode))
931 args.v3.ucLaneNum = dp_lane_count;
932 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
933 args.v3.ucLaneNum = 8;
935 args.v3.ucLaneNum = 4;
937 if (ENCODER_MODE_IS_DP(args.v3.ucEncoderMode) && (dp_clock == 270000))
938 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ;
939 if (enc_override != -1)
940 args.v3.acConfig.ucDigSel = enc_override;
942 args.v3.acConfig.ucDigSel = dig->dig_encoder;
943 args.v3.ucBitPerColor = radeon_atom_get_bpc(encoder);
946 args.v4.ucAction = action;
947 args.v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
948 if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE)
949 args.v4.ucPanelMode = panel_mode;
951 args.v4.ucEncoderMode = atombios_get_encoder_mode(encoder);
953 if (ENCODER_MODE_IS_DP(args.v4.ucEncoderMode))
954 args.v4.ucLaneNum = dp_lane_count;
955 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
956 args.v4.ucLaneNum = 8;
958 args.v4.ucLaneNum = 4;
960 if (ENCODER_MODE_IS_DP(args.v4.ucEncoderMode)) {
961 if (dp_clock == 540000)
962 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_5_40GHZ;
963 else if (dp_clock == 324000)
964 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_3_24GHZ;
965 else if (dp_clock == 270000)
966 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_2_70GHZ;
968 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_1_62GHZ;
971 if (enc_override != -1)
972 args.v4.acConfig.ucDigSel = enc_override;
974 args.v4.acConfig.ucDigSel = dig->dig_encoder;
975 args.v4.ucBitPerColor = radeon_atom_get_bpc(encoder);
976 if (hpd_id == RADEON_HPD_NONE)
977 args.v4.ucHPD_ID = 0;
979 args.v4.ucHPD_ID = hpd_id + 1;
982 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
987 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
991 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
996 atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mode)
998 atombios_dig_encoder_setup2(encoder, action, panel_mode, -1);
1001 union dig_transmitter_control {
1002 DIG_TRANSMITTER_CONTROL_PS_ALLOCATION v1;
1003 DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 v2;
1004 DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 v3;
1005 DIG_TRANSMITTER_CONTROL_PARAMETERS_V4 v4;
1006 DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5 v5;
1010 atombios_dig_transmitter_setup2(struct drm_encoder *encoder, int action, uint8_t lane_num, uint8_t lane_set, int fe)
1012 struct drm_device *dev = encoder->dev;
1013 struct radeon_device *rdev = dev->dev_private;
1014 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1015 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
1016 struct drm_connector *connector;
1017 union dig_transmitter_control args;
1023 int dp_lane_count = 0;
1024 int connector_object_id = 0;
1025 int igp_lane_info = 0;
1026 int dig_encoder = dig->dig_encoder;
1027 int hpd_id = RADEON_HPD_NONE;
1029 if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1030 connector = radeon_get_connector_for_encoder_init(encoder);
1031 /* just needed to avoid bailing in the encoder check. the encoder
1032 * isn't used for init
1036 connector = radeon_get_connector_for_encoder(encoder);
1039 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1040 struct radeon_connector_atom_dig *dig_connector =
1041 radeon_connector->con_priv;
1043 hpd_id = radeon_connector->hpd.hpd;
1044 dp_clock = dig_connector->dp_clock;
1045 dp_lane_count = dig_connector->dp_lane_count;
1046 connector_object_id =
1047 (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
1048 igp_lane_info = dig_connector->igp_lane_info;
1051 if (encoder->crtc) {
1052 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1053 pll_id = radeon_crtc->pll_id;
1056 /* no dig encoder assigned */
1057 if (dig_encoder == -1)
1060 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)))
1063 memset(&args, 0, sizeof(args));
1065 switch (radeon_encoder->encoder_id) {
1066 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1067 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
1069 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1070 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1071 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1072 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
1073 index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
1075 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1076 index = GetIndexIntoMasterTable(COMMAND, LVTMATransmitterControl);
1080 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1087 args.v1.ucAction = action;
1088 if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1089 args.v1.usInitInfo = cpu_to_le16(connector_object_id);
1090 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
1091 args.v1.asMode.ucLaneSel = lane_num;
1092 args.v1.asMode.ucLaneSet = lane_set;
1095 args.v1.usPixelClock = cpu_to_le16(dp_clock / 10);
1096 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1097 args.v1.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
1099 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1102 args.v1.ucConfig = ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL;
1105 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER;
1107 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER;
1109 if ((rdev->flags & RADEON_IS_IGP) &&
1110 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY)) {
1112 !radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) {
1113 if (igp_lane_info & 0x1)
1114 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_3;
1115 else if (igp_lane_info & 0x2)
1116 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_4_7;
1117 else if (igp_lane_info & 0x4)
1118 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_11;
1119 else if (igp_lane_info & 0x8)
1120 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_12_15;
1122 if (igp_lane_info & 0x3)
1123 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_7;
1124 else if (igp_lane_info & 0xc)
1125 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_15;
1130 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKB;
1132 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA;
1135 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
1136 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1137 if (dig->coherent_mode)
1138 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
1139 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1140 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_8LANE_LINK;
1144 args.v2.ucAction = action;
1145 if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1146 args.v2.usInitInfo = cpu_to_le16(connector_object_id);
1147 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
1148 args.v2.asMode.ucLaneSel = lane_num;
1149 args.v2.asMode.ucLaneSet = lane_set;
1152 args.v2.usPixelClock = cpu_to_le16(dp_clock / 10);
1153 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1154 args.v2.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
1156 args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1159 args.v2.acConfig.ucEncoderSel = dig_encoder;
1161 args.v2.acConfig.ucLinkSel = 1;
1163 switch (radeon_encoder->encoder_id) {
1164 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1165 args.v2.acConfig.ucTransmitterSel = 0;
1167 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1168 args.v2.acConfig.ucTransmitterSel = 1;
1170 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1171 args.v2.acConfig.ucTransmitterSel = 2;
1176 args.v2.acConfig.fCoherentMode = 1;
1177 args.v2.acConfig.fDPConnector = 1;
1178 } else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1179 if (dig->coherent_mode)
1180 args.v2.acConfig.fCoherentMode = 1;
1181 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1182 args.v2.acConfig.fDualLinkConnector = 1;
1186 args.v3.ucAction = action;
1187 if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1188 args.v3.usInitInfo = cpu_to_le16(connector_object_id);
1189 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
1190 args.v3.asMode.ucLaneSel = lane_num;
1191 args.v3.asMode.ucLaneSet = lane_set;
1194 args.v3.usPixelClock = cpu_to_le16(dp_clock / 10);
1195 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1196 args.v3.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
1198 args.v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1202 args.v3.ucLaneNum = dp_lane_count;
1203 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1204 args.v3.ucLaneNum = 8;
1206 args.v3.ucLaneNum = 4;
1209 args.v3.acConfig.ucLinkSel = 1;
1210 if (dig_encoder & 1)
1211 args.v3.acConfig.ucEncoderSel = 1;
1213 /* Select the PLL for the PHY
1214 * DP PHY should be clocked from external src if there is
1217 /* On DCE4, if there is an external clock, it generates the DP ref clock */
1218 if (is_dp && rdev->clock.dp_extclk)
1219 args.v3.acConfig.ucRefClkSource = 2; /* external src */
1221 args.v3.acConfig.ucRefClkSource = pll_id;
1223 switch (radeon_encoder->encoder_id) {
1224 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1225 args.v3.acConfig.ucTransmitterSel = 0;
1227 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1228 args.v3.acConfig.ucTransmitterSel = 1;
1230 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1231 args.v3.acConfig.ucTransmitterSel = 2;
1236 args.v3.acConfig.fCoherentMode = 1; /* DP requires coherent */
1237 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1238 if (dig->coherent_mode)
1239 args.v3.acConfig.fCoherentMode = 1;
1240 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1241 args.v3.acConfig.fDualLinkConnector = 1;
1245 args.v4.ucAction = action;
1246 if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1247 args.v4.usInitInfo = cpu_to_le16(connector_object_id);
1248 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
1249 args.v4.asMode.ucLaneSel = lane_num;
1250 args.v4.asMode.ucLaneSet = lane_set;
1253 args.v4.usPixelClock = cpu_to_le16(dp_clock / 10);
1254 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1255 args.v4.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
1257 args.v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1261 args.v4.ucLaneNum = dp_lane_count;
1262 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1263 args.v4.ucLaneNum = 8;
1265 args.v4.ucLaneNum = 4;
1268 args.v4.acConfig.ucLinkSel = 1;
1269 if (dig_encoder & 1)
1270 args.v4.acConfig.ucEncoderSel = 1;
1272 /* Select the PLL for the PHY
1273 * DP PHY should be clocked from external src if there is
1276 /* On DCE5 DCPLL usually generates the DP ref clock */
1278 if (rdev->clock.dp_extclk)
1279 args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_EXTCLK;
1281 args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_DCPLL;
1283 args.v4.acConfig.ucRefClkSource = pll_id;
1285 switch (radeon_encoder->encoder_id) {
1286 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1287 args.v4.acConfig.ucTransmitterSel = 0;
1289 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1290 args.v4.acConfig.ucTransmitterSel = 1;
1292 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1293 args.v4.acConfig.ucTransmitterSel = 2;
1298 args.v4.acConfig.fCoherentMode = 1; /* DP requires coherent */
1299 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1300 if (dig->coherent_mode)
1301 args.v4.acConfig.fCoherentMode = 1;
1302 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1303 args.v4.acConfig.fDualLinkConnector = 1;
1307 args.v5.ucAction = action;
1309 args.v5.usSymClock = cpu_to_le16(dp_clock / 10);
1311 args.v5.usSymClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1313 switch (radeon_encoder->encoder_id) {
1314 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1316 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYB;
1318 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYA;
1320 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1322 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYD;
1324 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYC;
1326 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1328 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYF;
1330 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYE;
1332 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
1333 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYG;
1337 args.v5.ucLaneNum = dp_lane_count;
1338 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1339 args.v5.ucLaneNum = 8;
1341 args.v5.ucLaneNum = 4;
1342 args.v5.ucConnObjId = connector_object_id;
1343 args.v5.ucDigMode = atombios_get_encoder_mode(encoder);
1345 if (is_dp && rdev->clock.dp_extclk)
1346 args.v5.asConfig.ucPhyClkSrcId = ENCODER_REFCLK_SRC_EXTCLK;
1348 args.v5.asConfig.ucPhyClkSrcId = pll_id;
1351 args.v5.asConfig.ucCoherentMode = 1; /* DP requires coherent */
1352 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1353 if (dig->coherent_mode)
1354 args.v5.asConfig.ucCoherentMode = 1;
1356 if (hpd_id == RADEON_HPD_NONE)
1357 args.v5.asConfig.ucHPDSel = 0;
1359 args.v5.asConfig.ucHPDSel = hpd_id + 1;
1360 args.v5.ucDigEncoderSel = (fe != -1) ? (1 << fe) : (1 << dig_encoder);
1361 args.v5.ucDPLaneSet = lane_set;
1364 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1369 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1373 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1377 atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t lane_num, uint8_t lane_set)
1379 atombios_dig_transmitter_setup2(encoder, action, lane_num, lane_set, -1);
1383 atombios_set_edp_panel_power(struct drm_connector *connector, int action)
1385 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1386 struct drm_device *dev = radeon_connector->base.dev;
1387 struct radeon_device *rdev = dev->dev_private;
1388 union dig_transmitter_control args;
1389 int index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
1392 if (connector->connector_type != DRM_MODE_CONNECTOR_eDP)
1395 if (!ASIC_IS_DCE4(rdev))
1398 if ((action != ATOM_TRANSMITTER_ACTION_POWER_ON) &&
1399 (action != ATOM_TRANSMITTER_ACTION_POWER_OFF))
1402 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1405 memset(&args, 0, sizeof(args));
1407 args.v1.ucAction = action;
1409 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1411 /* wait for the panel to power up */
1412 if (action == ATOM_TRANSMITTER_ACTION_POWER_ON) {
1415 for (i = 0; i < 300; i++) {
1416 if (radeon_hpd_sense(rdev, radeon_connector->hpd.hpd))
1426 union external_encoder_control {
1427 EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION v1;
1428 EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3 v3;
1432 atombios_external_encoder_setup(struct drm_encoder *encoder,
1433 struct drm_encoder *ext_encoder,
1436 struct drm_device *dev = encoder->dev;
1437 struct radeon_device *rdev = dev->dev_private;
1438 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1439 struct radeon_encoder *ext_radeon_encoder = to_radeon_encoder(ext_encoder);
1440 union external_encoder_control args;
1441 struct drm_connector *connector;
1442 int index = GetIndexIntoMasterTable(COMMAND, ExternalEncoderControl);
1445 int dp_lane_count = 0;
1446 int connector_object_id = 0;
1447 u32 ext_enum = (ext_radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
1449 if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT)
1450 connector = radeon_get_connector_for_encoder_init(encoder);
1452 connector = radeon_get_connector_for_encoder(encoder);
1455 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1456 struct radeon_connector_atom_dig *dig_connector =
1457 radeon_connector->con_priv;
1459 dp_clock = dig_connector->dp_clock;
1460 dp_lane_count = dig_connector->dp_lane_count;
1461 connector_object_id =
1462 (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
1465 memset(&args, 0, sizeof(args));
1467 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1472 /* no params on frev 1 */
1478 args.v1.sDigEncoder.ucAction = action;
1479 args.v1.sDigEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1480 args.v1.sDigEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder);
1482 if (ENCODER_MODE_IS_DP(args.v1.sDigEncoder.ucEncoderMode)) {
1483 if (dp_clock == 270000)
1484 args.v1.sDigEncoder.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
1485 args.v1.sDigEncoder.ucLaneNum = dp_lane_count;
1486 } else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1487 args.v1.sDigEncoder.ucLaneNum = 8;
1489 args.v1.sDigEncoder.ucLaneNum = 4;
1492 args.v3.sExtEncoder.ucAction = action;
1493 if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT)
1494 args.v3.sExtEncoder.usConnectorId = cpu_to_le16(connector_object_id);
1496 args.v3.sExtEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1497 args.v3.sExtEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder);
1499 if (ENCODER_MODE_IS_DP(args.v3.sExtEncoder.ucEncoderMode)) {
1500 if (dp_clock == 270000)
1501 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ;
1502 else if (dp_clock == 540000)
1503 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ;
1504 args.v3.sExtEncoder.ucLaneNum = dp_lane_count;
1505 } else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1506 args.v3.sExtEncoder.ucLaneNum = 8;
1508 args.v3.sExtEncoder.ucLaneNum = 4;
1510 case GRAPH_OBJECT_ENUM_ID1:
1511 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER1;
1513 case GRAPH_OBJECT_ENUM_ID2:
1514 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER2;
1516 case GRAPH_OBJECT_ENUM_ID3:
1517 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER3;
1520 args.v3.sExtEncoder.ucBitPerColor = radeon_atom_get_bpc(encoder);
1523 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1528 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1531 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1535 atombios_yuv_setup(struct drm_encoder *encoder, bool enable)
1537 struct drm_device *dev = encoder->dev;
1538 struct radeon_device *rdev = dev->dev_private;
1539 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1540 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1541 ENABLE_YUV_PS_ALLOCATION args;
1542 int index = GetIndexIntoMasterTable(COMMAND, EnableYUV);
1545 memset(&args, 0, sizeof(args));
1547 if (rdev->family >= CHIP_R600)
1548 reg = R600_BIOS_3_SCRATCH;
1550 reg = RADEON_BIOS_3_SCRATCH;
1552 /* XXX: fix up scratch reg handling */
1554 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1555 WREG32(reg, (ATOM_S3_TV1_ACTIVE |
1556 (radeon_crtc->crtc_id << 18)));
1557 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1558 WREG32(reg, (ATOM_S3_CV_ACTIVE | (radeon_crtc->crtc_id << 24)));
1563 args.ucEnable = ATOM_ENABLE;
1564 args.ucCRTC = radeon_crtc->crtc_id;
1566 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1572 radeon_atom_encoder_dpms_avivo(struct drm_encoder *encoder, int mode)
1574 struct drm_device *dev = encoder->dev;
1575 struct radeon_device *rdev = dev->dev_private;
1576 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1577 DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args;
1580 memset(&args, 0, sizeof(args));
1582 switch (radeon_encoder->encoder_id) {
1583 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1584 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1585 index = GetIndexIntoMasterTable(COMMAND, TMDSAOutputControl);
1587 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1588 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1589 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1590 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
1592 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1593 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
1595 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1596 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1597 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
1599 index = GetIndexIntoMasterTable(COMMAND, LVTMAOutputControl);
1601 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1602 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1603 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1604 index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
1605 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1606 index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
1608 index = GetIndexIntoMasterTable(COMMAND, DAC1OutputControl);
1610 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1611 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1612 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1613 index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
1614 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1615 index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
1617 index = GetIndexIntoMasterTable(COMMAND, DAC2OutputControl);
1624 case DRM_MODE_DPMS_ON:
1625 args.ucAction = ATOM_ENABLE;
1626 /* workaround for DVOOutputControl on some RS690 systems */
1627 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DDI) {
1628 u32 reg = RREG32(RADEON_BIOS_3_SCRATCH);
1629 WREG32(RADEON_BIOS_3_SCRATCH, reg & ~ATOM_S3_DFP2I_ACTIVE);
1630 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1631 WREG32(RADEON_BIOS_3_SCRATCH, reg);
1633 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1634 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1635 if (rdev->mode_info.bl_encoder) {
1636 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
1638 atombios_set_backlight_level(radeon_encoder, dig->backlight_level);
1640 args.ucAction = ATOM_LCD_BLON;
1641 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1645 case DRM_MODE_DPMS_STANDBY:
1646 case DRM_MODE_DPMS_SUSPEND:
1647 case DRM_MODE_DPMS_OFF:
1648 args.ucAction = ATOM_DISABLE;
1649 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1650 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1651 args.ucAction = ATOM_LCD_BLOFF;
1652 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1659 radeon_atom_encoder_dpms_dig(struct drm_encoder *encoder, int mode)
1661 struct drm_device *dev = encoder->dev;
1662 struct radeon_device *rdev = dev->dev_private;
1663 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1664 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
1665 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
1666 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1667 struct radeon_connector *radeon_connector = NULL;
1668 struct radeon_connector_atom_dig *radeon_dig_connector = NULL;
1669 bool travis_quirk = false;
1672 radeon_connector = to_radeon_connector(connector);
1673 radeon_dig_connector = radeon_connector->con_priv;
1674 if ((radeon_connector_encoder_get_dp_bridge_encoder_id(connector) ==
1675 ENCODER_OBJECT_ID_TRAVIS) &&
1676 (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) &&
1677 !ASIC_IS_DCE5(rdev))
1678 travis_quirk = true;
1682 case DRM_MODE_DPMS_ON:
1683 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE5(rdev)) {
1685 dig->panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE;
1687 dig->panel_mode = radeon_dp_get_panel_mode(encoder, connector);
1689 /* setup and enable the encoder */
1690 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0);
1691 atombios_dig_encoder_setup(encoder,
1692 ATOM_ENCODER_CMD_SETUP_PANEL_MODE,
1695 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev))
1696 atombios_external_encoder_setup(encoder, ext_encoder,
1697 EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP);
1699 } else if (ASIC_IS_DCE4(rdev)) {
1700 /* setup and enable the encoder */
1701 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0);
1703 /* setup and enable the encoder and transmitter */
1704 atombios_dig_encoder_setup(encoder, ATOM_ENABLE, 0);
1705 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP, 0, 0);
1707 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) {
1708 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
1709 atombios_set_edp_panel_power(connector,
1710 ATOM_TRANSMITTER_ACTION_POWER_ON);
1711 radeon_dig_connector->edp_on = true;
1714 /* enable the transmitter */
1715 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1716 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) {
1717 /* DP_SET_POWER_D0 is set in radeon_dp_link_train */
1718 radeon_dp_link_train(encoder, connector);
1719 if (ASIC_IS_DCE4(rdev))
1720 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_ON, 0);
1722 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1723 if (rdev->mode_info.bl_encoder)
1724 atombios_set_backlight_level(radeon_encoder, dig->backlight_level);
1726 atombios_dig_transmitter_setup(encoder,
1727 ATOM_TRANSMITTER_ACTION_LCD_BLON, 0, 0);
1730 atombios_external_encoder_setup(encoder, ext_encoder, ATOM_ENABLE);
1732 case DRM_MODE_DPMS_STANDBY:
1733 case DRM_MODE_DPMS_SUSPEND:
1734 case DRM_MODE_DPMS_OFF:
1736 /* don't power off encoders with active MST links */
1737 if (dig->active_mst_links)
1740 if (ASIC_IS_DCE4(rdev)) {
1741 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector)
1742 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_OFF, 0);
1745 atombios_external_encoder_setup(encoder, ext_encoder, ATOM_DISABLE);
1746 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1747 atombios_dig_transmitter_setup(encoder,
1748 ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0);
1750 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) &&
1751 connector && !travis_quirk)
1752 radeon_dp_set_rx_power_state(connector, DP_SET_POWER_D3);
1753 if (ASIC_IS_DCE4(rdev)) {
1754 /* disable the transmitter */
1755 atombios_dig_transmitter_setup(encoder,
1756 ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1758 /* disable the encoder and transmitter */
1759 atombios_dig_transmitter_setup(encoder,
1760 ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1761 atombios_dig_encoder_setup(encoder, ATOM_DISABLE, 0);
1763 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) {
1765 radeon_dp_set_rx_power_state(connector, DP_SET_POWER_D3);
1766 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
1767 atombios_set_edp_panel_power(connector,
1768 ATOM_TRANSMITTER_ACTION_POWER_OFF);
1769 radeon_dig_connector->edp_on = false;
1777 radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode)
1779 struct drm_device *dev = encoder->dev;
1780 struct radeon_device *rdev = dev->dev_private;
1781 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1782 int encoder_mode = atombios_get_encoder_mode(encoder);
1784 DRM_DEBUG_KMS("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n",
1785 radeon_encoder->encoder_id, mode, radeon_encoder->devices,
1786 radeon_encoder->active_device);
1788 if ((radeon_audio != 0) &&
1789 ((encoder_mode == ATOM_ENCODER_MODE_HDMI) ||
1790 ENCODER_MODE_IS_DP(encoder_mode)))
1791 radeon_audio_dpms(encoder, mode);
1793 switch (radeon_encoder->encoder_id) {
1794 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1795 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1796 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1797 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1798 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1799 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1800 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1801 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1802 radeon_atom_encoder_dpms_avivo(encoder, mode);
1804 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1805 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1806 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1807 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
1808 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1809 radeon_atom_encoder_dpms_dig(encoder, mode);
1811 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1812 if (ASIC_IS_DCE5(rdev)) {
1814 case DRM_MODE_DPMS_ON:
1815 atombios_dvo_setup(encoder, ATOM_ENABLE);
1817 case DRM_MODE_DPMS_STANDBY:
1818 case DRM_MODE_DPMS_SUSPEND:
1819 case DRM_MODE_DPMS_OFF:
1820 atombios_dvo_setup(encoder, ATOM_DISABLE);
1823 } else if (ASIC_IS_DCE3(rdev))
1824 radeon_atom_encoder_dpms_dig(encoder, mode);
1826 radeon_atom_encoder_dpms_avivo(encoder, mode);
1828 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1829 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1830 if (ASIC_IS_DCE5(rdev)) {
1832 case DRM_MODE_DPMS_ON:
1833 atombios_dac_setup(encoder, ATOM_ENABLE);
1835 case DRM_MODE_DPMS_STANDBY:
1836 case DRM_MODE_DPMS_SUSPEND:
1837 case DRM_MODE_DPMS_OFF:
1838 atombios_dac_setup(encoder, ATOM_DISABLE);
1842 radeon_atom_encoder_dpms_avivo(encoder, mode);
1848 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
1852 union crtc_source_param {
1853 SELECT_CRTC_SOURCE_PS_ALLOCATION v1;
1854 SELECT_CRTC_SOURCE_PARAMETERS_V2 v2;
1858 atombios_set_encoder_crtc_source(struct drm_encoder *encoder)
1860 struct drm_device *dev = encoder->dev;
1861 struct radeon_device *rdev = dev->dev_private;
1862 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1863 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1864 union crtc_source_param args;
1865 int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source);
1867 struct radeon_encoder_atom_dig *dig;
1869 memset(&args, 0, sizeof(args));
1871 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1879 if (ASIC_IS_AVIVO(rdev))
1880 args.v1.ucCRTC = radeon_crtc->crtc_id;
1882 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) {
1883 args.v1.ucCRTC = radeon_crtc->crtc_id;
1885 args.v1.ucCRTC = radeon_crtc->crtc_id << 2;
1888 switch (radeon_encoder->encoder_id) {
1889 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1890 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1891 args.v1.ucDevice = ATOM_DEVICE_DFP1_INDEX;
1893 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1894 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1895 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT)
1896 args.v1.ucDevice = ATOM_DEVICE_LCD1_INDEX;
1898 args.v1.ucDevice = ATOM_DEVICE_DFP3_INDEX;
1900 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1901 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1902 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1903 args.v1.ucDevice = ATOM_DEVICE_DFP2_INDEX;
1905 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1906 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1907 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1908 args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1909 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1910 args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1912 args.v1.ucDevice = ATOM_DEVICE_CRT1_INDEX;
1914 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1915 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1916 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1917 args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1918 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1919 args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1921 args.v1.ucDevice = ATOM_DEVICE_CRT2_INDEX;
1926 args.v2.ucCRTC = radeon_crtc->crtc_id;
1927 if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE) {
1928 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1930 if (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)
1931 args.v2.ucEncodeMode = ATOM_ENCODER_MODE_LVDS;
1932 else if (connector->connector_type == DRM_MODE_CONNECTOR_VGA)
1933 args.v2.ucEncodeMode = ATOM_ENCODER_MODE_CRT;
1935 args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder);
1936 } else if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1937 args.v2.ucEncodeMode = ATOM_ENCODER_MODE_LVDS;
1939 args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder);
1941 switch (radeon_encoder->encoder_id) {
1942 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1943 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1944 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1945 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
1946 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1947 dig = radeon_encoder->enc_priv;
1948 switch (dig->dig_encoder) {
1950 args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID;
1953 args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID;
1956 args.v2.ucEncoderID = ASIC_INT_DIG3_ENCODER_ID;
1959 args.v2.ucEncoderID = ASIC_INT_DIG4_ENCODER_ID;
1962 args.v2.ucEncoderID = ASIC_INT_DIG5_ENCODER_ID;
1965 args.v2.ucEncoderID = ASIC_INT_DIG6_ENCODER_ID;
1968 args.v2.ucEncoderID = ASIC_INT_DIG7_ENCODER_ID;
1972 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1973 args.v2.ucEncoderID = ASIC_INT_DVO_ENCODER_ID;
1975 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1976 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1977 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1978 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1979 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1981 args.v2.ucEncoderID = ASIC_INT_DAC1_ENCODER_ID;
1983 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1984 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1985 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1986 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1987 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1989 args.v2.ucEncoderID = ASIC_INT_DAC2_ENCODER_ID;
1996 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
2000 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2002 /* update scratch regs with new routing */
2003 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
2007 atombios_set_mst_encoder_crtc_source(struct drm_encoder *encoder, int fe)
2009 struct drm_device *dev = encoder->dev;
2010 struct radeon_device *rdev = dev->dev_private;
2011 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
2012 int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source);
2014 union crtc_source_param args;
2016 memset(&args, 0, sizeof(args));
2018 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
2021 if (frev != 1 && crev != 2)
2022 DRM_ERROR("Unknown table for MST %d, %d\n", frev, crev);
2024 args.v2.ucCRTC = radeon_crtc->crtc_id;
2025 args.v2.ucEncodeMode = ATOM_ENCODER_MODE_DP_MST;
2029 args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID;
2032 args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID;
2035 args.v2.ucEncoderID = ASIC_INT_DIG3_ENCODER_ID;
2038 args.v2.ucEncoderID = ASIC_INT_DIG4_ENCODER_ID;
2041 args.v2.ucEncoderID = ASIC_INT_DIG5_ENCODER_ID;
2044 args.v2.ucEncoderID = ASIC_INT_DIG6_ENCODER_ID;
2047 args.v2.ucEncoderID = ASIC_INT_DIG7_ENCODER_ID;
2050 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2054 atombios_apply_encoder_quirks(struct drm_encoder *encoder,
2055 struct drm_display_mode *mode)
2057 struct drm_device *dev = encoder->dev;
2058 struct radeon_device *rdev = dev->dev_private;
2059 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2060 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
2062 /* Funky macbooks */
2063 if ((dev->pdev->device == 0x71C5) &&
2064 (dev->pdev->subsystem_vendor == 0x106b) &&
2065 (dev->pdev->subsystem_device == 0x0080)) {
2066 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
2067 uint32_t lvtma_bit_depth_control = RREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL);
2069 lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN;
2070 lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN;
2072 WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL, lvtma_bit_depth_control);
2076 /* set scaler clears this on some chips */
2077 if (ASIC_IS_AVIVO(rdev) &&
2078 (!(radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)))) {
2079 if (ASIC_IS_DCE8(rdev)) {
2080 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
2081 WREG32(CIK_LB_DATA_FORMAT + radeon_crtc->crtc_offset,
2084 WREG32(CIK_LB_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
2085 } else if (ASIC_IS_DCE4(rdev)) {
2086 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
2087 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset,
2088 EVERGREEN_INTERLEAVE_EN);
2090 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
2092 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
2093 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset,
2094 AVIVO_D1MODE_INTERLEAVE_EN);
2096 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
2101 void radeon_atom_release_dig_encoder(struct radeon_device *rdev, int enc_idx)
2105 rdev->mode_info.active_encoders &= ~(1 << enc_idx);
2108 int radeon_atom_pick_dig_encoder(struct drm_encoder *encoder, int fe_idx)
2110 struct drm_device *dev = encoder->dev;
2111 struct radeon_device *rdev = dev->dev_private;
2112 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
2113 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2114 struct drm_encoder *test_encoder;
2115 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
2116 uint32_t dig_enc_in_use = 0;
2123 if (ASIC_IS_DCE6(rdev)) {
2125 switch (radeon_encoder->encoder_id) {
2126 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2132 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2138 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2144 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2149 } else if (ASIC_IS_DCE4(rdev)) {
2151 if (ASIC_IS_DCE41(rdev) && !ASIC_IS_DCE61(rdev)) {
2152 /* ontario follows DCE4 */
2153 if (rdev->family == CHIP_PALM) {
2159 /* llano follows DCE3.2 */
2160 enc_idx = radeon_crtc->crtc_id;
2162 switch (radeon_encoder->encoder_id) {
2163 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2169 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2175 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2186 /* on DCE32 and encoder can driver any block so just crtc id */
2187 if (ASIC_IS_DCE32(rdev)) {
2188 enc_idx = radeon_crtc->crtc_id;
2192 /* on DCE3 - LVTMA can only be driven by DIGB */
2193 list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) {
2194 struct radeon_encoder *radeon_test_encoder;
2196 if (encoder == test_encoder)
2199 if (!radeon_encoder_is_digital(test_encoder))
2202 radeon_test_encoder = to_radeon_encoder(test_encoder);
2203 dig = radeon_test_encoder->enc_priv;
2205 if (dig->dig_encoder >= 0)
2206 dig_enc_in_use |= (1 << dig->dig_encoder);
2209 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA) {
2210 if (dig_enc_in_use & 0x2)
2211 DRM_ERROR("LVDS required digital encoder 2 but it was in use - stealing\n");
2214 if (!(dig_enc_in_use & 1))
2219 if (enc_idx == -1) {
2220 DRM_ERROR("Got encoder index incorrect - returning 0\n");
2223 if (rdev->mode_info.active_encoders & (1 << enc_idx)) {
2224 DRM_ERROR("chosen encoder in use %d\n", enc_idx);
2226 rdev->mode_info.active_encoders |= (1 << enc_idx);
2230 /* This only needs to be called once at startup */
2232 radeon_atom_encoder_init(struct radeon_device *rdev)
2234 struct drm_device *dev = rdev->ddev;
2235 struct drm_encoder *encoder;
2237 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2238 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2239 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
2241 switch (radeon_encoder->encoder_id) {
2242 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2243 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2244 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2245 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2246 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2247 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT, 0, 0);
2253 if (ext_encoder && (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev)))
2254 atombios_external_encoder_setup(encoder, ext_encoder,
2255 EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT);
2260 radeon_atom_encoder_mode_set(struct drm_encoder *encoder,
2261 struct drm_display_mode *mode,
2262 struct drm_display_mode *adjusted_mode)
2264 struct drm_device *dev = encoder->dev;
2265 struct radeon_device *rdev = dev->dev_private;
2266 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2267 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
2270 radeon_encoder->pixel_clock = adjusted_mode->clock;
2272 /* need to call this here rather than in prepare() since we need some crtc info */
2273 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
2275 if (ASIC_IS_AVIVO(rdev) && !ASIC_IS_DCE4(rdev)) {
2276 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT))
2277 atombios_yuv_setup(encoder, true);
2279 atombios_yuv_setup(encoder, false);
2282 switch (radeon_encoder->encoder_id) {
2283 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
2284 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
2285 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
2286 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
2287 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_ENABLE);
2289 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2290 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2291 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2292 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2293 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2294 /* handled in dpms */
2296 case ENCODER_OBJECT_ID_INTERNAL_DDI:
2297 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
2298 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
2299 atombios_dvo_setup(encoder, ATOM_ENABLE);
2301 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
2302 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
2303 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
2304 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
2305 atombios_dac_setup(encoder, ATOM_ENABLE);
2306 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) {
2307 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
2308 atombios_tv_setup(encoder, ATOM_ENABLE);
2310 atombios_tv_setup(encoder, ATOM_DISABLE);
2315 atombios_apply_encoder_quirks(encoder, adjusted_mode);
2317 encoder_mode = atombios_get_encoder_mode(encoder);
2318 if (connector && (radeon_audio != 0) &&
2319 ((encoder_mode == ATOM_ENCODER_MODE_HDMI) ||
2320 ENCODER_MODE_IS_DP(encoder_mode)))
2321 radeon_audio_mode_set(encoder, adjusted_mode);
2325 atombios_dac_load_detect(struct drm_encoder *encoder, struct drm_connector *connector)
2327 struct drm_device *dev = encoder->dev;
2328 struct radeon_device *rdev = dev->dev_private;
2329 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2330 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2332 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT |
2333 ATOM_DEVICE_CV_SUPPORT |
2334 ATOM_DEVICE_CRT_SUPPORT)) {
2335 DAC_LOAD_DETECTION_PS_ALLOCATION args;
2336 int index = GetIndexIntoMasterTable(COMMAND, DAC_LoadDetection);
2339 memset(&args, 0, sizeof(args));
2341 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
2344 args.sDacload.ucMisc = 0;
2346 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) ||
2347 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1))
2348 args.sDacload.ucDacType = ATOM_DAC_A;
2350 args.sDacload.ucDacType = ATOM_DAC_B;
2352 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)
2353 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT1_SUPPORT);
2354 else if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)
2355 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT2_SUPPORT);
2356 else if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
2357 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CV_SUPPORT);
2359 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
2360 } else if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
2361 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_TV1_SUPPORT);
2363 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
2366 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2373 static enum drm_connector_status
2374 radeon_atom_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
2376 struct drm_device *dev = encoder->dev;
2377 struct radeon_device *rdev = dev->dev_private;
2378 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2379 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2380 uint32_t bios_0_scratch;
2382 if (!atombios_dac_load_detect(encoder, connector)) {
2383 DRM_DEBUG_KMS("detect returned false \n");
2384 return connector_status_unknown;
2387 if (rdev->family >= CHIP_R600)
2388 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
2390 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
2392 DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices);
2393 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2394 if (bios_0_scratch & ATOM_S0_CRT1_MASK)
2395 return connector_status_connected;
2397 if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2398 if (bios_0_scratch & ATOM_S0_CRT2_MASK)
2399 return connector_status_connected;
2401 if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
2402 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A))
2403 return connector_status_connected;
2405 if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
2406 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A))
2407 return connector_status_connected; /* CTV */
2408 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A))
2409 return connector_status_connected; /* STV */
2411 return connector_status_disconnected;
2414 static enum drm_connector_status
2415 radeon_atom_dig_detect(struct drm_encoder *encoder, struct drm_connector *connector)
2417 struct drm_device *dev = encoder->dev;
2418 struct radeon_device *rdev = dev->dev_private;
2419 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2420 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2421 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
2424 if (!ASIC_IS_DCE4(rdev))
2425 return connector_status_unknown;
2428 return connector_status_unknown;
2430 if ((radeon_connector->devices & ATOM_DEVICE_CRT_SUPPORT) == 0)
2431 return connector_status_unknown;
2433 /* load detect on the dp bridge */
2434 atombios_external_encoder_setup(encoder, ext_encoder,
2435 EXTERNAL_ENCODER_ACTION_V3_DACLOAD_DETECTION);
2437 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
2439 DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices);
2440 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2441 if (bios_0_scratch & ATOM_S0_CRT1_MASK)
2442 return connector_status_connected;
2444 if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2445 if (bios_0_scratch & ATOM_S0_CRT2_MASK)
2446 return connector_status_connected;
2448 if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
2449 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A))
2450 return connector_status_connected;
2452 if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
2453 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A))
2454 return connector_status_connected; /* CTV */
2455 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A))
2456 return connector_status_connected; /* STV */
2458 return connector_status_disconnected;
2462 radeon_atom_ext_encoder_setup_ddc(struct drm_encoder *encoder)
2464 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
2467 /* ddc_setup on the dp bridge */
2468 atombios_external_encoder_setup(encoder, ext_encoder,
2469 EXTERNAL_ENCODER_ACTION_V3_DDC_SETUP);
2473 static void radeon_atom_encoder_prepare(struct drm_encoder *encoder)
2475 struct radeon_device *rdev = encoder->dev->dev_private;
2476 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2477 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
2479 if ((radeon_encoder->active_device &
2480 (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
2481 (radeon_encoder_get_dp_bridge_encoder_id(encoder) !=
2482 ENCODER_OBJECT_ID_NONE)) {
2483 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
2485 if (dig->dig_encoder >= 0)
2486 radeon_atom_release_dig_encoder(rdev, dig->dig_encoder);
2487 dig->dig_encoder = radeon_atom_pick_dig_encoder(encoder, -1);
2488 if (radeon_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT) {
2489 if (rdev->family >= CHIP_R600)
2490 dig->afmt = rdev->mode_info.afmt[dig->dig_encoder];
2492 /* RS600/690/740 have only 1 afmt block */
2493 dig->afmt = rdev->mode_info.afmt[0];
2498 radeon_atom_output_lock(encoder, true);
2501 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2503 /* select the clock/data port if it uses a router */
2504 if (radeon_connector->router.cd_valid)
2505 radeon_router_select_cd_port(radeon_connector);
2507 /* turn eDP panel on for mode set */
2508 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
2509 atombios_set_edp_panel_power(connector,
2510 ATOM_TRANSMITTER_ACTION_POWER_ON);
2513 /* this is needed for the pll/ss setup to work correctly in some cases */
2514 atombios_set_encoder_crtc_source(encoder);
2515 /* set up the FMT blocks */
2516 if (ASIC_IS_DCE8(rdev))
2517 dce8_program_fmt(encoder);
2518 else if (ASIC_IS_DCE4(rdev))
2519 dce4_program_fmt(encoder);
2520 else if (ASIC_IS_DCE3(rdev))
2521 dce3_program_fmt(encoder);
2522 else if (ASIC_IS_AVIVO(rdev))
2523 avivo_program_fmt(encoder);
2526 static void radeon_atom_encoder_commit(struct drm_encoder *encoder)
2528 /* need to call this here as we need the crtc set up */
2529 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
2530 radeon_atom_output_lock(encoder, false);
2533 static void radeon_atom_encoder_disable(struct drm_encoder *encoder)
2535 struct drm_device *dev = encoder->dev;
2536 struct radeon_device *rdev = dev->dev_private;
2537 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2538 struct radeon_encoder_atom_dig *dig;
2540 /* check for pre-DCE3 cards with shared encoders;
2541 * can't really use the links individually, so don't disable
2542 * the encoder if it's in use by another connector
2544 if (!ASIC_IS_DCE3(rdev)) {
2545 struct drm_encoder *other_encoder;
2546 struct radeon_encoder *other_radeon_encoder;
2548 list_for_each_entry(other_encoder, &dev->mode_config.encoder_list, head) {
2549 other_radeon_encoder = to_radeon_encoder(other_encoder);
2550 if ((radeon_encoder->encoder_id == other_radeon_encoder->encoder_id) &&
2551 drm_helper_encoder_in_use(other_encoder))
2556 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
2558 switch (radeon_encoder->encoder_id) {
2559 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
2560 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
2561 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
2562 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
2563 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_DISABLE);
2565 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2566 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2567 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2568 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2569 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2570 /* handled in dpms */
2572 case ENCODER_OBJECT_ID_INTERNAL_DDI:
2573 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
2574 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
2575 atombios_dvo_setup(encoder, ATOM_DISABLE);
2577 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
2578 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
2579 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
2580 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
2581 atombios_dac_setup(encoder, ATOM_DISABLE);
2582 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
2583 atombios_tv_setup(encoder, ATOM_DISABLE);
2588 if (radeon_encoder_is_digital(encoder)) {
2589 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
2590 if (rdev->asic->display.hdmi_enable)
2591 radeon_hdmi_enable(rdev, encoder, false);
2593 if (atombios_get_encoder_mode(encoder) != ATOM_ENCODER_MODE_DP_MST) {
2594 dig = radeon_encoder->enc_priv;
2595 radeon_atom_release_dig_encoder(rdev, dig->dig_encoder);
2596 dig->dig_encoder = -1;
2597 radeon_encoder->active_device = 0;
2600 radeon_encoder->active_device = 0;
2603 /* these are handled by the primary encoders */
2604 static void radeon_atom_ext_prepare(struct drm_encoder *encoder)
2609 static void radeon_atom_ext_commit(struct drm_encoder *encoder)
2615 radeon_atom_ext_mode_set(struct drm_encoder *encoder,
2616 struct drm_display_mode *mode,
2617 struct drm_display_mode *adjusted_mode)
2622 static void radeon_atom_ext_disable(struct drm_encoder *encoder)
2628 radeon_atom_ext_dpms(struct drm_encoder *encoder, int mode)
2633 static const struct drm_encoder_helper_funcs radeon_atom_ext_helper_funcs = {
2634 .dpms = radeon_atom_ext_dpms,
2635 .prepare = radeon_atom_ext_prepare,
2636 .mode_set = radeon_atom_ext_mode_set,
2637 .commit = radeon_atom_ext_commit,
2638 .disable = radeon_atom_ext_disable,
2639 /* no detect for TMDS/LVDS yet */
2642 static const struct drm_encoder_helper_funcs radeon_atom_dig_helper_funcs = {
2643 .dpms = radeon_atom_encoder_dpms,
2644 .mode_fixup = radeon_atom_mode_fixup,
2645 .prepare = radeon_atom_encoder_prepare,
2646 .mode_set = radeon_atom_encoder_mode_set,
2647 .commit = radeon_atom_encoder_commit,
2648 .disable = radeon_atom_encoder_disable,
2649 .detect = radeon_atom_dig_detect,
2652 static const struct drm_encoder_helper_funcs radeon_atom_dac_helper_funcs = {
2653 .dpms = radeon_atom_encoder_dpms,
2654 .mode_fixup = radeon_atom_mode_fixup,
2655 .prepare = radeon_atom_encoder_prepare,
2656 .mode_set = radeon_atom_encoder_mode_set,
2657 .commit = radeon_atom_encoder_commit,
2658 .detect = radeon_atom_dac_detect,
2661 void radeon_enc_destroy(struct drm_encoder *encoder)
2663 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2664 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
2665 radeon_atom_backlight_exit(radeon_encoder);
2666 kfree(radeon_encoder->enc_priv);
2667 drm_encoder_cleanup(encoder);
2668 kfree(radeon_encoder);
2671 static const struct drm_encoder_funcs radeon_atom_enc_funcs = {
2672 .destroy = radeon_enc_destroy,
2675 static struct radeon_encoder_atom_dac *
2676 radeon_atombios_set_dac_info(struct radeon_encoder *radeon_encoder)
2678 struct drm_device *dev = radeon_encoder->base.dev;
2679 struct radeon_device *rdev = dev->dev_private;
2680 struct radeon_encoder_atom_dac *dac = kzalloc(sizeof(struct radeon_encoder_atom_dac), GFP_KERNEL);
2685 dac->tv_std = radeon_atombios_get_tv_info(rdev);
2689 static struct radeon_encoder_atom_dig *
2690 radeon_atombios_set_dig_info(struct radeon_encoder *radeon_encoder)
2692 int encoder_enum = (radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
2693 struct radeon_encoder_atom_dig *dig = kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
2698 /* coherent mode by default */
2699 dig->coherent_mode = true;
2700 dig->dig_encoder = -1;
2702 if (encoder_enum == 2)
2711 radeon_add_atom_encoder(struct drm_device *dev,
2712 uint32_t encoder_enum,
2713 uint32_t supported_device,
2716 struct radeon_device *rdev = dev->dev_private;
2717 struct drm_encoder *encoder;
2718 struct radeon_encoder *radeon_encoder;
2720 /* see if we already added it */
2721 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2722 radeon_encoder = to_radeon_encoder(encoder);
2723 if (radeon_encoder->encoder_enum == encoder_enum) {
2724 radeon_encoder->devices |= supported_device;
2731 radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL);
2732 if (!radeon_encoder)
2735 encoder = &radeon_encoder->base;
2736 switch (rdev->num_crtc) {
2738 encoder->possible_crtcs = 0x1;
2742 encoder->possible_crtcs = 0x3;
2745 encoder->possible_crtcs = 0xf;
2748 encoder->possible_crtcs = 0x3f;
2752 radeon_encoder->enc_priv = NULL;
2754 radeon_encoder->encoder_enum = encoder_enum;
2755 radeon_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
2756 radeon_encoder->devices = supported_device;
2757 radeon_encoder->rmx_type = RMX_OFF;
2758 radeon_encoder->underscan_type = UNDERSCAN_OFF;
2759 radeon_encoder->is_ext_encoder = false;
2760 radeon_encoder->caps = caps;
2762 switch (radeon_encoder->encoder_id) {
2763 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
2764 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
2765 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
2766 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
2767 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
2768 radeon_encoder->rmx_type = RMX_FULL;
2769 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs,
2770 DRM_MODE_ENCODER_LVDS, NULL);
2771 radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
2773 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs,
2774 DRM_MODE_ENCODER_TMDS, NULL);
2775 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2777 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
2779 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
2780 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs,
2781 DRM_MODE_ENCODER_DAC, NULL);
2782 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
2783 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
2785 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
2786 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
2787 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
2788 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs,
2789 DRM_MODE_ENCODER_TVDAC, NULL);
2790 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
2791 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
2793 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
2794 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
2795 case ENCODER_OBJECT_ID_INTERNAL_DDI:
2796 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2797 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2798 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2799 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2800 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2801 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
2802 radeon_encoder->rmx_type = RMX_FULL;
2803 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs,
2804 DRM_MODE_ENCODER_LVDS, NULL);
2805 radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
2806 } else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
2807 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs,
2808 DRM_MODE_ENCODER_DAC, NULL);
2809 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2811 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs,
2812 DRM_MODE_ENCODER_TMDS, NULL);
2813 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2815 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
2817 case ENCODER_OBJECT_ID_SI170B:
2818 case ENCODER_OBJECT_ID_CH7303:
2819 case ENCODER_OBJECT_ID_EXTERNAL_SDVOA:
2820 case ENCODER_OBJECT_ID_EXTERNAL_SDVOB:
2821 case ENCODER_OBJECT_ID_TITFP513:
2822 case ENCODER_OBJECT_ID_VT1623:
2823 case ENCODER_OBJECT_ID_HDMI_SI1930:
2824 case ENCODER_OBJECT_ID_TRAVIS:
2825 case ENCODER_OBJECT_ID_NUTMEG:
2826 /* these are handled by the primary encoders */
2827 radeon_encoder->is_ext_encoder = true;
2828 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
2829 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs,
2830 DRM_MODE_ENCODER_LVDS, NULL);
2831 else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT))
2832 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs,
2833 DRM_MODE_ENCODER_DAC, NULL);
2835 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs,
2836 DRM_MODE_ENCODER_TMDS, NULL);
2837 drm_encoder_helper_add(encoder, &radeon_atom_ext_helper_funcs);