2 * Copyright 2007-11 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
23 * Authors: Dave Airlie
27 #include <drm/drm_crtc_helper.h>
28 #include <drm/radeon_drm.h>
30 #include "radeon_audio.h"
32 #include <linux/backlight.h>
34 extern int atom_debug;
37 radeon_atom_get_backlight_level_from_reg(struct radeon_device *rdev)
42 if (rdev->family >= CHIP_R600)
43 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
45 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
47 backlight_level = ((bios_2_scratch & ATOM_S2_CURRENT_BL_LEVEL_MASK) >>
48 ATOM_S2_CURRENT_BL_LEVEL_SHIFT);
50 return backlight_level;
54 radeon_atom_set_backlight_level_to_reg(struct radeon_device *rdev,
59 if (rdev->family >= CHIP_R600)
60 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
62 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
64 bios_2_scratch &= ~ATOM_S2_CURRENT_BL_LEVEL_MASK;
65 bios_2_scratch |= ((backlight_level << ATOM_S2_CURRENT_BL_LEVEL_SHIFT) &
66 ATOM_S2_CURRENT_BL_LEVEL_MASK);
68 if (rdev->family >= CHIP_R600)
69 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
71 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
75 atombios_get_backlight_level(struct radeon_encoder *radeon_encoder)
77 struct drm_device *dev = radeon_encoder->base.dev;
78 struct radeon_device *rdev = dev->dev_private;
80 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU))
83 return radeon_atom_get_backlight_level_from_reg(rdev);
87 atombios_set_backlight_level(struct radeon_encoder *radeon_encoder, u8 level)
89 struct drm_encoder *encoder = &radeon_encoder->base;
90 struct drm_device *dev = radeon_encoder->base.dev;
91 struct radeon_device *rdev = dev->dev_private;
92 struct radeon_encoder_atom_dig *dig;
93 DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args;
96 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU))
99 if ((radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) &&
100 radeon_encoder->enc_priv) {
101 dig = radeon_encoder->enc_priv;
102 dig->backlight_level = level;
103 radeon_atom_set_backlight_level_to_reg(rdev, dig->backlight_level);
105 switch (radeon_encoder->encoder_id) {
106 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
107 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
108 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
109 if (dig->backlight_level == 0) {
110 args.ucAction = ATOM_LCD_BLOFF;
111 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
113 args.ucAction = ATOM_LCD_BL_BRIGHTNESS_CONTROL;
114 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
115 args.ucAction = ATOM_LCD_BLON;
116 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
119 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
120 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
121 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
122 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
123 if (dig->backlight_level == 0)
124 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0);
126 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_BL_BRIGHTNESS_CONTROL, 0, 0);
127 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLON, 0, 0);
136 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
138 static u8 radeon_atom_bl_level(struct backlight_device *bd)
142 /* Convert brightness to hardware level */
143 if (bd->props.brightness < 0)
145 else if (bd->props.brightness > RADEON_MAX_BL_LEVEL)
146 level = RADEON_MAX_BL_LEVEL;
148 level = bd->props.brightness;
153 static int radeon_atom_backlight_update_status(struct backlight_device *bd)
155 struct radeon_backlight_privdata *pdata = bl_get_data(bd);
156 struct radeon_encoder *radeon_encoder = pdata->encoder;
158 atombios_set_backlight_level(radeon_encoder, radeon_atom_bl_level(bd));
163 static int radeon_atom_backlight_get_brightness(struct backlight_device *bd)
165 struct radeon_backlight_privdata *pdata = bl_get_data(bd);
166 struct radeon_encoder *radeon_encoder = pdata->encoder;
167 struct drm_device *dev = radeon_encoder->base.dev;
168 struct radeon_device *rdev = dev->dev_private;
170 return radeon_atom_get_backlight_level_from_reg(rdev);
173 static const struct backlight_ops radeon_atom_backlight_ops = {
174 .get_brightness = radeon_atom_backlight_get_brightness,
175 .update_status = radeon_atom_backlight_update_status,
178 void radeon_atom_backlight_init(struct radeon_encoder *radeon_encoder,
179 struct drm_connector *drm_connector)
181 struct drm_device *dev = radeon_encoder->base.dev;
182 struct radeon_device *rdev = dev->dev_private;
183 struct backlight_device *bd;
184 struct backlight_properties props;
185 struct radeon_backlight_privdata *pdata;
186 struct radeon_encoder_atom_dig *dig;
189 /* Mac laptops with multiple GPUs use the gmux driver for backlight
190 * so don't register a backlight device
192 if ((rdev->pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE) &&
193 (rdev->pdev->device == 0x6741))
196 if (!radeon_encoder->enc_priv)
199 if (!rdev->is_atom_bios)
202 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU))
205 pdata = kmalloc(sizeof(struct radeon_backlight_privdata), GFP_KERNEL);
207 DRM_ERROR("Memory allocation failed\n");
211 memset(&props, 0, sizeof(props));
212 props.max_brightness = RADEON_MAX_BL_LEVEL;
213 props.type = BACKLIGHT_RAW;
214 snprintf(bl_name, sizeof(bl_name),
215 "radeon_bl%d", dev->primary->index);
216 bd = backlight_device_register(bl_name, drm_connector->kdev,
217 pdata, &radeon_atom_backlight_ops, &props);
219 DRM_ERROR("Backlight registration failed\n");
223 pdata->encoder = radeon_encoder;
225 dig = radeon_encoder->enc_priv;
228 bd->props.brightness = radeon_atom_backlight_get_brightness(bd);
229 /* Set a reasonable default here if the level is 0 otherwise
230 * fbdev will attempt to turn the backlight on after console
231 * unblanking and it will try and restore 0 which turns the backlight
234 if (bd->props.brightness == 0)
235 bd->props.brightness = RADEON_MAX_BL_LEVEL;
236 bd->props.power = FB_BLANK_UNBLANK;
237 backlight_update_status(bd);
239 DRM_INFO("radeon atom DIG backlight initialized\n");
248 static void radeon_atom_backlight_exit(struct radeon_encoder *radeon_encoder)
250 struct drm_device *dev = radeon_encoder->base.dev;
251 struct radeon_device *rdev = dev->dev_private;
252 struct backlight_device *bd = NULL;
253 struct radeon_encoder_atom_dig *dig;
255 if (!radeon_encoder->enc_priv)
258 if (!rdev->is_atom_bios)
261 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU))
264 dig = radeon_encoder->enc_priv;
269 struct radeon_legacy_backlight_privdata *pdata;
271 pdata = bl_get_data(bd);
272 backlight_device_unregister(bd);
275 DRM_INFO("radeon atom LVDS backlight unloaded\n");
279 #else /* !CONFIG_BACKLIGHT_CLASS_DEVICE */
281 void radeon_atom_backlight_init(struct radeon_encoder *encoder)
285 static void radeon_atom_backlight_exit(struct radeon_encoder *encoder)
291 /* evil but including atombios.h is much worse */
292 bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
293 struct drm_display_mode *mode);
295 static bool radeon_atom_mode_fixup(struct drm_encoder *encoder,
296 const struct drm_display_mode *mode,
297 struct drm_display_mode *adjusted_mode)
299 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
300 struct drm_device *dev = encoder->dev;
301 struct radeon_device *rdev = dev->dev_private;
303 /* set the active encoder to connector routing */
304 radeon_encoder_set_active_device(encoder);
305 drm_mode_set_crtcinfo(adjusted_mode, 0);
308 if ((mode->flags & DRM_MODE_FLAG_INTERLACE)
309 && (mode->crtc_vsync_start < (mode->crtc_vdisplay + 2)))
310 adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + 2;
312 /* get the native mode for scaling */
313 if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT)) {
314 radeon_panel_mode_fixup(encoder, adjusted_mode);
315 } else if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) {
316 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv;
318 if (tv_dac->tv_std == TV_STD_NTSC ||
319 tv_dac->tv_std == TV_STD_NTSC_J ||
320 tv_dac->tv_std == TV_STD_PAL_M)
321 radeon_atom_get_tv_timings(rdev, 0, adjusted_mode);
323 radeon_atom_get_tv_timings(rdev, 1, adjusted_mode);
325 } else if (radeon_encoder->rmx_type != RMX_OFF) {
326 radeon_panel_mode_fixup(encoder, adjusted_mode);
329 if (ASIC_IS_DCE3(rdev) &&
330 ((radeon_encoder->active_device & (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
331 (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE))) {
332 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
333 radeon_dp_set_link_config(connector, adjusted_mode);
340 atombios_dac_setup(struct drm_encoder *encoder, int action)
342 struct drm_device *dev = encoder->dev;
343 struct radeon_device *rdev = dev->dev_private;
344 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
345 DAC_ENCODER_CONTROL_PS_ALLOCATION args;
347 struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
349 memset(&args, 0, sizeof(args));
351 switch (radeon_encoder->encoder_id) {
352 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
353 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
354 index = GetIndexIntoMasterTable(COMMAND, DAC1EncoderControl);
356 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
357 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
358 index = GetIndexIntoMasterTable(COMMAND, DAC2EncoderControl);
362 args.ucAction = action;
364 if (radeon_encoder->active_device & (ATOM_DEVICE_CRT_SUPPORT))
365 args.ucDacStandard = ATOM_DAC1_PS2;
366 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
367 args.ucDacStandard = ATOM_DAC1_CV;
369 switch (dac_info->tv_std) {
372 case TV_STD_SCART_PAL:
375 args.ucDacStandard = ATOM_DAC1_PAL;
381 args.ucDacStandard = ATOM_DAC1_NTSC;
385 args.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
387 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
392 atombios_tv_setup(struct drm_encoder *encoder, int action)
394 struct drm_device *dev = encoder->dev;
395 struct radeon_device *rdev = dev->dev_private;
396 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
397 TV_ENCODER_CONTROL_PS_ALLOCATION args;
399 struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
401 memset(&args, 0, sizeof(args));
403 index = GetIndexIntoMasterTable(COMMAND, TVEncoderControl);
405 args.sTVEncoder.ucAction = action;
407 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
408 args.sTVEncoder.ucTvStandard = ATOM_TV_CV;
410 switch (dac_info->tv_std) {
412 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
415 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL;
418 args.sTVEncoder.ucTvStandard = ATOM_TV_PALM;
421 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL60;
424 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSCJ;
426 case TV_STD_SCART_PAL:
427 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL; /* ??? */
430 args.sTVEncoder.ucTvStandard = ATOM_TV_SECAM;
433 args.sTVEncoder.ucTvStandard = ATOM_TV_PALCN;
436 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
441 args.sTVEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
443 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
447 static u8 radeon_atom_get_bpc(struct drm_encoder *encoder)
452 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
453 bpc = radeon_crtc->bpc;
458 return PANEL_BPC_UNDEFINE;
460 return PANEL_6BIT_PER_COLOR;
463 return PANEL_8BIT_PER_COLOR;
465 return PANEL_10BIT_PER_COLOR;
467 return PANEL_12BIT_PER_COLOR;
469 return PANEL_16BIT_PER_COLOR;
473 union dvo_encoder_control {
474 ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION ext_tmds;
475 DVO_ENCODER_CONTROL_PS_ALLOCATION dvo;
476 DVO_ENCODER_CONTROL_PS_ALLOCATION_V3 dvo_v3;
477 DVO_ENCODER_CONTROL_PS_ALLOCATION_V1_4 dvo_v4;
481 atombios_dvo_setup(struct drm_encoder *encoder, int action)
483 struct drm_device *dev = encoder->dev;
484 struct radeon_device *rdev = dev->dev_private;
485 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
486 union dvo_encoder_control args;
487 int index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl);
490 memset(&args, 0, sizeof(args));
492 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
495 /* some R4xx chips have the wrong frev */
496 if (rdev->family <= CHIP_RV410)
504 args.ext_tmds.sXTmdsEncoder.ucEnable = action;
506 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
507 args.ext_tmds.sXTmdsEncoder.ucMisc |= PANEL_ENCODER_MISC_DUAL;
509 args.ext_tmds.sXTmdsEncoder.ucMisc |= ATOM_PANEL_MISC_888RGB;
513 args.dvo.sDVOEncoder.ucAction = action;
514 args.dvo.sDVOEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
515 /* DFP1, CRT1, TV1 depending on the type of port */
516 args.dvo.sDVOEncoder.ucDeviceType = ATOM_DEVICE_DFP1_INDEX;
518 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
519 args.dvo.sDVOEncoder.usDevAttr.sDigAttrib.ucAttribute |= PANEL_ENCODER_MISC_DUAL;
523 args.dvo_v3.ucAction = action;
524 args.dvo_v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
525 args.dvo_v3.ucDVOConfig = 0; /* XXX */
529 args.dvo_v4.ucAction = action;
530 args.dvo_v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
531 args.dvo_v4.ucDVOConfig = 0; /* XXX */
532 args.dvo_v4.ucBitPerColor = radeon_atom_get_bpc(encoder);
535 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
540 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
544 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
547 union lvds_encoder_control {
548 LVDS_ENCODER_CONTROL_PS_ALLOCATION v1;
549 LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 v2;
553 atombios_digital_setup(struct drm_encoder *encoder, int action)
555 struct drm_device *dev = encoder->dev;
556 struct radeon_device *rdev = dev->dev_private;
557 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
558 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
559 union lvds_encoder_control args;
561 int hdmi_detected = 0;
567 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
570 memset(&args, 0, sizeof(args));
572 switch (radeon_encoder->encoder_id) {
573 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
574 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
576 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
577 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
578 index = GetIndexIntoMasterTable(COMMAND, TMDS1EncoderControl);
580 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
581 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
582 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
584 index = GetIndexIntoMasterTable(COMMAND, TMDS2EncoderControl);
588 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
597 args.v1.ucAction = action;
599 args.v1.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
600 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
601 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
602 if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL)
603 args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
604 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
605 args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB;
608 args.v1.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
609 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
610 args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
611 /*if (pScrn->rgbBits == 8) */
612 args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB;
618 args.v2.ucAction = action;
620 if (dig->coherent_mode)
621 args.v2.ucMisc |= PANEL_ENCODER_MISC_COHERENT;
624 args.v2.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
625 args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
626 args.v2.ucTruncate = 0;
627 args.v2.ucSpatial = 0;
628 args.v2.ucTemporal = 0;
630 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
631 if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL)
632 args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
633 if (dig->lcd_misc & ATOM_PANEL_MISC_SPATIAL) {
634 args.v2.ucSpatial = PANEL_ENCODER_SPATIAL_DITHER_EN;
635 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
636 args.v2.ucSpatial |= PANEL_ENCODER_SPATIAL_DITHER_DEPTH;
638 if (dig->lcd_misc & ATOM_PANEL_MISC_TEMPORAL) {
639 args.v2.ucTemporal = PANEL_ENCODER_TEMPORAL_DITHER_EN;
640 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
641 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_DITHER_DEPTH;
642 if (((dig->lcd_misc >> ATOM_PANEL_MISC_GREY_LEVEL_SHIFT) & 0x3) == 2)
643 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_LEVEL_4;
647 args.v2.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
648 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
649 args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
653 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
658 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
662 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
666 atombios_get_encoder_mode(struct drm_encoder *encoder)
668 struct drm_device *dev = encoder->dev;
669 struct radeon_device *rdev = dev->dev_private;
670 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
671 struct drm_connector *connector;
672 struct radeon_connector *radeon_connector;
673 struct radeon_connector_atom_dig *dig_connector;
674 struct radeon_encoder_atom_dig *dig_enc;
676 if (radeon_encoder_is_digital(encoder)) {
677 dig_enc = radeon_encoder->enc_priv;
678 if (dig_enc->active_mst_links)
679 return ATOM_ENCODER_MODE_DP_MST;
681 if (radeon_encoder->is_mst_encoder || radeon_encoder->offset)
682 return ATOM_ENCODER_MODE_DP_MST;
683 /* dp bridges are always DP */
684 if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE)
685 return ATOM_ENCODER_MODE_DP;
687 /* DVO is always DVO */
688 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DVO1) ||
689 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1))
690 return ATOM_ENCODER_MODE_DVO;
692 connector = radeon_get_connector_for_encoder(encoder);
693 /* if we don't have an active device yet, just use one of
694 * the connectors tied to the encoder.
697 connector = radeon_get_connector_for_encoder_init(encoder);
698 radeon_connector = to_radeon_connector(connector);
700 switch (connector->connector_type) {
701 case DRM_MODE_CONNECTOR_DVII:
702 case DRM_MODE_CONNECTOR_HDMIB: /* HDMI-B is basically DL-DVI; analog works fine */
703 if (radeon_audio != 0) {
704 if (radeon_connector->use_digital &&
705 (radeon_connector->audio == RADEON_AUDIO_ENABLE))
706 return ATOM_ENCODER_MODE_HDMI;
707 else if (drm_detect_hdmi_monitor(radeon_connector_edid(connector)) &&
708 (radeon_connector->audio == RADEON_AUDIO_AUTO))
709 return ATOM_ENCODER_MODE_HDMI;
710 else if (radeon_connector->use_digital)
711 return ATOM_ENCODER_MODE_DVI;
713 return ATOM_ENCODER_MODE_CRT;
714 } else if (radeon_connector->use_digital) {
715 return ATOM_ENCODER_MODE_DVI;
717 return ATOM_ENCODER_MODE_CRT;
720 case DRM_MODE_CONNECTOR_DVID:
721 case DRM_MODE_CONNECTOR_HDMIA:
723 if (radeon_audio != 0) {
724 if (radeon_connector->audio == RADEON_AUDIO_ENABLE)
725 return ATOM_ENCODER_MODE_HDMI;
726 else if (drm_detect_hdmi_monitor(radeon_connector_edid(connector)) &&
727 (radeon_connector->audio == RADEON_AUDIO_AUTO))
728 return ATOM_ENCODER_MODE_HDMI;
730 return ATOM_ENCODER_MODE_DVI;
732 return ATOM_ENCODER_MODE_DVI;
735 case DRM_MODE_CONNECTOR_LVDS:
736 return ATOM_ENCODER_MODE_LVDS;
738 case DRM_MODE_CONNECTOR_DisplayPort:
739 dig_connector = radeon_connector->con_priv;
740 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
741 (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) {
742 if (radeon_audio != 0 &&
743 drm_detect_monitor_audio(radeon_connector_edid(connector)) &&
744 ASIC_IS_DCE4(rdev) && !ASIC_IS_DCE5(rdev))
745 return ATOM_ENCODER_MODE_DP_AUDIO;
746 return ATOM_ENCODER_MODE_DP;
747 } else if (radeon_audio != 0) {
748 if (radeon_connector->audio == RADEON_AUDIO_ENABLE)
749 return ATOM_ENCODER_MODE_HDMI;
750 else if (drm_detect_hdmi_monitor(radeon_connector_edid(connector)) &&
751 (radeon_connector->audio == RADEON_AUDIO_AUTO))
752 return ATOM_ENCODER_MODE_HDMI;
754 return ATOM_ENCODER_MODE_DVI;
756 return ATOM_ENCODER_MODE_DVI;
759 case DRM_MODE_CONNECTOR_eDP:
760 if (radeon_audio != 0 &&
761 drm_detect_monitor_audio(radeon_connector_edid(connector)) &&
762 ASIC_IS_DCE4(rdev) && !ASIC_IS_DCE5(rdev))
763 return ATOM_ENCODER_MODE_DP_AUDIO;
764 return ATOM_ENCODER_MODE_DP;
765 case DRM_MODE_CONNECTOR_DVIA:
766 case DRM_MODE_CONNECTOR_VGA:
767 return ATOM_ENCODER_MODE_CRT;
769 case DRM_MODE_CONNECTOR_Composite:
770 case DRM_MODE_CONNECTOR_SVIDEO:
771 case DRM_MODE_CONNECTOR_9PinDIN:
773 return ATOM_ENCODER_MODE_TV;
774 /*return ATOM_ENCODER_MODE_CV;*/
780 * DIG Encoder/Transmitter Setup
783 * - 2 DIG transmitter blocks. UNIPHY (links A and B) and LVTMA.
784 * Supports up to 3 digital outputs
785 * - 2 DIG encoder blocks.
786 * DIG1 can drive UNIPHY link A or link B
787 * DIG2 can drive UNIPHY link B or LVTMA
790 * - 3 DIG transmitter blocks. UNIPHY0/1/2 (links A and B).
791 * Supports up to 5 digital outputs
792 * - 2 DIG encoder blocks.
793 * DIG1/2 can drive UNIPHY0/1/2 link A or link B
796 * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B).
797 * Supports up to 6 digital outputs
798 * - 6 DIG encoder blocks.
799 * - DIG to PHY mapping is hardcoded
800 * DIG1 drives UNIPHY0 link A, A+B
801 * DIG2 drives UNIPHY0 link B
802 * DIG3 drives UNIPHY1 link A, A+B
803 * DIG4 drives UNIPHY1 link B
804 * DIG5 drives UNIPHY2 link A, A+B
805 * DIG6 drives UNIPHY2 link B
808 * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B).
809 * Supports up to 6 digital outputs
810 * - 2 DIG encoder blocks.
812 * DIG1/2 can drive UNIPHY0/1/2 link A or link B
814 * DIG1 drives UNIPHY0/1/2 link A
815 * DIG2 drives UNIPHY0/1/2 link B
818 * crtc -> dig encoder -> UNIPHY/LVTMA (1 or 2 links)
820 * crtc0 -> dig2 -> LVTMA links A+B -> TMDS/HDMI
821 * crtc1 -> dig1 -> UNIPHY0 link B -> DP
822 * crtc0 -> dig1 -> UNIPHY2 link A -> LVDS
823 * crtc1 -> dig2 -> UNIPHY1 link B+A -> TMDS/HDMI
826 union dig_encoder_control {
827 DIG_ENCODER_CONTROL_PS_ALLOCATION v1;
828 DIG_ENCODER_CONTROL_PARAMETERS_V2 v2;
829 DIG_ENCODER_CONTROL_PARAMETERS_V3 v3;
830 DIG_ENCODER_CONTROL_PARAMETERS_V4 v4;
834 atombios_dig_encoder_setup2(struct drm_encoder *encoder, int action, int panel_mode, int enc_override)
836 struct drm_device *dev = encoder->dev;
837 struct radeon_device *rdev = dev->dev_private;
838 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
839 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
840 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
841 union dig_encoder_control args;
845 int dp_lane_count = 0;
846 int hpd_id = RADEON_HPD_NONE;
849 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
850 struct radeon_connector_atom_dig *dig_connector =
851 radeon_connector->con_priv;
853 dp_clock = dig_connector->dp_clock;
854 dp_lane_count = dig_connector->dp_lane_count;
855 hpd_id = radeon_connector->hpd.hpd;
858 /* no dig encoder assigned */
859 if (dig->dig_encoder == -1)
862 memset(&args, 0, sizeof(args));
864 if (ASIC_IS_DCE4(rdev))
865 index = GetIndexIntoMasterTable(COMMAND, DIGxEncoderControl);
867 if (dig->dig_encoder)
868 index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl);
870 index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl);
873 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
880 args.v1.ucAction = action;
881 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
882 if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE)
883 args.v3.ucPanelMode = panel_mode;
885 args.v1.ucEncoderMode = atombios_get_encoder_mode(encoder);
887 if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode))
888 args.v1.ucLaneNum = dp_lane_count;
889 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
890 args.v1.ucLaneNum = 8;
892 args.v1.ucLaneNum = 4;
894 if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode) && (dp_clock == 270000))
895 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
896 switch (radeon_encoder->encoder_id) {
897 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
898 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER1;
900 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
901 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
902 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER2;
904 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
905 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER3;
909 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKB;
911 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKA;
915 args.v3.ucAction = action;
916 args.v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
917 if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE)
918 args.v3.ucPanelMode = panel_mode;
920 args.v3.ucEncoderMode = atombios_get_encoder_mode(encoder);
922 if (ENCODER_MODE_IS_DP(args.v3.ucEncoderMode))
923 args.v3.ucLaneNum = dp_lane_count;
924 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
925 args.v3.ucLaneNum = 8;
927 args.v3.ucLaneNum = 4;
929 if (ENCODER_MODE_IS_DP(args.v3.ucEncoderMode) && (dp_clock == 270000))
930 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ;
931 if (enc_override != -1)
932 args.v3.acConfig.ucDigSel = enc_override;
934 args.v3.acConfig.ucDigSel = dig->dig_encoder;
935 args.v3.ucBitPerColor = radeon_atom_get_bpc(encoder);
938 args.v4.ucAction = action;
939 args.v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
940 if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE)
941 args.v4.ucPanelMode = panel_mode;
943 args.v4.ucEncoderMode = atombios_get_encoder_mode(encoder);
945 if (ENCODER_MODE_IS_DP(args.v4.ucEncoderMode))
946 args.v4.ucLaneNum = dp_lane_count;
947 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
948 args.v4.ucLaneNum = 8;
950 args.v4.ucLaneNum = 4;
952 if (ENCODER_MODE_IS_DP(args.v4.ucEncoderMode)) {
953 if (dp_clock == 540000)
954 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_5_40GHZ;
955 else if (dp_clock == 324000)
956 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_3_24GHZ;
957 else if (dp_clock == 270000)
958 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_2_70GHZ;
960 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_1_62GHZ;
963 if (enc_override != -1)
964 args.v4.acConfig.ucDigSel = enc_override;
966 args.v4.acConfig.ucDigSel = dig->dig_encoder;
967 args.v4.ucBitPerColor = radeon_atom_get_bpc(encoder);
968 if (hpd_id == RADEON_HPD_NONE)
969 args.v4.ucHPD_ID = 0;
971 args.v4.ucHPD_ID = hpd_id + 1;
974 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
979 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
983 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
988 atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mode)
990 atombios_dig_encoder_setup2(encoder, action, panel_mode, -1);
993 union dig_transmitter_control {
994 DIG_TRANSMITTER_CONTROL_PS_ALLOCATION v1;
995 DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 v2;
996 DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 v3;
997 DIG_TRANSMITTER_CONTROL_PARAMETERS_V4 v4;
998 DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5 v5;
1002 atombios_dig_transmitter_setup2(struct drm_encoder *encoder, int action, uint8_t lane_num, uint8_t lane_set, int fe)
1004 struct drm_device *dev = encoder->dev;
1005 struct radeon_device *rdev = dev->dev_private;
1006 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1007 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
1008 struct drm_connector *connector;
1009 union dig_transmitter_control args;
1015 int dp_lane_count = 0;
1016 int connector_object_id = 0;
1017 int igp_lane_info = 0;
1018 int dig_encoder = dig->dig_encoder;
1019 int hpd_id = RADEON_HPD_NONE;
1021 if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1022 connector = radeon_get_connector_for_encoder_init(encoder);
1023 /* just needed to avoid bailing in the encoder check. the encoder
1024 * isn't used for init
1028 connector = radeon_get_connector_for_encoder(encoder);
1031 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1032 struct radeon_connector_atom_dig *dig_connector =
1033 radeon_connector->con_priv;
1035 hpd_id = radeon_connector->hpd.hpd;
1036 dp_clock = dig_connector->dp_clock;
1037 dp_lane_count = dig_connector->dp_lane_count;
1038 connector_object_id =
1039 (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
1040 igp_lane_info = dig_connector->igp_lane_info;
1043 if (encoder->crtc) {
1044 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1045 pll_id = radeon_crtc->pll_id;
1048 /* no dig encoder assigned */
1049 if (dig_encoder == -1)
1052 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)))
1055 memset(&args, 0, sizeof(args));
1057 switch (radeon_encoder->encoder_id) {
1058 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1059 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
1061 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1062 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1063 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1064 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
1065 index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
1067 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1068 index = GetIndexIntoMasterTable(COMMAND, LVTMATransmitterControl);
1072 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1079 args.v1.ucAction = action;
1080 if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1081 args.v1.usInitInfo = cpu_to_le16(connector_object_id);
1082 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
1083 args.v1.asMode.ucLaneSel = lane_num;
1084 args.v1.asMode.ucLaneSet = lane_set;
1087 args.v1.usPixelClock = cpu_to_le16(dp_clock / 10);
1088 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1089 args.v1.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
1091 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1094 args.v1.ucConfig = ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL;
1097 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER;
1099 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER;
1101 if ((rdev->flags & RADEON_IS_IGP) &&
1102 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY)) {
1104 !radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) {
1105 if (igp_lane_info & 0x1)
1106 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_3;
1107 else if (igp_lane_info & 0x2)
1108 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_4_7;
1109 else if (igp_lane_info & 0x4)
1110 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_11;
1111 else if (igp_lane_info & 0x8)
1112 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_12_15;
1114 if (igp_lane_info & 0x3)
1115 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_7;
1116 else if (igp_lane_info & 0xc)
1117 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_15;
1122 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKB;
1124 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA;
1127 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
1128 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1129 if (dig->coherent_mode)
1130 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
1131 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1132 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_8LANE_LINK;
1136 args.v2.ucAction = action;
1137 if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1138 args.v2.usInitInfo = cpu_to_le16(connector_object_id);
1139 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
1140 args.v2.asMode.ucLaneSel = lane_num;
1141 args.v2.asMode.ucLaneSet = lane_set;
1144 args.v2.usPixelClock = cpu_to_le16(dp_clock / 10);
1145 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1146 args.v2.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
1148 args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1151 args.v2.acConfig.ucEncoderSel = dig_encoder;
1153 args.v2.acConfig.ucLinkSel = 1;
1155 switch (radeon_encoder->encoder_id) {
1156 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1157 args.v2.acConfig.ucTransmitterSel = 0;
1159 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1160 args.v2.acConfig.ucTransmitterSel = 1;
1162 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1163 args.v2.acConfig.ucTransmitterSel = 2;
1168 args.v2.acConfig.fCoherentMode = 1;
1169 args.v2.acConfig.fDPConnector = 1;
1170 } else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1171 if (dig->coherent_mode)
1172 args.v2.acConfig.fCoherentMode = 1;
1173 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1174 args.v2.acConfig.fDualLinkConnector = 1;
1178 args.v3.ucAction = action;
1179 if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1180 args.v3.usInitInfo = cpu_to_le16(connector_object_id);
1181 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
1182 args.v3.asMode.ucLaneSel = lane_num;
1183 args.v3.asMode.ucLaneSet = lane_set;
1186 args.v3.usPixelClock = cpu_to_le16(dp_clock / 10);
1187 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1188 args.v3.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
1190 args.v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1194 args.v3.ucLaneNum = dp_lane_count;
1195 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1196 args.v3.ucLaneNum = 8;
1198 args.v3.ucLaneNum = 4;
1201 args.v3.acConfig.ucLinkSel = 1;
1202 if (dig_encoder & 1)
1203 args.v3.acConfig.ucEncoderSel = 1;
1205 /* Select the PLL for the PHY
1206 * DP PHY should be clocked from external src if there is
1209 /* On DCE4, if there is an external clock, it generates the DP ref clock */
1210 if (is_dp && rdev->clock.dp_extclk)
1211 args.v3.acConfig.ucRefClkSource = 2; /* external src */
1213 args.v3.acConfig.ucRefClkSource = pll_id;
1215 switch (radeon_encoder->encoder_id) {
1216 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1217 args.v3.acConfig.ucTransmitterSel = 0;
1219 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1220 args.v3.acConfig.ucTransmitterSel = 1;
1222 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1223 args.v3.acConfig.ucTransmitterSel = 2;
1228 args.v3.acConfig.fCoherentMode = 1; /* DP requires coherent */
1229 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1230 if (dig->coherent_mode)
1231 args.v3.acConfig.fCoherentMode = 1;
1232 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1233 args.v3.acConfig.fDualLinkConnector = 1;
1237 args.v4.ucAction = action;
1238 if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1239 args.v4.usInitInfo = cpu_to_le16(connector_object_id);
1240 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
1241 args.v4.asMode.ucLaneSel = lane_num;
1242 args.v4.asMode.ucLaneSet = lane_set;
1245 args.v4.usPixelClock = cpu_to_le16(dp_clock / 10);
1246 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1247 args.v4.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
1249 args.v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1253 args.v4.ucLaneNum = dp_lane_count;
1254 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1255 args.v4.ucLaneNum = 8;
1257 args.v4.ucLaneNum = 4;
1260 args.v4.acConfig.ucLinkSel = 1;
1261 if (dig_encoder & 1)
1262 args.v4.acConfig.ucEncoderSel = 1;
1264 /* Select the PLL for the PHY
1265 * DP PHY should be clocked from external src if there is
1268 /* On DCE5 DCPLL usually generates the DP ref clock */
1270 if (rdev->clock.dp_extclk)
1271 args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_EXTCLK;
1273 args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_DCPLL;
1275 args.v4.acConfig.ucRefClkSource = pll_id;
1277 switch (radeon_encoder->encoder_id) {
1278 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1279 args.v4.acConfig.ucTransmitterSel = 0;
1281 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1282 args.v4.acConfig.ucTransmitterSel = 1;
1284 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1285 args.v4.acConfig.ucTransmitterSel = 2;
1290 args.v4.acConfig.fCoherentMode = 1; /* DP requires coherent */
1291 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1292 if (dig->coherent_mode)
1293 args.v4.acConfig.fCoherentMode = 1;
1294 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1295 args.v4.acConfig.fDualLinkConnector = 1;
1299 args.v5.ucAction = action;
1301 args.v5.usSymClock = cpu_to_le16(dp_clock / 10);
1303 args.v5.usSymClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1305 switch (radeon_encoder->encoder_id) {
1306 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1308 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYB;
1310 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYA;
1312 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1314 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYD;
1316 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYC;
1318 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1320 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYF;
1322 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYE;
1324 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
1325 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYG;
1329 args.v5.ucLaneNum = dp_lane_count;
1330 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1331 args.v5.ucLaneNum = 8;
1333 args.v5.ucLaneNum = 4;
1334 args.v5.ucConnObjId = connector_object_id;
1335 args.v5.ucDigMode = atombios_get_encoder_mode(encoder);
1337 if (is_dp && rdev->clock.dp_extclk)
1338 args.v5.asConfig.ucPhyClkSrcId = ENCODER_REFCLK_SRC_EXTCLK;
1340 args.v5.asConfig.ucPhyClkSrcId = pll_id;
1343 args.v5.asConfig.ucCoherentMode = 1; /* DP requires coherent */
1344 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1345 if (dig->coherent_mode)
1346 args.v5.asConfig.ucCoherentMode = 1;
1348 if (hpd_id == RADEON_HPD_NONE)
1349 args.v5.asConfig.ucHPDSel = 0;
1351 args.v5.asConfig.ucHPDSel = hpd_id + 1;
1352 args.v5.ucDigEncoderSel = (fe != -1) ? (1 << fe) : (1 << dig_encoder);
1353 args.v5.ucDPLaneSet = lane_set;
1356 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1361 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1365 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1369 atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t lane_num, uint8_t lane_set)
1371 atombios_dig_transmitter_setup2(encoder, action, lane_num, lane_set, -1);
1375 atombios_set_edp_panel_power(struct drm_connector *connector, int action)
1377 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1378 struct drm_device *dev = radeon_connector->base.dev;
1379 struct radeon_device *rdev = dev->dev_private;
1380 union dig_transmitter_control args;
1381 int index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
1384 if (connector->connector_type != DRM_MODE_CONNECTOR_eDP)
1387 if (!ASIC_IS_DCE4(rdev))
1390 if ((action != ATOM_TRANSMITTER_ACTION_POWER_ON) &&
1391 (action != ATOM_TRANSMITTER_ACTION_POWER_OFF))
1394 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1397 memset(&args, 0, sizeof(args));
1399 args.v1.ucAction = action;
1401 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1403 /* wait for the panel to power up */
1404 if (action == ATOM_TRANSMITTER_ACTION_POWER_ON) {
1407 for (i = 0; i < 300; i++) {
1408 if (radeon_hpd_sense(rdev, radeon_connector->hpd.hpd))
1418 union external_encoder_control {
1419 EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION v1;
1420 EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3 v3;
1424 atombios_external_encoder_setup(struct drm_encoder *encoder,
1425 struct drm_encoder *ext_encoder,
1428 struct drm_device *dev = encoder->dev;
1429 struct radeon_device *rdev = dev->dev_private;
1430 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1431 struct radeon_encoder *ext_radeon_encoder = to_radeon_encoder(ext_encoder);
1432 union external_encoder_control args;
1433 struct drm_connector *connector;
1434 int index = GetIndexIntoMasterTable(COMMAND, ExternalEncoderControl);
1437 int dp_lane_count = 0;
1438 int connector_object_id = 0;
1439 u32 ext_enum = (ext_radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
1441 if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT)
1442 connector = radeon_get_connector_for_encoder_init(encoder);
1444 connector = radeon_get_connector_for_encoder(encoder);
1447 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1448 struct radeon_connector_atom_dig *dig_connector =
1449 radeon_connector->con_priv;
1451 dp_clock = dig_connector->dp_clock;
1452 dp_lane_count = dig_connector->dp_lane_count;
1453 connector_object_id =
1454 (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
1457 memset(&args, 0, sizeof(args));
1459 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1464 /* no params on frev 1 */
1470 args.v1.sDigEncoder.ucAction = action;
1471 args.v1.sDigEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1472 args.v1.sDigEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder);
1474 if (ENCODER_MODE_IS_DP(args.v1.sDigEncoder.ucEncoderMode)) {
1475 if (dp_clock == 270000)
1476 args.v1.sDigEncoder.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
1477 args.v1.sDigEncoder.ucLaneNum = dp_lane_count;
1478 } else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1479 args.v1.sDigEncoder.ucLaneNum = 8;
1481 args.v1.sDigEncoder.ucLaneNum = 4;
1484 args.v3.sExtEncoder.ucAction = action;
1485 if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT)
1486 args.v3.sExtEncoder.usConnectorId = cpu_to_le16(connector_object_id);
1488 args.v3.sExtEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1489 args.v3.sExtEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder);
1491 if (ENCODER_MODE_IS_DP(args.v3.sExtEncoder.ucEncoderMode)) {
1492 if (dp_clock == 270000)
1493 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ;
1494 else if (dp_clock == 540000)
1495 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ;
1496 args.v3.sExtEncoder.ucLaneNum = dp_lane_count;
1497 } else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1498 args.v3.sExtEncoder.ucLaneNum = 8;
1500 args.v3.sExtEncoder.ucLaneNum = 4;
1502 case GRAPH_OBJECT_ENUM_ID1:
1503 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER1;
1505 case GRAPH_OBJECT_ENUM_ID2:
1506 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER2;
1508 case GRAPH_OBJECT_ENUM_ID3:
1509 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER3;
1512 args.v3.sExtEncoder.ucBitPerColor = radeon_atom_get_bpc(encoder);
1515 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1520 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1523 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1527 atombios_yuv_setup(struct drm_encoder *encoder, bool enable)
1529 struct drm_device *dev = encoder->dev;
1530 struct radeon_device *rdev = dev->dev_private;
1531 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1532 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1533 ENABLE_YUV_PS_ALLOCATION args;
1534 int index = GetIndexIntoMasterTable(COMMAND, EnableYUV);
1537 memset(&args, 0, sizeof(args));
1539 if (rdev->family >= CHIP_R600)
1540 reg = R600_BIOS_3_SCRATCH;
1542 reg = RADEON_BIOS_3_SCRATCH;
1544 /* XXX: fix up scratch reg handling */
1546 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1547 WREG32(reg, (ATOM_S3_TV1_ACTIVE |
1548 (radeon_crtc->crtc_id << 18)));
1549 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1550 WREG32(reg, (ATOM_S3_CV_ACTIVE | (radeon_crtc->crtc_id << 24)));
1555 args.ucEnable = ATOM_ENABLE;
1556 args.ucCRTC = radeon_crtc->crtc_id;
1558 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1564 radeon_atom_encoder_dpms_avivo(struct drm_encoder *encoder, int mode)
1566 struct drm_device *dev = encoder->dev;
1567 struct radeon_device *rdev = dev->dev_private;
1568 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1569 DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args;
1572 memset(&args, 0, sizeof(args));
1574 switch (radeon_encoder->encoder_id) {
1575 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1576 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1577 index = GetIndexIntoMasterTable(COMMAND, TMDSAOutputControl);
1579 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1580 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1581 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1582 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
1584 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1585 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
1587 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1588 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1589 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
1591 index = GetIndexIntoMasterTable(COMMAND, LVTMAOutputControl);
1593 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1594 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1595 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1596 index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
1597 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1598 index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
1600 index = GetIndexIntoMasterTable(COMMAND, DAC1OutputControl);
1602 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1603 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1604 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1605 index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
1606 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1607 index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
1609 index = GetIndexIntoMasterTable(COMMAND, DAC2OutputControl);
1616 case DRM_MODE_DPMS_ON:
1617 args.ucAction = ATOM_ENABLE;
1618 /* workaround for DVOOutputControl on some RS690 systems */
1619 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DDI) {
1620 u32 reg = RREG32(RADEON_BIOS_3_SCRATCH);
1621 WREG32(RADEON_BIOS_3_SCRATCH, reg & ~ATOM_S3_DFP2I_ACTIVE);
1622 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1623 WREG32(RADEON_BIOS_3_SCRATCH, reg);
1625 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1626 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1627 args.ucAction = ATOM_LCD_BLON;
1628 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1631 case DRM_MODE_DPMS_STANDBY:
1632 case DRM_MODE_DPMS_SUSPEND:
1633 case DRM_MODE_DPMS_OFF:
1634 args.ucAction = ATOM_DISABLE;
1635 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1636 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1637 args.ucAction = ATOM_LCD_BLOFF;
1638 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1645 radeon_atom_encoder_dpms_dig(struct drm_encoder *encoder, int mode)
1647 struct drm_device *dev = encoder->dev;
1648 struct radeon_device *rdev = dev->dev_private;
1649 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1650 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
1651 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
1652 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1653 struct radeon_connector *radeon_connector = NULL;
1654 struct radeon_connector_atom_dig *radeon_dig_connector = NULL;
1655 bool travis_quirk = false;
1658 radeon_connector = to_radeon_connector(connector);
1659 radeon_dig_connector = radeon_connector->con_priv;
1660 if ((radeon_connector_encoder_get_dp_bridge_encoder_id(connector) ==
1661 ENCODER_OBJECT_ID_TRAVIS) &&
1662 (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) &&
1663 !ASIC_IS_DCE5(rdev))
1664 travis_quirk = true;
1668 case DRM_MODE_DPMS_ON:
1669 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE5(rdev)) {
1671 dig->panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE;
1673 dig->panel_mode = radeon_dp_get_panel_mode(encoder, connector);
1675 /* setup and enable the encoder */
1676 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0);
1677 atombios_dig_encoder_setup(encoder,
1678 ATOM_ENCODER_CMD_SETUP_PANEL_MODE,
1681 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev))
1682 atombios_external_encoder_setup(encoder, ext_encoder,
1683 EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP);
1685 } else if (ASIC_IS_DCE4(rdev)) {
1686 /* setup and enable the encoder */
1687 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0);
1689 /* setup and enable the encoder and transmitter */
1690 atombios_dig_encoder_setup(encoder, ATOM_ENABLE, 0);
1691 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP, 0, 0);
1693 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) {
1694 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
1695 atombios_set_edp_panel_power(connector,
1696 ATOM_TRANSMITTER_ACTION_POWER_ON);
1697 radeon_dig_connector->edp_on = true;
1700 /* enable the transmitter */
1701 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1702 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) {
1703 /* DP_SET_POWER_D0 is set in radeon_dp_link_train */
1704 radeon_dp_link_train(encoder, connector);
1705 if (ASIC_IS_DCE4(rdev))
1706 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_ON, 0);
1708 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1709 atombios_dig_transmitter_setup(encoder,
1710 ATOM_TRANSMITTER_ACTION_LCD_BLON, 0, 0);
1712 atombios_external_encoder_setup(encoder, ext_encoder, ATOM_ENABLE);
1714 case DRM_MODE_DPMS_STANDBY:
1715 case DRM_MODE_DPMS_SUSPEND:
1716 case DRM_MODE_DPMS_OFF:
1718 /* don't power off encoders with active MST links */
1719 if (dig->active_mst_links)
1722 if (ASIC_IS_DCE4(rdev)) {
1723 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector)
1724 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_OFF, 0);
1727 atombios_external_encoder_setup(encoder, ext_encoder, ATOM_DISABLE);
1728 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1729 atombios_dig_transmitter_setup(encoder,
1730 ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0);
1732 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) &&
1733 connector && !travis_quirk)
1734 radeon_dp_set_rx_power_state(connector, DP_SET_POWER_D3);
1735 if (ASIC_IS_DCE4(rdev)) {
1736 /* disable the transmitter */
1737 atombios_dig_transmitter_setup(encoder,
1738 ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1740 /* disable the encoder and transmitter */
1741 atombios_dig_transmitter_setup(encoder,
1742 ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1743 atombios_dig_encoder_setup(encoder, ATOM_DISABLE, 0);
1745 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) {
1747 radeon_dp_set_rx_power_state(connector, DP_SET_POWER_D3);
1748 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
1749 atombios_set_edp_panel_power(connector,
1750 ATOM_TRANSMITTER_ACTION_POWER_OFF);
1751 radeon_dig_connector->edp_on = false;
1759 radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode)
1761 struct drm_device *dev = encoder->dev;
1762 struct radeon_device *rdev = dev->dev_private;
1763 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1764 int encoder_mode = atombios_get_encoder_mode(encoder);
1766 DRM_DEBUG_KMS("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n",
1767 radeon_encoder->encoder_id, mode, radeon_encoder->devices,
1768 radeon_encoder->active_device);
1770 if ((radeon_audio != 0) &&
1771 ((encoder_mode == ATOM_ENCODER_MODE_HDMI) ||
1772 ENCODER_MODE_IS_DP(encoder_mode)))
1773 radeon_audio_dpms(encoder, mode);
1775 switch (radeon_encoder->encoder_id) {
1776 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1777 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1778 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1779 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1780 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1781 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1782 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1783 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1784 radeon_atom_encoder_dpms_avivo(encoder, mode);
1786 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1787 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1788 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1789 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
1790 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1791 radeon_atom_encoder_dpms_dig(encoder, mode);
1793 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1794 if (ASIC_IS_DCE5(rdev)) {
1796 case DRM_MODE_DPMS_ON:
1797 atombios_dvo_setup(encoder, ATOM_ENABLE);
1799 case DRM_MODE_DPMS_STANDBY:
1800 case DRM_MODE_DPMS_SUSPEND:
1801 case DRM_MODE_DPMS_OFF:
1802 atombios_dvo_setup(encoder, ATOM_DISABLE);
1805 } else if (ASIC_IS_DCE3(rdev))
1806 radeon_atom_encoder_dpms_dig(encoder, mode);
1808 radeon_atom_encoder_dpms_avivo(encoder, mode);
1810 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1811 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1812 if (ASIC_IS_DCE5(rdev)) {
1814 case DRM_MODE_DPMS_ON:
1815 atombios_dac_setup(encoder, ATOM_ENABLE);
1817 case DRM_MODE_DPMS_STANDBY:
1818 case DRM_MODE_DPMS_SUSPEND:
1819 case DRM_MODE_DPMS_OFF:
1820 atombios_dac_setup(encoder, ATOM_DISABLE);
1824 radeon_atom_encoder_dpms_avivo(encoder, mode);
1830 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
1834 union crtc_source_param {
1835 SELECT_CRTC_SOURCE_PS_ALLOCATION v1;
1836 SELECT_CRTC_SOURCE_PARAMETERS_V2 v2;
1840 atombios_set_encoder_crtc_source(struct drm_encoder *encoder)
1842 struct drm_device *dev = encoder->dev;
1843 struct radeon_device *rdev = dev->dev_private;
1844 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1845 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1846 union crtc_source_param args;
1847 int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source);
1849 struct radeon_encoder_atom_dig *dig;
1851 memset(&args, 0, sizeof(args));
1853 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1861 if (ASIC_IS_AVIVO(rdev))
1862 args.v1.ucCRTC = radeon_crtc->crtc_id;
1864 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) {
1865 args.v1.ucCRTC = radeon_crtc->crtc_id;
1867 args.v1.ucCRTC = radeon_crtc->crtc_id << 2;
1870 switch (radeon_encoder->encoder_id) {
1871 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1872 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1873 args.v1.ucDevice = ATOM_DEVICE_DFP1_INDEX;
1875 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1876 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1877 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT)
1878 args.v1.ucDevice = ATOM_DEVICE_LCD1_INDEX;
1880 args.v1.ucDevice = ATOM_DEVICE_DFP3_INDEX;
1882 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1883 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1884 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1885 args.v1.ucDevice = ATOM_DEVICE_DFP2_INDEX;
1887 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1888 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1889 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1890 args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1891 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1892 args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1894 args.v1.ucDevice = ATOM_DEVICE_CRT1_INDEX;
1896 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1897 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1898 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1899 args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1900 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1901 args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1903 args.v1.ucDevice = ATOM_DEVICE_CRT2_INDEX;
1908 args.v2.ucCRTC = radeon_crtc->crtc_id;
1909 if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE) {
1910 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1912 if (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)
1913 args.v2.ucEncodeMode = ATOM_ENCODER_MODE_LVDS;
1914 else if (connector->connector_type == DRM_MODE_CONNECTOR_VGA)
1915 args.v2.ucEncodeMode = ATOM_ENCODER_MODE_CRT;
1917 args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder);
1918 } else if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1919 args.v2.ucEncodeMode = ATOM_ENCODER_MODE_LVDS;
1921 args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder);
1923 switch (radeon_encoder->encoder_id) {
1924 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1925 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1926 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1927 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
1928 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1929 dig = radeon_encoder->enc_priv;
1930 switch (dig->dig_encoder) {
1932 args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID;
1935 args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID;
1938 args.v2.ucEncoderID = ASIC_INT_DIG3_ENCODER_ID;
1941 args.v2.ucEncoderID = ASIC_INT_DIG4_ENCODER_ID;
1944 args.v2.ucEncoderID = ASIC_INT_DIG5_ENCODER_ID;
1947 args.v2.ucEncoderID = ASIC_INT_DIG6_ENCODER_ID;
1950 args.v2.ucEncoderID = ASIC_INT_DIG7_ENCODER_ID;
1954 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1955 args.v2.ucEncoderID = ASIC_INT_DVO_ENCODER_ID;
1957 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1958 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1959 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1960 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1961 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1963 args.v2.ucEncoderID = ASIC_INT_DAC1_ENCODER_ID;
1965 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1966 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1967 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1968 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1969 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1971 args.v2.ucEncoderID = ASIC_INT_DAC2_ENCODER_ID;
1978 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1982 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1984 /* update scratch regs with new routing */
1985 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
1989 atombios_set_mst_encoder_crtc_source(struct drm_encoder *encoder, int fe)
1991 struct drm_device *dev = encoder->dev;
1992 struct radeon_device *rdev = dev->dev_private;
1993 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1994 int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source);
1996 union crtc_source_param args;
1998 memset(&args, 0, sizeof(args));
2000 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
2003 if (frev != 1 && crev != 2)
2004 DRM_ERROR("Unknown table for MST %d, %d\n", frev, crev);
2006 args.v2.ucCRTC = radeon_crtc->crtc_id;
2007 args.v2.ucEncodeMode = ATOM_ENCODER_MODE_DP_MST;
2011 args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID;
2014 args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID;
2017 args.v2.ucEncoderID = ASIC_INT_DIG3_ENCODER_ID;
2020 args.v2.ucEncoderID = ASIC_INT_DIG4_ENCODER_ID;
2023 args.v2.ucEncoderID = ASIC_INT_DIG5_ENCODER_ID;
2026 args.v2.ucEncoderID = ASIC_INT_DIG6_ENCODER_ID;
2029 args.v2.ucEncoderID = ASIC_INT_DIG7_ENCODER_ID;
2032 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2036 atombios_apply_encoder_quirks(struct drm_encoder *encoder,
2037 struct drm_display_mode *mode)
2039 struct drm_device *dev = encoder->dev;
2040 struct radeon_device *rdev = dev->dev_private;
2041 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2042 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
2044 /* Funky macbooks */
2045 if ((dev->pdev->device == 0x71C5) &&
2046 (dev->pdev->subsystem_vendor == 0x106b) &&
2047 (dev->pdev->subsystem_device == 0x0080)) {
2048 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
2049 uint32_t lvtma_bit_depth_control = RREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL);
2051 lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN;
2052 lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN;
2054 WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL, lvtma_bit_depth_control);
2058 /* set scaler clears this on some chips */
2059 if (ASIC_IS_AVIVO(rdev) &&
2060 (!(radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)))) {
2061 if (ASIC_IS_DCE8(rdev)) {
2062 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
2063 WREG32(CIK_LB_DATA_FORMAT + radeon_crtc->crtc_offset,
2066 WREG32(CIK_LB_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
2067 } else if (ASIC_IS_DCE4(rdev)) {
2068 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
2069 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset,
2070 EVERGREEN_INTERLEAVE_EN);
2072 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
2074 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
2075 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset,
2076 AVIVO_D1MODE_INTERLEAVE_EN);
2078 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
2083 void radeon_atom_release_dig_encoder(struct radeon_device *rdev, int enc_idx)
2087 rdev->mode_info.active_encoders &= ~(1 << enc_idx);
2090 int radeon_atom_pick_dig_encoder(struct drm_encoder *encoder, int fe_idx)
2092 struct drm_device *dev = encoder->dev;
2093 struct radeon_device *rdev = dev->dev_private;
2094 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
2095 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2096 struct drm_encoder *test_encoder;
2097 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
2098 uint32_t dig_enc_in_use = 0;
2105 if (ASIC_IS_DCE6(rdev)) {
2107 switch (radeon_encoder->encoder_id) {
2108 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2114 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2120 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2126 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2131 } else if (ASIC_IS_DCE4(rdev)) {
2133 if (ASIC_IS_DCE41(rdev) && !ASIC_IS_DCE61(rdev)) {
2134 /* ontario follows DCE4 */
2135 if (rdev->family == CHIP_PALM) {
2141 /* llano follows DCE3.2 */
2142 enc_idx = radeon_crtc->crtc_id;
2144 switch (radeon_encoder->encoder_id) {
2145 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2151 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2157 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2168 /* on DCE32 and encoder can driver any block so just crtc id */
2169 if (ASIC_IS_DCE32(rdev)) {
2170 enc_idx = radeon_crtc->crtc_id;
2174 /* on DCE3 - LVTMA can only be driven by DIGB */
2175 list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) {
2176 struct radeon_encoder *radeon_test_encoder;
2178 if (encoder == test_encoder)
2181 if (!radeon_encoder_is_digital(test_encoder))
2184 radeon_test_encoder = to_radeon_encoder(test_encoder);
2185 dig = radeon_test_encoder->enc_priv;
2187 if (dig->dig_encoder >= 0)
2188 dig_enc_in_use |= (1 << dig->dig_encoder);
2191 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA) {
2192 if (dig_enc_in_use & 0x2)
2193 DRM_ERROR("LVDS required digital encoder 2 but it was in use - stealing\n");
2196 if (!(dig_enc_in_use & 1))
2201 if (enc_idx == -1) {
2202 DRM_ERROR("Got encoder index incorrect - returning 0\n");
2205 if (rdev->mode_info.active_encoders & (1 << enc_idx)) {
2206 DRM_ERROR("chosen encoder in use %d\n", enc_idx);
2208 rdev->mode_info.active_encoders |= (1 << enc_idx);
2212 /* This only needs to be called once at startup */
2214 radeon_atom_encoder_init(struct radeon_device *rdev)
2216 struct drm_device *dev = rdev->ddev;
2217 struct drm_encoder *encoder;
2219 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2220 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2221 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
2223 switch (radeon_encoder->encoder_id) {
2224 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2225 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2226 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2227 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2228 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2229 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT, 0, 0);
2235 if (ext_encoder && (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev)))
2236 atombios_external_encoder_setup(encoder, ext_encoder,
2237 EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT);
2242 radeon_atom_encoder_mode_set(struct drm_encoder *encoder,
2243 struct drm_display_mode *mode,
2244 struct drm_display_mode *adjusted_mode)
2246 struct drm_device *dev = encoder->dev;
2247 struct radeon_device *rdev = dev->dev_private;
2248 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2249 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
2252 radeon_encoder->pixel_clock = adjusted_mode->clock;
2254 /* need to call this here rather than in prepare() since we need some crtc info */
2255 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
2257 if (ASIC_IS_AVIVO(rdev) && !ASIC_IS_DCE4(rdev)) {
2258 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT))
2259 atombios_yuv_setup(encoder, true);
2261 atombios_yuv_setup(encoder, false);
2264 switch (radeon_encoder->encoder_id) {
2265 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
2266 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
2267 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
2268 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
2269 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_ENABLE);
2271 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2272 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2273 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2274 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2275 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2276 /* handled in dpms */
2278 case ENCODER_OBJECT_ID_INTERNAL_DDI:
2279 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
2280 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
2281 atombios_dvo_setup(encoder, ATOM_ENABLE);
2283 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
2284 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
2285 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
2286 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
2287 atombios_dac_setup(encoder, ATOM_ENABLE);
2288 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) {
2289 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
2290 atombios_tv_setup(encoder, ATOM_ENABLE);
2292 atombios_tv_setup(encoder, ATOM_DISABLE);
2297 atombios_apply_encoder_quirks(encoder, adjusted_mode);
2299 encoder_mode = atombios_get_encoder_mode(encoder);
2300 if (connector && (radeon_audio != 0) &&
2301 ((encoder_mode == ATOM_ENCODER_MODE_HDMI) ||
2302 ENCODER_MODE_IS_DP(encoder_mode)))
2303 radeon_audio_mode_set(encoder, adjusted_mode);
2307 atombios_dac_load_detect(struct drm_encoder *encoder, struct drm_connector *connector)
2309 struct drm_device *dev = encoder->dev;
2310 struct radeon_device *rdev = dev->dev_private;
2311 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2312 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2314 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT |
2315 ATOM_DEVICE_CV_SUPPORT |
2316 ATOM_DEVICE_CRT_SUPPORT)) {
2317 DAC_LOAD_DETECTION_PS_ALLOCATION args;
2318 int index = GetIndexIntoMasterTable(COMMAND, DAC_LoadDetection);
2321 memset(&args, 0, sizeof(args));
2323 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
2326 args.sDacload.ucMisc = 0;
2328 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) ||
2329 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1))
2330 args.sDacload.ucDacType = ATOM_DAC_A;
2332 args.sDacload.ucDacType = ATOM_DAC_B;
2334 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)
2335 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT1_SUPPORT);
2336 else if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)
2337 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT2_SUPPORT);
2338 else if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
2339 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CV_SUPPORT);
2341 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
2342 } else if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
2343 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_TV1_SUPPORT);
2345 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
2348 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2355 static enum drm_connector_status
2356 radeon_atom_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
2358 struct drm_device *dev = encoder->dev;
2359 struct radeon_device *rdev = dev->dev_private;
2360 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2361 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2362 uint32_t bios_0_scratch;
2364 if (!atombios_dac_load_detect(encoder, connector)) {
2365 DRM_DEBUG_KMS("detect returned false \n");
2366 return connector_status_unknown;
2369 if (rdev->family >= CHIP_R600)
2370 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
2372 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
2374 DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices);
2375 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2376 if (bios_0_scratch & ATOM_S0_CRT1_MASK)
2377 return connector_status_connected;
2379 if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2380 if (bios_0_scratch & ATOM_S0_CRT2_MASK)
2381 return connector_status_connected;
2383 if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
2384 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A))
2385 return connector_status_connected;
2387 if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
2388 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A))
2389 return connector_status_connected; /* CTV */
2390 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A))
2391 return connector_status_connected; /* STV */
2393 return connector_status_disconnected;
2396 static enum drm_connector_status
2397 radeon_atom_dig_detect(struct drm_encoder *encoder, struct drm_connector *connector)
2399 struct drm_device *dev = encoder->dev;
2400 struct radeon_device *rdev = dev->dev_private;
2401 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2402 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2403 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
2406 if (!ASIC_IS_DCE4(rdev))
2407 return connector_status_unknown;
2410 return connector_status_unknown;
2412 if ((radeon_connector->devices & ATOM_DEVICE_CRT_SUPPORT) == 0)
2413 return connector_status_unknown;
2415 /* load detect on the dp bridge */
2416 atombios_external_encoder_setup(encoder, ext_encoder,
2417 EXTERNAL_ENCODER_ACTION_V3_DACLOAD_DETECTION);
2419 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
2421 DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices);
2422 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2423 if (bios_0_scratch & ATOM_S0_CRT1_MASK)
2424 return connector_status_connected;
2426 if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2427 if (bios_0_scratch & ATOM_S0_CRT2_MASK)
2428 return connector_status_connected;
2430 if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
2431 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A))
2432 return connector_status_connected;
2434 if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
2435 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A))
2436 return connector_status_connected; /* CTV */
2437 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A))
2438 return connector_status_connected; /* STV */
2440 return connector_status_disconnected;
2444 radeon_atom_ext_encoder_setup_ddc(struct drm_encoder *encoder)
2446 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
2449 /* ddc_setup on the dp bridge */
2450 atombios_external_encoder_setup(encoder, ext_encoder,
2451 EXTERNAL_ENCODER_ACTION_V3_DDC_SETUP);
2455 static void radeon_atom_encoder_prepare(struct drm_encoder *encoder)
2457 struct radeon_device *rdev = encoder->dev->dev_private;
2458 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2459 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
2461 if ((radeon_encoder->active_device &
2462 (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
2463 (radeon_encoder_get_dp_bridge_encoder_id(encoder) !=
2464 ENCODER_OBJECT_ID_NONE)) {
2465 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
2467 if (dig->dig_encoder >= 0)
2468 radeon_atom_release_dig_encoder(rdev, dig->dig_encoder);
2469 dig->dig_encoder = radeon_atom_pick_dig_encoder(encoder, -1);
2470 if (radeon_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT) {
2471 if (rdev->family >= CHIP_R600)
2472 dig->afmt = rdev->mode_info.afmt[dig->dig_encoder];
2474 /* RS600/690/740 have only 1 afmt block */
2475 dig->afmt = rdev->mode_info.afmt[0];
2480 radeon_atom_output_lock(encoder, true);
2483 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2485 /* select the clock/data port if it uses a router */
2486 if (radeon_connector->router.cd_valid)
2487 radeon_router_select_cd_port(radeon_connector);
2489 /* turn eDP panel on for mode set */
2490 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
2491 atombios_set_edp_panel_power(connector,
2492 ATOM_TRANSMITTER_ACTION_POWER_ON);
2495 /* this is needed for the pll/ss setup to work correctly in some cases */
2496 atombios_set_encoder_crtc_source(encoder);
2497 /* set up the FMT blocks */
2498 if (ASIC_IS_DCE8(rdev))
2499 dce8_program_fmt(encoder);
2500 else if (ASIC_IS_DCE4(rdev))
2501 dce4_program_fmt(encoder);
2502 else if (ASIC_IS_DCE3(rdev))
2503 dce3_program_fmt(encoder);
2504 else if (ASIC_IS_AVIVO(rdev))
2505 avivo_program_fmt(encoder);
2508 static void radeon_atom_encoder_commit(struct drm_encoder *encoder)
2510 /* need to call this here as we need the crtc set up */
2511 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
2512 radeon_atom_output_lock(encoder, false);
2515 static void radeon_atom_encoder_disable(struct drm_encoder *encoder)
2517 struct drm_device *dev = encoder->dev;
2518 struct radeon_device *rdev = dev->dev_private;
2519 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2520 struct radeon_encoder_atom_dig *dig;
2522 /* check for pre-DCE3 cards with shared encoders;
2523 * can't really use the links individually, so don't disable
2524 * the encoder if it's in use by another connector
2526 if (!ASIC_IS_DCE3(rdev)) {
2527 struct drm_encoder *other_encoder;
2528 struct radeon_encoder *other_radeon_encoder;
2530 list_for_each_entry(other_encoder, &dev->mode_config.encoder_list, head) {
2531 other_radeon_encoder = to_radeon_encoder(other_encoder);
2532 if ((radeon_encoder->encoder_id == other_radeon_encoder->encoder_id) &&
2533 drm_helper_encoder_in_use(other_encoder))
2538 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
2540 switch (radeon_encoder->encoder_id) {
2541 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
2542 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
2543 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
2544 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
2545 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_DISABLE);
2547 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2548 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2549 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2550 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2551 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2552 /* handled in dpms */
2554 case ENCODER_OBJECT_ID_INTERNAL_DDI:
2555 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
2556 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
2557 atombios_dvo_setup(encoder, ATOM_DISABLE);
2559 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
2560 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
2561 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
2562 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
2563 atombios_dac_setup(encoder, ATOM_DISABLE);
2564 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
2565 atombios_tv_setup(encoder, ATOM_DISABLE);
2570 if (radeon_encoder_is_digital(encoder)) {
2571 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
2572 if (rdev->asic->display.hdmi_enable)
2573 radeon_hdmi_enable(rdev, encoder, false);
2575 if (atombios_get_encoder_mode(encoder) != ATOM_ENCODER_MODE_DP_MST) {
2576 dig = radeon_encoder->enc_priv;
2577 radeon_atom_release_dig_encoder(rdev, dig->dig_encoder);
2578 dig->dig_encoder = -1;
2579 radeon_encoder->active_device = 0;
2582 radeon_encoder->active_device = 0;
2585 /* these are handled by the primary encoders */
2586 static void radeon_atom_ext_prepare(struct drm_encoder *encoder)
2591 static void radeon_atom_ext_commit(struct drm_encoder *encoder)
2597 radeon_atom_ext_mode_set(struct drm_encoder *encoder,
2598 struct drm_display_mode *mode,
2599 struct drm_display_mode *adjusted_mode)
2604 static void radeon_atom_ext_disable(struct drm_encoder *encoder)
2610 radeon_atom_ext_dpms(struct drm_encoder *encoder, int mode)
2615 static bool radeon_atom_ext_mode_fixup(struct drm_encoder *encoder,
2616 const struct drm_display_mode *mode,
2617 struct drm_display_mode *adjusted_mode)
2622 static const struct drm_encoder_helper_funcs radeon_atom_ext_helper_funcs = {
2623 .dpms = radeon_atom_ext_dpms,
2624 .mode_fixup = radeon_atom_ext_mode_fixup,
2625 .prepare = radeon_atom_ext_prepare,
2626 .mode_set = radeon_atom_ext_mode_set,
2627 .commit = radeon_atom_ext_commit,
2628 .disable = radeon_atom_ext_disable,
2629 /* no detect for TMDS/LVDS yet */
2632 static const struct drm_encoder_helper_funcs radeon_atom_dig_helper_funcs = {
2633 .dpms = radeon_atom_encoder_dpms,
2634 .mode_fixup = radeon_atom_mode_fixup,
2635 .prepare = radeon_atom_encoder_prepare,
2636 .mode_set = radeon_atom_encoder_mode_set,
2637 .commit = radeon_atom_encoder_commit,
2638 .disable = radeon_atom_encoder_disable,
2639 .detect = radeon_atom_dig_detect,
2642 static const struct drm_encoder_helper_funcs radeon_atom_dac_helper_funcs = {
2643 .dpms = radeon_atom_encoder_dpms,
2644 .mode_fixup = radeon_atom_mode_fixup,
2645 .prepare = radeon_atom_encoder_prepare,
2646 .mode_set = radeon_atom_encoder_mode_set,
2647 .commit = radeon_atom_encoder_commit,
2648 .detect = radeon_atom_dac_detect,
2651 void radeon_enc_destroy(struct drm_encoder *encoder)
2653 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2654 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
2655 radeon_atom_backlight_exit(radeon_encoder);
2656 kfree(radeon_encoder->enc_priv);
2657 drm_encoder_cleanup(encoder);
2658 kfree(radeon_encoder);
2661 static const struct drm_encoder_funcs radeon_atom_enc_funcs = {
2662 .destroy = radeon_enc_destroy,
2665 static struct radeon_encoder_atom_dac *
2666 radeon_atombios_set_dac_info(struct radeon_encoder *radeon_encoder)
2668 struct drm_device *dev = radeon_encoder->base.dev;
2669 struct radeon_device *rdev = dev->dev_private;
2670 struct radeon_encoder_atom_dac *dac = kzalloc(sizeof(struct radeon_encoder_atom_dac), GFP_KERNEL);
2675 dac->tv_std = radeon_atombios_get_tv_info(rdev);
2679 static struct radeon_encoder_atom_dig *
2680 radeon_atombios_set_dig_info(struct radeon_encoder *radeon_encoder)
2682 int encoder_enum = (radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
2683 struct radeon_encoder_atom_dig *dig = kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
2688 /* coherent mode by default */
2689 dig->coherent_mode = true;
2690 dig->dig_encoder = -1;
2692 if (encoder_enum == 2)
2701 radeon_add_atom_encoder(struct drm_device *dev,
2702 uint32_t encoder_enum,
2703 uint32_t supported_device,
2706 struct radeon_device *rdev = dev->dev_private;
2707 struct drm_encoder *encoder;
2708 struct radeon_encoder *radeon_encoder;
2710 /* see if we already added it */
2711 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2712 radeon_encoder = to_radeon_encoder(encoder);
2713 if (radeon_encoder->encoder_enum == encoder_enum) {
2714 radeon_encoder->devices |= supported_device;
2721 radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL);
2722 if (!radeon_encoder)
2725 encoder = &radeon_encoder->base;
2726 switch (rdev->num_crtc) {
2728 encoder->possible_crtcs = 0x1;
2732 encoder->possible_crtcs = 0x3;
2735 encoder->possible_crtcs = 0xf;
2738 encoder->possible_crtcs = 0x3f;
2742 radeon_encoder->enc_priv = NULL;
2744 radeon_encoder->encoder_enum = encoder_enum;
2745 radeon_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
2746 radeon_encoder->devices = supported_device;
2747 radeon_encoder->rmx_type = RMX_OFF;
2748 radeon_encoder->underscan_type = UNDERSCAN_OFF;
2749 radeon_encoder->is_ext_encoder = false;
2750 radeon_encoder->caps = caps;
2752 switch (radeon_encoder->encoder_id) {
2753 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
2754 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
2755 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
2756 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
2757 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
2758 radeon_encoder->rmx_type = RMX_FULL;
2759 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
2760 radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
2762 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
2763 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2765 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
2767 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
2768 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
2769 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
2770 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
2772 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
2773 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
2774 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
2775 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TVDAC);
2776 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
2777 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
2779 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
2780 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
2781 case ENCODER_OBJECT_ID_INTERNAL_DDI:
2782 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2783 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2784 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2785 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2786 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2787 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
2788 radeon_encoder->rmx_type = RMX_FULL;
2789 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
2790 radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
2791 } else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
2792 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
2793 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2795 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
2796 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2798 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
2800 case ENCODER_OBJECT_ID_SI170B:
2801 case ENCODER_OBJECT_ID_CH7303:
2802 case ENCODER_OBJECT_ID_EXTERNAL_SDVOA:
2803 case ENCODER_OBJECT_ID_EXTERNAL_SDVOB:
2804 case ENCODER_OBJECT_ID_TITFP513:
2805 case ENCODER_OBJECT_ID_VT1623:
2806 case ENCODER_OBJECT_ID_HDMI_SI1930:
2807 case ENCODER_OBJECT_ID_TRAVIS:
2808 case ENCODER_OBJECT_ID_NUTMEG:
2809 /* these are handled by the primary encoders */
2810 radeon_encoder->is_ext_encoder = true;
2811 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
2812 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
2813 else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT))
2814 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
2816 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
2817 drm_encoder_helper_add(encoder, &radeon_atom_ext_helper_funcs);