drivers/gpu/drm/radeon/ci_dpm.c

   1 /*
   2  * Copyright 2013 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/firmware.h>
  25 #include "drmP.h"
  26 #include "radeon.h"
  27 #include "radeon_ucode.h"
  28 #include "cikd.h"
  29 #include "r600_dpm.h"
  30 #include "ci_dpm.h"
  31 #include "atom.h"
  32 #include <linux/seq_file.h>
  33
  34 #define MC_CG_ARB_FREQ_F0           0x0a
  35 #define MC_CG_ARB_FREQ_F1           0x0b
  36 #define MC_CG_ARB_FREQ_F2           0x0c
  37 #define MC_CG_ARB_FREQ_F3           0x0d
  38
  39 #define SMC_RAM_END 0x40000
  40
  41 #define VOLTAGE_SCALE               4
  42 #define VOLTAGE_VID_OFFSET_SCALE1    625
  43 #define VOLTAGE_VID_OFFSET_SCALE2    100
  44
  45 static const struct ci_pt_defaults defaults_hawaii_xt =
  46 {
  47         1, 0xF, 0xFD, 0x19, 5, 0x14, 0, 0xB0000,
  48         { 0x84,  0x0,   0x0,   0x7F,  0x0,   0x0,   0x5A,  0x60,  0x51,  0x8E,  0x79,  0x6B,  0x5F,  0x90,  0x79  },
  49         { 0x1EA, 0x1EA, 0x1EA, 0x224, 0x224, 0x224, 0x24F, 0x24F, 0x24F, 0x28E, 0x28E, 0x28E, 0x2BC, 0x2BC, 0x2BC }
  50 };
  51
  52 static const struct ci_pt_defaults defaults_hawaii_pro =
  53 {
  54         1, 0xF, 0xFD, 0x19, 5, 0x14, 0, 0x65062,
  55         { 0x93,  0x0,   0x0,   0x97,  0x0,   0x0,   0x6B,  0x60,  0x51,  0x95,  0x79,  0x6B,  0x5F,  0x90,  0x79  },
  56         { 0x1EA, 0x1EA, 0x1EA, 0x224, 0x224, 0x224, 0x24F, 0x24F, 0x24F, 0x28E, 0x28E, 0x28E, 0x2BC, 0x2BC, 0x2BC }
  57 };
  58
  59 static const struct ci_pt_defaults defaults_bonaire_xt =
  60 {
  61         1, 0xF, 0xFD, 0x19, 5, 45, 0, 0xB0000,
  62         { 0x79,  0x253, 0x25D, 0xAE,  0x72,  0x80,  0x83,  0x86,  0x6F,  0xC8,  0xC9,  0xC9,  0x2F,  0x4D,  0x61  },
  63         { 0x17C, 0x172, 0x180, 0x1BC, 0x1B3, 0x1BD, 0x206, 0x200, 0x203, 0x25D, 0x25A, 0x255, 0x2C3, 0x2C5, 0x2B4 }
  64 };
  65
  66 static const struct ci_pt_defaults defaults_bonaire_pro =
  67 {
  68         1, 0xF, 0xFD, 0x19, 5, 45, 0, 0x65062,
  69         { 0x8C,  0x23F, 0x244, 0xA6,  0x83,  0x85,  0x86,  0x86,  0x83,  0xDB,  0xDB,  0xDA,  0x67,  0x60,  0x5F  },
  70         { 0x187, 0x193, 0x193, 0x1C7, 0x1D1, 0x1D1, 0x210, 0x219, 0x219, 0x266, 0x26C, 0x26C, 0x2C9, 0x2CB, 0x2CB }
  71 };
  72
  73 static const struct ci_pt_defaults defaults_saturn_xt =
  74 {
  75         1, 0xF, 0xFD, 0x19, 5, 55, 0, 0x70000,
  76         { 0x8C,  0x247, 0x249, 0xA6,  0x80,  0x81,  0x8B,  0x89,  0x86,  0xC9,  0xCA,  0xC9,  0x4D,  0x4D,  0x4D  },
  77         { 0x187, 0x187, 0x187, 0x1C7, 0x1C7, 0x1C7, 0x210, 0x210, 0x210, 0x266, 0x266, 0x266, 0x2C9, 0x2C9, 0x2C9 }
  78 };
  79
  80 static const struct ci_pt_defaults defaults_saturn_pro =
  81 {
  82         1, 0xF, 0xFD, 0x19, 5, 55, 0, 0x30000,
  83         { 0x96,  0x21D, 0x23B, 0xA1,  0x85,  0x87,  0x83,  0x84,  0x81,  0xE6,  0xE6,  0xE6,  0x71,  0x6A,  0x6A  },
  84         { 0x193, 0x19E, 0x19E, 0x1D2, 0x1DC, 0x1DC, 0x21A, 0x223, 0x223, 0x26E, 0x27E, 0x274, 0x2CF, 0x2D2, 0x2D2 }
  85 };
  86
  87 static const struct ci_pt_config_reg didt_config_ci[] =
  88 {
  89         { 0x10, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
  90         { 0x10, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
  91         { 0x10, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
  92         { 0x10, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
  93         { 0x11, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
  94         { 0x11, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
  95         { 0x11, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
  96         { 0x11, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
  97         { 0x12, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
  98         { 0x12, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
  99         { 0x12, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 100         { 0x12, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 101         { 0x2, 0x00003fff, 0, 0x4, CISLANDS_CONFIGREG_DIDT_IND },
 102         { 0x2, 0x03ff0000, 16, 0x80, CISLANDS_CONFIGREG_DIDT_IND },
 103         { 0x2, 0x78000000, 27, 0x3, CISLANDS_CONFIGREG_DIDT_IND },
 104         { 0x1, 0x0000ffff, 0, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
 105         { 0x1, 0xffff0000, 16, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
 106         { 0x0, 0x00000001, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 107         { 0x30, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 108         { 0x30, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 109         { 0x30, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 110         { 0x30, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 111         { 0x31, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 112         { 0x31, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 113         { 0x31, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 114         { 0x31, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 115         { 0x32, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 116         { 0x32, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 117         { 0x32, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 118         { 0x32, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 119         { 0x22, 0x00003fff, 0, 0x4, CISLANDS_CONFIGREG_DIDT_IND },
 120         { 0x22, 0x03ff0000, 16, 0x80, CISLANDS_CONFIGREG_DIDT_IND },
 121         { 0x22, 0x78000000, 27, 0x3, CISLANDS_CONFIGREG_DIDT_IND },
 122         { 0x21, 0x0000ffff, 0, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
 123         { 0x21, 0xffff0000, 16, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
 124         { 0x20, 0x00000001, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 125         { 0x50, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 126         { 0x50, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 127         { 0x50, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 128         { 0x50, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 129         { 0x51, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 130         { 0x51, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 131         { 0x51, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 132         { 0x51, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 133         { 0x52, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 134         { 0x52, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 135         { 0x52, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 136         { 0x52, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 137         { 0x42, 0x00003fff, 0, 0x4, CISLANDS_CONFIGREG_DIDT_IND },
 138         { 0x42, 0x03ff0000, 16, 0x80, CISLANDS_CONFIGREG_DIDT_IND },
 139         { 0x42, 0x78000000, 27, 0x3, CISLANDS_CONFIGREG_DIDT_IND },
 140         { 0x41, 0x0000ffff, 0, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
 141         { 0x41, 0xffff0000, 16, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
 142         { 0x40, 0x00000001, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 143         { 0x70, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 144         { 0x70, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 145         { 0x70, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 146         { 0x70, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 147         { 0x71, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 148         { 0x71, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 149         { 0x71, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 150         { 0x71, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 151         { 0x72, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 152         { 0x72, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 153         { 0x72, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 154         { 0x72, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 155         { 0x62, 0x00003fff, 0, 0x4, CISLANDS_CONFIGREG_DIDT_IND },
 156         { 0x62, 0x03ff0000, 16, 0x80, CISLANDS_CONFIGREG_DIDT_IND },
 157         { 0x62, 0x78000000, 27, 0x3, CISLANDS_CONFIGREG_DIDT_IND },
 158         { 0x61, 0x0000ffff, 0, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
 159         { 0x61, 0xffff0000, 16, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
 160         { 0x60, 0x00000001, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 161         { 0xFFFFFFFF }
 162 };
 163
 164 extern u8 rv770_get_memory_module_index(struct radeon_device *rdev);
 165 extern void btc_get_max_clock_from_voltage_dependency_table(struct radeon_clock_voltage_dependency_table *table,
 166                                                             u32 *max_clock);
 167 extern int ni_copy_and_switch_arb_sets(struct radeon_device *rdev,
 168                                        u32 arb_freq_src, u32 arb_freq_dest);
 169 extern u8 si_get_ddr3_mclk_frequency_ratio(u32 memory_clock);
 170 extern u8 si_get_mclk_frequency_ratio(u32 memory_clock, bool strobe_mode);
 171 extern void si_trim_voltage_table_to_fit_state_table(struct radeon_device *rdev,
 172                                                      u32 max_voltage_steps,
 173                                                      struct atom_voltage_table *voltage_table);
 174 extern void cik_enter_rlc_safe_mode(struct radeon_device *rdev);
 175 extern void cik_exit_rlc_safe_mode(struct radeon_device *rdev);
 176 extern int ci_mc_load_microcode(struct radeon_device *rdev);
 177 extern void cik_update_cg(struct radeon_device *rdev,
 178                           u32 block, bool enable);
 179
 180 static int ci_get_std_voltage_value_sidd(struct radeon_device *rdev,
 181                                          struct atom_voltage_table_entry *voltage_table,
 182                                          u16 *std_voltage_hi_sidd, u16 *std_voltage_lo_sidd);
 183 static int ci_set_power_limit(struct radeon_device *rdev, u32 n);
 184 static int ci_set_overdrive_target_tdp(struct radeon_device *rdev,
 185                                        u32 target_tdp);
 186 static int ci_update_uvd_dpm(struct radeon_device *rdev, bool gate);
 187
 188 static struct ci_power_info *ci_get_pi(struct radeon_device *rdev)
 189 {
 190         struct ci_power_info *pi = rdev->pm.dpm.priv;
 191
 192         return pi;
 193 }
 194
 195 static struct ci_ps *ci_get_ps(struct radeon_ps *rps)
 196 {
 197         struct ci_ps *ps = rps->ps_priv;
 198
 199         return ps;
 200 }
 201
 202 static void ci_initialize_powertune_defaults(struct radeon_device *rdev)
 203 {
 204         struct ci_power_info *pi = ci_get_pi(rdev);
 205
 206         switch (rdev->pdev->device) {
 207         case 0x6649:
 208         case 0x6650:
 209         case 0x6651:
 210         case 0x6658:
 211         case 0x665C:
 212         case 0x665D:
 213         default:
 214                 pi->powertune_defaults = &defaults_bonaire_xt;
 215                 break;
 216         case 0x6640:
 217         case 0x6641:
 218         case 0x6646:
 219         case 0x6647:
 220                 pi->powertune_defaults = &defaults_saturn_xt;
 221                 break;
 222         case 0x67B8:
 223         case 0x67B0:
 224                 pi->powertune_defaults = &defaults_hawaii_xt;
 225                 break;
 226         case 0x67BA:
 227         case 0x67B1:
 228                 pi->powertune_defaults = &defaults_hawaii_pro;
 229                 break;
 230         case 0x67A0:
 231         case 0x67A1:
 232         case 0x67A2:
 233         case 0x67A8:
 234         case 0x67A9:
 235         case 0x67AA:
 236         case 0x67B9:
 237         case 0x67BE:
 238                 pi->powertune_defaults = &defaults_bonaire_xt;
 239                 break;
 240         }
 241
 242         pi->dte_tj_offset = 0;
 243
 244         pi->caps_power_containment = true;
 245         pi->caps_cac = false;
 246         pi->caps_sq_ramping = false;
 247         pi->caps_db_ramping = false;
 248         pi->caps_td_ramping = false;
 249         pi->caps_tcp_ramping = false;
 250
 251         if (pi->caps_power_containment) {
 252                 pi->caps_cac = true;
 253                 pi->enable_bapm_feature = true;
 254                 pi->enable_tdc_limit_feature = true;
 255                 pi->enable_pkg_pwr_tracking_feature = true;
 256         }
 257 }
 258
 259 static u8 ci_convert_to_vid(u16 vddc)
 260 {
 261         return (6200 - (vddc * VOLTAGE_SCALE)) / 25;
 262 }
 263
 264 static int ci_populate_bapm_vddc_vid_sidd(struct radeon_device *rdev)
 265 {
 266         struct ci_power_info *pi = ci_get_pi(rdev);
 267         u8 *hi_vid = pi->smc_powertune_table.BapmVddCVidHiSidd;
 268         u8 *lo_vid = pi->smc_powertune_table.BapmVddCVidLoSidd;
 269         u8 *hi2_vid = pi->smc_powertune_table.BapmVddCVidHiSidd2;
 270         u32 i;
 271
 272         if (rdev->pm.dpm.dyn_state.cac_leakage_table.entries == NULL)
 273                 return -EINVAL;
 274         if (rdev->pm.dpm.dyn_state.cac_leakage_table.count > 8)
 275                 return -EINVAL;
 276         if (rdev->pm.dpm.dyn_state.cac_leakage_table.count !=
 277             rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count)
 278                 return -EINVAL;
 279
 280         for (i = 0; i < rdev->pm.dpm.dyn_state.cac_leakage_table.count; i++) {
 281                 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_EVV) {
 282                         lo_vid[i] = ci_convert_to_vid(rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc1);
 283                         hi_vid[i] = ci_convert_to_vid(rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc2);
 284                         hi2_vid[i] = ci_convert_to_vid(rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc3);
 285                 } else {
 286                         lo_vid[i] = ci_convert_to_vid(rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc);
 287                         hi_vid[i] = ci_convert_to_vid((u16)rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].leakage);
 288                 }
 289         }
 290         return 0;
 291 }
 292
 293 static int ci_populate_vddc_vid(struct radeon_device *rdev)
 294 {
 295         struct ci_power_info *pi = ci_get_pi(rdev);
 296         u8 *vid = pi->smc_powertune_table.VddCVid;
 297         u32 i;
 298
 299         if (pi->vddc_voltage_table.count > 8)
 300                 return -EINVAL;
 301
 302         for (i = 0; i < pi->vddc_voltage_table.count; i++)
 303                 vid[i] = ci_convert_to_vid(pi->vddc_voltage_table.entries[i].value);
 304
 305         return 0;
 306 }
 307
 308 static int ci_populate_svi_load_line(struct radeon_device *rdev)
 309 {
 310         struct ci_power_info *pi = ci_get_pi(rdev);
 311         const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults;
 312
 313         pi->smc_powertune_table.SviLoadLineEn = pt_defaults->svi_load_line_en;
 314         pi->smc_powertune_table.SviLoadLineVddC = pt_defaults->svi_load_line_vddc;
 315         pi->smc_powertune_table.SviLoadLineTrimVddC = 3;
 316         pi->smc_powertune_table.SviLoadLineOffsetVddC = 0;
 317
 318         return 0;
 319 }
 320
 321 static int ci_populate_tdc_limit(struct radeon_device *rdev)
 322 {
 323         struct ci_power_info *pi = ci_get_pi(rdev);
 324         const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults;
 325         u16 tdc_limit;
 326
 327         tdc_limit = rdev->pm.dpm.dyn_state.cac_tdp_table->tdc * 256;
 328         pi->smc_powertune_table.TDC_VDDC_PkgLimit = cpu_to_be16(tdc_limit);
 329         pi->smc_powertune_table.TDC_VDDC_ThrottleReleaseLimitPerc =
 330                 pt_defaults->tdc_vddc_throttle_release_limit_perc;
 331         pi->smc_powertune_table.TDC_MAWt = pt_defaults->tdc_mawt;
 332
 333         return 0;
 334 }
 335
 336 static int ci_populate_dw8(struct radeon_device *rdev)
 337 {
 338         struct ci_power_info *pi = ci_get_pi(rdev);
 339         const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults;
 340         int ret;
 341
 342         ret = ci_read_smc_sram_dword(rdev,
 343                                      SMU7_FIRMWARE_HEADER_LOCATION +
 344                                      offsetof(SMU7_Firmware_Header, PmFuseTable) +
 345                                      offsetof(SMU7_Discrete_PmFuses, TdcWaterfallCtl),
 346                                      (u32 *)&pi->smc_powertune_table.TdcWaterfallCtl,
 347                                      pi->sram_end);
 348         if (ret)
 349                 return -EINVAL;
 350         else
 351                 pi->smc_powertune_table.TdcWaterfallCtl = pt_defaults->tdc_waterfall_ctl;
 352
 353         return 0;
 354 }
 355
 356 static int ci_min_max_v_gnbl_pm_lid_from_bapm_vddc(struct radeon_device *rdev)
 357 {
 358         struct ci_power_info *pi = ci_get_pi(rdev);
 359         u8 *hi_vid = pi->smc_powertune_table.BapmVddCVidHiSidd;
 360         u8 *lo_vid = pi->smc_powertune_table.BapmVddCVidLoSidd;
 361         int i, min, max;
 362
 363         min = max = hi_vid[0];
 364         for (i = 0; i < 8; i++) {
 365                 if (0 != hi_vid[i]) {
 366                         if (min > hi_vid[i])
 367                                 min = hi_vid[i];
 368                         if (max < hi_vid[i])
 369                                 max = hi_vid[i];
 370                 }
 371
 372                 if (0 != lo_vid[i]) {
 373                         if (min > lo_vid[i])
 374                                 min = lo_vid[i];
 375                         if (max < lo_vid[i])
 376                                 max = lo_vid[i];
 377                 }
 378         }
 379
 380         if ((min == 0) || (max == 0))
 381                 return -EINVAL;
 382         pi->smc_powertune_table.GnbLPMLMaxVid = (u8)max;
 383         pi->smc_powertune_table.GnbLPMLMinVid = (u8)min;
 384
 385         return 0;
 386 }
 387
 388 static int ci_populate_bapm_vddc_base_leakage_sidd(struct radeon_device *rdev)
 389 {
 390         struct ci_power_info *pi = ci_get_pi(rdev);
 391         u16 hi_sidd = pi->smc_powertune_table.BapmVddCBaseLeakageHiSidd;
 392         u16 lo_sidd = pi->smc_powertune_table.BapmVddCBaseLeakageLoSidd;
 393         struct radeon_cac_tdp_table *cac_tdp_table =
 394                 rdev->pm.dpm.dyn_state.cac_tdp_table;
 395
 396         hi_sidd = cac_tdp_table->high_cac_leakage / 100 * 256;
 397         lo_sidd = cac_tdp_table->low_cac_leakage / 100 * 256;
 398
 399         pi->smc_powertune_table.BapmVddCBaseLeakageHiSidd = cpu_to_be16(hi_sidd);
 400         pi->smc_powertune_table.BapmVddCBaseLeakageLoSidd = cpu_to_be16(lo_sidd);
 401
 402         return 0;
 403 }
 404
 405 static int ci_populate_bapm_parameters_in_dpm_table(struct radeon_device *rdev)
 406 {
 407         struct ci_power_info *pi = ci_get_pi(rdev);
 408         const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults;
 409         SMU7_Discrete_DpmTable  *dpm_table = &pi->smc_state_table;
 410         struct radeon_cac_tdp_table *cac_tdp_table =
 411                 rdev->pm.dpm.dyn_state.cac_tdp_table;
 412         struct radeon_ppm_table *ppm = rdev->pm.dpm.dyn_state.ppm_table;
 413         int i, j, k;
 414         const u16 *def1;
 415         const u16 *def2;
 416
 417         dpm_table->DefaultTdp = cac_tdp_table->tdp * 256;
 418         dpm_table->TargetTdp = cac_tdp_table->configurable_tdp * 256;
 419
 420         dpm_table->DTETjOffset = (u8)pi->dte_tj_offset;
 421         dpm_table->GpuTjMax =
 422                 (u8)(pi->thermal_temp_setting.temperature_high / 1000);
 423         dpm_table->GpuTjHyst = 8;
 424
 425         dpm_table->DTEAmbientTempBase = pt_defaults->dte_ambient_temp_base;
 426
 427         if (ppm) {
 428                 dpm_table->PPM_PkgPwrLimit = cpu_to_be16((u16)ppm->dgpu_tdp * 256 / 1000);
 429                 dpm_table->PPM_TemperatureLimit = cpu_to_be16((u16)ppm->tj_max * 256);
 430         } else {
 431                 dpm_table->PPM_PkgPwrLimit = cpu_to_be16(0);
 432                 dpm_table->PPM_TemperatureLimit = cpu_to_be16(0);
 433         }
 434
 435         dpm_table->BAPM_TEMP_GRADIENT = cpu_to_be32(pt_defaults->bapm_temp_gradient);
 436         def1 = pt_defaults->bapmti_r;
 437         def2 = pt_defaults->bapmti_rc;
 438
 439         for (i = 0; i < SMU7_DTE_ITERATIONS; i++) {
 440                 for (j = 0; j < SMU7_DTE_SOURCES; j++) {
 441                         for (k = 0; k < SMU7_DTE_SINKS; k++) {
 442                                 dpm_table->BAPMTI_R[i][j][k] = cpu_to_be16(*def1);
 443                                 dpm_table->BAPMTI_RC[i][j][k] = cpu_to_be16(*def2);
 444                                 def1++;
 445                                 def2++;
 446                         }
 447                 }
 448         }
 449
 450         return 0;
 451 }
 452
 453 static int ci_populate_pm_base(struct radeon_device *rdev)
 454 {
 455         struct ci_power_info *pi = ci_get_pi(rdev);
 456         u32 pm_fuse_table_offset;
 457         int ret;
 458
 459         if (pi->caps_power_containment) {
 460                 ret = ci_read_smc_sram_dword(rdev,
 461                                              SMU7_FIRMWARE_HEADER_LOCATION +
 462                                              offsetof(SMU7_Firmware_Header, PmFuseTable),
 463                                              &pm_fuse_table_offset, pi->sram_end);
 464                 if (ret)
 465                         return ret;
 466                 ret = ci_populate_bapm_vddc_vid_sidd(rdev);
 467                 if (ret)
 468                         return ret;
 469                 ret = ci_populate_vddc_vid(rdev);
 470                 if (ret)
 471                         return ret;
 472                 ret = ci_populate_svi_load_line(rdev);
 473                 if (ret)
 474                         return ret;
 475                 ret = ci_populate_tdc_limit(rdev);
 476                 if (ret)
 477                         return ret;
 478                 ret = ci_populate_dw8(rdev);
 479                 if (ret)
 480                         return ret;
 481                 ret = ci_min_max_v_gnbl_pm_lid_from_bapm_vddc(rdev);
 482                 if (ret)
 483                         return ret;
 484                 ret = ci_populate_bapm_vddc_base_leakage_sidd(rdev);
 485                 if (ret)
 486                         return ret;
 487                 ret = ci_copy_bytes_to_smc(rdev, pm_fuse_table_offset,
 488                                            (u8 *)&pi->smc_powertune_table,
 489                                            sizeof(SMU7_Discrete_PmFuses), pi->sram_end);
 490                 if (ret)
 491                         return ret;
 492         }
 493
 494         return 0;
 495 }
 496
 497 static void ci_do_enable_didt(struct radeon_device *rdev, const bool enable)
 498 {
 499         struct ci_power_info *pi = ci_get_pi(rdev);
 500         u32 data;
 501
 502         if (pi->caps_sq_ramping) {
 503                 data = RREG32_DIDT(DIDT_SQ_CTRL0);
 504                 if (enable)
 505                         data |= DIDT_CTRL_EN;
 506                 else
 507                         data &= ~DIDT_CTRL_EN;
 508                 WREG32_DIDT(DIDT_SQ_CTRL0, data);
 509         }
 510
 511         if (pi->caps_db_ramping) {
 512                 data = RREG32_DIDT(DIDT_DB_CTRL0);
 513                 if (enable)
 514                         data |= DIDT_CTRL_EN;
 515                 else
 516                         data &= ~DIDT_CTRL_EN;
 517                 WREG32_DIDT(DIDT_DB_CTRL0, data);
 518         }
 519
 520         if (pi->caps_td_ramping) {
 521                 data = RREG32_DIDT(DIDT_TD_CTRL0);
 522                 if (enable)
 523                         data |= DIDT_CTRL_EN;
 524                 else
 525                         data &= ~DIDT_CTRL_EN;
 526                 WREG32_DIDT(DIDT_TD_CTRL0, data);
 527         }
 528
 529         if (pi->caps_tcp_ramping) {
 530                 data = RREG32_DIDT(DIDT_TCP_CTRL0);
 531                 if (enable)
 532                         data |= DIDT_CTRL_EN;
 533                 else
 534                         data &= ~DIDT_CTRL_EN;
 535                 WREG32_DIDT(DIDT_TCP_CTRL0, data);
 536         }
 537 }
 538
 539 static int ci_program_pt_config_registers(struct radeon_device *rdev,
 540                                           const struct ci_pt_config_reg *cac_config_regs)
 541 {
 542         const struct ci_pt_config_reg *config_regs = cac_config_regs;
 543         u32 data;
 544         u32 cache = 0;
 545
 546         if (config_regs == NULL)
 547                 return -EINVAL;
 548
 549         while (config_regs->offset != 0xFFFFFFFF) {
 550                 if (config_regs->type == CISLANDS_CONFIGREG_CACHE) {
 551                         cache |= ((config_regs->value << config_regs->shift) & config_regs->mask);
 552                 } else {
 553                         switch (config_regs->type) {
 554                         case CISLANDS_CONFIGREG_SMC_IND:
 555                                 data = RREG32_SMC(config_regs->offset);
 556                                 break;
 557                         case CISLANDS_CONFIGREG_DIDT_IND:
 558                                 data = RREG32_DIDT(config_regs->offset);
 559                                 break;
 560                         default:
 561                                 data = RREG32(config_regs->offset << 2);
 562                                 break;
 563                         }
 564
 565                         data &= ~config_regs->mask;
 566                         data |= ((config_regs->value << config_regs->shift) & config_regs->mask);
 567                         data |= cache;
 568
 569                         switch (config_regs->type) {
 570                         case CISLANDS_CONFIGREG_SMC_IND:
 571                                 WREG32_SMC(config_regs->offset, data);
 572                                 break;
 573                         case CISLANDS_CONFIGREG_DIDT_IND:
 574                                 WREG32_DIDT(config_regs->offset, data);
 575                                 break;
 576                         default:
 577                                 WREG32(config_regs->offset << 2, data);
 578                                 break;
 579                         }
 580                         cache = 0;
 581                 }
 582                 config_regs++;
 583         }
 584         return 0;
 585 }
 586
 587 static int ci_enable_didt(struct radeon_device *rdev, bool enable)
 588 {
 589         struct ci_power_info *pi = ci_get_pi(rdev);
 590         int ret;
 591
 592         if (pi->caps_sq_ramping || pi->caps_db_ramping ||
 593             pi->caps_td_ramping || pi->caps_tcp_ramping) {
 594                 cik_enter_rlc_safe_mode(rdev);
 595
 596                 if (enable) {
 597                         ret = ci_program_pt_config_registers(rdev, didt_config_ci);
 598                         if (ret) {
 599                                 cik_exit_rlc_safe_mode(rdev);
 600                                 return ret;
 601                         }
 602                 }
 603
 604                 ci_do_enable_didt(rdev, enable);
 605
 606                 cik_exit_rlc_safe_mode(rdev);
 607         }
 608
 609         return 0;
 610 }
 611
 612 static int ci_enable_power_containment(struct radeon_device *rdev, bool enable)
 613 {
 614         struct ci_power_info *pi = ci_get_pi(rdev);
 615         PPSMC_Result smc_result;
 616         int ret = 0;
 617
 618         if (enable) {
 619                 pi->power_containment_features = 0;
 620                 if (pi->caps_power_containment) {
 621                         if (pi->enable_bapm_feature) {
 622                                 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_EnableDTE);
 623                                 if (smc_result != PPSMC_Result_OK)
 624                                         ret = -EINVAL;
 625                                 else
 626                                         pi->power_containment_features |= POWERCONTAINMENT_FEATURE_BAPM;
 627                         }
 628
 629                         if (pi->enable_tdc_limit_feature) {
 630                                 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_TDCLimitEnable);
 631                                 if (smc_result != PPSMC_Result_OK)
 632                                         ret = -EINVAL;
 633                                 else
 634                                         pi->power_containment_features |= POWERCONTAINMENT_FEATURE_TDCLimit;
 635                         }
 636
 637                         if (pi->enable_pkg_pwr_tracking_feature) {
 638                                 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_PkgPwrLimitEnable);
 639                                 if (smc_result != PPSMC_Result_OK) {
 640                                         ret = -EINVAL;
 641                                 } else {
 642                                         struct radeon_cac_tdp_table *cac_tdp_table =
 643                                                 rdev->pm.dpm.dyn_state.cac_tdp_table;
 644                                         u32 default_pwr_limit =
 645                                                 (u32)(cac_tdp_table->maximum_power_delivery_limit * 256);
 646
 647                                         pi->power_containment_features |= POWERCONTAINMENT_FEATURE_PkgPwrLimit;
 648
 649                                         ci_set_power_limit(rdev, default_pwr_limit);
 650                                 }
 651                         }
 652                 }
 653         } else {
 654                 if (pi->caps_power_containment && pi->power_containment_features) {
 655                         if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_TDCLimit)
 656                                 ci_send_msg_to_smc(rdev, PPSMC_MSG_TDCLimitDisable);
 657
 658                         if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_BAPM)
 659                                 ci_send_msg_to_smc(rdev, PPSMC_MSG_DisableDTE);
 660
 661                         if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_PkgPwrLimit)
 662                                 ci_send_msg_to_smc(rdev, PPSMC_MSG_PkgPwrLimitDisable);
 663                         pi->power_containment_features = 0;
 664                 }
 665         }
 666
 667         return ret;
 668 }
 669
 670 static int ci_enable_smc_cac(struct radeon_device *rdev, bool enable)
 671 {
 672         struct ci_power_info *pi = ci_get_pi(rdev);
 673         PPSMC_Result smc_result;
 674         int ret = 0;
 675
 676         if (pi->caps_cac) {
 677                 if (enable) {
 678                         smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_EnableCac);
 679                         if (smc_result != PPSMC_Result_OK) {
 680                                 ret = -EINVAL;
 681                                 pi->cac_enabled = false;
 682                         } else {
 683                                 pi->cac_enabled = true;
 684                         }
 685                 } else if (pi->cac_enabled) {
 686                         ci_send_msg_to_smc(rdev, PPSMC_MSG_DisableCac);
 687                         pi->cac_enabled = false;
 688                 }
 689         }
 690
 691         return ret;
 692 }
 693
 694 static int ci_power_control_set_level(struct radeon_device *rdev)
 695 {
 696         struct ci_power_info *pi = ci_get_pi(rdev);
 697         struct radeon_cac_tdp_table *cac_tdp_table =
 698                 rdev->pm.dpm.dyn_state.cac_tdp_table;
 699         s32 adjust_percent;
 700         s32 target_tdp;
 701         int ret = 0;
 702         bool adjust_polarity = false; /* ??? */
 703
 704         if (pi->caps_power_containment &&
 705             (pi->power_containment_features & POWERCONTAINMENT_FEATURE_BAPM)) {
 706                 adjust_percent = adjust_polarity ?
 707                         rdev->pm.dpm.tdp_adjustment : (-1 * rdev->pm.dpm.tdp_adjustment);
 708                 target_tdp = ((100 + adjust_percent) *
 709                               (s32)cac_tdp_table->configurable_tdp) / 100;
 710                 target_tdp *= 256;
 711
 712                 ret = ci_set_overdrive_target_tdp(rdev, (u32)target_tdp);
 713         }
 714
 715         return ret;
 716 }
 717
 718 void ci_dpm_powergate_uvd(struct radeon_device *rdev, bool gate)
 719 {
 720         struct ci_power_info *pi = ci_get_pi(rdev);
 721
 722         if (pi->uvd_power_gated == gate)
 723                 return;
 724
 725         pi->uvd_power_gated = gate;
 726
 727         ci_update_uvd_dpm(rdev, gate);
 728 }
 729
 730 bool ci_dpm_vblank_too_short(struct radeon_device *rdev)
 731 {
 732         struct ci_power_info *pi = ci_get_pi(rdev);
 733         u32 vblank_time = r600_dpm_get_vblank_time(rdev);
 734         u32 switch_limit = pi->mem_gddr5 ? 450 : 300;
 735
 736         if (vblank_time < switch_limit)
 737                 return true;
 738         else
 739                 return false;
 740
 741 }
 742
 743 static void ci_apply_state_adjust_rules(struct radeon_device *rdev,
 744                                         struct radeon_ps *rps)
 745 {
 746         struct ci_ps *ps = ci_get_ps(rps);
 747         struct ci_power_info *pi = ci_get_pi(rdev);
 748         struct radeon_clock_and_voltage_limits *max_limits;
 749         bool disable_mclk_switching;
 750         u32 sclk, mclk;
 751         u32 max_sclk_vddc, max_mclk_vddci, max_mclk_vddc;
 752         int i;
 753
 754         if (rps->vce_active) {
 755                 rps->evclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].evclk;
 756                 rps->ecclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].ecclk;
 757         } else {
 758                 rps->evclk = 0;
 759                 rps->ecclk = 0;
 760         }
 761
 762         if ((rdev->pm.dpm.new_active_crtc_count > 1) ||
 763             ci_dpm_vblank_too_short(rdev))
 764                 disable_mclk_switching = true;
 765         else
 766                 disable_mclk_switching = false;
 767
 768         if ((rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) == ATOM_PPLIB_CLASSIFICATION_UI_BATTERY)
 769                 pi->battery_state = true;
 770         else
 771                 pi->battery_state = false;
 772
 773         if (rdev->pm.dpm.ac_power)
 774                 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
 775         else
 776                 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
 777
 778         if (rdev->pm.dpm.ac_power == false) {
 779                 for (i = 0; i < ps->performance_level_count; i++) {
 780                         if (ps->performance_levels[i].mclk > max_limits->mclk)
 781                                 ps->performance_levels[i].mclk = max_limits->mclk;
 782                         if (ps->performance_levels[i].sclk > max_limits->sclk)
 783                                 ps->performance_levels[i].sclk = max_limits->sclk;
 784                 }
 785         }
 786
 787         /* limit clocks to max supported clocks based on voltage dependency tables */
 788         btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk,
 789                                                         &max_sclk_vddc);
 790         btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
 791                                                         &max_mclk_vddci);
 792         btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
 793                                                         &max_mclk_vddc);
 794
 795         for (i = 0; i < ps->performance_level_count; i++) {
 796                 if (max_sclk_vddc) {
 797                         if (ps->performance_levels[i].sclk > max_sclk_vddc)
 798                                 ps->performance_levels[i].sclk = max_sclk_vddc;
 799                 }
 800                 if (max_mclk_vddci) {
 801                         if (ps->performance_levels[i].mclk > max_mclk_vddci)
 802                                 ps->performance_levels[i].mclk = max_mclk_vddci;
 803                 }
 804                 if (max_mclk_vddc) {
 805                         if (ps->performance_levels[i].mclk > max_mclk_vddc)
 806                                 ps->performance_levels[i].mclk = max_mclk_vddc;
 807                 }
 808         }
 809
 810         /* XXX validate the min clocks required for display */
 811
 812         if (disable_mclk_switching) {
 813                 mclk  = ps->performance_levels[ps->performance_level_count - 1].mclk;
 814                 sclk = ps->performance_levels[0].sclk;
 815         } else {
 816                 mclk = ps->performance_levels[0].mclk;
 817                 sclk = ps->performance_levels[0].sclk;
 818         }
 819
 820         if (rps->vce_active) {
 821                 if (sclk < rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].sclk)
 822                         sclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].sclk;
 823                 if (mclk < rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].mclk)
 824                         mclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].mclk;
 825         }
 826
 827         ps->performance_levels[0].sclk = sclk;
 828         ps->performance_levels[0].mclk = mclk;
 829
 830         if (ps->performance_levels[1].sclk < ps->performance_levels[0].sclk)
 831                 ps->performance_levels[1].sclk = ps->performance_levels[0].sclk;
 832
 833         if (disable_mclk_switching) {
 834                 if (ps->performance_levels[0].mclk < ps->performance_levels[1].mclk)
 835                         ps->performance_levels[0].mclk = ps->performance_levels[1].mclk;
 836         } else {
 837                 if (ps->performance_levels[1].mclk < ps->performance_levels[0].mclk)
 838                         ps->performance_levels[1].mclk = ps->performance_levels[0].mclk;
 839         }
 840 }
 841
 842 static int ci_set_thermal_temperature_range(struct radeon_device *rdev,
 843                                             int min_temp, int max_temp)
 844 {
 845         int low_temp = 0 * 1000;
 846         int high_temp = 255 * 1000;
 847         u32 tmp;
 848
 849         if (low_temp < min_temp)
 850                 low_temp = min_temp;
 851         if (high_temp > max_temp)
 852                 high_temp = max_temp;
 853         if (high_temp < low_temp) {
 854                 DRM_ERROR("invalid thermal range: %d - %d\n", low_temp, high_temp);
 855                 return -EINVAL;
 856         }
 857
 858         tmp = RREG32_SMC(CG_THERMAL_INT);
 859         tmp &= ~(CI_DIG_THERM_INTH_MASK | CI_DIG_THERM_INTL_MASK);
 860         tmp |= CI_DIG_THERM_INTH(high_temp / 1000) |
 861                 CI_DIG_THERM_INTL(low_temp / 1000);
 862         WREG32_SMC(CG_THERMAL_INT, tmp);
 863
 864 #if 0
 865         /* XXX: need to figure out how to handle this properly */
 866         tmp = RREG32_SMC(CG_THERMAL_CTRL);
 867         tmp &= DIG_THERM_DPM_MASK;
 868         tmp |= DIG_THERM_DPM(high_temp / 1000);
 869         WREG32_SMC(CG_THERMAL_CTRL, tmp);
 870 #endif
 871
 872         return 0;
 873 }
 874
 875 #if 0
 876 static int ci_read_smc_soft_register(struct radeon_device *rdev,
 877                                      u16 reg_offset, u32 *value)
 878 {
 879         struct ci_power_info *pi = ci_get_pi(rdev);
 880
 881         return ci_read_smc_sram_dword(rdev,
 882                                       pi->soft_regs_start + reg_offset,
 883                                       value, pi->sram_end);
 884 }
 885 #endif
 886
 887 static int ci_write_smc_soft_register(struct radeon_device *rdev,
 888                                       u16 reg_offset, u32 value)
 889 {
 890         struct ci_power_info *pi = ci_get_pi(rdev);
 891
 892         return ci_write_smc_sram_dword(rdev,
 893                                        pi->soft_regs_start + reg_offset,
 894                                        value, pi->sram_end);
 895 }
 896
 897 static void ci_init_fps_limits(struct radeon_device *rdev)
 898 {
 899         struct ci_power_info *pi = ci_get_pi(rdev);
 900         SMU7_Discrete_DpmTable *table = &pi->smc_state_table;
 901
 902         if (pi->caps_fps) {
 903                 u16 tmp;
 904
 905                 tmp = 45;
 906                 table->FpsHighT = cpu_to_be16(tmp);
 907
 908                 tmp = 30;
 909                 table->FpsLowT = cpu_to_be16(tmp);
 910         }
 911 }
 912
 913 static int ci_update_sclk_t(struct radeon_device *rdev)
 914 {
 915         struct ci_power_info *pi = ci_get_pi(rdev);
 916         int ret = 0;
 917         u32 low_sclk_interrupt_t = 0;
 918
 919         if (pi->caps_sclk_throttle_low_notification) {
 920                 low_sclk_interrupt_t = cpu_to_be32(pi->low_sclk_interrupt_t);
 921
 922                 ret = ci_copy_bytes_to_smc(rdev,
 923                                            pi->dpm_table_start +
 924                                            offsetof(SMU7_Discrete_DpmTable, LowSclkInterruptT),
 925                                            (u8 *)&low_sclk_interrupt_t,
 926                                            sizeof(u32), pi->sram_end);
 927
 928         }
 929
 930         return ret;
 931 }
 932
 933 static void ci_get_leakage_voltages(struct radeon_device *rdev)
 934 {
 935         struct ci_power_info *pi = ci_get_pi(rdev);
 936         u16 leakage_id, virtual_voltage_id;
 937         u16 vddc, vddci;
 938         int i;
 939
 940         pi->vddc_leakage.count = 0;
 941         pi->vddci_leakage.count = 0;
 942
 943         if (radeon_atom_get_leakage_id_from_vbios(rdev, &leakage_id) == 0) {
 944                 for (i = 0; i < CISLANDS_MAX_LEAKAGE_COUNT; i++) {
 945                         virtual_voltage_id = ATOM_VIRTUAL_VOLTAGE_ID0 + i;
 946                         if (radeon_atom_get_leakage_vddc_based_on_leakage_params(rdev, &vddc, &vddci,
 947                                                                                  virtual_voltage_id,
 948                                                                                  leakage_id) == 0) {
 949                                 if (vddc != 0 && vddc != virtual_voltage_id) {
 950                                         pi->vddc_leakage.actual_voltage[pi->vddc_leakage.count] = vddc;
 951                                         pi->vddc_leakage.leakage_id[pi->vddc_leakage.count] = virtual_voltage_id;
 952                                         pi->vddc_leakage.count++;
 953                                 }
 954                                 if (vddci != 0 && vddci != virtual_voltage_id) {
 955                                         pi->vddci_leakage.actual_voltage[pi->vddci_leakage.count] = vddci;
 956                                         pi->vddci_leakage.leakage_id[pi->vddci_leakage.count] = virtual_voltage_id;
 957                                         pi->vddci_leakage.count++;
 958                                 }
 959                         }
 960                 }
 961         }
 962 }
 963
 964 static void ci_set_dpm_event_sources(struct radeon_device *rdev, u32 sources)
 965 {
 966         struct ci_power_info *pi = ci_get_pi(rdev);
 967         bool want_thermal_protection;
 968         enum radeon_dpm_event_src dpm_event_src;
 969         u32 tmp;
 970
 971         switch (sources) {
 972         case 0:
 973         default:
 974                 want_thermal_protection = false;
 975                 break;
 976         case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL):
 977                 want_thermal_protection = true;
 978                 dpm_event_src = RADEON_DPM_EVENT_SRC_DIGITAL;
 979                 break;
 980         case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL):
 981                 want_thermal_protection = true;
 982                 dpm_event_src = RADEON_DPM_EVENT_SRC_EXTERNAL;
 983                 break;
 984         case ((1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL) |
 985               (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL)):
 986                 want_thermal_protection = true;
 987                 dpm_event_src = RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL;
 988                 break;
 989         }
 990
 991         if (want_thermal_protection) {
 992 #if 0
 993                 /* XXX: need to figure out how to handle this properly */
 994                 tmp = RREG32_SMC(CG_THERMAL_CTRL);
 995                 tmp &= DPM_EVENT_SRC_MASK;
 996                 tmp |= DPM_EVENT_SRC(dpm_event_src);
 997                 WREG32_SMC(CG_THERMAL_CTRL, tmp);
 998 #endif
 999
1000                 tmp = RREG32_SMC(GENERAL_PWRMGT);
1001                 if (pi->thermal_protection)
1002                         tmp &= ~THERMAL_PROTECTION_DIS;
1003                 else
1004                         tmp |= THERMAL_PROTECTION_DIS;
1005                 WREG32_SMC(GENERAL_PWRMGT, tmp);
1006         } else {
1007                 tmp = RREG32_SMC(GENERAL_PWRMGT);
1008                 tmp |= THERMAL_PROTECTION_DIS;
1009                 WREG32_SMC(GENERAL_PWRMGT, tmp);
1010         }
1011 }
1012
1013 static void ci_enable_auto_throttle_source(struct radeon_device *rdev,
1014                                            enum radeon_dpm_auto_throttle_src source,
1015                                            bool enable)
1016 {
1017         struct ci_power_info *pi = ci_get_pi(rdev);
1018
1019         if (enable) {
1020                 if (!(pi->active_auto_throttle_sources & (1 << source))) {
1021                         pi->active_auto_throttle_sources |= 1 << source;
1022                         ci_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources);
1023                 }
1024         } else {
1025                 if (pi->active_auto_throttle_sources & (1 << source)) {
1026                         pi->active_auto_throttle_sources &= ~(1 << source);
1027                         ci_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources);
1028                 }
1029         }
1030 }
1031
1032 static void ci_enable_vr_hot_gpio_interrupt(struct radeon_device *rdev)
1033 {
1034         if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REGULATOR_HOT)
1035                 ci_send_msg_to_smc(rdev, PPSMC_MSG_EnableVRHotGPIOInterrupt);
1036 }
1037
1038 static int ci_unfreeze_sclk_mclk_dpm(struct radeon_device *rdev)
1039 {
1040         struct ci_power_info *pi = ci_get_pi(rdev);
1041         PPSMC_Result smc_result;
1042
1043         if (!pi->need_update_smu7_dpm_table)
1044                 return 0;
1045
1046         if ((!pi->sclk_dpm_key_disabled) &&
1047             (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK))) {
1048                 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_SCLKDPM_UnfreezeLevel);
1049                 if (smc_result != PPSMC_Result_OK)
1050                         return -EINVAL;
1051         }
1052
1053         if ((!pi->mclk_dpm_key_disabled) &&
1054             (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) {
1055                 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_MCLKDPM_UnfreezeLevel);
1056                 if (smc_result != PPSMC_Result_OK)
1057                         return -EINVAL;
1058         }
1059
1060         pi->need_update_smu7_dpm_table = 0;
1061         return 0;
1062 }
1063
1064 static int ci_enable_sclk_mclk_dpm(struct radeon_device *rdev, bool enable)
1065 {
1066         struct ci_power_info *pi = ci_get_pi(rdev);
1067         PPSMC_Result smc_result;
1068
1069         if (enable) {
1070                 if (!pi->sclk_dpm_key_disabled) {
1071                         smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_DPM_Enable);
1072                         if (smc_result != PPSMC_Result_OK)
1073                                 return -EINVAL;
1074                 }
1075
1076                 if (!pi->mclk_dpm_key_disabled) {
1077                         smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_MCLKDPM_Enable);
1078                         if (smc_result != PPSMC_Result_OK)
1079                                 return -EINVAL;
1080
1081                         WREG32_P(MC_SEQ_CNTL_3, CAC_EN, ~CAC_EN);
1082
1083                         WREG32_SMC(LCAC_MC0_CNTL, 0x05);
1084                         WREG32_SMC(LCAC_MC1_CNTL, 0x05);
1085                         WREG32_SMC(LCAC_CPL_CNTL, 0x100005);
1086
1087                         udelay(10);
1088
1089                         WREG32_SMC(LCAC_MC0_CNTL, 0x400005);
1090                         WREG32_SMC(LCAC_MC1_CNTL, 0x400005);
1091                         WREG32_SMC(LCAC_CPL_CNTL, 0x500005);
1092                 }
1093         } else {
1094                 if (!pi->sclk_dpm_key_disabled) {
1095                         smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_DPM_Disable);
1096                         if (smc_result != PPSMC_Result_OK)
1097                                 return -EINVAL;
1098                 }
1099
1100                 if (!pi->mclk_dpm_key_disabled) {
1101                         smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_MCLKDPM_Disable);
1102                         if (smc_result != PPSMC_Result_OK)
1103                                 return -EINVAL;
1104                 }
1105         }
1106
1107         return 0;
1108 }
1109
1110 static int ci_start_dpm(struct radeon_device *rdev)
1111 {
1112         struct ci_power_info *pi = ci_get_pi(rdev);
1113         PPSMC_Result smc_result;
1114         int ret;
1115         u32 tmp;
1116
1117         tmp = RREG32_SMC(GENERAL_PWRMGT);
1118         tmp |= GLOBAL_PWRMGT_EN;
1119         WREG32_SMC(GENERAL_PWRMGT, tmp);
1120
1121         tmp = RREG32_SMC(SCLK_PWRMGT_CNTL);
1122         tmp |= DYNAMIC_PM_EN;
1123         WREG32_SMC(SCLK_PWRMGT_CNTL, tmp);
1124
1125         ci_write_smc_soft_register(rdev, offsetof(SMU7_SoftRegisters, VoltageChangeTimeout), 0x1000);
1126
1127         WREG32_P(BIF_LNCNT_RESET, 0, ~RESET_LNCNT_EN);
1128
1129         smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_Voltage_Cntl_Enable);
1130         if (smc_result != PPSMC_Result_OK)
1131                 return -EINVAL;
1132
1133         ret = ci_enable_sclk_mclk_dpm(rdev, true);
1134         if (ret)
1135                 return ret;
1136
1137         if (!pi->pcie_dpm_key_disabled) {
1138                 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_PCIeDPM_Enable);
1139                 if (smc_result != PPSMC_Result_OK)
1140                         return -EINVAL;
1141         }
1142
1143         return 0;
1144 }
1145
1146 static int ci_freeze_sclk_mclk_dpm(struct radeon_device *rdev)
1147 {
1148         struct ci_power_info *pi = ci_get_pi(rdev);
1149         PPSMC_Result smc_result;
1150
1151         if (!pi->need_update_smu7_dpm_table)
1152                 return 0;
1153
1154         if ((!pi->sclk_dpm_key_disabled) &&
1155             (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK))) {
1156                 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_SCLKDPM_FreezeLevel);
1157                 if (smc_result != PPSMC_Result_OK)
1158                         return -EINVAL;
1159         }
1160
1161         if ((!pi->mclk_dpm_key_disabled) &&
1162             (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) {
1163                 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_MCLKDPM_FreezeLevel);
1164                 if (smc_result != PPSMC_Result_OK)
1165                         return -EINVAL;
1166         }
1167
1168         return 0;
1169 }
1170
1171 static int ci_stop_dpm(struct radeon_device *rdev)
1172 {
1173         struct ci_power_info *pi = ci_get_pi(rdev);
1174         PPSMC_Result smc_result;
1175         int ret;
1176         u32 tmp;
1177
1178         tmp = RREG32_SMC(GENERAL_PWRMGT);
1179         tmp &= ~GLOBAL_PWRMGT_EN;
1180         WREG32_SMC(GENERAL_PWRMGT, tmp);
1181
1182         tmp = RREG32(SCLK_PWRMGT_CNTL);
1183         tmp &= ~DYNAMIC_PM_EN;
1184         WREG32_SMC(SCLK_PWRMGT_CNTL, tmp);
1185
1186         if (!pi->pcie_dpm_key_disabled) {
1187                 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_PCIeDPM_Disable);
1188                 if (smc_result != PPSMC_Result_OK)
1189                         return -EINVAL;
1190         }
1191
1192         ret = ci_enable_sclk_mclk_dpm(rdev, false);
1193         if (ret)
1194                 return ret;
1195
1196         smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_Voltage_Cntl_Disable);
1197         if (smc_result != PPSMC_Result_OK)
1198                 return -EINVAL;
1199
1200         return 0;
1201 }
1202
1203 static void ci_enable_sclk_control(struct radeon_device *rdev, bool enable)
1204 {
1205         u32 tmp = RREG32_SMC(SCLK_PWRMGT_CNTL);
1206
1207         if (enable)
1208                 tmp &= ~SCLK_PWRMGT_OFF;
1209         else
1210                 tmp |= SCLK_PWRMGT_OFF;
1211         WREG32_SMC(SCLK_PWRMGT_CNTL, tmp);
1212 }
1213
1214 #if 0
1215 static int ci_notify_hw_of_power_source(struct radeon_device *rdev,
1216                                         bool ac_power)
1217 {
1218         struct ci_power_info *pi = ci_get_pi(rdev);
1219         struct radeon_cac_tdp_table *cac_tdp_table =
1220                 rdev->pm.dpm.dyn_state.cac_tdp_table;
1221         u32 power_limit;
1222
1223         if (ac_power)
1224                 power_limit = (u32)(cac_tdp_table->maximum_power_delivery_limit * 256);
1225         else
1226                 power_limit = (u32)(cac_tdp_table->battery_power_limit * 256);
1227
1228         ci_set_power_limit(rdev, power_limit);
1229
1230         if (pi->caps_automatic_dc_transition) {
1231                 if (ac_power)
1232                         ci_send_msg_to_smc(rdev, PPSMC_MSG_RunningOnAC);
1233                 else
1234                         ci_send_msg_to_smc(rdev, PPSMC_MSG_Remove_DC_Clamp);
1235         }
1236
1237         return 0;
1238 }
1239 #endif
1240
1241 static PPSMC_Result ci_send_msg_to_smc_with_parameter(struct radeon_device *rdev,
1242                                                       PPSMC_Msg msg, u32 parameter)
1243 {
1244         WREG32(SMC_MSG_ARG_0, parameter);
1245         return ci_send_msg_to_smc(rdev, msg);
1246 }
1247
1248 static PPSMC_Result ci_send_msg_to_smc_return_parameter(struct radeon_device *rdev,
1249                                                         PPSMC_Msg msg, u32 *parameter)
1250 {
1251         PPSMC_Result smc_result;
1252
1253         smc_result = ci_send_msg_to_smc(rdev, msg);
1254
1255         if ((smc_result == PPSMC_Result_OK) && parameter)
1256                 *parameter = RREG32(SMC_MSG_ARG_0);
1257
1258         return smc_result;
1259 }
1260
1261 static int ci_dpm_force_state_sclk(struct radeon_device *rdev, u32 n)
1262 {
1263         struct ci_power_info *pi = ci_get_pi(rdev);
1264
1265         if (!pi->sclk_dpm_key_disabled) {
1266                 PPSMC_Result smc_result =
1267                         ci_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_DPM_ForceState, n);
1268                 if (smc_result != PPSMC_Result_OK)
1269                         return -EINVAL;
1270         }
1271
1272         return 0;
1273 }
1274
1275 static int ci_dpm_force_state_mclk(struct radeon_device *rdev, u32 n)
1276 {
1277         struct ci_power_info *pi = ci_get_pi(rdev);
1278
1279         if (!pi->mclk_dpm_key_disabled) {
1280                 PPSMC_Result smc_result =
1281                         ci_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_MCLKDPM_ForceState, n);
1282                 if (smc_result != PPSMC_Result_OK)
1283                         return -EINVAL;
1284         }
1285
1286         return 0;
1287 }
1288
1289 static int ci_dpm_force_state_pcie(struct radeon_device *rdev, u32 n)
1290 {
1291         struct ci_power_info *pi = ci_get_pi(rdev);
1292
1293         if (!pi->pcie_dpm_key_disabled) {
1294                 PPSMC_Result smc_result =
1295                         ci_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_PCIeDPM_ForceLevel, n);
1296                 if (smc_result != PPSMC_Result_OK)
1297                         return -EINVAL;
1298         }
1299
1300         return 0;
1301 }
1302
1303 static int ci_set_power_limit(struct radeon_device *rdev, u32 n)
1304 {
1305         struct ci_power_info *pi = ci_get_pi(rdev);
1306
1307         if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_PkgPwrLimit) {
1308                 PPSMC_Result smc_result =
1309                         ci_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_PkgPwrSetLimit, n);
1310                 if (smc_result != PPSMC_Result_OK)
1311                         return -EINVAL;
1312         }
1313
1314         return 0;
1315 }
1316
1317 static int ci_set_overdrive_target_tdp(struct radeon_device *rdev,
1318                                        u32 target_tdp)
1319 {
1320         PPSMC_Result smc_result =
1321                 ci_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_OverDriveSetTargetTdp, target_tdp);
1322         if (smc_result != PPSMC_Result_OK)
1323                 return -EINVAL;
1324         return 0;
1325 }
1326
1327 static int ci_set_boot_state(struct radeon_device *rdev)
1328 {
1329         return ci_enable_sclk_mclk_dpm(rdev, false);
1330 }
1331
1332 static u32 ci_get_average_sclk_freq(struct radeon_device *rdev)
1333 {
1334         u32 sclk_freq;
1335         PPSMC_Result smc_result =
1336                 ci_send_msg_to_smc_return_parameter(rdev,
1337                                                     PPSMC_MSG_API_GetSclkFrequency,
1338                                                     &sclk_freq);
1339         if (smc_result != PPSMC_Result_OK)
1340                 sclk_freq = 0;
1341
1342         return sclk_freq;
1343 }
1344
1345 static u32 ci_get_average_mclk_freq(struct radeon_device *rdev)
1346 {
1347         u32 mclk_freq;
1348         PPSMC_Result smc_result =
1349                 ci_send_msg_to_smc_return_parameter(rdev,
1350                                                     PPSMC_MSG_API_GetMclkFrequency,
1351                                                     &mclk_freq);
1352         if (smc_result != PPSMC_Result_OK)
1353                 mclk_freq = 0;
1354
1355         return mclk_freq;
1356 }
1357
1358 static void ci_dpm_start_smc(struct radeon_device *rdev)
1359 {
1360         int i;
1361
1362         ci_program_jump_on_start(rdev);
1363         ci_start_smc_clock(rdev);
1364         ci_start_smc(rdev);
1365         for (i = 0; i < rdev->usec_timeout; i++) {
1366                 if (RREG32_SMC(FIRMWARE_FLAGS) & INTERRUPTS_ENABLED)
1367                         break;
1368         }
1369 }
1370
1371 static void ci_dpm_stop_smc(struct radeon_device *rdev)
1372 {
1373         ci_reset_smc(rdev);
1374         ci_stop_smc_clock(rdev);
1375 }
1376
1377 static int ci_process_firmware_header(struct radeon_device *rdev)
1378 {
1379         struct ci_power_info *pi = ci_get_pi(rdev);
1380         u32 tmp;
1381         int ret;
1382
1383         ret = ci_read_smc_sram_dword(rdev,
1384                                      SMU7_FIRMWARE_HEADER_LOCATION +
1385                                      offsetof(SMU7_Firmware_Header, DpmTable),
1386                                      &tmp, pi->sram_end);
1387         if (ret)
1388                 return ret;
1389
1390         pi->dpm_table_start = tmp;
1391
1392         ret = ci_read_smc_sram_dword(rdev,
1393                                      SMU7_FIRMWARE_HEADER_LOCATION +
1394                                      offsetof(SMU7_Firmware_Header, SoftRegisters),
1395                                      &tmp, pi->sram_end);
1396         if (ret)
1397                 return ret;
1398
1399         pi->soft_regs_start = tmp;
1400
1401         ret = ci_read_smc_sram_dword(rdev,
1402                                      SMU7_FIRMWARE_HEADER_LOCATION +
1403                                      offsetof(SMU7_Firmware_Header, mcRegisterTable),
1404                                      &tmp, pi->sram_end);
1405         if (ret)
1406                 return ret;
1407
1408         pi->mc_reg_table_start = tmp;
1409
1410         ret = ci_read_smc_sram_dword(rdev,
1411                                      SMU7_FIRMWARE_HEADER_LOCATION +
1412                                      offsetof(SMU7_Firmware_Header, FanTable),
1413                                      &tmp, pi->sram_end);
1414         if (ret)
1415                 return ret;
1416
1417         pi->fan_table_start = tmp;
1418
1419         ret = ci_read_smc_sram_dword(rdev,
1420                                      SMU7_FIRMWARE_HEADER_LOCATION +
1421                                      offsetof(SMU7_Firmware_Header, mcArbDramTimingTable),
1422                                      &tmp, pi->sram_end);
1423         if (ret)
1424                 return ret;
1425
1426         pi->arb_table_start = tmp;
1427
1428         return 0;
1429 }
1430
1431 static void ci_read_clock_registers(struct radeon_device *rdev)
1432 {
1433         struct ci_power_info *pi = ci_get_pi(rdev);
1434
1435         pi->clock_registers.cg_spll_func_cntl =
1436                 RREG32_SMC(CG_SPLL_FUNC_CNTL);
1437         pi->clock_registers.cg_spll_func_cntl_2 =
1438                 RREG32_SMC(CG_SPLL_FUNC_CNTL_2);
1439         pi->clock_registers.cg_spll_func_cntl_3 =
1440                 RREG32_SMC(CG_SPLL_FUNC_CNTL_3);
1441         pi->clock_registers.cg_spll_func_cntl_4 =
1442                 RREG32_SMC(CG_SPLL_FUNC_CNTL_4);
1443         pi->clock_registers.cg_spll_spread_spectrum =
1444                 RREG32_SMC(CG_SPLL_SPREAD_SPECTRUM);
1445         pi->clock_registers.cg_spll_spread_spectrum_2 =
1446                 RREG32_SMC(CG_SPLL_SPREAD_SPECTRUM_2);
1447         pi->clock_registers.dll_cntl = RREG32(DLL_CNTL);
1448         pi->clock_registers.mclk_pwrmgt_cntl = RREG32(MCLK_PWRMGT_CNTL);
1449         pi->clock_registers.mpll_ad_func_cntl = RREG32(MPLL_AD_FUNC_CNTL);
1450         pi->clock_registers.mpll_dq_func_cntl = RREG32(MPLL_DQ_FUNC_CNTL);
1451         pi->clock_registers.mpll_func_cntl = RREG32(MPLL_FUNC_CNTL);
1452         pi->clock_registers.mpll_func_cntl_1 = RREG32(MPLL_FUNC_CNTL_1);
1453         pi->clock_registers.mpll_func_cntl_2 = RREG32(MPLL_FUNC_CNTL_2);
1454         pi->clock_registers.mpll_ss1 = RREG32(MPLL_SS1);
1455         pi->clock_registers.mpll_ss2 = RREG32(MPLL_SS2);
1456 }
1457
1458 static void ci_init_sclk_t(struct radeon_device *rdev)
1459 {
1460         struct ci_power_info *pi = ci_get_pi(rdev);
1461
1462         pi->low_sclk_interrupt_t = 0;
1463 }
1464
1465 static void ci_enable_thermal_protection(struct radeon_device *rdev,
1466                                          bool enable)
1467 {
1468         u32 tmp = RREG32_SMC(GENERAL_PWRMGT);
1469
1470         if (enable)
1471                 tmp &= ~THERMAL_PROTECTION_DIS;
1472         else
1473                 tmp |= THERMAL_PROTECTION_DIS;
1474         WREG32_SMC(GENERAL_PWRMGT, tmp);
1475 }
1476
1477 static void ci_enable_acpi_power_management(struct radeon_device *rdev)
1478 {
1479         u32 tmp = RREG32_SMC(GENERAL_PWRMGT);
1480
1481         tmp |= STATIC_PM_EN;
1482
1483         WREG32_SMC(GENERAL_PWRMGT, tmp);
1484 }
1485
1486 #if 0
1487 static int ci_enter_ulp_state(struct radeon_device *rdev)
1488 {
1489
1490         WREG32(SMC_MESSAGE_0, PPSMC_MSG_SwitchToMinimumPower);
1491
1492         udelay(25000);
1493
1494         return 0;
1495 }
1496
1497 static int ci_exit_ulp_state(struct radeon_device *rdev)
1498 {
1499         int i;
1500
1501         WREG32(SMC_MESSAGE_0, PPSMC_MSG_ResumeFromMinimumPower);
1502
1503         udelay(7000);
1504
1505         for (i = 0; i < rdev->usec_timeout; i++) {
1506                 if (RREG32(SMC_RESP_0) == 1)
1507                         break;
1508                 udelay(1000);
1509         }
1510
1511         return 0;
1512 }
1513 #endif
1514
1515 static int ci_notify_smc_display_change(struct radeon_device *rdev,
1516                                         bool has_display)
1517 {
1518         PPSMC_Msg msg = has_display ? PPSMC_MSG_HasDisplay : PPSMC_MSG_NoDisplay;
1519
1520         return (ci_send_msg_to_smc(rdev, msg) == PPSMC_Result_OK) ?  0 : -EINVAL;
1521 }
1522
1523 static int ci_enable_ds_master_switch(struct radeon_device *rdev,
1524                                       bool enable)
1525 {
1526         struct ci_power_info *pi = ci_get_pi(rdev);
1527
1528         if (enable) {
1529                 if (pi->caps_sclk_ds) {
1530                         if (ci_send_msg_to_smc(rdev, PPSMC_MSG_MASTER_DeepSleep_ON) != PPSMC_Result_OK)
1531                                 return -EINVAL;
1532                 } else {
1533                         if (ci_send_msg_to_smc(rdev, PPSMC_MSG_MASTER_DeepSleep_OFF) != PPSMC_Result_OK)
1534                                 return -EINVAL;
1535                 }
1536         } else {
1537                 if (pi->caps_sclk_ds) {
1538                         if (ci_send_msg_to_smc(rdev, PPSMC_MSG_MASTER_DeepSleep_OFF) != PPSMC_Result_OK)
1539                                 return -EINVAL;
1540                 }
1541         }
1542
1543         return 0;
1544 }
1545
1546 static void ci_program_display_gap(struct radeon_device *rdev)
1547 {
1548         u32 tmp = RREG32_SMC(CG_DISPLAY_GAP_CNTL);
1549         u32 pre_vbi_time_in_us;
1550         u32 frame_time_in_us;
1551         u32 ref_clock = rdev->clock.spll.reference_freq;
1552         u32 refresh_rate = r600_dpm_get_vrefresh(rdev);
1553         u32 vblank_time = r600_dpm_get_vblank_time(rdev);
1554
1555         tmp &= ~DISP_GAP_MASK;
1556         if (rdev->pm.dpm.new_active_crtc_count > 0)
1557                 tmp |= DISP_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM);
1558         else
1559                 tmp |= DISP_GAP(R600_PM_DISPLAY_GAP_IGNORE);
1560         WREG32_SMC(CG_DISPLAY_GAP_CNTL, tmp);
1561
1562         if (refresh_rate == 0)
1563                 refresh_rate = 60;
1564         if (vblank_time == 0xffffffff)
1565                 vblank_time = 500;
1566         frame_time_in_us = 1000000 / refresh_rate;
1567         pre_vbi_time_in_us =
1568                 frame_time_in_us - 200 - vblank_time;
1569         tmp = pre_vbi_time_in_us * (ref_clock / 100);
1570
1571         WREG32_SMC(CG_DISPLAY_GAP_CNTL2, tmp);
1572         ci_write_smc_soft_register(rdev, offsetof(SMU7_SoftRegisters, PreVBlankGap), 0x64);
1573         ci_write_smc_soft_register(rdev, offsetof(SMU7_SoftRegisters, VBlankTimeout), (frame_time_in_us - pre_vbi_time_in_us));
1574
1575
1576         ci_notify_smc_display_change(rdev, (rdev->pm.dpm.new_active_crtc_count == 1));
1577
1578 }
1579
1580 static void ci_enable_spread_spectrum(struct radeon_device *rdev, bool enable)
1581 {
1582         struct ci_power_info *pi = ci_get_pi(rdev);
1583         u32 tmp;
1584
1585         if (enable) {
1586                 if (pi->caps_sclk_ss_support) {
1587                         tmp = RREG32_SMC(GENERAL_PWRMGT);
1588                         tmp |= DYN_SPREAD_SPECTRUM_EN;
1589                         WREG32_SMC(GENERAL_PWRMGT, tmp);
1590                 }
1591         } else {
1592                 tmp = RREG32_SMC(CG_SPLL_SPREAD_SPECTRUM);
1593                 tmp &= ~SSEN;
1594                 WREG32_SMC(CG_SPLL_SPREAD_SPECTRUM, tmp);
1595
1596                 tmp = RREG32_SMC(GENERAL_PWRMGT);
1597                 tmp &= ~DYN_SPREAD_SPECTRUM_EN;
1598                 WREG32_SMC(GENERAL_PWRMGT, tmp);
1599         }
1600 }
1601
1602 static void ci_program_sstp(struct radeon_device *rdev)
1603 {
1604         WREG32_SMC(CG_SSP, (SSTU(R600_SSTU_DFLT) | SST(R600_SST_DFLT)));
1605 }
1606
1607 static void ci_enable_display_gap(struct radeon_device *rdev)
1608 {
1609         u32 tmp = RREG32_SMC(CG_DISPLAY_GAP_CNTL);
1610
1611         tmp &= ~(DISP_GAP_MASK | DISP_GAP_MCHG_MASK);
1612         tmp |= (DISP_GAP(R600_PM_DISPLAY_GAP_IGNORE) |
1613                 DISP_GAP_MCHG(R600_PM_DISPLAY_GAP_VBLANK));
1614
1615         WREG32_SMC(CG_DISPLAY_GAP_CNTL, tmp);
1616 }
1617
1618 static void ci_program_vc(struct radeon_device *rdev)
1619 {
1620         u32 tmp;
1621
1622         tmp = RREG32_SMC(SCLK_PWRMGT_CNTL);
1623         tmp &= ~(RESET_SCLK_CNT | RESET_BUSY_CNT);
1624         WREG32_SMC(SCLK_PWRMGT_CNTL, tmp);
1625
1626         WREG32_SMC(CG_FTV_0, CISLANDS_VRC_DFLT0);
1627         WREG32_SMC(CG_FTV_1, CISLANDS_VRC_DFLT1);
1628         WREG32_SMC(CG_FTV_2, CISLANDS_VRC_DFLT2);
1629         WREG32_SMC(CG_FTV_3, CISLANDS_VRC_DFLT3);
1630         WREG32_SMC(CG_FTV_4, CISLANDS_VRC_DFLT4);
1631         WREG32_SMC(CG_FTV_5, CISLANDS_VRC_DFLT5);
1632         WREG32_SMC(CG_FTV_6, CISLANDS_VRC_DFLT6);
1633         WREG32_SMC(CG_FTV_7, CISLANDS_VRC_DFLT7);
1634 }
1635
1636 static void ci_clear_vc(struct radeon_device *rdev)
1637 {
1638         u32 tmp;
1639
1640         tmp = RREG32_SMC(SCLK_PWRMGT_CNTL);
1641         tmp |= (RESET_SCLK_CNT | RESET_BUSY_CNT);
1642         WREG32_SMC(SCLK_PWRMGT_CNTL, tmp);
1643
1644         WREG32_SMC(CG_FTV_0, 0);
1645         WREG32_SMC(CG_FTV_1, 0);
1646         WREG32_SMC(CG_FTV_2, 0);
1647         WREG32_SMC(CG_FTV_3, 0);
1648         WREG32_SMC(CG_FTV_4, 0);
1649         WREG32_SMC(CG_FTV_5, 0);
1650         WREG32_SMC(CG_FTV_6, 0);
1651         WREG32_SMC(CG_FTV_7, 0);
1652 }
1653
1654 static int ci_upload_firmware(struct radeon_device *rdev)
1655 {
1656         struct ci_power_info *pi = ci_get_pi(rdev);
1657         int i, ret;
1658
1659         for (i = 0; i < rdev->usec_timeout; i++) {
1660                 if (RREG32_SMC(RCU_UC_EVENTS) & BOOT_SEQ_DONE)
1661                         break;
1662         }
1663         WREG32_SMC(SMC_SYSCON_MISC_CNTL, 1);
1664
1665         ci_stop_smc_clock(rdev);
1666         ci_reset_smc(rdev);
1667
1668         ret = ci_load_smc_ucode(rdev, pi->sram_end);
1669
1670         return ret;
1671
1672 }
1673
1674 static int ci_get_svi2_voltage_table(struct radeon_device *rdev,
1675                                      struct radeon_clock_voltage_dependency_table *voltage_dependency_table,
1676                                      struct atom_voltage_table *voltage_table)
1677 {
1678         u32 i;
1679
1680         if (voltage_dependency_table == NULL)
1681                 return -EINVAL;
1682
1683         voltage_table->mask_low = 0;
1684         voltage_table->phase_delay = 0;
1685
1686         voltage_table->count = voltage_dependency_table->count;
1687         for (i = 0; i < voltage_table->count; i++) {
1688                 voltage_table->entries[i].value = voltage_dependency_table->entries[i].v;
1689                 voltage_table->entries[i].smio_low = 0;
1690         }
1691
1692         return 0;
1693 }
1694
1695 static int ci_construct_voltage_tables(struct radeon_device *rdev)
1696 {
1697         struct ci_power_info *pi = ci_get_pi(rdev);
1698         int ret;
1699
1700         if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) {
1701                 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDC,
1702                                                     VOLTAGE_OBJ_GPIO_LUT,
1703                                                     &pi->vddc_voltage_table);
1704                 if (ret)
1705                         return ret;
1706         } else if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2) {
1707                 ret = ci_get_svi2_voltage_table(rdev,
1708                                                 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
1709                                                 &pi->vddc_voltage_table);
1710                 if (ret)
1711                         return ret;
1712         }
1713
1714         if (pi->vddc_voltage_table.count > SMU7_MAX_LEVELS_VDDC)
1715                 si_trim_voltage_table_to_fit_state_table(rdev, SMU7_MAX_LEVELS_VDDC,
1716                                                          &pi->vddc_voltage_table);
1717
1718         if (pi->vddci_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) {
1719                 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDCI,
1720                                                     VOLTAGE_OBJ_GPIO_LUT,
1721                                                     &pi->vddci_voltage_table);
1722                 if (ret)
1723                         return ret;
1724         } else if (pi->vddci_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2) {
1725                 ret = ci_get_svi2_voltage_table(rdev,
1726                                                 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
1727                                                 &pi->vddci_voltage_table);
1728                 if (ret)
1729                         return ret;
1730         }
1731
1732         if (pi->vddci_voltage_table.count > SMU7_MAX_LEVELS_VDDCI)
1733                 si_trim_voltage_table_to_fit_state_table(rdev, SMU7_MAX_LEVELS_VDDCI,
1734                                                          &pi->vddci_voltage_table);
1735
1736         if (pi->mvdd_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) {
1737                 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_MVDDC,
1738                                                     VOLTAGE_OBJ_GPIO_LUT,
1739                                                     &pi->mvdd_voltage_table);
1740                 if (ret)
1741                         return ret;
1742         } else if (pi->mvdd_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2) {
1743                 ret = ci_get_svi2_voltage_table(rdev,
1744                                                 &rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk,
1745                                                 &pi->mvdd_voltage_table);
1746                 if (ret)
1747                         return ret;
1748         }
1749
1750         if (pi->mvdd_voltage_table.count > SMU7_MAX_LEVELS_MVDD)
1751                 si_trim_voltage_table_to_fit_state_table(rdev, SMU7_MAX_LEVELS_MVDD,
1752                                                          &pi->mvdd_voltage_table);
1753
1754         return 0;
1755 }
1756
1757 static void ci_populate_smc_voltage_table(struct radeon_device *rdev,
1758                                           struct atom_voltage_table_entry *voltage_table,
1759                                           SMU7_Discrete_VoltageLevel *smc_voltage_table)
1760 {
1761         int ret;
1762
1763         ret = ci_get_std_voltage_value_sidd(rdev, voltage_table,
1764                                             &smc_voltage_table->StdVoltageHiSidd,
1765                                             &smc_voltage_table->StdVoltageLoSidd);
1766
1767         if (ret) {
1768                 smc_voltage_table->StdVoltageHiSidd = voltage_table->value * VOLTAGE_SCALE;
1769                 smc_voltage_table->StdVoltageLoSidd = voltage_table->value * VOLTAGE_SCALE;
1770         }
1771
1772         smc_voltage_table->Voltage = cpu_to_be16(voltage_table->value * VOLTAGE_SCALE);
1773         smc_voltage_table->StdVoltageHiSidd =
1774                 cpu_to_be16(smc_voltage_table->StdVoltageHiSidd);
1775         smc_voltage_table->StdVoltageLoSidd =
1776                 cpu_to_be16(smc_voltage_table->StdVoltageLoSidd);
1777 }
1778
1779 static int ci_populate_smc_vddc_table(struct radeon_device *rdev,
1780                                       SMU7_Discrete_DpmTable *table)
1781 {
1782         struct ci_power_info *pi = ci_get_pi(rdev);
1783         unsigned int count;
1784
1785         table->VddcLevelCount = pi->vddc_voltage_table.count;
1786         for (count = 0; count < table->VddcLevelCount; count++) {
1787                 ci_populate_smc_voltage_table(rdev,
1788                                               &pi->vddc_voltage_table.entries[count],
1789                                               &table->VddcLevel[count]);
1790
1791                 if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO)
1792                         table->VddcLevel[count].Smio |=
1793                                 pi->vddc_voltage_table.entries[count].smio_low;
1794                 else
1795                         table->VddcLevel[count].Smio = 0;
1796         }
1797         table->VddcLevelCount = cpu_to_be32(table->VddcLevelCount);
1798
1799         return 0;
1800 }
1801
1802 static int ci_populate_smc_vddci_table(struct radeon_device *rdev,
1803                                        SMU7_Discrete_DpmTable *table)
1804 {
1805         unsigned int count;
1806         struct ci_power_info *pi = ci_get_pi(rdev);
1807
1808         table->VddciLevelCount = pi->vddci_voltage_table.count;
1809         for (count = 0; count < table->VddciLevelCount; count++) {
1810                 ci_populate_smc_voltage_table(rdev,
1811                                               &pi->vddci_voltage_table.entries[count],
1812                                               &table->VddciLevel[count]);
1813
1814                 if (pi->vddci_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO)
1815                         table->VddciLevel[count].Smio |=
1816                                 pi->vddci_voltage_table.entries[count].smio_low;
1817                 else
1818                         table->VddciLevel[count].Smio = 0;
1819         }
1820         table->VddciLevelCount = cpu_to_be32(table->VddciLevelCount);
1821
1822         return 0;
1823 }
1824
1825 static int ci_populate_smc_mvdd_table(struct radeon_device *rdev,
1826                                       SMU7_Discrete_DpmTable *table)
1827 {
1828         struct ci_power_info *pi = ci_get_pi(rdev);
1829         unsigned int count;
1830
1831         table->MvddLevelCount = pi->mvdd_voltage_table.count;
1832         for (count = 0; count < table->MvddLevelCount; count++) {
1833                 ci_populate_smc_voltage_table(rdev,
1834                                               &pi->mvdd_voltage_table.entries[count],
1835                                               &table->MvddLevel[count]);
1836
1837                 if (pi->mvdd_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO)
1838                         table->MvddLevel[count].Smio |=
1839                                 pi->mvdd_voltage_table.entries[count].smio_low;
1840                 else
1841                         table->MvddLevel[count].Smio = 0;
1842         }
1843         table->MvddLevelCount = cpu_to_be32(table->MvddLevelCount);
1844
1845         return 0;
1846 }
1847
1848 static int ci_populate_smc_voltage_tables(struct radeon_device *rdev,
1849                                           SMU7_Discrete_DpmTable *table)
1850 {
1851         int ret;
1852
1853         ret = ci_populate_smc_vddc_table(rdev, table);
1854         if (ret)
1855                 return ret;
1856
1857         ret = ci_populate_smc_vddci_table(rdev, table);
1858         if (ret)
1859                 return ret;
1860
1861         ret = ci_populate_smc_mvdd_table(rdev, table);
1862         if (ret)
1863                 return ret;
1864
1865         return 0;
1866 }
1867
1868 static int ci_populate_mvdd_value(struct radeon_device *rdev, u32 mclk,
1869                                   SMU7_Discrete_VoltageLevel *voltage)
1870 {
1871         struct ci_power_info *pi = ci_get_pi(rdev);
1872         u32 i = 0;
1873
1874         if (pi->mvdd_control != CISLANDS_VOLTAGE_CONTROL_NONE) {
1875                 for (i = 0; i < rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.count; i++) {
1876                         if (mclk <= rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.entries[i].clk) {
1877                                 voltage->Voltage = pi->mvdd_voltage_table.entries[i].value;
1878                                 break;
1879                         }
1880                 }
1881
1882                 if (i >= rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.count)
1883                         return -EINVAL;
1884         }
1885
1886         return -EINVAL;
1887 }
1888
1889 static int ci_get_std_voltage_value_sidd(struct radeon_device *rdev,
1890                                          struct atom_voltage_table_entry *voltage_table,
1891                                          u16 *std_voltage_hi_sidd, u16 *std_voltage_lo_sidd)
1892 {
1893         u16 v_index, idx;
1894         bool voltage_found = false;
1895         *std_voltage_hi_sidd = voltage_table->value * VOLTAGE_SCALE;
1896         *std_voltage_lo_sidd = voltage_table->value * VOLTAGE_SCALE;
1897
1898         if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries == NULL)
1899                 return -EINVAL;
1900
1901         if (rdev->pm.dpm.dyn_state.cac_leakage_table.entries) {
1902                 for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {
1903                         if (voltage_table->value ==
1904                             rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) {
1905                                 voltage_found = true;
1906                                 if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count)
1907                                         idx = v_index;
1908                                 else
1909                                         idx = rdev->pm.dpm.dyn_state.cac_leakage_table.count - 1;
1910                                 *std_voltage_lo_sidd =
1911                                         rdev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].vddc * VOLTAGE_SCALE;
1912                                 *std_voltage_hi_sidd =
1913                                         rdev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].leakage * VOLTAGE_SCALE;
1914                                 break;
1915                         }
1916                 }
1917
1918                 if (!voltage_found) {
1919                         for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {
1920                                 if (voltage_table->value <=
1921                                     rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) {
1922                                         voltage_found = true;
1923                                         if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count)
1924                                                 idx = v_index;
1925                                         else
1926                                                 idx = rdev->pm.dpm.dyn_state.cac_leakage_table.count - 1;
1927                                         *std_voltage_lo_sidd =
1928                                                 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].vddc * VOLTAGE_SCALE;
1929                                         *std_voltage_hi_sidd =
1930                                                 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].leakage * VOLTAGE_SCALE;
1931                                         break;
1932                                 }
1933                         }
1934                 }
1935         }
1936
1937         return 0;
1938 }
1939
1940 static void ci_populate_phase_value_based_on_sclk(struct radeon_device *rdev,
1941                                                   const struct radeon_phase_shedding_limits_table *limits,
1942                                                   u32 sclk,
1943                                                   u32 *phase_shedding)
1944 {
1945         unsigned int i;
1946
1947         *phase_shedding = 1;
1948
1949         for (i = 0; i < limits->count; i++) {
1950                 if (sclk < limits->entries[i].sclk) {
1951                         *phase_shedding = i;
1952                         break;
1953                 }
1954         }
1955 }
1956
1957 static void ci_populate_phase_value_based_on_mclk(struct radeon_device *rdev,
1958                                                   const struct radeon_phase_shedding_limits_table *limits,
1959                                                   u32 mclk,
1960                                                   u32 *phase_shedding)
1961 {
1962         unsigned int i;
1963
1964         *phase_shedding = 1;
1965
1966         for (i = 0; i < limits->count; i++) {
1967                 if (mclk < limits->entries[i].mclk) {
1968                         *phase_shedding = i;
1969                         break;
1970                 }
1971         }
1972 }
1973
1974 static int ci_init_arb_table_index(struct radeon_device *rdev)
1975 {
1976         struct ci_power_info *pi = ci_get_pi(rdev);
1977         u32 tmp;
1978         int ret;
1979
1980         ret = ci_read_smc_sram_dword(rdev, pi->arb_table_start,
1981                                      &tmp, pi->sram_end);
1982         if (ret)
1983                 return ret;
1984
1985         tmp &= 0x00FFFFFF;
1986         tmp |= MC_CG_ARB_FREQ_F1 << 24;
1987
1988         return ci_write_smc_sram_dword(rdev, pi->arb_table_start,
1989                                        tmp, pi->sram_end);
1990 }
1991
1992 static int ci_get_dependency_volt_by_clk(struct radeon_device *rdev,
1993                                          struct radeon_clock_voltage_dependency_table *allowed_clock_voltage_table,
1994                                          u32 clock, u32 *voltage)
1995 {
1996         u32 i = 0;
1997
1998         if (allowed_clock_voltage_table->count == 0)
1999                 return -EINVAL;
2000
2001         for (i = 0; i < allowed_clock_voltage_table->count; i++) {
2002                 if (allowed_clock_voltage_table->entries[i].clk >= clock) {
2003                         *voltage = allowed_clock_voltage_table->entries[i].v;
2004                         return 0;
2005                 }
2006         }
2007
2008         *voltage = allowed_clock_voltage_table->entries[i-1].v;
2009
2010         return 0;
2011 }
2012
2013 static u8 ci_get_sleep_divider_id_from_clock(struct radeon_device *rdev,
2014                                              u32 sclk, u32 min_sclk_in_sr)
2015 {
2016         u32 i;
2017         u32 tmp;
2018         u32 min = (min_sclk_in_sr > CISLAND_MINIMUM_ENGINE_CLOCK) ?
2019                 min_sclk_in_sr : CISLAND_MINIMUM_ENGINE_CLOCK;
2020
2021         if (sclk < min)
2022                 return 0;
2023
2024         for (i = CISLAND_MAX_DEEPSLEEP_DIVIDER_ID;  ; i--) {
2025                 tmp = sclk / (1 << i);
2026                 if (tmp >= min || i == 0)
2027                         break;
2028         }
2029
2030         return (u8)i;
2031 }
2032
2033 static int ci_initial_switch_from_arb_f0_to_f1(struct radeon_device *rdev)
2034 {
2035         return ni_copy_and_switch_arb_sets(rdev, MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1);
2036 }
2037
2038 static int ci_reset_to_default(struct radeon_device *rdev)
2039 {
2040         return (ci_send_msg_to_smc(rdev, PPSMC_MSG_ResetToDefaults) == PPSMC_Result_OK) ?
2041                 0 : -EINVAL;
2042 }
2043
2044 static int ci_force_switch_to_arb_f0(struct radeon_device *rdev)
2045 {
2046         u32 tmp;
2047
2048         tmp = (RREG32_SMC(SMC_SCRATCH9) & 0x0000ff00) >> 8;
2049
2050         if (tmp == MC_CG_ARB_FREQ_F0)
2051                 return 0;
2052
2053         return ni_copy_and_switch_arb_sets(rdev, tmp, MC_CG_ARB_FREQ_F0);
2054 }
2055
2056 static int ci_populate_memory_timing_parameters(struct radeon_device *rdev,
2057                                                 u32 sclk,
2058                                                 u32 mclk,
2059                                                 SMU7_Discrete_MCArbDramTimingTableEntry *arb_regs)
2060 {
2061         u32 dram_timing;
2062         u32 dram_timing2;
2063         u32 burst_time;
2064
2065         radeon_atom_set_engine_dram_timings(rdev, sclk, mclk);
2066
2067         dram_timing  = RREG32(MC_ARB_DRAM_TIMING);
2068         dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2);
2069         burst_time = RREG32(MC_ARB_BURST_TIME) & STATE0_MASK;
2070
2071         arb_regs->McArbDramTiming  = cpu_to_be32(dram_timing);
2072         arb_regs->McArbDramTiming2 = cpu_to_be32(dram_timing2);
2073         arb_regs->McArbBurstTime = (u8)burst_time;
2074
2075         return 0;
2076 }
2077
2078 static int ci_do_program_memory_timing_parameters(struct radeon_device *rdev)
2079 {
2080         struct ci_power_info *pi = ci_get_pi(rdev);
2081         SMU7_Discrete_MCArbDramTimingTable arb_regs;
2082         u32 i, j;
2083         int ret =  0;
2084
2085         memset(&arb_regs, 0, sizeof(SMU7_Discrete_MCArbDramTimingTable));
2086
2087         for (i = 0; i < pi->dpm_table.sclk_table.count; i++) {
2088                 for (j = 0; j < pi->dpm_table.mclk_table.count; j++) {
2089                         ret = ci_populate_memory_timing_parameters(rdev,
2090                                                                    pi->dpm_table.sclk_table.dpm_levels[i].value,
2091                                                                    pi->dpm_table.mclk_table.dpm_levels[j].value,
2092                                                                    &arb_regs.entries[i][j]);
2093                         if (ret)
2094                                 break;
2095                 }
2096         }
2097
2098         if (ret == 0)
2099                 ret = ci_copy_bytes_to_smc(rdev,
2100                                            pi->arb_table_start,
2101                                            (u8 *)&arb_regs,
2102                                            sizeof(SMU7_Discrete_MCArbDramTimingTable),
2103                                            pi->sram_end);
2104
2105         return ret;
2106 }
2107
2108 static int ci_program_memory_timing_parameters(struct radeon_device *rdev)
2109 {
2110         struct ci_power_info *pi = ci_get_pi(rdev);
2111
2112         if (pi->need_update_smu7_dpm_table == 0)
2113                 return 0;
2114
2115         return ci_do_program_memory_timing_parameters(rdev);
2116 }
2117
2118 static void ci_populate_smc_initial_state(struct radeon_device *rdev,
2119                                           struct radeon_ps *radeon_boot_state)
2120 {
2121         struct ci_ps *boot_state = ci_get_ps(radeon_boot_state);
2122         struct ci_power_info *pi = ci_get_pi(rdev);
2123         u32 level = 0;
2124
2125         for (level = 0; level < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; level++) {
2126                 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[level].clk >=
2127                     boot_state->performance_levels[0].sclk) {
2128                         pi->smc_state_table.GraphicsBootLevel = level;
2129                         break;
2130                 }
2131         }
2132
2133         for (level = 0; level < rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk.count; level++) {
2134                 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk.entries[level].clk >=
2135                     boot_state->performance_levels[0].mclk) {
2136                         pi->smc_state_table.MemoryBootLevel = level;
2137                         break;
2138                 }
2139         }
2140 }
2141
2142 static u32 ci_get_dpm_level_enable_mask_value(struct ci_single_dpm_table *dpm_table)
2143 {
2144         u32 i;
2145         u32 mask_value = 0;
2146
2147         for (i = dpm_table->count; i > 0; i--) {
2148                 mask_value = mask_value << 1;
2149                 if (dpm_table->dpm_levels[i-1].enabled)
2150                         mask_value |= 0x1;
2151                 else
2152                         mask_value &= 0xFFFFFFFE;
2153         }
2154
2155         return mask_value;
2156 }
2157
2158 static void ci_populate_smc_link_level(struct radeon_device *rdev,
2159                                        SMU7_Discrete_DpmTable *table)
2160 {
2161         struct ci_power_info *pi = ci_get_pi(rdev);
2162         struct ci_dpm_table *dpm_table = &pi->dpm_table;
2163         u32 i;
2164
2165         for (i = 0; i < dpm_table->pcie_speed_table.count; i++) {
2166                 table->LinkLevel[i].PcieGenSpeed =
2167                         (u8)dpm_table->pcie_speed_table.dpm_levels[i].value;
2168                 table->LinkLevel[i].PcieLaneCount =
2169                         r600_encode_pci_lane_width(dpm_table->pcie_speed_table.dpm_levels[i].param1);
2170                 table->LinkLevel[i].EnabledForActivity = 1;
2171                 table->LinkLevel[i].DownT = cpu_to_be32(5);
2172                 table->LinkLevel[i].UpT = cpu_to_be32(30);
2173         }
2174
2175         pi->smc_state_table.LinkLevelCount = (u8)dpm_table->pcie_speed_table.count;
2176         pi->dpm_level_enable_mask.pcie_dpm_enable_mask =
2177                 ci_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table);
2178 }
2179
2180 static int ci_populate_smc_uvd_level(struct radeon_device *rdev,
2181                                      SMU7_Discrete_DpmTable *table)
2182 {
2183         u32 count;
2184         struct atom_clock_dividers dividers;
2185         int ret = -EINVAL;
2186
2187         table->UvdLevelCount =
2188                 rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count;
2189
2190         for (count = 0; count < table->UvdLevelCount; count++) {
2191                 table->UvdLevel[count].VclkFrequency =
2192                         rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[count].vclk;
2193                 table->UvdLevel[count].DclkFrequency =
2194                         rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[count].dclk;
2195                 table->UvdLevel[count].MinVddc =
2196                         rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[count].v * VOLTAGE_SCALE;
2197                 table->UvdLevel[count].MinVddcPhases = 1;
2198
2199                 ret = radeon_atom_get_clock_dividers(rdev,
2200                                                      COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
2201                                                      table->UvdLevel[count].VclkFrequency, false, &dividers);
2202                 if (ret)
2203                         return ret;
2204
2205                 table->UvdLevel[count].VclkDivider = (u8)dividers.post_divider;
2206
2207                 ret = radeon_atom_get_clock_dividers(rdev,
2208                                                      COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
2209                                                      table->UvdLevel[count].DclkFrequency, false, &dividers);
2210                 if (ret)
2211                         return ret;
2212
2213                 table->UvdLevel[count].DclkDivider = (u8)dividers.post_divider;
2214
2215                 table->UvdLevel[count].VclkFrequency = cpu_to_be32(table->UvdLevel[count].VclkFrequency);
2216                 table->UvdLevel[count].DclkFrequency = cpu_to_be32(table->UvdLevel[count].DclkFrequency);
2217                 table->UvdLevel[count].MinVddc = cpu_to_be16(table->UvdLevel[count].MinVddc);
2218         }
2219
2220         return ret;
2221 }
2222
2223 static int ci_populate_smc_vce_level(struct radeon_device *rdev,
2224                                      SMU7_Discrete_DpmTable *table)
2225 {
2226         u32 count;
2227         struct atom_clock_dividers dividers;
2228         int ret = -EINVAL;
2229
2230         table->VceLevelCount =
2231                 rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.count;
2232
2233         for (count = 0; count < table->VceLevelCount; count++) {
2234                 table->VceLevel[count].Frequency =
2235                         rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[count].evclk;
2236                 table->VceLevel[count].MinVoltage =
2237                         (u16)rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[count].v * VOLTAGE_SCALE;
2238                 table->VceLevel[count].MinPhases = 1;
2239
2240                 ret = radeon_atom_get_clock_dividers(rdev,
2241                                                      COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
2242                                                      table->VceLevel[count].Frequency, false, &dividers);
2243                 if (ret)
2244                         return ret;
2245
2246                 table->VceLevel[count].Divider = (u8)dividers.post_divider;
2247
2248                 table->VceLevel[count].Frequency = cpu_to_be32(table->VceLevel[count].Frequency);
2249                 table->VceLevel[count].MinVoltage = cpu_to_be16(table->VceLevel[count].MinVoltage);
2250         }
2251
2252         return ret;
2253
2254 }
2255
2256 static int ci_populate_smc_acp_level(struct radeon_device *rdev,
2257                                      SMU7_Discrete_DpmTable *table)
2258 {
2259         u32 count;
2260         struct atom_clock_dividers dividers;
2261         int ret = -EINVAL;
2262
2263         table->AcpLevelCount = (u8)
2264                 (rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.count);
2265
2266         for (count = 0; count < table->AcpLevelCount; count++) {
2267                 table->AcpLevel[count].Frequency =
2268                         rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries[count].clk;
2269                 table->AcpLevel[count].MinVoltage =
2270                         rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries[count].v;
2271                 table->AcpLevel[count].MinPhases = 1;
2272
2273                 ret = radeon_atom_get_clock_dividers(rdev,
2274                                                      COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
2275                                                      table->AcpLevel[count].Frequency, false, &dividers);
2276                 if (ret)
2277                         return ret;
2278
2279                 table->AcpLevel[count].Divider = (u8)dividers.post_divider;
2280
2281                 table->AcpLevel[count].Frequency = cpu_to_be32(table->AcpLevel[count].Frequency);
2282                 table->AcpLevel[count].MinVoltage = cpu_to_be16(table->AcpLevel[count].MinVoltage);
2283         }
2284
2285         return ret;
2286 }
2287
2288 static int ci_populate_smc_samu_level(struct radeon_device *rdev,
2289                                       SMU7_Discrete_DpmTable *table)
2290 {
2291         u32 count;
2292         struct atom_clock_dividers dividers;
2293         int ret = -EINVAL;
2294
2295         table->SamuLevelCount =
2296                 rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.count;
2297
2298         for (count = 0; count < table->SamuLevelCount; count++) {
2299                 table->SamuLevel[count].Frequency =
2300                         rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries[count].clk;
2301                 table->SamuLevel[count].MinVoltage =
2302                         rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries[count].v * VOLTAGE_SCALE;
2303                 table->SamuLevel[count].MinPhases = 1;
2304
2305                 ret = radeon_atom_get_clock_dividers(rdev,
2306                                                      COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
2307                                                      table->SamuLevel[count].Frequency, false, &dividers);
2308                 if (ret)
2309                         return ret;
2310
2311                 table->SamuLevel[count].Divider = (u8)dividers.post_divider;
2312
2313                 table->SamuLevel[count].Frequency = cpu_to_be32(table->SamuLevel[count].Frequency);
2314                 table->SamuLevel[count].MinVoltage = cpu_to_be16(table->SamuLevel[count].MinVoltage);
2315         }
2316
2317         return ret;
2318 }
2319
2320 static int ci_calculate_mclk_params(struct radeon_device *rdev,
2321                                     u32 memory_clock,
2322                                     SMU7_Discrete_MemoryLevel *mclk,
2323                                     bool strobe_mode,
2324                                     bool dll_state_on)
2325 {
2326         struct ci_power_info *pi = ci_get_pi(rdev);
2327         u32  dll_cntl = pi->clock_registers.dll_cntl;
2328         u32  mclk_pwrmgt_cntl = pi->clock_registers.mclk_pwrmgt_cntl;
2329         u32  mpll_ad_func_cntl = pi->clock_registers.mpll_ad_func_cntl;
2330         u32  mpll_dq_func_cntl = pi->clock_registers.mpll_dq_func_cntl;
2331         u32  mpll_func_cntl = pi->clock_registers.mpll_func_cntl;
2332         u32  mpll_func_cntl_1 = pi->clock_registers.mpll_func_cntl_1;
2333         u32  mpll_func_cntl_2 = pi->clock_registers.mpll_func_cntl_2;
2334         u32  mpll_ss1 = pi->clock_registers.mpll_ss1;
2335         u32  mpll_ss2 = pi->clock_registers.mpll_ss2;
2336         struct atom_mpll_param mpll_param;
2337         int ret;
2338
2339         ret = radeon_atom_get_memory_pll_dividers(rdev, memory_clock, strobe_mode, &mpll_param);
2340         if (ret)
2341                 return ret;
2342
2343         mpll_func_cntl &= ~BWCTRL_MASK;
2344         mpll_func_cntl |= BWCTRL(mpll_param.bwcntl);
2345
2346         mpll_func_cntl_1 &= ~(CLKF_MASK | CLKFRAC_MASK | VCO_MODE_MASK);
2347         mpll_func_cntl_1 |= CLKF(mpll_param.clkf) |
2348                 CLKFRAC(mpll_param.clkfrac) | VCO_MODE(mpll_param.vco_mode);
2349
2350         mpll_ad_func_cntl &= ~YCLK_POST_DIV_MASK;
2351         mpll_ad_func_cntl |= YCLK_POST_DIV(mpll_param.post_div);
2352
2353         if (pi->mem_gddr5) {
2354                 mpll_dq_func_cntl &= ~(YCLK_SEL_MASK | YCLK_POST_DIV_MASK);
2355                 mpll_dq_func_cntl |= YCLK_SEL(mpll_param.yclk_sel) |
2356                         YCLK_POST_DIV(mpll_param.post_div);
2357         }
2358
2359         if (pi->caps_mclk_ss_support) {
2360                 struct radeon_atom_ss ss;
2361                 u32 freq_nom;
2362                 u32 tmp;
2363                 u32 reference_clock = rdev->clock.mpll.reference_freq;
2364
2365                 if (pi->mem_gddr5)
2366                         freq_nom = memory_clock * 4;
2367                 else
2368                         freq_nom = memory_clock * 2;
2369
2370                 tmp = (freq_nom / reference_clock);
2371                 tmp = tmp * tmp;
2372                 if (radeon_atombios_get_asic_ss_info(rdev, &ss,
2373                                                      ASIC_INTERNAL_MEMORY_SS, freq_nom)) {
2374                         u32 clks = reference_clock * 5 / ss.rate;
2375                         u32 clkv = (u32)((((131 * ss.percentage * ss.rate) / 100) * tmp) / freq_nom);
2376
2377                         mpll_ss1 &= ~CLKV_MASK;
2378                         mpll_ss1 |= CLKV(clkv);
2379
2380                         mpll_ss2 &= ~CLKS_MASK;
2381                         mpll_ss2 |= CLKS(clks);
2382                 }
2383         }
2384
2385         mclk_pwrmgt_cntl &= ~DLL_SPEED_MASK;
2386         mclk_pwrmgt_cntl |= DLL_SPEED(mpll_param.dll_speed);
2387
2388         if (dll_state_on)
2389                 mclk_pwrmgt_cntl |= MRDCK0_PDNB | MRDCK1_PDNB;
2390         else
2391                 mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB);
2392
2393         mclk->MclkFrequency = memory_clock;
2394         mclk->MpllFuncCntl = mpll_func_cntl;
2395         mclk->MpllFuncCntl_1 = mpll_func_cntl_1;
2396         mclk->MpllFuncCntl_2 = mpll_func_cntl_2;
2397         mclk->MpllAdFuncCntl = mpll_ad_func_cntl;
2398         mclk->MpllDqFuncCntl = mpll_dq_func_cntl;
2399         mclk->MclkPwrmgtCntl = mclk_pwrmgt_cntl;
2400         mclk->DllCntl = dll_cntl;
2401         mclk->MpllSs1 = mpll_ss1;
2402         mclk->MpllSs2 = mpll_ss2;
2403
2404         return 0;
2405 }
2406
2407 static int ci_populate_single_memory_level(struct radeon_device *rdev,
2408                                            u32 memory_clock,
2409                                            SMU7_Discrete_MemoryLevel *memory_level)
2410 {
2411         struct ci_power_info *pi = ci_get_pi(rdev);
2412         int ret;
2413         bool dll_state_on;
2414
2415         if (rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk.entries) {
2416                 ret = ci_get_dependency_volt_by_clk(rdev,
2417                                                     &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
2418                                                     memory_clock, &memory_level->MinVddc);
2419                 if (ret)
2420                         return ret;
2421         }
2422
2423         if (rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk.entries) {
2424                 ret = ci_get_dependency_volt_by_clk(rdev,
2425                                                     &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
2426                                                     memory_clock, &memory_level->MinVddci);
2427                 if (ret)
2428                         return ret;
2429         }
2430
2431         if (rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.entries) {
2432                 ret = ci_get_dependency_volt_by_clk(rdev,
2433                                                     &rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk,
2434                                                     memory_clock, &memory_level->MinMvdd);
2435                 if (ret)
2436                         return ret;
2437         }
2438
2439         memory_level->MinVddcPhases = 1;
2440
2441         if (pi->vddc_phase_shed_control)
2442                 ci_populate_phase_value_based_on_mclk(rdev,
2443                                                       &rdev->pm.dpm.dyn_state.phase_shedding_limits_table,
2444                                                       memory_clock,
2445                                                       &memory_level->MinVddcPhases);
2446
2447         memory_level->EnabledForThrottle = 1;
2448         memory_level->EnabledForActivity = 1;
2449         memory_level->UpH = 0;
2450         memory_level->DownH = 100;
2451         memory_level->VoltageDownH = 0;
2452         memory_level->ActivityLevel = (u16)pi->mclk_activity_target;
2453
2454         memory_level->StutterEnable = false;
2455         memory_level->StrobeEnable = false;
2456         memory_level->EdcReadEnable = false;
2457         memory_level->EdcWriteEnable = false;
2458         memory_level->RttEnable = false;
2459
2460         memory_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
2461
2462         if (pi->mclk_stutter_mode_threshold &&
2463             (memory_clock <= pi->mclk_stutter_mode_threshold) &&
2464             (pi->uvd_enabled == false) &&
2465             (RREG32(DPG_PIPE_STUTTER_CONTROL) & STUTTER_ENABLE) &&
2466             (rdev->pm.dpm.new_active_crtc_count <= 2))
2467                 memory_level->StutterEnable = true;
2468
2469         if (pi->mclk_strobe_mode_threshold &&
2470             (memory_clock <= pi->mclk_strobe_mode_threshold))
2471                 memory_level->StrobeEnable = 1;
2472
2473         if (pi->mem_gddr5) {
2474                 memory_level->StrobeRatio =
2475                         si_get_mclk_frequency_ratio(memory_clock, memory_level->StrobeEnable);
2476                 if (pi->mclk_edc_enable_threshold &&
2477                     (memory_clock > pi->mclk_edc_enable_threshold))
2478                         memory_level->EdcReadEnable = true;
2479
2480                 if (pi->mclk_edc_wr_enable_threshold &&
2481                     (memory_clock > pi->mclk_edc_wr_enable_threshold))
2482                         memory_level->EdcWriteEnable = true;
2483
2484                 if (memory_level->StrobeEnable) {
2485                         if (si_get_mclk_frequency_ratio(memory_clock, true) >=
2486                             ((RREG32(MC_SEQ_MISC7) >> 16) & 0xf))
2487                                 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
2488                         else
2489                                 dll_state_on = ((RREG32(MC_SEQ_MISC6) >> 1) & 0x1) ? true : false;
2490                 } else {
2491                         dll_state_on = pi->dll_default_on;
2492                 }
2493         } else {
2494                 memory_level->StrobeRatio = si_get_ddr3_mclk_frequency_ratio(memory_clock);
2495                 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
2496         }
2497
2498         ret = ci_calculate_mclk_params(rdev, memory_clock, memory_level, memory_level->StrobeEnable, dll_state_on);
2499         if (ret)
2500                 return ret;
2501
2502         memory_level->MinVddc = cpu_to_be32(memory_level->MinVddc * VOLTAGE_SCALE);
2503         memory_level->MinVddcPhases = cpu_to_be32(memory_level->MinVddcPhases);
2504         memory_level->MinVddci = cpu_to_be32(memory_level->MinVddci * VOLTAGE_SCALE);
2505         memory_level->MinMvdd = cpu_to_be32(memory_level->MinMvdd * VOLTAGE_SCALE);
2506
2507         memory_level->MclkFrequency = cpu_to_be32(memory_level->MclkFrequency);
2508         memory_level->ActivityLevel = cpu_to_be16(memory_level->ActivityLevel);
2509         memory_level->MpllFuncCntl = cpu_to_be32(memory_level->MpllFuncCntl);
2510         memory_level->MpllFuncCntl_1 = cpu_to_be32(memory_level->MpllFuncCntl_1);
2511         memory_level->MpllFuncCntl_2 = cpu_to_be32(memory_level->MpllFuncCntl_2);
2512         memory_level->MpllAdFuncCntl = cpu_to_be32(memory_level->MpllAdFuncCntl);
2513         memory_level->MpllDqFuncCntl = cpu_to_be32(memory_level->MpllDqFuncCntl);
2514         memory_level->MclkPwrmgtCntl = cpu_to_be32(memory_level->MclkPwrmgtCntl);
2515         memory_level->DllCntl = cpu_to_be32(memory_level->DllCntl);
2516         memory_level->MpllSs1 = cpu_to_be32(memory_level->MpllSs1);
2517         memory_level->MpllSs2 = cpu_to_be32(memory_level->MpllSs2);
2518
2519         return 0;
2520 }
2521
2522 static int ci_populate_smc_acpi_level(struct radeon_device *rdev,
2523                                       SMU7_Discrete_DpmTable *table)
2524 {
2525         struct ci_power_info *pi = ci_get_pi(rdev);
2526         struct atom_clock_dividers dividers;
2527         SMU7_Discrete_VoltageLevel voltage_level;
2528         u32 spll_func_cntl = pi->clock_registers.cg_spll_func_cntl;
2529         u32 spll_func_cntl_2 = pi->clock_registers.cg_spll_func_cntl_2;
2530         u32 dll_cntl = pi->clock_registers.dll_cntl;
2531         u32 mclk_pwrmgt_cntl = pi->clock_registers.mclk_pwrmgt_cntl;
2532         int ret;
2533
2534         table->ACPILevel.Flags &= ~PPSMC_SWSTATE_FLAG_DC;
2535
2536         if (pi->acpi_vddc)
2537                 table->ACPILevel.MinVddc = cpu_to_be32(pi->acpi_vddc * VOLTAGE_SCALE);
2538         else
2539                 table->ACPILevel.MinVddc = cpu_to_be32(pi->min_vddc_in_pp_table * VOLTAGE_SCALE);
2540
2541         table->ACPILevel.MinVddcPhases = pi->vddc_phase_shed_control ? 0 : 1;
2542
2543         table->ACPILevel.SclkFrequency = rdev->clock.spll.reference_freq;
2544
2545         ret = radeon_atom_get_clock_dividers(rdev,
2546                                              COMPUTE_GPUCLK_INPUT_FLAG_SCLK,
2547                                              table->ACPILevel.SclkFrequency, false, &dividers);
2548         if (ret)
2549                 return ret;
2550
2551         table->ACPILevel.SclkDid = (u8)dividers.post_divider;
2552         table->ACPILevel.DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
2553         table->ACPILevel.DeepSleepDivId = 0;
2554
2555         spll_func_cntl &= ~SPLL_PWRON;
2556         spll_func_cntl |= SPLL_RESET;
2557
2558         spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK;
2559         spll_func_cntl_2 |= SCLK_MUX_SEL(4);
2560
2561         table->ACPILevel.CgSpllFuncCntl = spll_func_cntl;
2562         table->ACPILevel.CgSpllFuncCntl2 = spll_func_cntl_2;
2563         table->ACPILevel.CgSpllFuncCntl3 = pi->clock_registers.cg_spll_func_cntl_3;
2564         table->ACPILevel.CgSpllFuncCntl4 = pi->clock_registers.cg_spll_func_cntl_4;
2565         table->ACPILevel.SpllSpreadSpectrum = pi->clock_registers.cg_spll_spread_spectrum;
2566         table->ACPILevel.SpllSpreadSpectrum2 = pi->clock_registers.cg_spll_spread_spectrum_2;
2567         table->ACPILevel.CcPwrDynRm = 0;
2568         table->ACPILevel.CcPwrDynRm1 = 0;
2569
2570         table->ACPILevel.Flags = cpu_to_be32(table->ACPILevel.Flags);
2571         table->ACPILevel.MinVddcPhases = cpu_to_be32(table->ACPILevel.MinVddcPhases);
2572         table->ACPILevel.SclkFrequency = cpu_to_be32(table->ACPILevel.SclkFrequency);
2573         table->ACPILevel.CgSpllFuncCntl = cpu_to_be32(table->ACPILevel.CgSpllFuncCntl);
2574         table->ACPILevel.CgSpllFuncCntl2 = cpu_to_be32(table->ACPILevel.CgSpllFuncCntl2);
2575         table->ACPILevel.CgSpllFuncCntl3 = cpu_to_be32(table->ACPILevel.CgSpllFuncCntl3);
2576         table->ACPILevel.CgSpllFuncCntl4 = cpu_to_be32(table->ACPILevel.CgSpllFuncCntl4);
2577         table->ACPILevel.SpllSpreadSpectrum = cpu_to_be32(table->ACPILevel.SpllSpreadSpectrum);
2578         table->ACPILevel.SpllSpreadSpectrum2 = cpu_to_be32(table->ACPILevel.SpllSpreadSpectrum2);
2579         table->ACPILevel.CcPwrDynRm = cpu_to_be32(table->ACPILevel.CcPwrDynRm);
2580         table->ACPILevel.CcPwrDynRm1 = cpu_to_be32(table->ACPILevel.CcPwrDynRm1);
2581
2582         table->MemoryACPILevel.MinVddc = table->ACPILevel.MinVddc;
2583         table->MemoryACPILevel.MinVddcPhases = table->ACPILevel.MinVddcPhases;
2584
2585         if (pi->vddci_control != CISLANDS_VOLTAGE_CONTROL_NONE) {
2586                 if (pi->acpi_vddci)
2587                         table->MemoryACPILevel.MinVddci =
2588                                 cpu_to_be32(pi->acpi_vddci * VOLTAGE_SCALE);
2589                 else
2590                         table->MemoryACPILevel.MinVddci =
2591                                 cpu_to_be32(pi->min_vddci_in_pp_table * VOLTAGE_SCALE);
2592         }
2593
2594         if (ci_populate_mvdd_value(rdev, 0, &voltage_level))
2595                 table->MemoryACPILevel.MinMvdd = 0;
2596         else
2597                 table->MemoryACPILevel.MinMvdd =
2598                         cpu_to_be32(voltage_level.Voltage * VOLTAGE_SCALE);
2599
2600         mclk_pwrmgt_cntl |= MRDCK0_RESET | MRDCK1_RESET;
2601         mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB);
2602
2603         dll_cntl &= ~(MRDCK0_BYPASS | MRDCK1_BYPASS);
2604
2605         table->MemoryACPILevel.DllCntl = cpu_to_be32(dll_cntl);
2606         table->MemoryACPILevel.MclkPwrmgtCntl = cpu_to_be32(mclk_pwrmgt_cntl);
2607         table->MemoryACPILevel.MpllAdFuncCntl =
2608                 cpu_to_be32(pi->clock_registers.mpll_ad_func_cntl);
2609         table->MemoryACPILevel.MpllDqFuncCntl =
2610                 cpu_to_be32(pi->clock_registers.mpll_dq_func_cntl);
2611         table->MemoryACPILevel.MpllFuncCntl =
2612                 cpu_to_be32(pi->clock_registers.mpll_func_cntl);
2613         table->MemoryACPILevel.MpllFuncCntl_1 =
2614                 cpu_to_be32(pi->clock_registers.mpll_func_cntl_1);
2615         table->MemoryACPILevel.MpllFuncCntl_2 =
2616                 cpu_to_be32(pi->clock_registers.mpll_func_cntl_2);
2617         table->MemoryACPILevel.MpllSs1 = cpu_to_be32(pi->clock_registers.mpll_ss1);
2618         table->MemoryACPILevel.MpllSs2 = cpu_to_be32(pi->clock_registers.mpll_ss2);
2619
2620         table->MemoryACPILevel.EnabledForThrottle = 0;
2621         table->MemoryACPILevel.EnabledForActivity = 0;
2622         table->MemoryACPILevel.UpH = 0;
2623         table->MemoryACPILevel.DownH = 100;
2624         table->MemoryACPILevel.VoltageDownH = 0;
2625         table->MemoryACPILevel.ActivityLevel =
2626                 cpu_to_be16((u16)pi->mclk_activity_target);
2627
2628         table->MemoryACPILevel.StutterEnable = false;
2629         table->MemoryACPILevel.StrobeEnable = false;
2630         table->MemoryACPILevel.EdcReadEnable = false;
2631         table->MemoryACPILevel.EdcWriteEnable = false;
2632         table->MemoryACPILevel.RttEnable = false;
2633
2634         return 0;
2635 }
2636
2637
2638 static int ci_enable_ulv(struct radeon_device *rdev, bool enable)
2639 {
2640         struct ci_power_info *pi = ci_get_pi(rdev);
2641         struct ci_ulv_parm *ulv = &pi->ulv;
2642
2643         if (ulv->supported) {
2644                 if (enable)
2645                         return (ci_send_msg_to_smc(rdev, PPSMC_MSG_EnableULV) == PPSMC_Result_OK) ?
2646                                 0 : -EINVAL;
2647                 else
2648                         return (ci_send_msg_to_smc(rdev, PPSMC_MSG_DisableULV) == PPSMC_Result_OK) ?
2649                                 0 : -EINVAL;
2650         }
2651
2652         return 0;
2653 }
2654
2655 static int ci_populate_ulv_level(struct radeon_device *rdev,
2656                                  SMU7_Discrete_Ulv *state)
2657 {
2658         struct ci_power_info *pi = ci_get_pi(rdev);
2659         u16 ulv_voltage = rdev->pm.dpm.backbias_response_time;
2660
2661         state->CcPwrDynRm = 0;
2662         state->CcPwrDynRm1 = 0;
2663
2664         if (ulv_voltage == 0) {
2665                 pi->ulv.supported = false;
2666                 return 0;
2667         }
2668
2669         if (pi->voltage_control != CISLANDS_VOLTAGE_CONTROL_BY_SVID2) {
2670                 if (ulv_voltage > rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v)
2671                         state->VddcOffset = 0;
2672                 else
2673                         state->VddcOffset =
2674                                 rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v - ulv_voltage;
2675         } else {
2676                 if (ulv_voltage > rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v)
2677                         state->VddcOffsetVid = 0;
2678                 else
2679                         state->VddcOffsetVid = (u8)
2680                                 ((rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v - ulv_voltage) *
2681                                  VOLTAGE_VID_OFFSET_SCALE2 / VOLTAGE_VID_OFFSET_SCALE1);
2682         }
2683         state->VddcPhase = pi->vddc_phase_shed_control ? 0 : 1;
2684
2685         state->CcPwrDynRm = cpu_to_be32(state->CcPwrDynRm);
2686         state->CcPwrDynRm1 = cpu_to_be32(state->CcPwrDynRm1);
2687         state->VddcOffset = cpu_to_be16(state->VddcOffset);
2688
2689         return 0;
2690 }
2691
2692 static int ci_calculate_sclk_params(struct radeon_device *rdev,
2693                                     u32 engine_clock,
2694                                     SMU7_Discrete_GraphicsLevel *sclk)
2695 {
2696         struct ci_power_info *pi = ci_get_pi(rdev);
2697         struct atom_clock_dividers dividers;
2698         u32 spll_func_cntl_3 = pi->clock_registers.cg_spll_func_cntl_3;
2699         u32 spll_func_cntl_4 = pi->clock_registers.cg_spll_func_cntl_4;
2700         u32 cg_spll_spread_spectrum = pi->clock_registers.cg_spll_spread_spectrum;
2701         u32 cg_spll_spread_spectrum_2 = pi->clock_registers.cg_spll_spread_spectrum_2;
2702         u32 reference_clock = rdev->clock.spll.reference_freq;
2703         u32 reference_divider;
2704         u32 fbdiv;
2705         int ret;
2706
2707         ret = radeon_atom_get_clock_dividers(rdev,
2708                                              COMPUTE_GPUCLK_INPUT_FLAG_SCLK,
2709                                              engine_clock, false, &dividers);
2710         if (ret)
2711                 return ret;
2712
2713         reference_divider = 1 + dividers.ref_div;
2714         fbdiv = dividers.fb_div & 0x3FFFFFF;
2715
2716         spll_func_cntl_3 &= ~SPLL_FB_DIV_MASK;
2717         spll_func_cntl_3 |= SPLL_FB_DIV(fbdiv);
2718         spll_func_cntl_3 |= SPLL_DITHEN;
2719
2720         if (pi->caps_sclk_ss_support) {
2721                 struct radeon_atom_ss ss;
2722                 u32 vco_freq = engine_clock * dividers.post_div;
2723
2724                 if (radeon_atombios_get_asic_ss_info(rdev, &ss,
2725                                                      ASIC_INTERNAL_ENGINE_SS, vco_freq)) {
2726                         u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate);
2727                         u32 clk_v = 4 * ss.percentage * fbdiv / (clk_s * 10000);
2728
2729                         cg_spll_spread_spectrum &= ~CLK_S_MASK;
2730                         cg_spll_spread_spectrum |= CLK_S(clk_s);
2731                         cg_spll_spread_spectrum |= SSEN;
2732
2733                         cg_spll_spread_spectrum_2 &= ~CLK_V_MASK;
2734                         cg_spll_spread_spectrum_2 |= CLK_V(clk_v);
2735                 }
2736         }
2737
2738         sclk->SclkFrequency = engine_clock;
2739         sclk->CgSpllFuncCntl3 = spll_func_cntl_3;
2740         sclk->CgSpllFuncCntl4 = spll_func_cntl_4;
2741         sclk->SpllSpreadSpectrum = cg_spll_spread_spectrum;
2742         sclk->SpllSpreadSpectrum2  = cg_spll_spread_spectrum_2;
2743         sclk->SclkDid = (u8)dividers.post_divider;
2744
2745         return 0;
2746 }
2747
2748 static int ci_populate_single_graphic_level(struct radeon_device *rdev,
2749                                             u32 engine_clock,
2750                                             u16 sclk_activity_level_t,
2751                                             SMU7_Discrete_GraphicsLevel *graphic_level)
2752 {
2753         struct ci_power_info *pi = ci_get_pi(rdev);
2754         int ret;
2755
2756         ret = ci_calculate_sclk_params(rdev, engine_clock, graphic_level);
2757         if (ret)
2758                 return ret;
2759
2760         ret = ci_get_dependency_volt_by_clk(rdev,
2761                                             &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk,
2762                                             engine_clock, &graphic_level->MinVddc);
2763         if (ret)
2764                 return ret;
2765
2766         graphic_level->SclkFrequency = engine_clock;
2767
2768         graphic_level->Flags =  0;
2769         graphic_level->MinVddcPhases = 1;
2770
2771         if (pi->vddc_phase_shed_control)
2772                 ci_populate_phase_value_based_on_sclk(rdev,
2773                                                       &rdev->pm.dpm.dyn_state.phase_shedding_limits_table,
2774                                                       engine_clock,
2775                                                       &graphic_level->MinVddcPhases);
2776
2777         graphic_level->ActivityLevel = sclk_activity_level_t;
2778
2779         graphic_level->CcPwrDynRm = 0;
2780         graphic_level->CcPwrDynRm1 = 0;
2781         graphic_level->EnabledForActivity = 1;
2782         graphic_level->EnabledForThrottle = 1;
2783         graphic_level->UpH = 0;
2784         graphic_level->DownH = 0;
2785         graphic_level->VoltageDownH = 0;
2786         graphic_level->PowerThrottle = 0;
2787
2788         if (pi->caps_sclk_ds)
2789                 graphic_level->DeepSleepDivId = ci_get_sleep_divider_id_from_clock(rdev,
2790                                                                                    engine_clock,
2791                                                                                    CISLAND_MINIMUM_ENGINE_CLOCK);
2792
2793         graphic_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
2794
2795         graphic_level->Flags = cpu_to_be32(graphic_level->Flags);
2796         graphic_level->MinVddc = cpu_to_be32(graphic_level->MinVddc * VOLTAGE_SCALE);
2797         graphic_level->MinVddcPhases = cpu_to_be32(graphic_level->MinVddcPhases);
2798         graphic_level->SclkFrequency = cpu_to_be32(graphic_level->SclkFrequency);
2799         graphic_level->ActivityLevel = cpu_to_be16(graphic_level->ActivityLevel);
2800         graphic_level->CgSpllFuncCntl3 = cpu_to_be32(graphic_level->CgSpllFuncCntl3);
2801         graphic_level->CgSpllFuncCntl4 = cpu_to_be32(graphic_level->CgSpllFuncCntl4);
2802         graphic_level->SpllSpreadSpectrum = cpu_to_be32(graphic_level->SpllSpreadSpectrum);
2803         graphic_level->SpllSpreadSpectrum2 = cpu_to_be32(graphic_level->SpllSpreadSpectrum2);
2804         graphic_level->CcPwrDynRm = cpu_to_be32(graphic_level->CcPwrDynRm);
2805         graphic_level->CcPwrDynRm1 = cpu_to_be32(graphic_level->CcPwrDynRm1);
2806
2807         return 0;
2808 }
2809
2810 static int ci_populate_all_graphic_levels(struct radeon_device *rdev)
2811 {
2812         struct ci_power_info *pi = ci_get_pi(rdev);
2813         struct ci_dpm_table *dpm_table = &pi->dpm_table;
2814         u32 level_array_address = pi->dpm_table_start +
2815                 offsetof(SMU7_Discrete_DpmTable, GraphicsLevel);
2816         u32 level_array_size = sizeof(SMU7_Discrete_GraphicsLevel) *
2817                 SMU7_MAX_LEVELS_GRAPHICS;
2818         SMU7_Discrete_GraphicsLevel *levels = pi->smc_state_table.GraphicsLevel;
2819         u32 i, ret;
2820
2821         memset(levels, 0, level_array_size);
2822
2823         for (i = 0; i < dpm_table->sclk_table.count; i++) {
2824                 ret = ci_populate_single_graphic_level(rdev,
2825                                                        dpm_table->sclk_table.dpm_levels[i].value,
2826                                                        (u16)pi->activity_target[i],
2827                                                        &pi->smc_state_table.GraphicsLevel[i]);
2828                 if (ret)
2829                         return ret;
2830                 if (i == (dpm_table->sclk_table.count - 1))
2831                         pi->smc_state_table.GraphicsLevel[i].DisplayWatermark =
2832                                 PPSMC_DISPLAY_WATERMARK_HIGH;
2833         }
2834
2835         pi->smc_state_table.GraphicsDpmLevelCount = (u8)dpm_table->sclk_table.count;
2836         pi->dpm_level_enable_mask.sclk_dpm_enable_mask =
2837                 ci_get_dpm_level_enable_mask_value(&dpm_table->sclk_table);
2838
2839         ret = ci_copy_bytes_to_smc(rdev, level_array_address,
2840                                    (u8 *)levels, level_array_size,
2841                                    pi->sram_end);
2842         if (ret)
2843                 return ret;
2844
2845         return 0;
2846 }
2847
2848 static int ci_populate_ulv_state(struct radeon_device *rdev,
2849                                  SMU7_Discrete_Ulv *ulv_level)
2850 {
2851         return ci_populate_ulv_level(rdev, ulv_level);
2852 }
2853
2854 static int ci_populate_all_memory_levels(struct radeon_device *rdev)
2855 {
2856         struct ci_power_info *pi = ci_get_pi(rdev);
2857         struct ci_dpm_table *dpm_table = &pi->dpm_table;
2858         u32 level_array_address = pi->dpm_table_start +
2859                 offsetof(SMU7_Discrete_DpmTable, MemoryLevel);
2860         u32 level_array_size = sizeof(SMU7_Discrete_MemoryLevel) *
2861                 SMU7_MAX_LEVELS_MEMORY;
2862         SMU7_Discrete_MemoryLevel *levels = pi->smc_state_table.MemoryLevel;
2863         u32 i, ret;
2864
2865         memset(levels, 0, level_array_size);
2866
2867         for (i = 0; i < dpm_table->mclk_table.count; i++) {
2868                 if (dpm_table->mclk_table.dpm_levels[i].value == 0)
2869                         return -EINVAL;
2870                 ret = ci_populate_single_memory_level(rdev,
2871                                                       dpm_table->mclk_table.dpm_levels[i].value,
2872                                                       &pi->smc_state_table.MemoryLevel[i]);
2873                 if (ret)
2874                         return ret;
2875         }
2876
2877         pi->smc_state_table.MemoryLevel[0].ActivityLevel = cpu_to_be16(0x1F);
2878
2879         pi->smc_state_table.MemoryDpmLevelCount = (u8)dpm_table->mclk_table.count;
2880         pi->dpm_level_enable_mask.mclk_dpm_enable_mask =
2881                 ci_get_dpm_level_enable_mask_value(&dpm_table->mclk_table);
2882
2883         pi->smc_state_table.MemoryLevel[dpm_table->mclk_table.count - 1].DisplayWatermark =
2884                 PPSMC_DISPLAY_WATERMARK_HIGH;
2885
2886         ret = ci_copy_bytes_to_smc(rdev, level_array_address,
2887                                    (u8 *)levels, level_array_size,
2888                                    pi->sram_end);
2889         if (ret)
2890                 return ret;
2891
2892         return 0;
2893 }
2894
2895 static void ci_reset_single_dpm_table(struct radeon_device *rdev,
2896                                       struct ci_single_dpm_table* dpm_table,
2897                                       u32 count)
2898 {
2899         u32 i;
2900
2901         dpm_table->count = count;
2902         for (i = 0; i < MAX_REGULAR_DPM_NUMBER; i++)
2903                 dpm_table->dpm_levels[i].enabled = false;
2904 }
2905
2906 static void ci_setup_pcie_table_entry(struct ci_single_dpm_table* dpm_table,
2907                                       u32 index, u32 pcie_gen, u32 pcie_lanes)
2908 {
2909         dpm_table->dpm_levels[index].value = pcie_gen;
2910         dpm_table->dpm_levels[index].param1 = pcie_lanes;
2911         dpm_table->dpm_levels[index].enabled = true;
2912 }
2913
2914 static int ci_setup_default_pcie_tables(struct radeon_device *rdev)
2915 {
2916         struct ci_power_info *pi = ci_get_pi(rdev);
2917
2918         if (!pi->use_pcie_performance_levels && !pi->use_pcie_powersaving_levels)
2919                 return -EINVAL;
2920
2921         if (pi->use_pcie_performance_levels && !pi->use_pcie_powersaving_levels) {
2922                 pi->pcie_gen_powersaving = pi->pcie_gen_performance;
2923                 pi->pcie_lane_powersaving = pi->pcie_lane_performance;
2924         } else if (!pi->use_pcie_performance_levels && pi->use_pcie_powersaving_levels) {
2925                 pi->pcie_gen_performance = pi->pcie_gen_powersaving;
2926                 pi->pcie_lane_performance = pi->pcie_lane_powersaving;
2927         }
2928
2929         ci_reset_single_dpm_table(rdev,
2930                                   &pi->dpm_table.pcie_speed_table,
2931                                   SMU7_MAX_LEVELS_LINK);
2932
2933         ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 0,
2934                                   pi->pcie_gen_powersaving.min,
2935                                   pi->pcie_lane_powersaving.min);
2936         ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 1,
2937                                   pi->pcie_gen_performance.min,
2938                                   pi->pcie_lane_performance.min);
2939         ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 2,
2940                                   pi->pcie_gen_powersaving.min,
2941                                   pi->pcie_lane_powersaving.max);
2942         ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 3,
2943                                   pi->pcie_gen_performance.min,
2944                                   pi->pcie_lane_performance.max);
2945         ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 4,
2946                                   pi->pcie_gen_powersaving.max,
2947                                   pi->pcie_lane_powersaving.max);
2948         ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 5,
2949                                   pi->pcie_gen_performance.max,
2950                                   pi->pcie_lane_performance.max);
2951
2952         pi->dpm_table.pcie_speed_table.count = 6;
2953
2954         return 0;
2955 }
2956
2957 static int ci_setup_default_dpm_tables(struct radeon_device *rdev)
2958 {
2959         struct ci_power_info *pi = ci_get_pi(rdev);
2960         struct radeon_clock_voltage_dependency_table *allowed_sclk_vddc_table =
2961                 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
2962         struct radeon_clock_voltage_dependency_table *allowed_mclk_table =
2963                 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk;
2964         struct radeon_cac_leakage_table *std_voltage_table =
2965                 &rdev->pm.dpm.dyn_state.cac_leakage_table;
2966         u32 i;
2967
2968         if (allowed_sclk_vddc_table == NULL)
2969                 return -EINVAL;
2970         if (allowed_sclk_vddc_table->count < 1)
2971                 return -EINVAL;
2972         if (allowed_mclk_table == NULL)
2973                 return -EINVAL;
2974         if (allowed_mclk_table->count < 1)
2975                 return -EINVAL;
2976
2977         memset(&pi->dpm_table, 0, sizeof(struct ci_dpm_table));
2978
2979         ci_reset_single_dpm_table(rdev,
2980                                   &pi->dpm_table.sclk_table,
2981                                   SMU7_MAX_LEVELS_GRAPHICS);
2982         ci_reset_single_dpm_table(rdev,
2983                                   &pi->dpm_table.mclk_table,
2984                                   SMU7_MAX_LEVELS_MEMORY);
2985         ci_reset_single_dpm_table(rdev,
2986                                   &pi->dpm_table.vddc_table,
2987                                   SMU7_MAX_LEVELS_VDDC);
2988         ci_reset_single_dpm_table(rdev,
2989                                   &pi->dpm_table.vddci_table,
2990                                   SMU7_MAX_LEVELS_VDDCI);
2991         ci_reset_single_dpm_table(rdev,
2992                                   &pi->dpm_table.mvdd_table,
2993                                   SMU7_MAX_LEVELS_MVDD);
2994
2995         pi->dpm_table.sclk_table.count = 0;
2996         for (i = 0; i < allowed_sclk_vddc_table->count; i++) {
2997                 if ((i == 0) ||
2998                     (pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count-1].value !=
2999                      allowed_sclk_vddc_table->entries[i].clk)) {
3000                         pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count].value =
3001                                 allowed_sclk_vddc_table->entries[i].clk;
3002                         pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count].enabled = true;
3003                         pi->dpm_table.sclk_table.count++;
3004                 }
3005         }
3006
3007         pi->dpm_table.mclk_table.count = 0;
3008         for (i = 0; i < allowed_mclk_table->count; i++) {
3009                 if ((i==0) ||
3010                     (pi->dpm_table.mclk_table.dpm_levels[pi->dpm_table.mclk_table.count-1].value !=
3011                      allowed_mclk_table->entries[i].clk)) {
3012                         pi->dpm_table.mclk_table.dpm_levels[pi->dpm_table.mclk_table.count].value =
3013                                 allowed_mclk_table->entries[i].clk;
3014                         pi->dpm_table.mclk_table.dpm_levels[pi->dpm_table.mclk_table.count].enabled = true;
3015                         pi->dpm_table.mclk_table.count++;
3016                 }
3017         }
3018
3019         for (i = 0; i < allowed_sclk_vddc_table->count; i++) {
3020                 pi->dpm_table.vddc_table.dpm_levels[i].value =
3021                         allowed_sclk_vddc_table->entries[i].v;
3022                 pi->dpm_table.vddc_table.dpm_levels[i].param1 =
3023                         std_voltage_table->entries[i].leakage;
3024                 pi->dpm_table.vddc_table.dpm_levels[i].enabled = true;
3025         }
3026         pi->dpm_table.vddc_table.count = allowed_sclk_vddc_table->count;
3027
3028         allowed_mclk_table = &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk;
3029         if (allowed_mclk_table) {
3030                 for (i = 0; i < allowed_mclk_table->count; i++) {
3031                         pi->dpm_table.vddci_table.dpm_levels[i].value =
3032                                 allowed_mclk_table->entries[i].v;
3033                         pi->dpm_table.vddci_table.dpm_levels[i].enabled = true;
3034                 }
3035                 pi->dpm_table.vddci_table.count = allowed_mclk_table->count;
3036         }
3037
3038         allowed_mclk_table = &rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk;
3039         if (allowed_mclk_table) {
3040                 for (i = 0; i < allowed_mclk_table->count; i++) {
3041                         pi->dpm_table.mvdd_table.dpm_levels[i].value =
3042                                 allowed_mclk_table->entries[i].v;
3043                         pi->dpm_table.mvdd_table.dpm_levels[i].enabled = true;
3044                 }
3045                 pi->dpm_table.mvdd_table.count = allowed_mclk_table->count;
3046         }
3047
3048         ci_setup_default_pcie_tables(rdev);
3049
3050         return 0;
3051 }
3052
3053 static int ci_find_boot_level(struct ci_single_dpm_table *table,
3054                               u32 value, u32 *boot_level)
3055 {
3056         u32 i;
3057         int ret = -EINVAL;
3058
3059         for(i = 0; i < table->count; i++) {
3060                 if (value == table->dpm_levels[i].value) {
3061                         *boot_level = i;
3062                         ret = 0;
3063                 }
3064         }
3065
3066         return ret;
3067 }
3068
3069 static int ci_init_smc_table(struct radeon_device *rdev)
3070 {
3071         struct ci_power_info *pi = ci_get_pi(rdev);
3072         struct ci_ulv_parm *ulv = &pi->ulv;
3073         struct radeon_ps *radeon_boot_state = rdev->pm.dpm.boot_ps;
3074         SMU7_Discrete_DpmTable *table = &pi->smc_state_table;
3075         int ret;
3076
3077         ret = ci_setup_default_dpm_tables(rdev);
3078         if (ret)
3079                 return ret;
3080
3081         if (pi->voltage_control != CISLANDS_VOLTAGE_CONTROL_NONE)
3082                 ci_populate_smc_voltage_tables(rdev, table);
3083
3084         ci_init_fps_limits(rdev);
3085
3086         if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC)
3087                 table->SystemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC;
3088
3089         if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC)
3090                 table->SystemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;
3091
3092         if (pi->mem_gddr5)
3093                 table->SystemFlags |= PPSMC_SYSTEMFLAG_GDDR5;
3094
3095         if (ulv->supported) {
3096                 ret = ci_populate_ulv_state(rdev, &pi->smc_state_table.Ulv);
3097                 if (ret)
3098                         return ret;
3099                 WREG32_SMC(CG_ULV_PARAMETER, ulv->cg_ulv_parameter);
3100         }
3101
3102         ret = ci_populate_all_graphic_levels(rdev);
3103         if (ret)
3104                 return ret;
3105
3106         ret = ci_populate_all_memory_levels(rdev);
3107         if (ret)
3108                 return ret;
3109
3110         ci_populate_smc_link_level(rdev, table);
3111
3112         ret = ci_populate_smc_acpi_level(rdev, table);
3113         if (ret)
3114                 return ret;
3115
3116         ret = ci_populate_smc_vce_level(rdev, table);
3117         if (ret)
3118                 return ret;
3119
3120         ret = ci_populate_smc_acp_level(rdev, table);
3121         if (ret)
3122                 return ret;
3123
3124         ret = ci_populate_smc_samu_level(rdev, table);
3125         if (ret)
3126                 return ret;
3127
3128         ret = ci_do_program_memory_timing_parameters(rdev);
3129         if (ret)
3130                 return ret;
3131
3132         ret = ci_populate_smc_uvd_level(rdev, table);
3133         if (ret)
3134                 return ret;
3135
3136         table->UvdBootLevel  = 0;
3137         table->VceBootLevel  = 0;
3138         table->AcpBootLevel  = 0;
3139         table->SamuBootLevel  = 0;
3140         table->GraphicsBootLevel  = 0;
3141         table->MemoryBootLevel  = 0;
3142
3143         ret = ci_find_boot_level(&pi->dpm_table.sclk_table,
3144                                  pi->vbios_boot_state.sclk_bootup_value,
3145                                  (u32 *)&pi->smc_state_table.GraphicsBootLevel);
3146
3147         ret = ci_find_boot_level(&pi->dpm_table.mclk_table,
3148                                  pi->vbios_boot_state.mclk_bootup_value,
3149                                  (u32 *)&pi->smc_state_table.MemoryBootLevel);
3150
3151         table->BootVddc = pi->vbios_boot_state.vddc_bootup_value;
3152         table->BootVddci = pi->vbios_boot_state.vddci_bootup_value;
3153         table->BootMVdd = pi->vbios_boot_state.mvdd_bootup_value;
3154
3155         ci_populate_smc_initial_state(rdev, radeon_boot_state);
3156
3157         ret = ci_populate_bapm_parameters_in_dpm_table(rdev);
3158         if (ret)
3159                 return ret;
3160
3161         table->UVDInterval = 1;
3162         table->VCEInterval = 1;
3163         table->ACPInterval = 1;
3164         table->SAMUInterval = 1;
3165         table->GraphicsVoltageChangeEnable = 1;
3166         table->GraphicsThermThrottleEnable = 1;
3167         table->GraphicsInterval = 1;
3168         table->VoltageInterval = 1;
3169         table->ThermalInterval = 1;
3170         table->TemperatureLimitHigh = (u16)((pi->thermal_temp_setting.temperature_high *
3171                                              CISLANDS_Q88_FORMAT_CONVERSION_UNIT) / 1000);
3172         table->TemperatureLimitLow = (u16)((pi->thermal_temp_setting.temperature_low *
3173                                             CISLANDS_Q88_FORMAT_CONVERSION_UNIT) / 1000);
3174         table->MemoryVoltageChangeEnable = 1;
3175         table->MemoryInterval = 1;
3176         table->VoltageResponseTime = 0;
3177         table->VddcVddciDelta = 4000;
3178         table->PhaseResponseTime = 0;
3179         table->MemoryThermThrottleEnable = 1;
3180         table->PCIeBootLinkLevel = 0;
3181         table->PCIeGenInterval = 1;
3182         if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2)
3183                 table->SVI2Enable  = 1;
3184         else
3185                 table->SVI2Enable  = 0;
3186
3187         table->ThermGpio = 17;
3188         table->SclkStepSize = 0x4000;
3189
3190         table->SystemFlags = cpu_to_be32(table->SystemFlags);
3191         table->SmioMaskVddcVid = cpu_to_be32(table->SmioMaskVddcVid);
3192         table->SmioMaskVddcPhase = cpu_to_be32(table->SmioMaskVddcPhase);
3193         table->SmioMaskVddciVid = cpu_to_be32(table->SmioMaskVddciVid);
3194         table->SmioMaskMvddVid = cpu_to_be32(table->SmioMaskMvddVid);
3195         table->SclkStepSize = cpu_to_be32(table->SclkStepSize);
3196         table->TemperatureLimitHigh = cpu_to_be16(table->TemperatureLimitHigh);
3197         table->TemperatureLimitLow = cpu_to_be16(table->TemperatureLimitLow);
3198         table->VddcVddciDelta = cpu_to_be16(table->VddcVddciDelta);
3199         table->VoltageResponseTime = cpu_to_be16(table->VoltageResponseTime);
3200         table->PhaseResponseTime = cpu_to_be16(table->PhaseResponseTime);
3201         table->BootVddc = cpu_to_be16(table->BootVddc * VOLTAGE_SCALE);
3202         table->BootVddci = cpu_to_be16(table->BootVddci * VOLTAGE_SCALE);
3203         table->BootMVdd = cpu_to_be16(table->BootMVdd * VOLTAGE_SCALE);
3204
3205         ret = ci_copy_bytes_to_smc(rdev,
3206                                    pi->dpm_table_start +
3207                                    offsetof(SMU7_Discrete_DpmTable, SystemFlags),
3208                                    (u8 *)&table->SystemFlags,
3209                                    sizeof(SMU7_Discrete_DpmTable) - 3 * sizeof(SMU7_PIDController),
3210                                    pi->sram_end);
3211         if (ret)
3212                 return ret;
3213
3214         return 0;
3215 }
3216
3217 static void ci_trim_single_dpm_states(struct radeon_device *rdev,
3218                                       struct ci_single_dpm_table *dpm_table,
3219                                       u32 low_limit, u32 high_limit)
3220 {
3221         u32 i;
3222
3223         for (i = 0; i < dpm_table->count; i++) {
3224                 if ((dpm_table->dpm_levels[i].value < low_limit) ||
3225                     (dpm_table->dpm_levels[i].value > high_limit))
3226                         dpm_table->dpm_levels[i].enabled = false;
3227                 else
3228                         dpm_table->dpm_levels[i].enabled = true;
3229         }
3230 }
3231
3232 static void ci_trim_pcie_dpm_states(struct radeon_device *rdev,
3233                                     u32 speed_low, u32 lanes_low,
3234                                     u32 speed_high, u32 lanes_high)
3235 {
3236         struct ci_power_info *pi = ci_get_pi(rdev);
3237         struct ci_single_dpm_table *pcie_table = &pi->dpm_table.pcie_speed_table;
3238         u32 i, j;
3239
3240         for (i = 0; i < pcie_table->count; i++) {
3241                 if ((pcie_table->dpm_levels[i].value < speed_low) ||
3242                     (pcie_table->dpm_levels[i].param1 < lanes_low) ||
3243                     (pcie_table->dpm_levels[i].value > speed_high) ||
3244                     (pcie_table->dpm_levels[i].param1 > lanes_high))
3245                         pcie_table->dpm_levels[i].enabled = false;
3246                 else
3247                         pcie_table->dpm_levels[i].enabled = true;
3248         }
3249
3250         for (i = 0; i < pcie_table->count; i++) {
3251                 if (pcie_table->dpm_levels[i].enabled) {
3252                         for (j = i + 1; j < pcie_table->count; j++) {
3253                                 if (pcie_table->dpm_levels[j].enabled) {
3254                                         if ((pcie_table->dpm_levels[i].value == pcie_table->dpm_levels[j].value) &&
3255                                             (pcie_table->dpm_levels[i].param1 == pcie_table->dpm_levels[j].param1))
3256                                                 pcie_table->dpm_levels[j].enabled = false;
3257                                 }
3258                         }
3259                 }
3260         }
3261 }
3262
3263 static int ci_trim_dpm_states(struct radeon_device *rdev,
3264                               struct radeon_ps *radeon_state)
3265 {
3266         struct ci_ps *state = ci_get_ps(radeon_state);
3267         struct ci_power_info *pi = ci_get_pi(rdev);
3268         u32 high_limit_count;
3269
3270         if (state->performance_level_count < 1)
3271                 return -EINVAL;
3272
3273         if (state->performance_level_count == 1)
3274                 high_limit_count = 0;
3275         else
3276                 high_limit_count = 1;
3277
3278         ci_trim_single_dpm_states(rdev,
3279                                   &pi->dpm_table.sclk_table,
3280                                   state->performance_levels[0].sclk,
3281                                   state->performance_levels[high_limit_count].sclk);
3282
3283         ci_trim_single_dpm_states(rdev,
3284                                   &pi->dpm_table.mclk_table,
3285                                   state->performance_levels[0].mclk,
3286                                   state->performance_levels[high_limit_count].mclk);
3287
3288         ci_trim_pcie_dpm_states(rdev,
3289                                 state->performance_levels[0].pcie_gen,
3290                                 state->performance_levels[0].pcie_lane,
3291                                 state->performance_levels[high_limit_count].pcie_gen,
3292                                 state->performance_levels[high_limit_count].pcie_lane);
3293
3294         return 0;
3295 }
3296
3297 static int ci_apply_disp_minimum_voltage_request(struct radeon_device *rdev)
3298 {
3299         struct radeon_clock_voltage_dependency_table *disp_voltage_table =
3300                 &rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk;
3301         struct radeon_clock_voltage_dependency_table *vddc_table =
3302                 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
3303         u32 requested_voltage = 0;
3304         u32 i;
3305
3306         if (disp_voltage_table == NULL)
3307                 return -EINVAL;
3308         if (!disp_voltage_table->count)
3309                 return -EINVAL;
3310
3311         for (i = 0; i < disp_voltage_table->count; i++) {
3312                 if (rdev->clock.current_dispclk == disp_voltage_table->entries[i].clk)
3313                         requested_voltage = disp_voltage_table->entries[i].v;
3314         }
3315
3316         for (i = 0; i < vddc_table->count; i++) {
3317                 if (requested_voltage <= vddc_table->entries[i].v) {
3318                         requested_voltage = vddc_table->entries[i].v;
3319                         return (ci_send_msg_to_smc_with_parameter(rdev,
3320                                                                   PPSMC_MSG_VddC_Request,
3321                                                                   requested_voltage * VOLTAGE_SCALE) == PPSMC_Result_OK) ?
3322                                 0 : -EINVAL;
3323                 }
3324         }
3325
3326         return -EINVAL;
3327 }
3328
3329 static int ci_upload_dpm_level_enable_mask(struct radeon_device *rdev)
3330 {
3331         struct ci_power_info *pi = ci_get_pi(rdev);
3332         PPSMC_Result result;
3333
3334         if (!pi->sclk_dpm_key_disabled) {
3335                 if (pi->dpm_level_enable_mask.sclk_dpm_enable_mask) {
3336                         result = ci_send_msg_to_smc_with_parameter(rdev,
3337                                                                    PPSMC_MSG_SCLKDPM_SetEnabledMask,
3338                                                                    pi->dpm_level_enable_mask.sclk_dpm_enable_mask);
3339                         if (result != PPSMC_Result_OK)
3340                                 return -EINVAL;
3341                 }
3342         }
3343
3344         if (!pi->mclk_dpm_key_disabled) {
3345                 if (pi->dpm_level_enable_mask.mclk_dpm_enable_mask) {
3346                         result = ci_send_msg_to_smc_with_parameter(rdev,
3347                                                                    PPSMC_MSG_MCLKDPM_SetEnabledMask,
3348                                                                    pi->dpm_level_enable_mask.mclk_dpm_enable_mask);
3349                         if (result != PPSMC_Result_OK)
3350                                 return -EINVAL;
3351                 }
3352         }
3353
3354         if (!pi->pcie_dpm_key_disabled) {
3355                 if (pi->dpm_level_enable_mask.pcie_dpm_enable_mask) {
3356                         result = ci_send_msg_to_smc_with_parameter(rdev,
3357                                                                    PPSMC_MSG_PCIeDPM_SetEnabledMask,
3358                                                                    pi->dpm_level_enable_mask.pcie_dpm_enable_mask);
3359                         if (result != PPSMC_Result_OK)
3360                                 return -EINVAL;
3361                 }
3362         }
3363
3364         ci_apply_disp_minimum_voltage_request(rdev);
3365
3366         return 0;
3367 }
3368
3369 static void ci_find_dpm_states_clocks_in_dpm_table(struct radeon_device *rdev,
3370                                                    struct radeon_ps *radeon_state)
3371 {
3372         struct ci_power_info *pi = ci_get_pi(rdev);
3373         struct ci_ps *state = ci_get_ps(radeon_state);
3374         struct ci_single_dpm_table *sclk_table = &pi->dpm_table.sclk_table;
3375         u32 sclk = state->performance_levels[state->performance_level_count-1].sclk;
3376         struct ci_single_dpm_table *mclk_table = &pi->dpm_table.mclk_table;
3377         u32 mclk = state->performance_levels[state->performance_level_count-1].mclk;
3378         u32 i;
3379
3380         pi->need_update_smu7_dpm_table = 0;
3381
3382         for (i = 0; i < sclk_table->count; i++) {
3383                 if (sclk == sclk_table->dpm_levels[i].value)
3384                         break;
3385         }
3386
3387         if (i >= sclk_table->count) {
3388                 pi->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_SCLK;
3389         } else {
3390                 /* XXX check display min clock requirements */
3391                 if (0 != CISLAND_MINIMUM_ENGINE_CLOCK)
3392                         pi->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_SCLK;
3393         }
3394
3395         for (i = 0; i < mclk_table->count; i++) {
3396                 if (mclk == mclk_table->dpm_levels[i].value)
3397                         break;
3398         }
3399
3400         if (i >= mclk_table->count)
3401                 pi->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_MCLK;
3402
3403         if (rdev->pm.dpm.current_active_crtc_count !=
3404             rdev->pm.dpm.new_active_crtc_count)
3405                 pi->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_MCLK;
3406 }
3407
3408 static int ci_populate_and_upload_sclk_mclk_dpm_levels(struct radeon_device *rdev,
3409                                                        struct radeon_ps *radeon_state)
3410 {
3411         struct ci_power_info *pi = ci_get_pi(rdev);
3412         struct ci_ps *state = ci_get_ps(radeon_state);
3413         u32 sclk = state->performance_levels[state->performance_level_count-1].sclk;
3414         u32 mclk = state->performance_levels[state->performance_level_count-1].mclk;
3415         struct ci_dpm_table *dpm_table = &pi->dpm_table;
3416         int ret;
3417
3418         if (!pi->need_update_smu7_dpm_table)
3419                 return 0;
3420
3421         if (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_SCLK)
3422                 dpm_table->sclk_table.dpm_levels[dpm_table->sclk_table.count-1].value = sclk;
3423
3424         if (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)
3425                 dpm_table->mclk_table.dpm_levels[dpm_table->mclk_table.count-1].value = mclk;
3426
3427         if (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK)) {
3428                 ret = ci_populate_all_graphic_levels(rdev);
3429                 if (ret)
3430                         return ret;
3431         }
3432
3433         if (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_MCLK | DPMTABLE_UPDATE_MCLK)) {
3434                 ret = ci_populate_all_memory_levels(rdev);
3435                 if (ret)
3436                         return ret;
3437         }
3438
3439         return 0;
3440 }
3441
3442 static int ci_enable_uvd_dpm(struct radeon_device *rdev, bool enable)
3443 {
3444         struct ci_power_info *pi = ci_get_pi(rdev);
3445         const struct radeon_clock_and_voltage_limits *max_limits;
3446         int i;
3447
3448         if (rdev->pm.dpm.ac_power)
3449                 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
3450         else
3451                 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
3452
3453         if (enable) {
3454                 pi->dpm_level_enable_mask.uvd_dpm_enable_mask = 0;
3455
3456                 for (i = rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count - 1; i >= 0; i--) {
3457                         if (rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) {
3458                                 pi->dpm_level_enable_mask.uvd_dpm_enable_mask |= 1 << i;
3459
3460                                 if (!pi->caps_uvd_dpm)
3461                                         break;
3462                         }
3463                 }
3464
3465                 ci_send_msg_to_smc_with_parameter(rdev,
3466                                                   PPSMC_MSG_UVDDPM_SetEnabledMask,
3467                                                   pi->dpm_level_enable_mask.uvd_dpm_enable_mask);
3468
3469                 if (pi->last_mclk_dpm_enable_mask & 0x1) {
3470                         pi->uvd_enabled = true;
3471                         pi->dpm_level_enable_mask.mclk_dpm_enable_mask &= 0xFFFFFFFE;
3472                         ci_send_msg_to_smc_with_parameter(rdev,
3473                                                           PPSMC_MSG_MCLKDPM_SetEnabledMask,
3474                                                           pi->dpm_level_enable_mask.mclk_dpm_enable_mask);
3475                 }
3476         } else {
3477                 if (pi->last_mclk_dpm_enable_mask & 0x1) {
3478                         pi->uvd_enabled = false;
3479                         pi->dpm_level_enable_mask.mclk_dpm_enable_mask |= 1;
3480                         ci_send_msg_to_smc_with_parameter(rdev,
3481                                                           PPSMC_MSG_MCLKDPM_SetEnabledMask,
3482                                                           pi->dpm_level_enable_mask.mclk_dpm_enable_mask);
3483                 }
3484         }
3485
3486         return (ci_send_msg_to_smc(rdev, enable ?
3487                                    PPSMC_MSG_UVDDPM_Enable : PPSMC_MSG_UVDDPM_Disable) == PPSMC_Result_OK) ?
3488                 0 : -EINVAL;
3489 }
3490
3491 static int ci_enable_vce_dpm(struct radeon_device *rdev, bool enable)
3492 {
3493         struct ci_power_info *pi = ci_get_pi(rdev);
3494         const struct radeon_clock_and_voltage_limits *max_limits;
3495         int i;
3496
3497         if (rdev->pm.dpm.ac_power)
3498                 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
3499         else
3500                 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
3501
3502         if (enable) {
3503                 pi->dpm_level_enable_mask.vce_dpm_enable_mask = 0;
3504                 for (i = rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.count - 1; i >= 0; i--) {
3505                         if (rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) {
3506                                 pi->dpm_level_enable_mask.vce_dpm_enable_mask |= 1 << i;
3507
3508                                 if (!pi->caps_vce_dpm)
3509                                         break;
3510                         }
3511                 }
3512
3513                 ci_send_msg_to_smc_with_parameter(rdev,
3514                                                   PPSMC_MSG_VCEDPM_SetEnabledMask,
3515                                                   pi->dpm_level_enable_mask.vce_dpm_enable_mask);
3516         }
3517
3518         return (ci_send_msg_to_smc(rdev, enable ?
3519                                    PPSMC_MSG_VCEDPM_Enable : PPSMC_MSG_VCEDPM_Disable) == PPSMC_Result_OK) ?
3520                 0 : -EINVAL;
3521 }
3522
3523 #if 0
3524 static int ci_enable_samu_dpm(struct radeon_device *rdev, bool enable)
3525 {
3526         struct ci_power_info *pi = ci_get_pi(rdev);
3527         const struct radeon_clock_and_voltage_limits *max_limits;
3528         int i;
3529
3530         if (rdev->pm.dpm.ac_power)
3531                 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
3532         else
3533                 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
3534
3535         if (enable) {
3536                 pi->dpm_level_enable_mask.samu_dpm_enable_mask = 0;
3537                 for (i = rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.count - 1; i >= 0; i--) {
3538                         if (rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) {
3539                                 pi->dpm_level_enable_mask.samu_dpm_enable_mask |= 1 << i;
3540
3541                                 if (!pi->caps_samu_dpm)
3542                                         break;
3543                         }
3544                 }
3545
3546                 ci_send_msg_to_smc_with_parameter(rdev,
3547                                                   PPSMC_MSG_SAMUDPM_SetEnabledMask,
3548                                                   pi->dpm_level_enable_mask.samu_dpm_enable_mask);
3549         }
3550         return (ci_send_msg_to_smc(rdev, enable ?
3551                                    PPSMC_MSG_SAMUDPM_Enable : PPSMC_MSG_SAMUDPM_Disable) == PPSMC_Result_OK) ?
3552                 0 : -EINVAL;
3553 }
3554
3555 static int ci_enable_acp_dpm(struct radeon_device *rdev, bool enable)
3556 {
3557         struct ci_power_info *pi = ci_get_pi(rdev);
3558         const struct radeon_clock_and_voltage_limits *max_limits;
3559         int i;
3560
3561         if (rdev->pm.dpm.ac_power)
3562                 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
3563         else
3564                 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
3565
3566         if (enable) {
3567                 pi->dpm_level_enable_mask.acp_dpm_enable_mask = 0;
3568                 for (i = rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.count - 1; i >= 0; i--) {
3569                         if (rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) {
3570                                 pi->dpm_level_enable_mask.acp_dpm_enable_mask |= 1 << i;
3571
3572                                 if (!pi->caps_acp_dpm)
3573                                         break;
3574                         }
3575                 }
3576
3577                 ci_send_msg_to_smc_with_parameter(rdev,
3578                                                   PPSMC_MSG_ACPDPM_SetEnabledMask,
3579                                                   pi->dpm_level_enable_mask.acp_dpm_enable_mask);
3580         }
3581
3582         return (ci_send_msg_to_smc(rdev, enable ?
3583                                    PPSMC_MSG_ACPDPM_Enable : PPSMC_MSG_ACPDPM_Disable) == PPSMC_Result_OK) ?
3584                 0 : -EINVAL;
3585 }
3586 #endif
3587
3588 static int ci_update_uvd_dpm(struct radeon_device *rdev, bool gate)
3589 {
3590         struct ci_power_info *pi = ci_get_pi(rdev);
3591         u32 tmp;
3592
3593         if (!gate) {
3594                 if (pi->caps_uvd_dpm ||
3595                     (rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count <= 0))
3596                         pi->smc_state_table.UvdBootLevel = 0;
3597                 else
3598                         pi->smc_state_table.UvdBootLevel =
3599                                 rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count - 1;
3600
3601                 tmp = RREG32_SMC(DPM_TABLE_475);
3602                 tmp &= ~UvdBootLevel_MASK;
3603                 tmp |= UvdBootLevel(pi->smc_state_table.UvdBootLevel);
3604                 WREG32_SMC(DPM_TABLE_475, tmp);
3605         }
3606
3607         return ci_enable_uvd_dpm(rdev, !gate);
3608 }
3609
3610 static u8 ci_get_vce_boot_level(struct radeon_device *rdev)
3611 {
3612         u8 i;
3613         u32 min_evclk = 30000; /* ??? */
3614         struct radeon_vce_clock_voltage_dependency_table *table =
3615                 &rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
3616
3617         for (i = 0; i < table->count; i++) {
3618                 if (table->entries[i].evclk >= min_evclk)
3619                         return i;
3620         }
3621
3622         return table->count - 1;
3623 }
3624
3625 static int ci_update_vce_dpm(struct radeon_device *rdev,
3626                              struct radeon_ps *radeon_new_state,
3627                              struct radeon_ps *radeon_current_state)
3628 {
3629         struct ci_power_info *pi = ci_get_pi(rdev);
3630         int ret = 0;
3631         u32 tmp;
3632
3633         if (radeon_current_state->evclk != radeon_new_state->evclk) {
3634                 if (radeon_new_state->evclk) {
3635                         /* turn the clocks on when encoding */
3636                         cik_update_cg(rdev, RADEON_CG_BLOCK_VCE, false);
3637
3638                         pi->smc_state_table.VceBootLevel = ci_get_vce_boot_level(rdev);
3639                         tmp = RREG32_SMC(DPM_TABLE_475);
3640                         tmp &= ~VceBootLevel_MASK;
3641                         tmp |= VceBootLevel(pi->smc_state_table.VceBootLevel);
3642                         WREG32_SMC(DPM_TABLE_475, tmp);
3643
3644                         ret = ci_enable_vce_dpm(rdev, true);
3645                 } else {
3646                         /* turn the clocks off when not encoding */
3647                         cik_update_cg(rdev, RADEON_CG_BLOCK_VCE, true);
3648
3649                         ret = ci_enable_vce_dpm(rdev, false);
3650                 }
3651         }
3652         return ret;
3653 }
3654
3655 #if 0
3656 static int ci_update_samu_dpm(struct radeon_device *rdev, bool gate)
3657 {
3658         return ci_enable_samu_dpm(rdev, gate);
3659 }
3660
3661 static int ci_update_acp_dpm(struct radeon_device *rdev, bool gate)
3662 {
3663         struct ci_power_info *pi = ci_get_pi(rdev);
3664         u32 tmp;
3665
3666         if (!gate) {
3667                 pi->smc_state_table.AcpBootLevel = 0;
3668
3669                 tmp = RREG32_SMC(DPM_TABLE_475);
3670                 tmp &= ~AcpBootLevel_MASK;
3671                 tmp |= AcpBootLevel(pi->smc_state_table.AcpBootLevel);
3672                 WREG32_SMC(DPM_TABLE_475, tmp);
3673         }
3674
3675         return ci_enable_acp_dpm(rdev, !gate);
3676 }
3677 #endif
3678
3679 static int ci_generate_dpm_level_enable_mask(struct radeon_device *rdev,
3680                                              struct radeon_ps *radeon_state)
3681 {
3682         struct ci_power_info *pi = ci_get_pi(rdev);
3683         int ret;
3684
3685         ret = ci_trim_dpm_states(rdev, radeon_state);
3686         if (ret)
3687                 return ret;
3688
3689         pi->dpm_level_enable_mask.sclk_dpm_enable_mask =
3690                 ci_get_dpm_level_enable_mask_value(&pi->dpm_table.sclk_table);
3691         pi->dpm_level_enable_mask.mclk_dpm_enable_mask =
3692                 ci_get_dpm_level_enable_mask_value(&pi->dpm_table.mclk_table);
3693         pi->last_mclk_dpm_enable_mask =
3694                 pi->dpm_level_enable_mask.mclk_dpm_enable_mask;
3695         if (pi->uvd_enabled) {
3696                 if (pi->dpm_level_enable_mask.mclk_dpm_enable_mask & 1)
3697                         pi->dpm_level_enable_mask.mclk_dpm_enable_mask &= 0xFFFFFFFE;
3698         }
3699         pi->dpm_level_enable_mask.pcie_dpm_enable_mask =
3700                 ci_get_dpm_level_enable_mask_value(&pi->dpm_table.pcie_speed_table);
3701
3702         return 0;
3703 }
3704
3705 static u32 ci_get_lowest_enabled_level(struct radeon_device *rdev,
3706                                        u32 level_mask)
3707 {
3708         u32 level = 0;
3709
3710         while ((level_mask & (1 << level)) == 0)
3711                 level++;
3712
3713         return level;
3714 }
3715
3716
3717 int ci_dpm_force_performance_level(struct radeon_device *rdev,
3718                                    enum radeon_dpm_forced_level level)
3719 {
3720         struct ci_power_info *pi = ci_get_pi(rdev);
3721         PPSMC_Result smc_result;
3722         u32 tmp, levels, i;
3723         int ret;
3724
3725         if (level == RADEON_DPM_FORCED_LEVEL_HIGH) {
3726                 if ((!pi->sclk_dpm_key_disabled) &&
3727                     pi->dpm_level_enable_mask.sclk_dpm_enable_mask) {
3728                         levels = 0;
3729                         tmp = pi->dpm_level_enable_mask.sclk_dpm_enable_mask;
3730                         while (tmp >>= 1)
3731                                 levels++;
3732                         if (levels) {
3733                                 ret = ci_dpm_force_state_sclk(rdev, levels);
3734                                 if (ret)
3735                                         return ret;
3736                                 for (i = 0; i < rdev->usec_timeout; i++) {
3737                                         tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX) &
3738                                                CURR_SCLK_INDEX_MASK) >> CURR_SCLK_INDEX_SHIFT;
3739                                         if (tmp == levels)
3740                                                 break;
3741                                         udelay(1);
3742                                 }
3743                         }
3744                 }
3745                 if ((!pi->mclk_dpm_key_disabled) &&
3746                     pi->dpm_level_enable_mask.mclk_dpm_enable_mask) {
3747                         levels = 0;
3748                         tmp = pi->dpm_level_enable_mask.mclk_dpm_enable_mask;
3749                         while (tmp >>= 1)
3750                                 levels++;
3751                         if (levels) {
3752                                 ret = ci_dpm_force_state_mclk(rdev, levels);
3753                                 if (ret)
3754                                         return ret;
3755                                 for (i = 0; i < rdev->usec_timeout; i++) {
3756                                         tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX) &
3757                                                CURR_MCLK_INDEX_MASK) >> CURR_MCLK_INDEX_SHIFT;
3758                                         if (tmp == levels)
3759                                                 break;
3760                                         udelay(1);
3761                                 }
3762                         }
3763                 }
3764                 if ((!pi->pcie_dpm_key_disabled) &&
3765                     pi->dpm_level_enable_mask.pcie_dpm_enable_mask) {
3766                         levels = 0;
3767                         tmp = pi->dpm_level_enable_mask.pcie_dpm_enable_mask;
3768                         while (tmp >>= 1)
3769                                 levels++;
3770                         if (levels) {
3771                                 ret = ci_dpm_force_state_pcie(rdev, level);
3772                                 if (ret)
3773                                         return ret;
3774                                 for (i = 0; i < rdev->usec_timeout; i++) {
3775                                         tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX_1) &
3776                                                CURR_PCIE_INDEX_MASK) >> CURR_PCIE_INDEX_SHIFT;
3777                                         if (tmp == levels)
3778                                                 break;
3779                                         udelay(1);
3780                                 }
3781                         }
3782                 }
3783         } else if (level == RADEON_DPM_FORCED_LEVEL_LOW) {
3784                 if ((!pi->sclk_dpm_key_disabled) &&
3785                     pi->dpm_level_enable_mask.sclk_dpm_enable_mask) {
3786                         levels = ci_get_lowest_enabled_level(rdev,
3787                                                              pi->dpm_level_enable_mask.sclk_dpm_enable_mask);
3788                         ret = ci_dpm_force_state_sclk(rdev, levels);
3789                         if (ret)
3790                                 return ret;
3791                         for (i = 0; i < rdev->usec_timeout; i++) {
3792                                 tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX) &
3793                                        CURR_SCLK_INDEX_MASK) >> CURR_SCLK_INDEX_SHIFT;
3794                                 if (tmp == levels)
3795                                         break;
3796                                 udelay(1);
3797                         }
3798                 }
3799                 if ((!pi->mclk_dpm_key_disabled) &&
3800                     pi->dpm_level_enable_mask.mclk_dpm_enable_mask) {
3801                         levels = ci_get_lowest_enabled_level(rdev,
3802                                                              pi->dpm_level_enable_mask.mclk_dpm_enable_mask);
3803                         ret = ci_dpm_force_state_mclk(rdev, levels);
3804                         if (ret)
3805                                 return ret;
3806                         for (i = 0; i < rdev->usec_timeout; i++) {
3807                                 tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX) &
3808                                        CURR_MCLK_INDEX_MASK) >> CURR_MCLK_INDEX_SHIFT;
3809                                 if (tmp == levels)
3810                                         break;
3811                                 udelay(1);
3812                         }
3813                 }
3814                 if ((!pi->pcie_dpm_key_disabled) &&
3815                     pi->dpm_level_enable_mask.pcie_dpm_enable_mask) {
3816                         levels = ci_get_lowest_enabled_level(rdev,
3817                                                              pi->dpm_level_enable_mask.pcie_dpm_enable_mask);
3818                         ret = ci_dpm_force_state_pcie(rdev, levels);
3819                         if (ret)
3820                                 return ret;
3821                         for (i = 0; i < rdev->usec_timeout; i++) {
3822                                 tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX_1) &
3823                                        CURR_PCIE_INDEX_MASK) >> CURR_PCIE_INDEX_SHIFT;
3824                                 if (tmp == levels)
3825                                         break;
3826                                 udelay(1);
3827                         }
3828                 }
3829         } else if (level == RADEON_DPM_FORCED_LEVEL_AUTO) {
3830                 if (!pi->sclk_dpm_key_disabled) {
3831                         smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_NoForcedLevel);
3832                         if (smc_result != PPSMC_Result_OK)
3833                                 return -EINVAL;
3834                 }
3835                 if (!pi->mclk_dpm_key_disabled) {
3836                         smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_MCLKDPM_NoForcedLevel);
3837                         if (smc_result != PPSMC_Result_OK)
3838                                 return -EINVAL;
3839                 }
3840                 if (!pi->pcie_dpm_key_disabled) {
3841                         smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_PCIeDPM_UnForceLevel);
3842                         if (smc_result != PPSMC_Result_OK)
3843                                 return -EINVAL;
3844                 }
3845         }
3846
3847         rdev->pm.dpm.forced_level = level;
3848
3849         return 0;
3850 }
3851
3852 static int ci_set_mc_special_registers(struct radeon_device *rdev,
3853                                        struct ci_mc_reg_table *table)
3854 {
3855         struct ci_power_info *pi = ci_get_pi(rdev);
3856         u8 i, j, k;
3857         u32 temp_reg;
3858
3859         for (i = 0, j = table->last; i < table->last; i++) {
3860                 if (j >= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
3861                         return -EINVAL;
3862                 switch(table->mc_reg_address[i].s1 << 2) {
3863                 case MC_SEQ_MISC1:
3864                         temp_reg = RREG32(MC_PMG_CMD_EMRS);
3865                         table->mc_reg_address[j].s1 = MC_PMG_CMD_EMRS >> 2;
3866                         table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_EMRS_LP >> 2;
3867                         for (k = 0; k < table->num_entries; k++) {
3868                                 table->mc_reg_table_entry[k].mc_data[j] =
3869                                         ((temp_reg & 0xffff0000)) | ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16);
3870                         }
3871                         j++;
3872                         if (j >= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
3873                                 return -EINVAL;
3874
3875                         temp_reg = RREG32(MC_PMG_CMD_MRS);
3876                         table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS >> 2;
3877                         table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS_LP >> 2;
3878                         for (k = 0; k < table->num_entries; k++) {
3879                                 table->mc_reg_table_entry[k].mc_data[j] =
3880                                         (temp_reg & 0xffff0000) | (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
3881                                 if (!pi->mem_gddr5)
3882                                         table->mc_reg_table_entry[k].mc_data[j] |= 0x100;
3883                         }
3884                         j++;
3885                         if (j > SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
3886                                 return -EINVAL;
3887
3888                         if (!pi->mem_gddr5) {
3889                                 table->mc_reg_address[j].s1 = MC_PMG_AUTO_CMD >> 2;
3890                                 table->mc_reg_address[j].s0 = MC_PMG_AUTO_CMD >> 2;
3891                                 for (k = 0; k < table->num_entries; k++) {
3892                                         table->mc_reg_table_entry[k].mc_data[j] =
3893                                                 (table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16;
3894                                 }
3895                                 j++;
3896                                 if (j > SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
3897                                         return -EINVAL;
3898                         }
3899                         break;
3900                 case MC_SEQ_RESERVE_M:
3901                         temp_reg = RREG32(MC_PMG_CMD_MRS1);
3902                         table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS1 >> 2;
3903                         table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS1_LP >> 2;
3904                         for (k = 0; k < table->num_entries; k++) {
3905                                 table->mc_reg_table_entry[k].mc_data[j] =
3906                                         (temp_reg & 0xffff0000) | (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
3907                         }
3908                         j++;
3909                         if (j > SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
3910                                 return -EINVAL;
3911                         break;
3912                 default:
3913                         break;
3914                 }
3915
3916         }
3917
3918         table->last = j;
3919
3920         return 0;
3921 }
3922
3923 static bool ci_check_s0_mc_reg_index(u16 in_reg, u16 *out_reg)
3924 {
3925         bool result = true;
3926
3927         switch(in_reg) {
3928         case MC_SEQ_RAS_TIMING >> 2:
3929                 *out_reg = MC_SEQ_RAS_TIMING_LP >> 2;
3930                 break;
3931         case MC_SEQ_DLL_STBY >> 2:
3932                 *out_reg = MC_SEQ_DLL_STBY_LP >> 2;
3933                 break;
3934         case MC_SEQ_G5PDX_CMD0 >> 2:
3935                 *out_reg = MC_SEQ_G5PDX_CMD0_LP >> 2;
3936                 break;
3937         case MC_SEQ_G5PDX_CMD1 >> 2:
3938                 *out_reg = MC_SEQ_G5PDX_CMD1_LP >> 2;
3939                 break;
3940         case MC_SEQ_G5PDX_CTRL >> 2:
3941                 *out_reg = MC_SEQ_G5PDX_CTRL_LP >> 2;
3942                 break;
3943         case MC_SEQ_CAS_TIMING >> 2:
3944                 *out_reg = MC_SEQ_CAS_TIMING_LP >> 2;
3945             break;
3946         case MC_SEQ_MISC_TIMING >> 2:
3947                 *out_reg = MC_SEQ_MISC_TIMING_LP >> 2;
3948                 break;
3949         case MC_SEQ_MISC_TIMING2 >> 2:
3950                 *out_reg = MC_SEQ_MISC_TIMING2_LP >> 2;
3951                 break;
3952         case MC_SEQ_PMG_DVS_CMD >> 2:
3953                 *out_reg = MC_SEQ_PMG_DVS_CMD_LP >> 2;
3954                 break;
3955         case MC_SEQ_PMG_DVS_CTL >> 2:
3956                 *out_reg = MC_SEQ_PMG_DVS_CTL_LP >> 2;
3957                 break;
3958         case MC_SEQ_RD_CTL_D0 >> 2:
3959                 *out_reg = MC_SEQ_RD_CTL_D0_LP >> 2;
3960                 break;
3961         case MC_SEQ_RD_CTL_D1 >> 2:
3962                 *out_reg = MC_SEQ_RD_CTL_D1_LP >> 2;
3963                 break;
3964         case MC_SEQ_WR_CTL_D0 >> 2:
3965                 *out_reg = MC_SEQ_WR_CTL_D0_LP >> 2;
3966                 break;
3967         case MC_SEQ_WR_CTL_D1 >> 2:
3968                 *out_reg = MC_SEQ_WR_CTL_D1_LP >> 2;
3969                 break;
3970         case MC_PMG_CMD_EMRS >> 2:
3971                 *out_reg = MC_SEQ_PMG_CMD_EMRS_LP >> 2;
3972                 break;
3973         case MC_PMG_CMD_MRS >> 2:
3974                 *out_reg = MC_SEQ_PMG_CMD_MRS_LP >> 2;
3975                 break;
3976         case MC_PMG_CMD_MRS1 >> 2:
3977                 *out_reg = MC_SEQ_PMG_CMD_MRS1_LP >> 2;
3978                 break;
3979         case MC_SEQ_PMG_TIMING >> 2:
3980                 *out_reg = MC_SEQ_PMG_TIMING_LP >> 2;
3981                 break;
3982         case MC_PMG_CMD_MRS2 >> 2:
3983                 *out_reg = MC_SEQ_PMG_CMD_MRS2_LP >> 2;
3984                 break;
3985         case MC_SEQ_WR_CTL_2 >> 2:
3986                 *out_reg = MC_SEQ_WR_CTL_2_LP >> 2;
3987                 break;
3988         default:
3989                 result = false;
3990                 break;
3991         }
3992
3993         return result;
3994 }
3995
3996 static void ci_set_valid_flag(struct ci_mc_reg_table *table)
3997 {
3998         u8 i, j;
3999
4000         for (i = 0; i < table->last; i++) {
4001                 for (j = 1; j < table->num_entries; j++) {
4002                         if (table->mc_reg_table_entry[j-1].mc_data[i] !=
4003                             table->mc_reg_table_entry[j].mc_data[i]) {
4004                                 table->valid_flag |= 1 << i;
4005                                 break;
4006                         }
4007                 }
4008         }
4009 }
4010
4011 static void ci_set_s0_mc_reg_index(struct ci_mc_reg_table *table)
4012 {
4013         u32 i;
4014         u16 address;
4015
4016         for (i = 0; i < table->last; i++) {
4017                 table->mc_reg_address[i].s0 =
4018                         ci_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address) ?
4019                         address : table->mc_reg_address[i].s1;
4020         }
4021 }
4022
4023 static int ci_copy_vbios_mc_reg_table(const struct atom_mc_reg_table *table,
4024                                       struct ci_mc_reg_table *ci_table)
4025 {
4026         u8 i, j;
4027
4028         if (table->last > SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
4029                 return -EINVAL;
4030         if (table->num_entries > MAX_AC_TIMING_ENTRIES)
4031                 return -EINVAL;
4032
4033         for (i = 0; i < table->last; i++)
4034                 ci_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1;
4035
4036         ci_table->last = table->last;
4037
4038         for (i = 0; i < table->num_entries; i++) {
4039                 ci_table->mc_reg_table_entry[i].mclk_max =
4040                         table->mc_reg_table_entry[i].mclk_max;
4041                 for (j = 0; j < table->last; j++)
4042                         ci_table->mc_reg_table_entry[i].mc_data[j] =
4043                                 table->mc_reg_table_entry[i].mc_data[j];
4044         }
4045         ci_table->num_entries = table->num_entries;
4046
4047         return 0;
4048 }
4049
4050 static int ci_initialize_mc_reg_table(struct radeon_device *rdev)
4051 {
4052         struct ci_power_info *pi = ci_get_pi(rdev);
4053         struct atom_mc_reg_table *table;
4054         struct ci_mc_reg_table *ci_table = &pi->mc_reg_table;
4055         u8 module_index = rv770_get_memory_module_index(rdev);
4056         int ret;
4057
4058         table = kzalloc(sizeof(struct atom_mc_reg_table), GFP_KERNEL);
4059         if (!table)
4060                 return -ENOMEM;
4061
4062         WREG32(MC_SEQ_RAS_TIMING_LP, RREG32(MC_SEQ_RAS_TIMING));
4063         WREG32(MC_SEQ_CAS_TIMING_LP, RREG32(MC_SEQ_CAS_TIMING));
4064         WREG32(MC_SEQ_DLL_STBY_LP, RREG32(MC_SEQ_DLL_STBY));
4065         WREG32(MC_SEQ_G5PDX_CMD0_LP, RREG32(MC_SEQ_G5PDX_CMD0));
4066         WREG32(MC_SEQ_G5PDX_CMD1_LP, RREG32(MC_SEQ_G5PDX_CMD1));
4067         WREG32(MC_SEQ_G5PDX_CTRL_LP, RREG32(MC_SEQ_G5PDX_CTRL));
4068         WREG32(MC_SEQ_PMG_DVS_CMD_LP, RREG32(MC_SEQ_PMG_DVS_CMD));
4069         WREG32(MC_SEQ_PMG_DVS_CTL_LP, RREG32(MC_SEQ_PMG_DVS_CTL));
4070         WREG32(MC_SEQ_MISC_TIMING_LP, RREG32(MC_SEQ_MISC_TIMING));
4071         WREG32(MC_SEQ_MISC_TIMING2_LP, RREG32(MC_SEQ_MISC_TIMING2));
4072         WREG32(MC_SEQ_PMG_CMD_EMRS_LP, RREG32(MC_PMG_CMD_EMRS));
4073         WREG32(MC_SEQ_PMG_CMD_MRS_LP, RREG32(MC_PMG_CMD_MRS));
4074         WREG32(MC_SEQ_PMG_CMD_MRS1_LP, RREG32(MC_PMG_CMD_MRS1));
4075         WREG32(MC_SEQ_WR_CTL_D0_LP, RREG32(MC_SEQ_WR_CTL_D0));
4076         WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1));
4077         WREG32(MC_SEQ_RD_CTL_D0_LP, RREG32(MC_SEQ_RD_CTL_D0));
4078         WREG32(MC_SEQ_RD_CTL_D1_LP, RREG32(MC_SEQ_RD_CTL_D1));
4079         WREG32(MC_SEQ_PMG_TIMING_LP, RREG32(MC_SEQ_PMG_TIMING));
4080         WREG32(MC_SEQ_PMG_CMD_MRS2_LP, RREG32(MC_PMG_CMD_MRS2));
4081         WREG32(MC_SEQ_WR_CTL_2_LP, RREG32(MC_SEQ_WR_CTL_2));
4082
4083         ret = radeon_atom_init_mc_reg_table(rdev, module_index, table);
4084         if (ret)
4085                 goto init_mc_done;
4086
4087         ret = ci_copy_vbios_mc_reg_table(table, ci_table);
4088         if (ret)
4089                 goto init_mc_done;
4090
4091         ci_set_s0_mc_reg_index(ci_table);
4092
4093         ret = ci_set_mc_special_registers(rdev, ci_table);
4094         if (ret)
4095                 goto init_mc_done;
4096
4097         ci_set_valid_flag(ci_table);
4098
4099 init_mc_done:
4100         kfree(table);
4101
4102         return ret;
4103 }
4104
4105 static int ci_populate_mc_reg_addresses(struct radeon_device *rdev,
4106                                         SMU7_Discrete_MCRegisters *mc_reg_table)
4107 {
4108         struct ci_power_info *pi = ci_get_pi(rdev);
4109         u32 i, j;
4110
4111         for (i = 0, j = 0; j < pi->mc_reg_table.last; j++) {
4112                 if (pi->mc_reg_table.valid_flag & (1 << j)) {
4113                         if (i >= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
4114                                 return -EINVAL;
4115                         mc_reg_table->address[i].s0 = cpu_to_be16(pi->mc_reg_table.mc_reg_address[j].s0);
4116                         mc_reg_table->address[i].s1 = cpu_to_be16(pi->mc_reg_table.mc_reg_address[j].s1);
4117                         i++;
4118                 }
4119         }
4120
4121         mc_reg_table->last = (u8)i;
4122
4123         return 0;
4124 }
4125
4126 static void ci_convert_mc_registers(const struct ci_mc_reg_entry *entry,
4127                                     SMU7_Discrete_MCRegisterSet *data,
4128                                     u32 num_entries, u32 valid_flag)
4129 {
4130         u32 i, j;
4131
4132         for (i = 0, j = 0; j < num_entries; j++) {
4133                 if (valid_flag & (1 << j)) {
4134                         data->value[i] = cpu_to_be32(entry->mc_data[j]);
4135                         i++;
4136                 }
4137         }
4138 }
4139
4140 static void ci_convert_mc_reg_table_entry_to_smc(struct radeon_device *rdev,
4141                                                  const u32 memory_clock,
4142                                                  SMU7_Discrete_MCRegisterSet *mc_reg_table_data)
4143 {
4144         struct ci_power_info *pi = ci_get_pi(rdev);
4145         u32 i = 0;
4146
4147         for(i = 0; i < pi->mc_reg_table.num_entries; i++) {
4148                 if (memory_clock <= pi->mc_reg_table.mc_reg_table_entry[i].mclk_max)
4149                         break;
4150         }
4151
4152         if ((i == pi->mc_reg_table.num_entries) && (i > 0))
4153                 --i;
4154
4155         ci_convert_mc_registers(&pi->mc_reg_table.mc_reg_table_entry[i],
4156                                 mc_reg_table_data, pi->mc_reg_table.last,
4157                                 pi->mc_reg_table.valid_flag);
4158 }
4159
4160 static void ci_convert_mc_reg_table_to_smc(struct radeon_device *rdev,
4161                                            SMU7_Discrete_MCRegisters *mc_reg_table)
4162 {
4163         struct ci_power_info *pi = ci_get_pi(rdev);
4164         u32 i;
4165
4166         for (i = 0; i < pi->dpm_table.mclk_table.count; i++)
4167                 ci_convert_mc_reg_table_entry_to_smc(rdev,
4168                                                      pi->dpm_table.mclk_table.dpm_levels[i].value,
4169                                                      &mc_reg_table->data[i]);
4170 }
4171
4172 static int ci_populate_initial_mc_reg_table(struct radeon_device *rdev)
4173 {
4174         struct ci_power_info *pi = ci_get_pi(rdev);
4175         int ret;
4176
4177         memset(&pi->smc_mc_reg_table, 0, sizeof(SMU7_Discrete_MCRegisters));
4178
4179         ret = ci_populate_mc_reg_addresses(rdev, &pi->smc_mc_reg_table);
4180         if (ret)
4181                 return ret;
4182         ci_convert_mc_reg_table_to_smc(rdev, &pi->smc_mc_reg_table);
4183
4184         return ci_copy_bytes_to_smc(rdev,
4185                                     pi->mc_reg_table_start,
4186                                     (u8 *)&pi->smc_mc_reg_table,
4187                                     sizeof(SMU7_Discrete_MCRegisters),
4188                                     pi->sram_end);
4189 }
4190
4191 static int ci_update_and_upload_mc_reg_table(struct radeon_device *rdev)
4192 {
4193         struct ci_power_info *pi = ci_get_pi(rdev);
4194
4195         if (!(pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK))
4196                 return 0;
4197
4198         memset(&pi->smc_mc_reg_table, 0, sizeof(SMU7_Discrete_MCRegisters));
4199
4200         ci_convert_mc_reg_table_to_smc(rdev, &pi->smc_mc_reg_table);
4201
4202         return ci_copy_bytes_to_smc(rdev,
4203                                     pi->mc_reg_table_start +
4204                                     offsetof(SMU7_Discrete_MCRegisters, data[0]),
4205                                     (u8 *)&pi->smc_mc_reg_table.data[0],
4206                                     sizeof(SMU7_Discrete_MCRegisterSet) *
4207                                     pi->dpm_table.mclk_table.count,
4208                                     pi->sram_end);
4209 }
4210
4211 static void ci_enable_voltage_control(struct radeon_device *rdev)
4212 {
4213         u32 tmp = RREG32_SMC(GENERAL_PWRMGT);
4214
4215         tmp |= VOLT_PWRMGT_EN;
4216         WREG32_SMC(GENERAL_PWRMGT, tmp);
4217 }
4218
4219 static enum radeon_pcie_gen ci_get_maximum_link_speed(struct radeon_device *rdev,
4220                                                       struct radeon_ps *radeon_state)
4221 {
4222         struct ci_ps *state = ci_get_ps(radeon_state);
4223         int i;
4224         u16 pcie_speed, max_speed = 0;
4225
4226         for (i = 0; i < state->performance_level_count; i++) {
4227                 pcie_speed = state->performance_levels[i].pcie_gen;
4228                 if (max_speed < pcie_speed)
4229                         max_speed = pcie_speed;
4230         }
4231
4232         return max_speed;
4233 }
4234
4235 static u16 ci_get_current_pcie_speed(struct radeon_device *rdev)
4236 {
4237         u32 speed_cntl = 0;
4238
4239         speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL) & LC_CURRENT_DATA_RATE_MASK;
4240         speed_cntl >>= LC_CURRENT_DATA_RATE_SHIFT;
4241
4242         return (u16)speed_cntl;
4243 }
4244
4245 static int ci_get_current_pcie_lane_number(struct radeon_device *rdev)
4246 {
4247         u32 link_width = 0;
4248
4249         link_width = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL) & LC_LINK_WIDTH_RD_MASK;
4250         link_width >>= LC_LINK_WIDTH_RD_SHIFT;
4251
4252         switch (link_width) {
4253         case RADEON_PCIE_LC_LINK_WIDTH_X1:
4254                 return 1;
4255         case RADEON_PCIE_LC_LINK_WIDTH_X2:
4256                 return 2;
4257         case RADEON_PCIE_LC_LINK_WIDTH_X4:
4258                 return 4;
4259         case RADEON_PCIE_LC_LINK_WIDTH_X8:
4260                 return 8;
4261         case RADEON_PCIE_LC_LINK_WIDTH_X12:
4262                 /* not actually supported */
4263                 return 12;
4264         case RADEON_PCIE_LC_LINK_WIDTH_X0:
4265         case RADEON_PCIE_LC_LINK_WIDTH_X16:
4266         default:
4267                 return 16;
4268         }
4269 }
4270
4271 static void ci_request_link_speed_change_before_state_change(struct radeon_device *rdev,
4272                                                              struct radeon_ps *radeon_new_state,
4273                                                              struct radeon_ps *radeon_current_state)
4274 {
4275         struct ci_power_info *pi = ci_get_pi(rdev);
4276         enum radeon_pcie_gen target_link_speed =
4277                 ci_get_maximum_link_speed(rdev, radeon_new_state);
4278         enum radeon_pcie_gen current_link_speed;
4279
4280         if (pi->force_pcie_gen == RADEON_PCIE_GEN_INVALID)
4281                 current_link_speed = ci_get_maximum_link_speed(rdev, radeon_current_state);
4282         else
4283                 current_link_speed = pi->force_pcie_gen;
4284
4285         pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID;
4286         pi->pspp_notify_required = false;
4287         if (target_link_speed > current_link_speed) {
4288                 switch (target_link_speed) {
4289 #ifdef CONFIG_ACPI
4290                 case RADEON_PCIE_GEN3:
4291                         if (radeon_acpi_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN3, false) == 0)
4292                                 break;
4293                         pi->force_pcie_gen = RADEON_PCIE_GEN2;
4294                         if (current_link_speed == RADEON_PCIE_GEN2)
4295                                 break;
4296                 case RADEON_PCIE_GEN2:
4297                         if (radeon_acpi_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN2, false) == 0)
4298                                 break;
4299 #endif
4300                 default:
4301                         pi->force_pcie_gen = ci_get_current_pcie_speed(rdev);
4302                         break;
4303                 }
4304         } else {
4305                 if (target_link_speed < current_link_speed)
4306                         pi->pspp_notify_required = true;
4307         }
4308 }
4309
4310 static void ci_notify_link_speed_change_after_state_change(struct radeon_device *rdev,
4311                                                            struct radeon_ps *radeon_new_state,
4312                                                            struct radeon_ps *radeon_current_state)
4313 {
4314         struct ci_power_info *pi = ci_get_pi(rdev);
4315         enum radeon_pcie_gen target_link_speed =
4316                 ci_get_maximum_link_speed(rdev, radeon_new_state);
4317         u8 request;
4318
4319         if (pi->pspp_notify_required) {
4320                 if (target_link_speed == RADEON_PCIE_GEN3)
4321                         request = PCIE_PERF_REQ_PECI_GEN3;
4322                 else if (target_link_speed == RADEON_PCIE_GEN2)
4323                         request = PCIE_PERF_REQ_PECI_GEN2;
4324                 else
4325                         request = PCIE_PERF_REQ_PECI_GEN1;
4326
4327                 if ((request == PCIE_PERF_REQ_PECI_GEN1) &&
4328                     (ci_get_current_pcie_speed(rdev) > 0))
4329                         return;
4330
4331 #ifdef CONFIG_ACPI
4332                 radeon_acpi_pcie_performance_request(rdev, request, false);
4333 #endif
4334         }
4335 }
4336
4337 static int ci_set_private_data_variables_based_on_pptable(struct radeon_device *rdev)
4338 {
4339         struct ci_power_info *pi = ci_get_pi(rdev);
4340         struct radeon_clock_voltage_dependency_table *allowed_sclk_vddc_table =
4341                 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
4342         struct radeon_clock_voltage_dependency_table *allowed_mclk_vddc_table =
4343                 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk;
4344         struct radeon_clock_voltage_dependency_table *allowed_mclk_vddci_table =
4345                 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk;
4346
4347         if (allowed_sclk_vddc_table == NULL)
4348                 return -EINVAL;
4349         if (allowed_sclk_vddc_table->count < 1)
4350                 return -EINVAL;
4351         if (allowed_mclk_vddc_table == NULL)
4352                 return -EINVAL;
4353         if (allowed_mclk_vddc_table->count < 1)
4354                 return -EINVAL;
4355         if (allowed_mclk_vddci_table == NULL)
4356                 return -EINVAL;
4357         if (allowed_mclk_vddci_table->count < 1)
4358                 return -EINVAL;
4359
4360         pi->min_vddc_in_pp_table = allowed_sclk_vddc_table->entries[0].v;
4361         pi->max_vddc_in_pp_table =
4362                 allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].v;
4363
4364         pi->min_vddci_in_pp_table = allowed_mclk_vddci_table->entries[0].v;
4365         pi->max_vddci_in_pp_table =
4366                 allowed_mclk_vddci_table->entries[allowed_mclk_vddci_table->count - 1].v;
4367
4368         rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk =
4369                 allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].clk;
4370         rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk =
4371                 allowed_mclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].clk;
4372         rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc =
4373                 allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].v;
4374         rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddci =
4375                 allowed_mclk_vddci_table->entries[allowed_mclk_vddci_table->count - 1].v;
4376
4377         return 0;
4378 }
4379
4380 static void ci_patch_with_vddc_leakage(struct radeon_device *rdev, u16 *vddc)
4381 {
4382         struct ci_power_info *pi = ci_get_pi(rdev);
4383         struct ci_leakage_voltage *leakage_table = &pi->vddc_leakage;
4384         u32 leakage_index;
4385
4386         for (leakage_index = 0; leakage_index < leakage_table->count; leakage_index++) {
4387                 if (leakage_table->leakage_id[leakage_index] == *vddc) {
4388                         *vddc = leakage_table->actual_voltage[leakage_index];
4389                         break;
4390                 }
4391         }
4392 }
4393
4394 static void ci_patch_with_vddci_leakage(struct radeon_device *rdev, u16 *vddci)
4395 {
4396         struct ci_power_info *pi = ci_get_pi(rdev);
4397         struct ci_leakage_voltage *leakage_table = &pi->vddci_leakage;
4398         u32 leakage_index;
4399
4400         for (leakage_index = 0; leakage_index < leakage_table->count; leakage_index++) {
4401                 if (leakage_table->leakage_id[leakage_index] == *vddci) {
4402                         *vddci = leakage_table->actual_voltage[leakage_index];
4403                         break;
4404                 }
4405         }
4406 }
4407
4408 static void ci_patch_clock_voltage_dependency_table_with_vddc_leakage(struct radeon_device *rdev,
4409                                                                       struct radeon_clock_voltage_dependency_table *table)
4410 {
4411         u32 i;
4412
4413         if (table) {
4414                 for (i = 0; i < table->count; i++)
4415                         ci_patch_with_vddc_leakage(rdev, &table->entries[i].v);
4416         }
4417 }
4418
4419 static void ci_patch_clock_voltage_dependency_table_with_vddci_leakage(struct radeon_device *rdev,
4420                                                                        struct radeon_clock_voltage_dependency_table *table)
4421 {
4422         u32 i;
4423
4424         if (table) {
4425                 for (i = 0; i < table->count; i++)
4426                         ci_patch_with_vddci_leakage(rdev, &table->entries[i].v);
4427         }
4428 }
4429
4430 static void ci_patch_vce_clock_voltage_dependency_table_with_vddc_leakage(struct radeon_device *rdev,
4431                                                                           struct radeon_vce_clock_voltage_dependency_table *table)
4432 {
4433         u32 i;
4434
4435         if (table) {
4436                 for (i = 0; i < table->count; i++)
4437                         ci_patch_with_vddc_leakage(rdev, &table->entries[i].v);
4438         }
4439 }
4440
4441 static void ci_patch_uvd_clock_voltage_dependency_table_with_vddc_leakage(struct radeon_device *rdev,
4442                                                                           struct radeon_uvd_clock_voltage_dependency_table *table)
4443 {
4444         u32 i;
4445
4446         if (table) {
4447                 for (i = 0; i < table->count; i++)
4448                         ci_patch_with_vddc_leakage(rdev, &table->entries[i].v);
4449         }
4450 }
4451
4452 static void ci_patch_vddc_phase_shed_limit_table_with_vddc_leakage(struct radeon_device *rdev,
4453                                                                    struct radeon_phase_shedding_limits_table *table)
4454 {
4455         u32 i;
4456
4457         if (table) {
4458                 for (i = 0; i < table->count; i++)
4459                         ci_patch_with_vddc_leakage(rdev, &table->entries[i].voltage);
4460         }
4461 }
4462
4463 static void ci_patch_clock_voltage_limits_with_vddc_leakage(struct radeon_device *rdev,
4464                                                             struct radeon_clock_and_voltage_limits *table)
4465 {
4466         if (table) {
4467                 ci_patch_with_vddc_leakage(rdev, (u16 *)&table->vddc);
4468                 ci_patch_with_vddci_leakage(rdev, (u16 *)&table->vddci);
4469         }
4470 }
4471
4472 static void ci_patch_cac_leakage_table_with_vddc_leakage(struct radeon_device *rdev,
4473                                                          struct radeon_cac_leakage_table *table)
4474 {
4475         u32 i;
4476
4477         if (table) {
4478                 for (i = 0; i < table->count; i++)
4479                         ci_patch_with_vddc_leakage(rdev, &table->entries[i].vddc);
4480         }
4481 }
4482
4483 static void ci_patch_dependency_tables_with_leakage(struct radeon_device *rdev)
4484 {
4485
4486         ci_patch_clock_voltage_dependency_table_with_vddc_leakage(rdev,
4487                                                                   &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk);
4488         ci_patch_clock_voltage_dependency_table_with_vddc_leakage(rdev,
4489                                                                   &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk);
4490         ci_patch_clock_voltage_dependency_table_with_vddc_leakage(rdev,
4491                                                                   &rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk);
4492         ci_patch_clock_voltage_dependency_table_with_vddci_leakage(rdev,
4493                                                                    &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk);
4494         ci_patch_vce_clock_voltage_dependency_table_with_vddc_leakage(rdev,
4495                                                                       &rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table);
4496         ci_patch_uvd_clock_voltage_dependency_table_with_vddc_leakage(rdev,
4497                                                                       &rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table);
4498         ci_patch_clock_voltage_dependency_table_with_vddc_leakage(rdev,
4499                                                                   &rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table);
4500         ci_patch_clock_voltage_dependency_table_with_vddc_leakage(rdev,
4501                                                                   &rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table);
4502         ci_patch_vddc_phase_shed_limit_table_with_vddc_leakage(rdev,
4503                                                                &rdev->pm.dpm.dyn_state.phase_shedding_limits_table);
4504         ci_patch_clock_voltage_limits_with_vddc_leakage(rdev,
4505                                                         &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac);
4506         ci_patch_clock_voltage_limits_with_vddc_leakage(rdev,
4507                                                         &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc);
4508         ci_patch_cac_leakage_table_with_vddc_leakage(rdev,
4509                                                      &rdev->pm.dpm.dyn_state.cac_leakage_table);
4510
4511 }
4512
4513 static void ci_get_memory_type(struct radeon_device *rdev)
4514 {
4515         struct ci_power_info *pi = ci_get_pi(rdev);
4516         u32 tmp;
4517
4518         tmp = RREG32(MC_SEQ_MISC0);
4519
4520         if (((tmp & MC_SEQ_MISC0_GDDR5_MASK) >> MC_SEQ_MISC0_GDDR5_SHIFT) ==
4521             MC_SEQ_MISC0_GDDR5_VALUE)
4522                 pi->mem_gddr5 = true;
4523         else
4524                 pi->mem_gddr5 = false;
4525
4526 }
4527
4528 static void ci_update_current_ps(struct radeon_device *rdev,
4529                                  struct radeon_ps *rps)
4530 {
4531         struct ci_ps *new_ps = ci_get_ps(rps);
4532         struct ci_power_info *pi = ci_get_pi(rdev);
4533
4534         pi->current_rps = *rps;
4535         pi->current_ps = *new_ps;
4536         pi->current_rps.ps_priv = &pi->current_ps;
4537 }
4538
4539 static void ci_update_requested_ps(struct radeon_device *rdev,
4540                                    struct radeon_ps *rps)
4541 {
4542         struct ci_ps *new_ps = ci_get_ps(rps);
4543         struct ci_power_info *pi = ci_get_pi(rdev);
4544
4545         pi->requested_rps = *rps;
4546         pi->requested_ps = *new_ps;
4547         pi->requested_rps.ps_priv = &pi->requested_ps;
4548 }
4549
4550 int ci_dpm_pre_set_power_state(struct radeon_device *rdev)
4551 {
4552         struct ci_power_info *pi = ci_get_pi(rdev);
4553         struct radeon_ps requested_ps = *rdev->pm.dpm.requested_ps;
4554         struct radeon_ps *new_ps = &requested_ps;
4555
4556         ci_update_requested_ps(rdev, new_ps);
4557
4558         ci_apply_state_adjust_rules(rdev, &pi->requested_rps);
4559
4560         return 0;
4561 }
4562
4563 void ci_dpm_post_set_power_state(struct radeon_device *rdev)
4564 {
4565         struct ci_power_info *pi = ci_get_pi(rdev);
4566         struct radeon_ps *new_ps = &pi->requested_rps;
4567
4568         ci_update_current_ps(rdev, new_ps);
4569 }
4570
4571
4572 void ci_dpm_setup_asic(struct radeon_device *rdev)
4573 {
4574         int r;
4575
4576         r = ci_mc_load_microcode(rdev);
4577         if (r)
4578                 DRM_ERROR("Failed to load MC firmware!\n");
4579         ci_read_clock_registers(rdev);
4580         ci_get_memory_type(rdev);
4581         ci_enable_acpi_power_management(rdev);
4582         ci_init_sclk_t(rdev);
4583 }
4584
4585 int ci_dpm_enable(struct radeon_device *rdev)
4586 {
4587         struct ci_power_info *pi = ci_get_pi(rdev);
4588         struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;
4589         int ret;
4590
4591         if (ci_is_smc_running(rdev))
4592                 return -EINVAL;
4593         if (pi->voltage_control != CISLANDS_VOLTAGE_CONTROL_NONE) {
4594                 ci_enable_voltage_control(rdev);
4595                 ret = ci_construct_voltage_tables(rdev);
4596                 if (ret) {
4597                         DRM_ERROR("ci_construct_voltage_tables failed\n");
4598                         return ret;
4599                 }
4600         }
4601         if (pi->caps_dynamic_ac_timing) {
4602                 ret = ci_initialize_mc_reg_table(rdev);
4603                 if (ret)
4604                         pi->caps_dynamic_ac_timing = false;
4605         }
4606         if (pi->dynamic_ss)
4607                 ci_enable_spread_spectrum(rdev, true);
4608         if (pi->thermal_protection)
4609                 ci_enable_thermal_protection(rdev, true);
4610         ci_program_sstp(rdev);
4611         ci_enable_display_gap(rdev);
4612         ci_program_vc(rdev);
4613         ret = ci_upload_firmware(rdev);
4614         if (ret) {
4615                 DRM_ERROR("ci_upload_firmware failed\n");
4616                 return ret;
4617         }
4618         ret = ci_process_firmware_header(rdev);
4619         if (ret) {
4620                 DRM_ERROR("ci_process_firmware_header failed\n");
4621                 return ret;
4622         }
4623         ret = ci_initial_switch_from_arb_f0_to_f1(rdev);
4624         if (ret) {
4625                 DRM_ERROR("ci_initial_switch_from_arb_f0_to_f1 failed\n");
4626                 return ret;
4627         }
4628         ret = ci_init_smc_table(rdev);
4629         if (ret) {
4630                 DRM_ERROR("ci_init_smc_table failed\n");
4631                 return ret;
4632         }
4633         ret = ci_init_arb_table_index(rdev);
4634         if (ret) {
4635                 DRM_ERROR("ci_init_arb_table_index failed\n");
4636                 return ret;
4637         }
4638         if (pi->caps_dynamic_ac_timing) {
4639                 ret = ci_populate_initial_mc_reg_table(rdev);
4640                 if (ret) {
4641                         DRM_ERROR("ci_populate_initial_mc_reg_table failed\n");
4642                         return ret;
4643                 }
4644         }
4645         ret = ci_populate_pm_base(rdev);
4646         if (ret) {
4647                 DRM_ERROR("ci_populate_pm_base failed\n");
4648                 return ret;
4649         }
4650         ci_dpm_start_smc(rdev);
4651         ci_enable_vr_hot_gpio_interrupt(rdev);
4652         ret = ci_notify_smc_display_change(rdev, false);
4653         if (ret) {
4654                 DRM_ERROR("ci_notify_smc_display_change failed\n");
4655                 return ret;
4656         }
4657         ci_enable_sclk_control(rdev, true);
4658         ret = ci_enable_ulv(rdev, true);
4659         if (ret) {
4660                 DRM_ERROR("ci_enable_ulv failed\n");
4661                 return ret;
4662         }
4663         ret = ci_enable_ds_master_switch(rdev, true);
4664         if (ret) {
4665                 DRM_ERROR("ci_enable_ds_master_switch failed\n");
4666                 return ret;
4667         }
4668         ret = ci_start_dpm(rdev);
4669         if (ret) {
4670                 DRM_ERROR("ci_start_dpm failed\n");
4671                 return ret;
4672         }
4673         ret = ci_enable_didt(rdev, true);
4674         if (ret) {
4675                 DRM_ERROR("ci_enable_didt failed\n");
4676                 return ret;
4677         }
4678         ret = ci_enable_smc_cac(rdev, true);
4679         if (ret) {
4680                 DRM_ERROR("ci_enable_smc_cac failed\n");
4681                 return ret;
4682         }
4683         ret = ci_enable_power_containment(rdev, true);
4684         if (ret) {
4685                 DRM_ERROR("ci_enable_power_containment failed\n");
4686                 return ret;
4687         }
4688
4689         ci_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, true);
4690
4691         ci_update_current_ps(rdev, boot_ps);
4692
4693         return 0;
4694 }
4695
4696 int ci_dpm_late_enable(struct radeon_device *rdev)
4697 {
4698         int ret;
4699
4700         if (rdev->irq.installed &&
4701             r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) {
4702 #if 0
4703                 PPSMC_Result result;
4704 #endif
4705                 ret = ci_set_thermal_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
4706                 if (ret) {
4707                         DRM_ERROR("ci_set_thermal_temperature_range failed\n");
4708                         return ret;
4709                 }
4710                 rdev->irq.dpm_thermal = true;
4711                 radeon_irq_set(rdev);
4712 #if 0
4713                 result = ci_send_msg_to_smc(rdev, PPSMC_MSG_EnableThermalInterrupt);
4714
4715                 if (result != PPSMC_Result_OK)
4716                         DRM_DEBUG_KMS("Could not enable thermal interrupts.\n");
4717 #endif
4718         }
4719
4720         ci_dpm_powergate_uvd(rdev, true);
4721
4722         return 0;
4723 }
4724
4725 void ci_dpm_disable(struct radeon_device *rdev)
4726 {
4727         struct ci_power_info *pi = ci_get_pi(rdev);
4728         struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;
4729
4730         ci_dpm_powergate_uvd(rdev, false);
4731
4732         if (!ci_is_smc_running(rdev))
4733                 return;
4734
4735         if (pi->thermal_protection)
4736                 ci_enable_thermal_protection(rdev, false);
4737         ci_enable_power_containment(rdev, false);
4738         ci_enable_smc_cac(rdev, false);
4739         ci_enable_didt(rdev, false);
4740         ci_enable_spread_spectrum(rdev, false);
4741         ci_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, false);
4742         ci_stop_dpm(rdev);
4743         ci_enable_ds_master_switch(rdev, true);
4744         ci_enable_ulv(rdev, false);
4745         ci_clear_vc(rdev);
4746         ci_reset_to_default(rdev);
4747         ci_dpm_stop_smc(rdev);
4748         ci_force_switch_to_arb_f0(rdev);
4749
4750         ci_update_current_ps(rdev, boot_ps);
4751 }
4752
4753 int ci_dpm_set_power_state(struct radeon_device *rdev)
4754 {
4755         struct ci_power_info *pi = ci_get_pi(rdev);
4756         struct radeon_ps *new_ps = &pi->requested_rps;
4757         struct radeon_ps *old_ps = &pi->current_rps;
4758         int ret;
4759
4760         ci_find_dpm_states_clocks_in_dpm_table(rdev, new_ps);
4761         if (pi->pcie_performance_request)
4762                 ci_request_link_speed_change_before_state_change(rdev, new_ps, old_ps);
4763         ret = ci_freeze_sclk_mclk_dpm(rdev);
4764         if (ret) {
4765                 DRM_ERROR("ci_freeze_sclk_mclk_dpm failed\n");
4766                 return ret;
4767         }
4768         ret = ci_populate_and_upload_sclk_mclk_dpm_levels(rdev, new_ps);
4769         if (ret) {
4770                 DRM_ERROR("ci_populate_and_upload_sclk_mclk_dpm_levels failed\n");
4771                 return ret;
4772         }
4773         ret = ci_generate_dpm_level_enable_mask(rdev, new_ps);
4774         if (ret) {
4775                 DRM_ERROR("ci_generate_dpm_level_enable_mask failed\n");
4776                 return ret;
4777         }
4778
4779         ret = ci_update_vce_dpm(rdev, new_ps, old_ps);
4780         if (ret) {
4781                 DRM_ERROR("ci_update_vce_dpm failed\n");
4782                 return ret;
4783         }
4784
4785         ret = ci_update_sclk_t(rdev);
4786         if (ret) {
4787                 DRM_ERROR("ci_update_sclk_t failed\n");
4788                 return ret;
4789         }
4790         if (pi->caps_dynamic_ac_timing) {
4791                 ret = ci_update_and_upload_mc_reg_table(rdev);
4792                 if (ret) {
4793                         DRM_ERROR("ci_update_and_upload_mc_reg_table failed\n");
4794                         return ret;
4795                 }
4796         }
4797         ret = ci_program_memory_timing_parameters(rdev);
4798         if (ret) {
4799                 DRM_ERROR("ci_program_memory_timing_parameters failed\n");
4800                 return ret;
4801         }
4802         ret = ci_unfreeze_sclk_mclk_dpm(rdev);
4803         if (ret) {
4804                 DRM_ERROR("ci_unfreeze_sclk_mclk_dpm failed\n");
4805                 return ret;
4806         }
4807         ret = ci_upload_dpm_level_enable_mask(rdev);
4808         if (ret) {
4809                 DRM_ERROR("ci_upload_dpm_level_enable_mask failed\n");
4810                 return ret;
4811         }
4812         if (pi->pcie_performance_request)
4813                 ci_notify_link_speed_change_after_state_change(rdev, new_ps, old_ps);
4814
4815         return 0;
4816 }
4817
4818 int ci_dpm_power_control_set_level(struct radeon_device *rdev)
4819 {
4820         return ci_power_control_set_level(rdev);
4821 }
4822
4823 void ci_dpm_reset_asic(struct radeon_device *rdev)
4824 {
4825         ci_set_boot_state(rdev);
4826 }
4827
4828 void ci_dpm_display_configuration_changed(struct radeon_device *rdev)
4829 {
4830         ci_program_display_gap(rdev);
4831 }
4832
4833 union power_info {
4834         struct _ATOM_POWERPLAY_INFO info;
4835         struct _ATOM_POWERPLAY_INFO_V2 info_2;
4836         struct _ATOM_POWERPLAY_INFO_V3 info_3;
4837         struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
4838         struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
4839         struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
4840 };
4841
4842 union pplib_clock_info {
4843         struct _ATOM_PPLIB_R600_CLOCK_INFO r600;
4844         struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780;
4845         struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
4846         struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo;
4847         struct _ATOM_PPLIB_SI_CLOCK_INFO si;
4848         struct _ATOM_PPLIB_CI_CLOCK_INFO ci;
4849 };
4850
4851 union pplib_power_state {
4852         struct _ATOM_PPLIB_STATE v1;
4853         struct _ATOM_PPLIB_STATE_V2 v2;
4854 };
4855
4856 static void ci_parse_pplib_non_clock_info(struct radeon_device *rdev,
4857                                           struct radeon_ps *rps,
4858                                           struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info,
4859                                           u8 table_rev)
4860 {
4861         rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings);
4862         rps->class = le16_to_cpu(non_clock_info->usClassification);
4863         rps->class2 = le16_to_cpu(non_clock_info->usClassification2);
4864
4865         if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) {
4866                 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK);
4867                 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK);
4868         } else {
4869                 rps->vclk = 0;
4870                 rps->dclk = 0;
4871         }
4872
4873         if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT)
4874                 rdev->pm.dpm.boot_ps = rps;
4875         if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE)
4876                 rdev->pm.dpm.uvd_ps = rps;
4877 }
4878
4879 static void ci_parse_pplib_clock_info(struct radeon_device *rdev,
4880                                       struct radeon_ps *rps, int index,
4881                                       union pplib_clock_info *clock_info)
4882 {
4883         struct ci_power_info *pi = ci_get_pi(rdev);
4884         struct ci_ps *ps = ci_get_ps(rps);
4885         struct ci_pl *pl = &ps->performance_levels[index];
4886
4887         ps->performance_level_count = index + 1;
4888
4889         pl->sclk = le16_to_cpu(clock_info->ci.usEngineClockLow);
4890         pl->sclk |= clock_info->ci.ucEngineClockHigh << 16;
4891         pl->mclk = le16_to_cpu(clock_info->ci.usMemoryClockLow);
4892         pl->mclk |= clock_info->ci.ucMemoryClockHigh << 16;
4893
4894         pl->pcie_gen = r600_get_pcie_gen_support(rdev,
4895                                                  pi->sys_pcie_mask,
4896                                                  pi->vbios_boot_state.pcie_gen_bootup_value,
4897                                                  clock_info->ci.ucPCIEGen);
4898         pl->pcie_lane = r600_get_pcie_lane_support(rdev,
4899                                                    pi->vbios_boot_state.pcie_lane_bootup_value,
4900                                                    le16_to_cpu(clock_info->ci.usPCIELane));
4901
4902         if (rps->class & ATOM_PPLIB_CLASSIFICATION_ACPI) {
4903                 pi->acpi_pcie_gen = pl->pcie_gen;
4904         }
4905
4906         if (rps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV) {
4907                 pi->ulv.supported = true;
4908                 pi->ulv.pl = *pl;
4909                 pi->ulv.cg_ulv_parameter = CISLANDS_CGULVPARAMETER_DFLT;
4910         }
4911
4912         /* patch up boot state */
4913         if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) {
4914                 pl->mclk = pi->vbios_boot_state.mclk_bootup_value;
4915                 pl->sclk = pi->vbios_boot_state.sclk_bootup_value;
4916                 pl->pcie_gen = pi->vbios_boot_state.pcie_gen_bootup_value;
4917                 pl->pcie_lane = pi->vbios_boot_state.pcie_lane_bootup_value;
4918         }
4919
4920         switch (rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) {
4921         case ATOM_PPLIB_CLASSIFICATION_UI_BATTERY:
4922                 pi->use_pcie_powersaving_levels = true;
4923                 if (pi->pcie_gen_powersaving.max < pl->pcie_gen)
4924                         pi->pcie_gen_powersaving.max = pl->pcie_gen;
4925                 if (pi->pcie_gen_powersaving.min > pl->pcie_gen)
4926                         pi->pcie_gen_powersaving.min = pl->pcie_gen;
4927                 if (pi->pcie_lane_powersaving.max < pl->pcie_lane)
4928                         pi->pcie_lane_powersaving.max = pl->pcie_lane;
4929                 if (pi->pcie_lane_powersaving.min > pl->pcie_lane)
4930                         pi->pcie_lane_powersaving.min = pl->pcie_lane;
4931                 break;
4932         case ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE:
4933                 pi->use_pcie_performance_levels = true;
4934                 if (pi->pcie_gen_performance.max < pl->pcie_gen)
4935                         pi->pcie_gen_performance.max = pl->pcie_gen;
4936                 if (pi->pcie_gen_performance.min > pl->pcie_gen)
4937                         pi->pcie_gen_performance.min = pl->pcie_gen;
4938                 if (pi->pcie_lane_performance.max < pl->pcie_lane)
4939                         pi->pcie_lane_performance.max = pl->pcie_lane;
4940                 if (pi->pcie_lane_performance.min > pl->pcie_lane)
4941                         pi->pcie_lane_performance.min = pl->pcie_lane;
4942                 break;
4943         default:
4944                 break;
4945         }
4946 }
4947
4948 static int ci_parse_power_table(struct radeon_device *rdev)
4949 {
4950         struct radeon_mode_info *mode_info = &rdev->mode_info;
4951         struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
4952         union pplib_power_state *power_state;
4953         int i, j, k, non_clock_array_index, clock_array_index;
4954         union pplib_clock_info *clock_info;
4955         struct _StateArray *state_array;
4956         struct _ClockInfoArray *clock_info_array;
4957         struct _NonClockInfoArray *non_clock_info_array;
4958         union power_info *power_info;
4959         int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
4960         u16 data_offset;
4961         u8 frev, crev;
4962         u8 *power_state_offset;
4963         struct ci_ps *ps;
4964
4965         if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
4966                                    &frev, &crev, &data_offset))
4967                 return -EINVAL;
4968         power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
4969
4970         state_array = (struct _StateArray *)
4971                 (mode_info->atom_context->bios + data_offset +
4972                  le16_to_cpu(power_info->pplib.usStateArrayOffset));
4973         clock_info_array = (struct _ClockInfoArray *)
4974                 (mode_info->atom_context->bios + data_offset +
4975                  le16_to_cpu(power_info->pplib.usClockInfoArrayOffset));
4976         non_clock_info_array = (struct _NonClockInfoArray *)
4977                 (mode_info->atom_context->bios + data_offset +
4978                  le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset));
4979
4980         rdev->pm.dpm.ps = kzalloc(sizeof(struct radeon_ps) *
4981                                   state_array->ucNumEntries, GFP_KERNEL);
4982         if (!rdev->pm.dpm.ps)
4983                 return -ENOMEM;
4984         power_state_offset = (u8 *)state_array->states;
4985         for (i = 0; i < state_array->ucNumEntries; i++) {
4986                 u8 *idx;
4987                 power_state = (union pplib_power_state *)power_state_offset;
4988                 non_clock_array_index = power_state->v2.nonClockInfoIndex;
4989                 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
4990                         &non_clock_info_array->nonClockInfo[non_clock_array_index];
4991                 if (!rdev->pm.power_state[i].clock_info)
4992                         return -EINVAL;
4993                 ps = kzalloc(sizeof(struct ci_ps), GFP_KERNEL);
4994                 if (ps == NULL) {
4995                         kfree(rdev->pm.dpm.ps);
4996                         return -ENOMEM;
4997                 }
4998                 rdev->pm.dpm.ps[i].ps_priv = ps;
4999                 ci_parse_pplib_non_clock_info(rdev, &rdev->pm.dpm.ps[i],
5000                                               non_clock_info,
5001                                               non_clock_info_array->ucEntrySize);
5002                 k = 0;
5003                 idx = (u8 *)&power_state->v2.clockInfoIndex[0];
5004                 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) {
5005                         clock_array_index = idx[j];
5006                         if (clock_array_index >= clock_info_array->ucNumEntries)
5007                                 continue;
5008                         if (k >= CISLANDS_MAX_HARDWARE_POWERLEVELS)
5009                                 break;
5010                         clock_info = (union pplib_clock_info *)
5011                                 ((u8 *)&clock_info_array->clockInfo[0] +
5012                                  (clock_array_index * clock_info_array->ucEntrySize));
5013                         ci_parse_pplib_clock_info(rdev,
5014                                                   &rdev->pm.dpm.ps[i], k,
5015                                                   clock_info);
5016                         k++;
5017                 }
5018                 power_state_offset += 2 + power_state->v2.ucNumDPMLevels;
5019         }
5020         rdev->pm.dpm.num_ps = state_array->ucNumEntries;
5021
5022         /* fill in the vce power states */
5023         for (i = 0; i < RADEON_MAX_VCE_LEVELS; i++) {
5024                 u32 sclk, mclk;
5025                 clock_array_index = rdev->pm.dpm.vce_states[i].clk_idx;
5026                 clock_info = (union pplib_clock_info *)
5027                         &clock_info_array->clockInfo[clock_array_index * clock_info_array->ucEntrySize];
5028                 sclk = le16_to_cpu(clock_info->ci.usEngineClockLow);
5029                 sclk |= clock_info->ci.ucEngineClockHigh << 16;
5030                 mclk = le16_to_cpu(clock_info->ci.usMemoryClockLow);
5031                 mclk |= clock_info->ci.ucMemoryClockHigh << 16;
5032                 rdev->pm.dpm.vce_states[i].sclk = sclk;
5033                 rdev->pm.dpm.vce_states[i].mclk = mclk;
5034         }
5035
5036         return 0;
5037 }
5038
5039 static int ci_get_vbios_boot_values(struct radeon_device *rdev,
5040                                     struct ci_vbios_boot_state *boot_state)
5041 {
5042         struct radeon_mode_info *mode_info = &rdev->mode_info;
5043         int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
5044         ATOM_FIRMWARE_INFO_V2_2 *firmware_info;
5045         u8 frev, crev;
5046         u16 data_offset;
5047
5048         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
5049                                    &frev, &crev, &data_offset)) {
5050                 firmware_info =
5051                         (ATOM_FIRMWARE_INFO_V2_2 *)(mode_info->atom_context->bios +
5052                                                     data_offset);
5053                 boot_state->mvdd_bootup_value = le16_to_cpu(firmware_info->usBootUpMVDDCVoltage);
5054                 boot_state->vddc_bootup_value = le16_to_cpu(firmware_info->usBootUpVDDCVoltage);
5055                 boot_state->vddci_bootup_value = le16_to_cpu(firmware_info->usBootUpVDDCIVoltage);
5056                 boot_state->pcie_gen_bootup_value = ci_get_current_pcie_speed(rdev);
5057                 boot_state->pcie_lane_bootup_value = ci_get_current_pcie_lane_number(rdev);
5058                 boot_state->sclk_bootup_value = le32_to_cpu(firmware_info->ulDefaultEngineClock);
5059                 boot_state->mclk_bootup_value = le32_to_cpu(firmware_info->ulDefaultMemoryClock);
5060
5061                 return 0;
5062         }
5063         return -EINVAL;
5064 }
5065
5066 void ci_dpm_fini(struct radeon_device *rdev)
5067 {
5068         int i;
5069
5070         for (i = 0; i < rdev->pm.dpm.num_ps; i++) {
5071                 kfree(rdev->pm.dpm.ps[i].ps_priv);
5072         }
5073         kfree(rdev->pm.dpm.ps);
5074         kfree(rdev->pm.dpm.priv);
5075         kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries);
5076         r600_free_extended_power_table(rdev);
5077 }
5078
5079 int ci_dpm_init(struct radeon_device *rdev)
5080 {
5081         int index = GetIndexIntoMasterTable(DATA, ASIC_InternalSS_Info);
5082         u16 data_offset, size;
5083         u8 frev, crev;
5084         struct ci_power_info *pi;
5085         int ret;
5086         u32 mask;
5087
5088         pi = kzalloc(sizeof(struct ci_power_info), GFP_KERNEL);
5089         if (pi == NULL)
5090                 return -ENOMEM;
5091         rdev->pm.dpm.priv = pi;
5092
5093         ret = drm_pcie_get_speed_cap_mask(rdev->ddev, &mask);
5094         if (ret)
5095                 pi->sys_pcie_mask = 0;
5096         else
5097                 pi->sys_pcie_mask = mask;
5098         pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID;
5099
5100         pi->pcie_gen_performance.max = RADEON_PCIE_GEN1;
5101         pi->pcie_gen_performance.min = RADEON_PCIE_GEN3;
5102         pi->pcie_gen_powersaving.max = RADEON_PCIE_GEN1;
5103         pi->pcie_gen_powersaving.min = RADEON_PCIE_GEN3;
5104
5105         pi->pcie_lane_performance.max = 0;
5106         pi->pcie_lane_performance.min = 16;
5107         pi->pcie_lane_powersaving.max = 0;
5108         pi->pcie_lane_powersaving.min = 16;
5109
5110         ret = ci_get_vbios_boot_values(rdev, &pi->vbios_boot_state);
5111         if (ret) {
5112                 ci_dpm_fini(rdev);
5113                 return ret;
5114         }
5115
5116         ret = r600_get_platform_caps(rdev);
5117         if (ret) {
5118                 ci_dpm_fini(rdev);
5119                 return ret;
5120         }
5121
5122         ret = r600_parse_extended_power_table(rdev);
5123         if (ret) {
5124                 ci_dpm_fini(rdev);
5125                 return ret;
5126         }
5127
5128         ret = ci_parse_power_table(rdev);
5129         if (ret) {
5130                 ci_dpm_fini(rdev);
5131                 return ret;
5132         }
5133
5134         pi->dll_default_on = false;
5135         pi->sram_end = SMC_RAM_END;
5136
5137         pi->activity_target[0] = CISLAND_TARGETACTIVITY_DFLT;
5138         pi->activity_target[1] = CISLAND_TARGETACTIVITY_DFLT;
5139         pi->activity_target[2] = CISLAND_TARGETACTIVITY_DFLT;
5140         pi->activity_target[3] = CISLAND_TARGETACTIVITY_DFLT;
5141         pi->activity_target[4] = CISLAND_TARGETACTIVITY_DFLT;
5142         pi->activity_target[5] = CISLAND_TARGETACTIVITY_DFLT;
5143         pi->activity_target[6] = CISLAND_TARGETACTIVITY_DFLT;
5144         pi->activity_target[7] = CISLAND_TARGETACTIVITY_DFLT;
5145
5146         pi->mclk_activity_target = CISLAND_MCLK_TARGETACTIVITY_DFLT;
5147
5148         pi->sclk_dpm_key_disabled = 0;
5149         pi->mclk_dpm_key_disabled = 0;
5150         pi->pcie_dpm_key_disabled = 0;
5151
5152         /* mclk dpm is unstable on some R7 260X cards with the old mc ucode */
5153         if ((rdev->pdev->device == 0x6658) &&
5154             (rdev->mc_fw->size == (BONAIRE_MC_UCODE_SIZE * 4))) {
5155                 pi->mclk_dpm_key_disabled = 1;
5156         }
5157
5158         pi->caps_sclk_ds = true;
5159
5160         pi->mclk_strobe_mode_threshold = 40000;
5161         pi->mclk_stutter_mode_threshold = 40000;
5162         pi->mclk_edc_enable_threshold = 40000;
5163         pi->mclk_edc_wr_enable_threshold = 40000;
5164
5165         ci_initialize_powertune_defaults(rdev);
5166
5167         pi->caps_fps = false;
5168
5169         pi->caps_sclk_throttle_low_notification = false;
5170
5171         pi->caps_uvd_dpm = true;
5172         pi->caps_vce_dpm = true;
5173
5174         ci_get_leakage_voltages(rdev);
5175         ci_patch_dependency_tables_with_leakage(rdev);
5176         ci_set_private_data_variables_based_on_pptable(rdev);
5177
5178         rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries =
5179                 kzalloc(4 * sizeof(struct radeon_clock_voltage_dependency_entry), GFP_KERNEL);
5180         if (!rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries) {
5181                 ci_dpm_fini(rdev);
5182                 return -ENOMEM;
5183         }
5184         rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count = 4;
5185         rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].clk = 0;
5186         rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].v = 0;
5187         rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].clk = 36000;
5188         rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].v = 720;
5189         rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].clk = 54000;
5190         rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].v = 810;
5191         rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].clk = 72000;
5192         rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].v = 900;
5193
5194         rdev->pm.dpm.dyn_state.mclk_sclk_ratio = 4;
5195         rdev->pm.dpm.dyn_state.sclk_mclk_delta = 15000;
5196         rdev->pm.dpm.dyn_state.vddc_vddci_delta = 200;
5197
5198         rdev->pm.dpm.dyn_state.valid_sclk_values.count = 0;
5199         rdev->pm.dpm.dyn_state.valid_sclk_values.values = NULL;
5200         rdev->pm.dpm.dyn_state.valid_mclk_values.count = 0;
5201         rdev->pm.dpm.dyn_state.valid_mclk_values.values = NULL;
5202
5203         if (rdev->family == CHIP_HAWAII) {
5204                 pi->thermal_temp_setting.temperature_low = 94500;
5205                 pi->thermal_temp_setting.temperature_high = 95000;
5206                 pi->thermal_temp_setting.temperature_shutdown = 104000;
5207         } else {
5208                 pi->thermal_temp_setting.temperature_low = 99500;
5209                 pi->thermal_temp_setting.temperature_high = 100000;
5210                 pi->thermal_temp_setting.temperature_shutdown = 104000;
5211         }
5212
5213         pi->uvd_enabled = false;
5214
5215         pi->voltage_control = CISLANDS_VOLTAGE_CONTROL_NONE;
5216         pi->vddci_control = CISLANDS_VOLTAGE_CONTROL_NONE;
5217         pi->mvdd_control = CISLANDS_VOLTAGE_CONTROL_NONE;
5218         if (radeon_atom_is_voltage_gpio(rdev, VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_GPIO_LUT))
5219                 pi->voltage_control = CISLANDS_VOLTAGE_CONTROL_BY_GPIO;
5220         else if (radeon_atom_is_voltage_gpio(rdev, VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_SVID2))
5221                 pi->voltage_control = CISLANDS_VOLTAGE_CONTROL_BY_SVID2;
5222
5223         if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_VDDCI_CONTROL) {
5224                 if (radeon_atom_is_voltage_gpio(rdev, VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT))
5225                         pi->vddci_control = CISLANDS_VOLTAGE_CONTROL_BY_GPIO;
5226                 else if (radeon_atom_is_voltage_gpio(rdev, VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_SVID2))
5227                         pi->vddci_control = CISLANDS_VOLTAGE_CONTROL_BY_SVID2;
5228                 else
5229                         rdev->pm.dpm.platform_caps &= ~ATOM_PP_PLATFORM_CAP_VDDCI_CONTROL;
5230         }
5231
5232         if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_MVDDCONTROL) {
5233                 if (radeon_atom_is_voltage_gpio(rdev, VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_GPIO_LUT))
5234                         pi->mvdd_control = CISLANDS_VOLTAGE_CONTROL_BY_GPIO;
5235                 else if (radeon_atom_is_voltage_gpio(rdev, VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_SVID2))
5236                         pi->mvdd_control = CISLANDS_VOLTAGE_CONTROL_BY_SVID2;
5237                 else
5238                         rdev->pm.dpm.platform_caps &= ~ATOM_PP_PLATFORM_CAP_MVDDCONTROL;
5239         }
5240
5241         pi->vddc_phase_shed_control = true;
5242
5243 #if defined(CONFIG_ACPI)
5244         pi->pcie_performance_request =
5245                 radeon_acpi_is_pcie_performance_request_supported(rdev);
5246 #else
5247         pi->pcie_performance_request = false;
5248 #endif
5249
5250         if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
5251                                    &frev, &crev, &data_offset)) {
5252                 pi->caps_sclk_ss_support = true;
5253                 pi->caps_mclk_ss_support = true;
5254                 pi->dynamic_ss = true;
5255         } else {
5256                 pi->caps_sclk_ss_support = false;
5257                 pi->caps_mclk_ss_support = false;
5258                 pi->dynamic_ss = true;
5259         }
5260
5261         if (rdev->pm.int_thermal_type != THERMAL_TYPE_NONE)
5262                 pi->thermal_protection = true;
5263         else
5264                 pi->thermal_protection = false;
5265
5266         pi->caps_dynamic_ac_timing = true;
5267
5268         pi->uvd_power_gated = false;
5269
5270         /* make sure dc limits are valid */
5271         if ((rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk == 0) ||
5272             (rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk == 0))
5273                 rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc =
5274                         rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
5275
5276         return 0;
5277 }
5278
5279 void ci_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
5280                                                     struct seq_file *m)
5281 {
5282         u32 sclk = ci_get_average_sclk_freq(rdev);
5283         u32 mclk = ci_get_average_mclk_freq(rdev);
5284
5285         seq_printf(m, "power level avg    sclk: %u mclk: %u\n",
5286                    sclk, mclk);
5287 }
5288
5289 void ci_dpm_print_power_state(struct radeon_device *rdev,
5290                               struct radeon_ps *rps)
5291 {
5292         struct ci_ps *ps = ci_get_ps(rps);
5293         struct ci_pl *pl;
5294         int i;
5295
5296         r600_dpm_print_class_info(rps->class, rps->class2);
5297         r600_dpm_print_cap_info(rps->caps);
5298         printk("\tuvd    vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
5299         for (i = 0; i < ps->performance_level_count; i++) {
5300                 pl = &ps->performance_levels[i];
5301                 printk("\t\tpower level %d    sclk: %u mclk: %u pcie gen: %u pcie lanes: %u\n",
5302                        i, pl->sclk, pl->mclk, pl->pcie_gen + 1, pl->pcie_lane);
5303         }
5304         r600_dpm_print_ps_status(rdev, rps);
5305 }
5306
5307 u32 ci_dpm_get_sclk(struct radeon_device *rdev, bool low)
5308 {
5309         struct ci_power_info *pi = ci_get_pi(rdev);
5310         struct ci_ps *requested_state = ci_get_ps(&pi->requested_rps);
5311
5312         if (low)
5313                 return requested_state->performance_levels[0].sclk;
5314         else
5315                 return requested_state->performance_levels[requested_state->performance_level_count - 1].sclk;
5316 }
5317
5318 u32 ci_dpm_get_mclk(struct radeon_device *rdev, bool low)
5319 {
5320         struct ci_power_info *pi = ci_get_pi(rdev);
5321         struct ci_ps *requested_state = ci_get_ps(&pi->requested_rps);
5322
5323         if (low)
5324                 return requested_state->performance_levels[0].mclk;
5325         else
5326                 return requested_state->performance_levels[requested_state->performance_level_count - 1].mclk;
5327 }