drivers/gpu/drm/radeon/ci_dpm.c

   1 /*
   2  * Copyright 2013 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/firmware.h>
  25 #include "drmP.h"
  26 #include "radeon.h"
  27 #include "radeon_asic.h"
  28 #include "radeon_ucode.h"
  29 #include "cikd.h"
  30 #include "r600_dpm.h"
  31 #include "ci_dpm.h"
  32 #include "atom.h"
  33 #include <linux/seq_file.h>
  34
  35 #define MC_CG_ARB_FREQ_F0           0x0a
  36 #define MC_CG_ARB_FREQ_F1           0x0b
  37 #define MC_CG_ARB_FREQ_F2           0x0c
  38 #define MC_CG_ARB_FREQ_F3           0x0d
  39
  40 #define SMC_RAM_END 0x40000
  41
  42 #define VOLTAGE_SCALE               4
  43 #define VOLTAGE_VID_OFFSET_SCALE1    625
  44 #define VOLTAGE_VID_OFFSET_SCALE2    100
  45
  46 static const struct ci_pt_defaults defaults_hawaii_xt =
  47 {
  48         1, 0xF, 0xFD, 0x19, 5, 0x14, 0, 0xB0000,
  49         { 0x84,  0x0,   0x0,   0x7F,  0x0,   0x0,   0x5A,  0x60,  0x51,  0x8E,  0x79,  0x6B,  0x5F,  0x90,  0x79  },
  50         { 0x1EA, 0x1EA, 0x1EA, 0x224, 0x224, 0x224, 0x24F, 0x24F, 0x24F, 0x28E, 0x28E, 0x28E, 0x2BC, 0x2BC, 0x2BC }
  51 };
  52
  53 static const struct ci_pt_defaults defaults_hawaii_pro =
  54 {
  55         1, 0xF, 0xFD, 0x19, 5, 0x14, 0, 0x65062,
  56         { 0x93,  0x0,   0x0,   0x97,  0x0,   0x0,   0x6B,  0x60,  0x51,  0x95,  0x79,  0x6B,  0x5F,  0x90,  0x79  },
  57         { 0x1EA, 0x1EA, 0x1EA, 0x224, 0x224, 0x224, 0x24F, 0x24F, 0x24F, 0x28E, 0x28E, 0x28E, 0x2BC, 0x2BC, 0x2BC }
  58 };
  59
  60 static const struct ci_pt_defaults defaults_bonaire_xt =
  61 {
  62         1, 0xF, 0xFD, 0x19, 5, 45, 0, 0xB0000,
  63         { 0x79,  0x253, 0x25D, 0xAE,  0x72,  0x80,  0x83,  0x86,  0x6F,  0xC8,  0xC9,  0xC9,  0x2F,  0x4D,  0x61  },
  64         { 0x17C, 0x172, 0x180, 0x1BC, 0x1B3, 0x1BD, 0x206, 0x200, 0x203, 0x25D, 0x25A, 0x255, 0x2C3, 0x2C5, 0x2B4 }
  65 };
  66
  67 static const struct ci_pt_defaults defaults_bonaire_pro =
  68 {
  69         1, 0xF, 0xFD, 0x19, 5, 45, 0, 0x65062,
  70         { 0x8C,  0x23F, 0x244, 0xA6,  0x83,  0x85,  0x86,  0x86,  0x83,  0xDB,  0xDB,  0xDA,  0x67,  0x60,  0x5F  },
  71         { 0x187, 0x193, 0x193, 0x1C7, 0x1D1, 0x1D1, 0x210, 0x219, 0x219, 0x266, 0x26C, 0x26C, 0x2C9, 0x2CB, 0x2CB }
  72 };
  73
  74 static const struct ci_pt_defaults defaults_saturn_xt =
  75 {
  76         1, 0xF, 0xFD, 0x19, 5, 55, 0, 0x70000,
  77         { 0x8C,  0x247, 0x249, 0xA6,  0x80,  0x81,  0x8B,  0x89,  0x86,  0xC9,  0xCA,  0xC9,  0x4D,  0x4D,  0x4D  },
  78         { 0x187, 0x187, 0x187, 0x1C7, 0x1C7, 0x1C7, 0x210, 0x210, 0x210, 0x266, 0x266, 0x266, 0x2C9, 0x2C9, 0x2C9 }
  79 };
  80
  81 static const struct ci_pt_defaults defaults_saturn_pro =
  82 {
  83         1, 0xF, 0xFD, 0x19, 5, 55, 0, 0x30000,
  84         { 0x96,  0x21D, 0x23B, 0xA1,  0x85,  0x87,  0x83,  0x84,  0x81,  0xE6,  0xE6,  0xE6,  0x71,  0x6A,  0x6A  },
  85         { 0x193, 0x19E, 0x19E, 0x1D2, 0x1DC, 0x1DC, 0x21A, 0x223, 0x223, 0x26E, 0x27E, 0x274, 0x2CF, 0x2D2, 0x2D2 }
  86 };
  87
  88 static const struct ci_pt_config_reg didt_config_ci[] =
  89 {
  90         { 0x10, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
  91         { 0x10, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
  92         { 0x10, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
  93         { 0x10, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
  94         { 0x11, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
  95         { 0x11, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
  96         { 0x11, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
  97         { 0x11, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
  98         { 0x12, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
  99         { 0x12, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 100         { 0x12, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 101         { 0x12, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 102         { 0x2, 0x00003fff, 0, 0x4, CISLANDS_CONFIGREG_DIDT_IND },
 103         { 0x2, 0x03ff0000, 16, 0x80, CISLANDS_CONFIGREG_DIDT_IND },
 104         { 0x2, 0x78000000, 27, 0x3, CISLANDS_CONFIGREG_DIDT_IND },
 105         { 0x1, 0x0000ffff, 0, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
 106         { 0x1, 0xffff0000, 16, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
 107         { 0x0, 0x00000001, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 108         { 0x30, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 109         { 0x30, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 110         { 0x30, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 111         { 0x30, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 112         { 0x31, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 113         { 0x31, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 114         { 0x31, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 115         { 0x31, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 116         { 0x32, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 117         { 0x32, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 118         { 0x32, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 119         { 0x32, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 120         { 0x22, 0x00003fff, 0, 0x4, CISLANDS_CONFIGREG_DIDT_IND },
 121         { 0x22, 0x03ff0000, 16, 0x80, CISLANDS_CONFIGREG_DIDT_IND },
 122         { 0x22, 0x78000000, 27, 0x3, CISLANDS_CONFIGREG_DIDT_IND },
 123         { 0x21, 0x0000ffff, 0, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
 124         { 0x21, 0xffff0000, 16, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
 125         { 0x20, 0x00000001, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 126         { 0x50, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 127         { 0x50, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 128         { 0x50, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 129         { 0x50, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 130         { 0x51, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 131         { 0x51, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 132         { 0x51, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 133         { 0x51, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 134         { 0x52, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 135         { 0x52, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 136         { 0x52, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 137         { 0x52, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 138         { 0x42, 0x00003fff, 0, 0x4, CISLANDS_CONFIGREG_DIDT_IND },
 139         { 0x42, 0x03ff0000, 16, 0x80, CISLANDS_CONFIGREG_DIDT_IND },
 140         { 0x42, 0x78000000, 27, 0x3, CISLANDS_CONFIGREG_DIDT_IND },
 141         { 0x41, 0x0000ffff, 0, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
 142         { 0x41, 0xffff0000, 16, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
 143         { 0x40, 0x00000001, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 144         { 0x70, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 145         { 0x70, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 146         { 0x70, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 147         { 0x70, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 148         { 0x71, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 149         { 0x71, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 150         { 0x71, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 151         { 0x71, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 152         { 0x72, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 153         { 0x72, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 154         { 0x72, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 155         { 0x72, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 156         { 0x62, 0x00003fff, 0, 0x4, CISLANDS_CONFIGREG_DIDT_IND },
 157         { 0x62, 0x03ff0000, 16, 0x80, CISLANDS_CONFIGREG_DIDT_IND },
 158         { 0x62, 0x78000000, 27, 0x3, CISLANDS_CONFIGREG_DIDT_IND },
 159         { 0x61, 0x0000ffff, 0, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
 160         { 0x61, 0xffff0000, 16, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
 161         { 0x60, 0x00000001, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 162         { 0xFFFFFFFF }
 163 };
 164
 165 extern u8 rv770_get_memory_module_index(struct radeon_device *rdev);
 166 extern int ni_copy_and_switch_arb_sets(struct radeon_device *rdev,
 167                                        u32 arb_freq_src, u32 arb_freq_dest);
 168 extern u8 si_get_ddr3_mclk_frequency_ratio(u32 memory_clock);
 169 extern u8 si_get_mclk_frequency_ratio(u32 memory_clock, bool strobe_mode);
 170 extern void si_trim_voltage_table_to_fit_state_table(struct radeon_device *rdev,
 171                                                      u32 max_voltage_steps,
 172                                                      struct atom_voltage_table *voltage_table);
 173 extern void cik_enter_rlc_safe_mode(struct radeon_device *rdev);
 174 extern void cik_exit_rlc_safe_mode(struct radeon_device *rdev);
 175 extern int ci_mc_load_microcode(struct radeon_device *rdev);
 176 extern void cik_update_cg(struct radeon_device *rdev,
 177                           u32 block, bool enable);
 178
 179 static int ci_get_std_voltage_value_sidd(struct radeon_device *rdev,
 180                                          struct atom_voltage_table_entry *voltage_table,
 181                                          u16 *std_voltage_hi_sidd, u16 *std_voltage_lo_sidd);
 182 static int ci_set_power_limit(struct radeon_device *rdev, u32 n);
 183 static int ci_set_overdrive_target_tdp(struct radeon_device *rdev,
 184                                        u32 target_tdp);
 185 static int ci_update_uvd_dpm(struct radeon_device *rdev, bool gate);
 186
 187 static struct ci_power_info *ci_get_pi(struct radeon_device *rdev)
 188 {
 189         struct ci_power_info *pi = rdev->pm.dpm.priv;
 190
 191         return pi;
 192 }
 193
 194 static struct ci_ps *ci_get_ps(struct radeon_ps *rps)
 195 {
 196         struct ci_ps *ps = rps->ps_priv;
 197
 198         return ps;
 199 }
 200
 201 static void ci_initialize_powertune_defaults(struct radeon_device *rdev)
 202 {
 203         struct ci_power_info *pi = ci_get_pi(rdev);
 204
 205         switch (rdev->pdev->device) {
 206         case 0x6649:
 207         case 0x6650:
 208         case 0x6651:
 209         case 0x6658:
 210         case 0x665C:
 211         case 0x665D:
 212         default:
 213                 pi->powertune_defaults = &defaults_bonaire_xt;
 214                 break;
 215         case 0x6640:
 216         case 0x6641:
 217         case 0x6646:
 218         case 0x6647:
 219                 pi->powertune_defaults = &defaults_saturn_xt;
 220                 break;
 221         case 0x67B8:
 222         case 0x67B0:
 223                 pi->powertune_defaults = &defaults_hawaii_xt;
 224                 break;
 225         case 0x67BA:
 226         case 0x67B1:
 227                 pi->powertune_defaults = &defaults_hawaii_pro;
 228                 break;
 229         case 0x67A0:
 230         case 0x67A1:
 231         case 0x67A2:
 232         case 0x67A8:
 233         case 0x67A9:
 234         case 0x67AA:
 235         case 0x67B9:
 236         case 0x67BE:
 237                 pi->powertune_defaults = &defaults_bonaire_xt;
 238                 break;
 239         }
 240
 241         pi->dte_tj_offset = 0;
 242
 243         pi->caps_power_containment = true;
 244         pi->caps_cac = false;
 245         pi->caps_sq_ramping = false;
 246         pi->caps_db_ramping = false;
 247         pi->caps_td_ramping = false;
 248         pi->caps_tcp_ramping = false;
 249
 250         if (pi->caps_power_containment) {
 251                 pi->caps_cac = true;
 252                 pi->enable_bapm_feature = true;
 253                 pi->enable_tdc_limit_feature = true;
 254                 pi->enable_pkg_pwr_tracking_feature = true;
 255         }
 256 }
 257
 258 static u8 ci_convert_to_vid(u16 vddc)
 259 {
 260         return (6200 - (vddc * VOLTAGE_SCALE)) / 25;
 261 }
 262
 263 static int ci_populate_bapm_vddc_vid_sidd(struct radeon_device *rdev)
 264 {
 265         struct ci_power_info *pi = ci_get_pi(rdev);
 266         u8 *hi_vid = pi->smc_powertune_table.BapmVddCVidHiSidd;
 267         u8 *lo_vid = pi->smc_powertune_table.BapmVddCVidLoSidd;
 268         u8 *hi2_vid = pi->smc_powertune_table.BapmVddCVidHiSidd2;
 269         u32 i;
 270
 271         if (rdev->pm.dpm.dyn_state.cac_leakage_table.entries == NULL)
 272                 return -EINVAL;
 273         if (rdev->pm.dpm.dyn_state.cac_leakage_table.count > 8)
 274                 return -EINVAL;
 275         if (rdev->pm.dpm.dyn_state.cac_leakage_table.count !=
 276             rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count)
 277                 return -EINVAL;
 278
 279         for (i = 0; i < rdev->pm.dpm.dyn_state.cac_leakage_table.count; i++) {
 280                 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_EVV) {
 281                         lo_vid[i] = ci_convert_to_vid(rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc1);
 282                         hi_vid[i] = ci_convert_to_vid(rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc2);
 283                         hi2_vid[i] = ci_convert_to_vid(rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc3);
 284                 } else {
 285                         lo_vid[i] = ci_convert_to_vid(rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc);
 286                         hi_vid[i] = ci_convert_to_vid((u16)rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].leakage);
 287                 }
 288         }
 289         return 0;
 290 }
 291
 292 static int ci_populate_vddc_vid(struct radeon_device *rdev)
 293 {
 294         struct ci_power_info *pi = ci_get_pi(rdev);
 295         u8 *vid = pi->smc_powertune_table.VddCVid;
 296         u32 i;
 297
 298         if (pi->vddc_voltage_table.count > 8)
 299                 return -EINVAL;
 300
 301         for (i = 0; i < pi->vddc_voltage_table.count; i++)
 302                 vid[i] = ci_convert_to_vid(pi->vddc_voltage_table.entries[i].value);
 303
 304         return 0;
 305 }
 306
 307 static int ci_populate_svi_load_line(struct radeon_device *rdev)
 308 {
 309         struct ci_power_info *pi = ci_get_pi(rdev);
 310         const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults;
 311
 312         pi->smc_powertune_table.SviLoadLineEn = pt_defaults->svi_load_line_en;
 313         pi->smc_powertune_table.SviLoadLineVddC = pt_defaults->svi_load_line_vddc;
 314         pi->smc_powertune_table.SviLoadLineTrimVddC = 3;
 315         pi->smc_powertune_table.SviLoadLineOffsetVddC = 0;
 316
 317         return 0;
 318 }
 319
 320 static int ci_populate_tdc_limit(struct radeon_device *rdev)
 321 {
 322         struct ci_power_info *pi = ci_get_pi(rdev);
 323         const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults;
 324         u16 tdc_limit;
 325
 326         tdc_limit = rdev->pm.dpm.dyn_state.cac_tdp_table->tdc * 256;
 327         pi->smc_powertune_table.TDC_VDDC_PkgLimit = cpu_to_be16(tdc_limit);
 328         pi->smc_powertune_table.TDC_VDDC_ThrottleReleaseLimitPerc =
 329                 pt_defaults->tdc_vddc_throttle_release_limit_perc;
 330         pi->smc_powertune_table.TDC_MAWt = pt_defaults->tdc_mawt;
 331
 332         return 0;
 333 }
 334
 335 static int ci_populate_dw8(struct radeon_device *rdev)
 336 {
 337         struct ci_power_info *pi = ci_get_pi(rdev);
 338         const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults;
 339         int ret;
 340
 341         ret = ci_read_smc_sram_dword(rdev,
 342                                      SMU7_FIRMWARE_HEADER_LOCATION +
 343                                      offsetof(SMU7_Firmware_Header, PmFuseTable) +
 344                                      offsetof(SMU7_Discrete_PmFuses, TdcWaterfallCtl),
 345                                      (u32 *)&pi->smc_powertune_table.TdcWaterfallCtl,
 346                                      pi->sram_end);
 347         if (ret)
 348                 return -EINVAL;
 349         else
 350                 pi->smc_powertune_table.TdcWaterfallCtl = pt_defaults->tdc_waterfall_ctl;
 351
 352         return 0;
 353 }
 354
 355 static int ci_min_max_v_gnbl_pm_lid_from_bapm_vddc(struct radeon_device *rdev)
 356 {
 357         struct ci_power_info *pi = ci_get_pi(rdev);
 358         u8 *hi_vid = pi->smc_powertune_table.BapmVddCVidHiSidd;
 359         u8 *lo_vid = pi->smc_powertune_table.BapmVddCVidLoSidd;
 360         int i, min, max;
 361
 362         min = max = hi_vid[0];
 363         for (i = 0; i < 8; i++) {
 364                 if (0 != hi_vid[i]) {
 365                         if (min > hi_vid[i])
 366                                 min = hi_vid[i];
 367                         if (max < hi_vid[i])
 368                                 max = hi_vid[i];
 369                 }
 370
 371                 if (0 != lo_vid[i]) {
 372                         if (min > lo_vid[i])
 373                                 min = lo_vid[i];
 374                         if (max < lo_vid[i])
 375                                 max = lo_vid[i];
 376                 }
 377         }
 378
 379         if ((min == 0) || (max == 0))
 380                 return -EINVAL;
 381         pi->smc_powertune_table.GnbLPMLMaxVid = (u8)max;
 382         pi->smc_powertune_table.GnbLPMLMinVid = (u8)min;
 383
 384         return 0;
 385 }
 386
 387 static int ci_populate_bapm_vddc_base_leakage_sidd(struct radeon_device *rdev)
 388 {
 389         struct ci_power_info *pi = ci_get_pi(rdev);
 390         u16 hi_sidd = pi->smc_powertune_table.BapmVddCBaseLeakageHiSidd;
 391         u16 lo_sidd = pi->smc_powertune_table.BapmVddCBaseLeakageLoSidd;
 392         struct radeon_cac_tdp_table *cac_tdp_table =
 393                 rdev->pm.dpm.dyn_state.cac_tdp_table;
 394
 395         hi_sidd = cac_tdp_table->high_cac_leakage / 100 * 256;
 396         lo_sidd = cac_tdp_table->low_cac_leakage / 100 * 256;
 397
 398         pi->smc_powertune_table.BapmVddCBaseLeakageHiSidd = cpu_to_be16(hi_sidd);
 399         pi->smc_powertune_table.BapmVddCBaseLeakageLoSidd = cpu_to_be16(lo_sidd);
 400
 401         return 0;
 402 }
 403
 404 static int ci_populate_bapm_parameters_in_dpm_table(struct radeon_device *rdev)
 405 {
 406         struct ci_power_info *pi = ci_get_pi(rdev);
 407         const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults;
 408         SMU7_Discrete_DpmTable  *dpm_table = &pi->smc_state_table;
 409         struct radeon_cac_tdp_table *cac_tdp_table =
 410                 rdev->pm.dpm.dyn_state.cac_tdp_table;
 411         struct radeon_ppm_table *ppm = rdev->pm.dpm.dyn_state.ppm_table;
 412         int i, j, k;
 413         const u16 *def1;
 414         const u16 *def2;
 415
 416         dpm_table->DefaultTdp = cac_tdp_table->tdp * 256;
 417         dpm_table->TargetTdp = cac_tdp_table->configurable_tdp * 256;
 418
 419         dpm_table->DTETjOffset = (u8)pi->dte_tj_offset;
 420         dpm_table->GpuTjMax =
 421                 (u8)(pi->thermal_temp_setting.temperature_high / 1000);
 422         dpm_table->GpuTjHyst = 8;
 423
 424         dpm_table->DTEAmbientTempBase = pt_defaults->dte_ambient_temp_base;
 425
 426         if (ppm) {
 427                 dpm_table->PPM_PkgPwrLimit = cpu_to_be16((u16)ppm->dgpu_tdp * 256 / 1000);
 428                 dpm_table->PPM_TemperatureLimit = cpu_to_be16((u16)ppm->tj_max * 256);
 429         } else {
 430                 dpm_table->PPM_PkgPwrLimit = cpu_to_be16(0);
 431                 dpm_table->PPM_TemperatureLimit = cpu_to_be16(0);
 432         }
 433
 434         dpm_table->BAPM_TEMP_GRADIENT = cpu_to_be32(pt_defaults->bapm_temp_gradient);
 435         def1 = pt_defaults->bapmti_r;
 436         def2 = pt_defaults->bapmti_rc;
 437
 438         for (i = 0; i < SMU7_DTE_ITERATIONS; i++) {
 439                 for (j = 0; j < SMU7_DTE_SOURCES; j++) {
 440                         for (k = 0; k < SMU7_DTE_SINKS; k++) {
 441                                 dpm_table->BAPMTI_R[i][j][k] = cpu_to_be16(*def1);
 442                                 dpm_table->BAPMTI_RC[i][j][k] = cpu_to_be16(*def2);
 443                                 def1++;
 444                                 def2++;
 445                         }
 446                 }
 447         }
 448
 449         return 0;
 450 }
 451
 452 static int ci_populate_pm_base(struct radeon_device *rdev)
 453 {
 454         struct ci_power_info *pi = ci_get_pi(rdev);
 455         u32 pm_fuse_table_offset;
 456         int ret;
 457
 458         if (pi->caps_power_containment) {
 459                 ret = ci_read_smc_sram_dword(rdev,
 460                                              SMU7_FIRMWARE_HEADER_LOCATION +
 461                                              offsetof(SMU7_Firmware_Header, PmFuseTable),
 462                                              &pm_fuse_table_offset, pi->sram_end);
 463                 if (ret)
 464                         return ret;
 465                 ret = ci_populate_bapm_vddc_vid_sidd(rdev);
 466                 if (ret)
 467                         return ret;
 468                 ret = ci_populate_vddc_vid(rdev);
 469                 if (ret)
 470                         return ret;
 471                 ret = ci_populate_svi_load_line(rdev);
 472                 if (ret)
 473                         return ret;
 474                 ret = ci_populate_tdc_limit(rdev);
 475                 if (ret)
 476                         return ret;
 477                 ret = ci_populate_dw8(rdev);
 478                 if (ret)
 479                         return ret;
 480                 ret = ci_min_max_v_gnbl_pm_lid_from_bapm_vddc(rdev);
 481                 if (ret)
 482                         return ret;
 483                 ret = ci_populate_bapm_vddc_base_leakage_sidd(rdev);
 484                 if (ret)
 485                         return ret;
 486                 ret = ci_copy_bytes_to_smc(rdev, pm_fuse_table_offset,
 487                                            (u8 *)&pi->smc_powertune_table,
 488                                            sizeof(SMU7_Discrete_PmFuses), pi->sram_end);
 489                 if (ret)
 490                         return ret;
 491         }
 492
 493         return 0;
 494 }
 495
 496 static void ci_do_enable_didt(struct radeon_device *rdev, const bool enable)
 497 {
 498         struct ci_power_info *pi = ci_get_pi(rdev);
 499         u32 data;
 500
 501         if (pi->caps_sq_ramping) {
 502                 data = RREG32_DIDT(DIDT_SQ_CTRL0);
 503                 if (enable)
 504                         data |= DIDT_CTRL_EN;
 505                 else
 506                         data &= ~DIDT_CTRL_EN;
 507                 WREG32_DIDT(DIDT_SQ_CTRL0, data);
 508         }
 509
 510         if (pi->caps_db_ramping) {
 511                 data = RREG32_DIDT(DIDT_DB_CTRL0);
 512                 if (enable)
 513                         data |= DIDT_CTRL_EN;
 514                 else
 515                         data &= ~DIDT_CTRL_EN;
 516                 WREG32_DIDT(DIDT_DB_CTRL0, data);
 517         }
 518
 519         if (pi->caps_td_ramping) {
 520                 data = RREG32_DIDT(DIDT_TD_CTRL0);
 521                 if (enable)
 522                         data |= DIDT_CTRL_EN;
 523                 else
 524                         data &= ~DIDT_CTRL_EN;
 525                 WREG32_DIDT(DIDT_TD_CTRL0, data);
 526         }
 527
 528         if (pi->caps_tcp_ramping) {
 529                 data = RREG32_DIDT(DIDT_TCP_CTRL0);
 530                 if (enable)
 531                         data |= DIDT_CTRL_EN;
 532                 else
 533                         data &= ~DIDT_CTRL_EN;
 534                 WREG32_DIDT(DIDT_TCP_CTRL0, data);
 535         }
 536 }
 537
 538 static int ci_program_pt_config_registers(struct radeon_device *rdev,
 539                                           const struct ci_pt_config_reg *cac_config_regs)
 540 {
 541         const struct ci_pt_config_reg *config_regs = cac_config_regs;
 542         u32 data;
 543         u32 cache = 0;
 544
 545         if (config_regs == NULL)
 546                 return -EINVAL;
 547
 548         while (config_regs->offset != 0xFFFFFFFF) {
 549                 if (config_regs->type == CISLANDS_CONFIGREG_CACHE) {
 550                         cache |= ((config_regs->value << config_regs->shift) & config_regs->mask);
 551                 } else {
 552                         switch (config_regs->type) {
 553                         case CISLANDS_CONFIGREG_SMC_IND:
 554                                 data = RREG32_SMC(config_regs->offset);
 555                                 break;
 556                         case CISLANDS_CONFIGREG_DIDT_IND:
 557                                 data = RREG32_DIDT(config_regs->offset);
 558                                 break;
 559                         default:
 560                                 data = RREG32(config_regs->offset << 2);
 561                                 break;
 562                         }
 563
 564                         data &= ~config_regs->mask;
 565                         data |= ((config_regs->value << config_regs->shift) & config_regs->mask);
 566                         data |= cache;
 567
 568                         switch (config_regs->type) {
 569                         case CISLANDS_CONFIGREG_SMC_IND:
 570                                 WREG32_SMC(config_regs->offset, data);
 571                                 break;
 572                         case CISLANDS_CONFIGREG_DIDT_IND:
 573                                 WREG32_DIDT(config_regs->offset, data);
 574                                 break;
 575                         default:
 576                                 WREG32(config_regs->offset << 2, data);
 577                                 break;
 578                         }
 579                         cache = 0;
 580                 }
 581                 config_regs++;
 582         }
 583         return 0;
 584 }
 585
 586 static int ci_enable_didt(struct radeon_device *rdev, bool enable)
 587 {
 588         struct ci_power_info *pi = ci_get_pi(rdev);
 589         int ret;
 590
 591         if (pi->caps_sq_ramping || pi->caps_db_ramping ||
 592             pi->caps_td_ramping || pi->caps_tcp_ramping) {
 593                 cik_enter_rlc_safe_mode(rdev);
 594
 595                 if (enable) {
 596                         ret = ci_program_pt_config_registers(rdev, didt_config_ci);
 597                         if (ret) {
 598                                 cik_exit_rlc_safe_mode(rdev);
 599                                 return ret;
 600                         }
 601                 }
 602
 603                 ci_do_enable_didt(rdev, enable);
 604
 605                 cik_exit_rlc_safe_mode(rdev);
 606         }
 607
 608         return 0;
 609 }
 610
 611 static int ci_enable_power_containment(struct radeon_device *rdev, bool enable)
 612 {
 613         struct ci_power_info *pi = ci_get_pi(rdev);
 614         PPSMC_Result smc_result;
 615         int ret = 0;
 616
 617         if (enable) {
 618                 pi->power_containment_features = 0;
 619                 if (pi->caps_power_containment) {
 620                         if (pi->enable_bapm_feature) {
 621                                 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_EnableDTE);
 622                                 if (smc_result != PPSMC_Result_OK)
 623                                         ret = -EINVAL;
 624                                 else
 625                                         pi->power_containment_features |= POWERCONTAINMENT_FEATURE_BAPM;
 626                         }
 627
 628                         if (pi->enable_tdc_limit_feature) {
 629                                 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_TDCLimitEnable);
 630                                 if (smc_result != PPSMC_Result_OK)
 631                                         ret = -EINVAL;
 632                                 else
 633                                         pi->power_containment_features |= POWERCONTAINMENT_FEATURE_TDCLimit;
 634                         }
 635
 636                         if (pi->enable_pkg_pwr_tracking_feature) {
 637                                 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_PkgPwrLimitEnable);
 638                                 if (smc_result != PPSMC_Result_OK) {
 639                                         ret = -EINVAL;
 640                                 } else {
 641                                         struct radeon_cac_tdp_table *cac_tdp_table =
 642                                                 rdev->pm.dpm.dyn_state.cac_tdp_table;
 643                                         u32 default_pwr_limit =
 644                                                 (u32)(cac_tdp_table->maximum_power_delivery_limit * 256);
 645
 646                                         pi->power_containment_features |= POWERCONTAINMENT_FEATURE_PkgPwrLimit;
 647
 648                                         ci_set_power_limit(rdev, default_pwr_limit);
 649                                 }
 650                         }
 651                 }
 652         } else {
 653                 if (pi->caps_power_containment && pi->power_containment_features) {
 654                         if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_TDCLimit)
 655                                 ci_send_msg_to_smc(rdev, PPSMC_MSG_TDCLimitDisable);
 656
 657                         if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_BAPM)
 658                                 ci_send_msg_to_smc(rdev, PPSMC_MSG_DisableDTE);
 659
 660                         if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_PkgPwrLimit)
 661                                 ci_send_msg_to_smc(rdev, PPSMC_MSG_PkgPwrLimitDisable);
 662                         pi->power_containment_features = 0;
 663                 }
 664         }
 665
 666         return ret;
 667 }
 668
 669 static int ci_enable_smc_cac(struct radeon_device *rdev, bool enable)
 670 {
 671         struct ci_power_info *pi = ci_get_pi(rdev);
 672         PPSMC_Result smc_result;
 673         int ret = 0;
 674
 675         if (pi->caps_cac) {
 676                 if (enable) {
 677                         smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_EnableCac);
 678                         if (smc_result != PPSMC_Result_OK) {
 679                                 ret = -EINVAL;
 680                                 pi->cac_enabled = false;
 681                         } else {
 682                                 pi->cac_enabled = true;
 683                         }
 684                 } else if (pi->cac_enabled) {
 685                         ci_send_msg_to_smc(rdev, PPSMC_MSG_DisableCac);
 686                         pi->cac_enabled = false;
 687                 }
 688         }
 689
 690         return ret;
 691 }
 692
 693 static int ci_power_control_set_level(struct radeon_device *rdev)
 694 {
 695         struct ci_power_info *pi = ci_get_pi(rdev);
 696         struct radeon_cac_tdp_table *cac_tdp_table =
 697                 rdev->pm.dpm.dyn_state.cac_tdp_table;
 698         s32 adjust_percent;
 699         s32 target_tdp;
 700         int ret = 0;
 701         bool adjust_polarity = false; /* ??? */
 702
 703         if (pi->caps_power_containment &&
 704             (pi->power_containment_features & POWERCONTAINMENT_FEATURE_BAPM)) {
 705                 adjust_percent = adjust_polarity ?
 706                         rdev->pm.dpm.tdp_adjustment : (-1 * rdev->pm.dpm.tdp_adjustment);
 707                 target_tdp = ((100 + adjust_percent) *
 708                               (s32)cac_tdp_table->configurable_tdp) / 100;
 709                 target_tdp *= 256;
 710
 711                 ret = ci_set_overdrive_target_tdp(rdev, (u32)target_tdp);
 712         }
 713
 714         return ret;
 715 }
 716
 717 void ci_dpm_powergate_uvd(struct radeon_device *rdev, bool gate)
 718 {
 719         struct ci_power_info *pi = ci_get_pi(rdev);
 720
 721         if (pi->uvd_power_gated == gate)
 722                 return;
 723
 724         pi->uvd_power_gated = gate;
 725
 726         ci_update_uvd_dpm(rdev, gate);
 727 }
 728
 729 bool ci_dpm_vblank_too_short(struct radeon_device *rdev)
 730 {
 731         struct ci_power_info *pi = ci_get_pi(rdev);
 732         u32 vblank_time = r600_dpm_get_vblank_time(rdev);
 733         u32 switch_limit = pi->mem_gddr5 ? 450 : 300;
 734
 735         if (vblank_time < switch_limit)
 736                 return true;
 737         else
 738                 return false;
 739
 740 }
 741
 742 static void ci_apply_state_adjust_rules(struct radeon_device *rdev,
 743                                         struct radeon_ps *rps)
 744 {
 745         struct ci_ps *ps = ci_get_ps(rps);
 746         struct ci_power_info *pi = ci_get_pi(rdev);
 747         struct radeon_clock_and_voltage_limits *max_limits;
 748         bool disable_mclk_switching;
 749         u32 sclk, mclk;
 750         int i;
 751
 752         if (rps->vce_active) {
 753                 rps->evclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].evclk;
 754                 rps->ecclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].ecclk;
 755         } else {
 756                 rps->evclk = 0;
 757                 rps->ecclk = 0;
 758         }
 759
 760         if ((rdev->pm.dpm.new_active_crtc_count > 1) ||
 761             ci_dpm_vblank_too_short(rdev))
 762                 disable_mclk_switching = true;
 763         else
 764                 disable_mclk_switching = false;
 765
 766         if ((rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) == ATOM_PPLIB_CLASSIFICATION_UI_BATTERY)
 767                 pi->battery_state = true;
 768         else
 769                 pi->battery_state = false;
 770
 771         if (rdev->pm.dpm.ac_power)
 772                 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
 773         else
 774                 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
 775
 776         if (rdev->pm.dpm.ac_power == false) {
 777                 for (i = 0; i < ps->performance_level_count; i++) {
 778                         if (ps->performance_levels[i].mclk > max_limits->mclk)
 779                                 ps->performance_levels[i].mclk = max_limits->mclk;
 780                         if (ps->performance_levels[i].sclk > max_limits->sclk)
 781                                 ps->performance_levels[i].sclk = max_limits->sclk;
 782                 }
 783         }
 784
 785         /* XXX validate the min clocks required for display */
 786
 787         if (disable_mclk_switching) {
 788                 mclk  = ps->performance_levels[ps->performance_level_count - 1].mclk;
 789                 sclk = ps->performance_levels[0].sclk;
 790         } else {
 791                 mclk = ps->performance_levels[0].mclk;
 792                 sclk = ps->performance_levels[0].sclk;
 793         }
 794
 795         if (rps->vce_active) {
 796                 if (sclk < rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].sclk)
 797                         sclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].sclk;
 798                 if (mclk < rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].mclk)
 799                         mclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].mclk;
 800         }
 801
 802         ps->performance_levels[0].sclk = sclk;
 803         ps->performance_levels[0].mclk = mclk;
 804
 805         if (ps->performance_levels[1].sclk < ps->performance_levels[0].sclk)
 806                 ps->performance_levels[1].sclk = ps->performance_levels[0].sclk;
 807
 808         if (disable_mclk_switching) {
 809                 if (ps->performance_levels[0].mclk < ps->performance_levels[1].mclk)
 810                         ps->performance_levels[0].mclk = ps->performance_levels[1].mclk;
 811         } else {
 812                 if (ps->performance_levels[1].mclk < ps->performance_levels[0].mclk)
 813                         ps->performance_levels[1].mclk = ps->performance_levels[0].mclk;
 814         }
 815 }
 816
 817 static int ci_thermal_set_temperature_range(struct radeon_device *rdev,
 818                                             int min_temp, int max_temp)
 819 {
 820         int low_temp = 0 * 1000;
 821         int high_temp = 255 * 1000;
 822         u32 tmp;
 823
 824         if (low_temp < min_temp)
 825                 low_temp = min_temp;
 826         if (high_temp > max_temp)
 827                 high_temp = max_temp;
 828         if (high_temp < low_temp) {
 829                 DRM_ERROR("invalid thermal range: %d - %d\n", low_temp, high_temp);
 830                 return -EINVAL;
 831         }
 832
 833         tmp = RREG32_SMC(CG_THERMAL_INT);
 834         tmp &= ~(CI_DIG_THERM_INTH_MASK | CI_DIG_THERM_INTL_MASK);
 835         tmp |= CI_DIG_THERM_INTH(high_temp / 1000) |
 836                 CI_DIG_THERM_INTL(low_temp / 1000);
 837         WREG32_SMC(CG_THERMAL_INT, tmp);
 838
 839 #if 0
 840         /* XXX: need to figure out how to handle this properly */
 841         tmp = RREG32_SMC(CG_THERMAL_CTRL);
 842         tmp &= DIG_THERM_DPM_MASK;
 843         tmp |= DIG_THERM_DPM(high_temp / 1000);
 844         WREG32_SMC(CG_THERMAL_CTRL, tmp);
 845 #endif
 846
 847         rdev->pm.dpm.thermal.min_temp = low_temp;
 848         rdev->pm.dpm.thermal.max_temp = high_temp;
 849
 850         return 0;
 851 }
 852
 853 static int ci_thermal_enable_alert(struct radeon_device *rdev,
 854                                    bool enable)
 855 {
 856         u32 thermal_int = RREG32_SMC(CG_THERMAL_INT);
 857         PPSMC_Result result;
 858
 859         if (enable) {
 860                 thermal_int &= ~(THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW);
 861                 rdev->irq.dpm_thermal = false;
 862                 result = ci_send_msg_to_smc(rdev, PPSMC_MSG_Thermal_Cntl_Enable);
 863                 if (result != PPSMC_Result_OK) {
 864                         DRM_DEBUG_KMS("Could not enable thermal interrupts.\n");
 865                         return -EINVAL;
 866                 }
 867         } else {
 868                 thermal_int |= THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW;
 869                 rdev->irq.dpm_thermal = true;
 870                 result = ci_send_msg_to_smc(rdev, PPSMC_MSG_Thermal_Cntl_Disable);
 871                 if (result != PPSMC_Result_OK) {
 872                         DRM_DEBUG_KMS("Could not disable thermal interrupts.\n");
 873                         return -EINVAL;
 874                 }
 875         }
 876
 877         WREG32_SMC(CG_THERMAL_INT, thermal_int);
 878
 879         return 0;
 880 }
 881
 882 #if 0
 883 static int ci_read_smc_soft_register(struct radeon_device *rdev,
 884                                      u16 reg_offset, u32 *value)
 885 {
 886         struct ci_power_info *pi = ci_get_pi(rdev);
 887
 888         return ci_read_smc_sram_dword(rdev,
 889                                       pi->soft_regs_start + reg_offset,
 890                                       value, pi->sram_end);
 891 }
 892 #endif
 893
 894 static int ci_write_smc_soft_register(struct radeon_device *rdev,
 895                                       u16 reg_offset, u32 value)
 896 {
 897         struct ci_power_info *pi = ci_get_pi(rdev);
 898
 899         return ci_write_smc_sram_dword(rdev,
 900                                        pi->soft_regs_start + reg_offset,
 901                                        value, pi->sram_end);
 902 }
 903
 904 static void ci_init_fps_limits(struct radeon_device *rdev)
 905 {
 906         struct ci_power_info *pi = ci_get_pi(rdev);
 907         SMU7_Discrete_DpmTable *table = &pi->smc_state_table;
 908
 909         if (pi->caps_fps) {
 910                 u16 tmp;
 911
 912                 tmp = 45;
 913                 table->FpsHighT = cpu_to_be16(tmp);
 914
 915                 tmp = 30;
 916                 table->FpsLowT = cpu_to_be16(tmp);
 917         }
 918 }
 919
 920 static int ci_update_sclk_t(struct radeon_device *rdev)
 921 {
 922         struct ci_power_info *pi = ci_get_pi(rdev);
 923         int ret = 0;
 924         u32 low_sclk_interrupt_t = 0;
 925
 926         if (pi->caps_sclk_throttle_low_notification) {
 927                 low_sclk_interrupt_t = cpu_to_be32(pi->low_sclk_interrupt_t);
 928
 929                 ret = ci_copy_bytes_to_smc(rdev,
 930                                            pi->dpm_table_start +
 931                                            offsetof(SMU7_Discrete_DpmTable, LowSclkInterruptT),
 932                                            (u8 *)&low_sclk_interrupt_t,
 933                                            sizeof(u32), pi->sram_end);
 934
 935         }
 936
 937         return ret;
 938 }
 939
 940 static void ci_get_leakage_voltages(struct radeon_device *rdev)
 941 {
 942         struct ci_power_info *pi = ci_get_pi(rdev);
 943         u16 leakage_id, virtual_voltage_id;
 944         u16 vddc, vddci;
 945         int i;
 946
 947         pi->vddc_leakage.count = 0;
 948         pi->vddci_leakage.count = 0;
 949
 950         if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_EVV) {
 951                 for (i = 0; i < CISLANDS_MAX_LEAKAGE_COUNT; i++) {
 952                         virtual_voltage_id = ATOM_VIRTUAL_VOLTAGE_ID0 + i;
 953                         if (radeon_atom_get_voltage_evv(rdev, virtual_voltage_id, &vddc) != 0)
 954                                 continue;
 955                         if (vddc != 0 && vddc != virtual_voltage_id) {
 956                                 pi->vddc_leakage.actual_voltage[pi->vddc_leakage.count] = vddc;
 957                                 pi->vddc_leakage.leakage_id[pi->vddc_leakage.count] = virtual_voltage_id;
 958                                 pi->vddc_leakage.count++;
 959                         }
 960                 }
 961         } else if (radeon_atom_get_leakage_id_from_vbios(rdev, &leakage_id) == 0) {
 962                 for (i = 0; i < CISLANDS_MAX_LEAKAGE_COUNT; i++) {
 963                         virtual_voltage_id = ATOM_VIRTUAL_VOLTAGE_ID0 + i;
 964                         if (radeon_atom_get_leakage_vddc_based_on_leakage_params(rdev, &vddc, &vddci,
 965                                                                                  virtual_voltage_id,
 966                                                                                  leakage_id) == 0) {
 967                                 if (vddc != 0 && vddc != virtual_voltage_id) {
 968                                         pi->vddc_leakage.actual_voltage[pi->vddc_leakage.count] = vddc;
 969                                         pi->vddc_leakage.leakage_id[pi->vddc_leakage.count] = virtual_voltage_id;
 970                                         pi->vddc_leakage.count++;
 971                                 }
 972                                 if (vddci != 0 && vddci != virtual_voltage_id) {
 973                                         pi->vddci_leakage.actual_voltage[pi->vddci_leakage.count] = vddci;
 974                                         pi->vddci_leakage.leakage_id[pi->vddci_leakage.count] = virtual_voltage_id;
 975                                         pi->vddci_leakage.count++;
 976                                 }
 977                         }
 978                 }
 979         }
 980 }
 981
 982 static void ci_set_dpm_event_sources(struct radeon_device *rdev, u32 sources)
 983 {
 984         struct ci_power_info *pi = ci_get_pi(rdev);
 985         bool want_thermal_protection;
 986         enum radeon_dpm_event_src dpm_event_src;
 987         u32 tmp;
 988
 989         switch (sources) {
 990         case 0:
 991         default:
 992                 want_thermal_protection = false;
 993                 break;
 994         case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL):
 995                 want_thermal_protection = true;
 996                 dpm_event_src = RADEON_DPM_EVENT_SRC_DIGITAL;
 997                 break;
 998         case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL):
 999                 want_thermal_protection = true;
1000                 dpm_event_src = RADEON_DPM_EVENT_SRC_EXTERNAL;
1001                 break;
1002         case ((1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL) |
1003               (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL)):
1004                 want_thermal_protection = true;
1005                 dpm_event_src = RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL;
1006                 break;
1007         }
1008
1009         if (want_thermal_protection) {
1010 #if 0
1011                 /* XXX: need to figure out how to handle this properly */
1012                 tmp = RREG32_SMC(CG_THERMAL_CTRL);
1013                 tmp &= DPM_EVENT_SRC_MASK;
1014                 tmp |= DPM_EVENT_SRC(dpm_event_src);
1015                 WREG32_SMC(CG_THERMAL_CTRL, tmp);
1016 #endif
1017
1018                 tmp = RREG32_SMC(GENERAL_PWRMGT);
1019                 if (pi->thermal_protection)
1020                         tmp &= ~THERMAL_PROTECTION_DIS;
1021                 else
1022                         tmp |= THERMAL_PROTECTION_DIS;
1023                 WREG32_SMC(GENERAL_PWRMGT, tmp);
1024         } else {
1025                 tmp = RREG32_SMC(GENERAL_PWRMGT);
1026                 tmp |= THERMAL_PROTECTION_DIS;
1027                 WREG32_SMC(GENERAL_PWRMGT, tmp);
1028         }
1029 }
1030
1031 static void ci_enable_auto_throttle_source(struct radeon_device *rdev,
1032                                            enum radeon_dpm_auto_throttle_src source,
1033                                            bool enable)
1034 {
1035         struct ci_power_info *pi = ci_get_pi(rdev);
1036
1037         if (enable) {
1038                 if (!(pi->active_auto_throttle_sources & (1 << source))) {
1039                         pi->active_auto_throttle_sources |= 1 << source;
1040                         ci_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources);
1041                 }
1042         } else {
1043                 if (pi->active_auto_throttle_sources & (1 << source)) {
1044                         pi->active_auto_throttle_sources &= ~(1 << source);
1045                         ci_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources);
1046                 }
1047         }
1048 }
1049
1050 static void ci_enable_vr_hot_gpio_interrupt(struct radeon_device *rdev)
1051 {
1052         if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REGULATOR_HOT)
1053                 ci_send_msg_to_smc(rdev, PPSMC_MSG_EnableVRHotGPIOInterrupt);
1054 }
1055
1056 static int ci_unfreeze_sclk_mclk_dpm(struct radeon_device *rdev)
1057 {
1058         struct ci_power_info *pi = ci_get_pi(rdev);
1059         PPSMC_Result smc_result;
1060
1061         if (!pi->need_update_smu7_dpm_table)
1062                 return 0;
1063
1064         if ((!pi->sclk_dpm_key_disabled) &&
1065             (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK))) {
1066                 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_SCLKDPM_UnfreezeLevel);
1067                 if (smc_result != PPSMC_Result_OK)
1068                         return -EINVAL;
1069         }
1070
1071         if ((!pi->mclk_dpm_key_disabled) &&
1072             (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) {
1073                 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_MCLKDPM_UnfreezeLevel);
1074                 if (smc_result != PPSMC_Result_OK)
1075                         return -EINVAL;
1076         }
1077
1078         pi->need_update_smu7_dpm_table = 0;
1079         return 0;
1080 }
1081
1082 static int ci_enable_sclk_mclk_dpm(struct radeon_device *rdev, bool enable)
1083 {
1084         struct ci_power_info *pi = ci_get_pi(rdev);
1085         PPSMC_Result smc_result;
1086
1087         if (enable) {
1088                 if (!pi->sclk_dpm_key_disabled) {
1089                         smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_DPM_Enable);
1090                         if (smc_result != PPSMC_Result_OK)
1091                                 return -EINVAL;
1092                 }
1093
1094                 if (!pi->mclk_dpm_key_disabled) {
1095                         smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_MCLKDPM_Enable);
1096                         if (smc_result != PPSMC_Result_OK)
1097                                 return -EINVAL;
1098
1099                         WREG32_P(MC_SEQ_CNTL_3, CAC_EN, ~CAC_EN);
1100
1101                         WREG32_SMC(LCAC_MC0_CNTL, 0x05);
1102                         WREG32_SMC(LCAC_MC1_CNTL, 0x05);
1103                         WREG32_SMC(LCAC_CPL_CNTL, 0x100005);
1104
1105                         udelay(10);
1106
1107                         WREG32_SMC(LCAC_MC0_CNTL, 0x400005);
1108                         WREG32_SMC(LCAC_MC1_CNTL, 0x400005);
1109                         WREG32_SMC(LCAC_CPL_CNTL, 0x500005);
1110                 }
1111         } else {
1112                 if (!pi->sclk_dpm_key_disabled) {
1113                         smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_DPM_Disable);
1114                         if (smc_result != PPSMC_Result_OK)
1115                                 return -EINVAL;
1116                 }
1117
1118                 if (!pi->mclk_dpm_key_disabled) {
1119                         smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_MCLKDPM_Disable);
1120                         if (smc_result != PPSMC_Result_OK)
1121                                 return -EINVAL;
1122                 }
1123         }
1124
1125         return 0;
1126 }
1127
1128 static int ci_start_dpm(struct radeon_device *rdev)
1129 {
1130         struct ci_power_info *pi = ci_get_pi(rdev);
1131         PPSMC_Result smc_result;
1132         int ret;
1133         u32 tmp;
1134
1135         tmp = RREG32_SMC(GENERAL_PWRMGT);
1136         tmp |= GLOBAL_PWRMGT_EN;
1137         WREG32_SMC(GENERAL_PWRMGT, tmp);
1138
1139         tmp = RREG32_SMC(SCLK_PWRMGT_CNTL);
1140         tmp |= DYNAMIC_PM_EN;
1141         WREG32_SMC(SCLK_PWRMGT_CNTL, tmp);
1142
1143         ci_write_smc_soft_register(rdev, offsetof(SMU7_SoftRegisters, VoltageChangeTimeout), 0x1000);
1144
1145         WREG32_P(BIF_LNCNT_RESET, 0, ~RESET_LNCNT_EN);
1146
1147         smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_Voltage_Cntl_Enable);
1148         if (smc_result != PPSMC_Result_OK)
1149                 return -EINVAL;
1150
1151         ret = ci_enable_sclk_mclk_dpm(rdev, true);
1152         if (ret)
1153                 return ret;
1154
1155         if (!pi->pcie_dpm_key_disabled) {
1156                 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_PCIeDPM_Enable);
1157                 if (smc_result != PPSMC_Result_OK)
1158                         return -EINVAL;
1159         }
1160
1161         return 0;
1162 }
1163
1164 static int ci_freeze_sclk_mclk_dpm(struct radeon_device *rdev)
1165 {
1166         struct ci_power_info *pi = ci_get_pi(rdev);
1167         PPSMC_Result smc_result;
1168
1169         if (!pi->need_update_smu7_dpm_table)
1170                 return 0;
1171
1172         if ((!pi->sclk_dpm_key_disabled) &&
1173             (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK))) {
1174                 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_SCLKDPM_FreezeLevel);
1175                 if (smc_result != PPSMC_Result_OK)
1176                         return -EINVAL;
1177         }
1178
1179         if ((!pi->mclk_dpm_key_disabled) &&
1180             (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) {
1181                 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_MCLKDPM_FreezeLevel);
1182                 if (smc_result != PPSMC_Result_OK)
1183                         return -EINVAL;
1184         }
1185
1186         return 0;
1187 }
1188
1189 static int ci_stop_dpm(struct radeon_device *rdev)
1190 {
1191         struct ci_power_info *pi = ci_get_pi(rdev);
1192         PPSMC_Result smc_result;
1193         int ret;
1194         u32 tmp;
1195
1196         tmp = RREG32_SMC(GENERAL_PWRMGT);
1197         tmp &= ~GLOBAL_PWRMGT_EN;
1198         WREG32_SMC(GENERAL_PWRMGT, tmp);
1199
1200         tmp = RREG32_SMC(SCLK_PWRMGT_CNTL);
1201         tmp &= ~DYNAMIC_PM_EN;
1202         WREG32_SMC(SCLK_PWRMGT_CNTL, tmp);
1203
1204         if (!pi->pcie_dpm_key_disabled) {
1205                 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_PCIeDPM_Disable);
1206                 if (smc_result != PPSMC_Result_OK)
1207                         return -EINVAL;
1208         }
1209
1210         ret = ci_enable_sclk_mclk_dpm(rdev, false);
1211         if (ret)
1212                 return ret;
1213
1214         smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_Voltage_Cntl_Disable);
1215         if (smc_result != PPSMC_Result_OK)
1216                 return -EINVAL;
1217
1218         return 0;
1219 }
1220
1221 static void ci_enable_sclk_control(struct radeon_device *rdev, bool enable)
1222 {
1223         u32 tmp = RREG32_SMC(SCLK_PWRMGT_CNTL);
1224
1225         if (enable)
1226                 tmp &= ~SCLK_PWRMGT_OFF;
1227         else
1228                 tmp |= SCLK_PWRMGT_OFF;
1229         WREG32_SMC(SCLK_PWRMGT_CNTL, tmp);
1230 }
1231
1232 #if 0
1233 static int ci_notify_hw_of_power_source(struct radeon_device *rdev,
1234                                         bool ac_power)
1235 {
1236         struct ci_power_info *pi = ci_get_pi(rdev);
1237         struct radeon_cac_tdp_table *cac_tdp_table =
1238                 rdev->pm.dpm.dyn_state.cac_tdp_table;
1239         u32 power_limit;
1240
1241         if (ac_power)
1242                 power_limit = (u32)(cac_tdp_table->maximum_power_delivery_limit * 256);
1243         else
1244                 power_limit = (u32)(cac_tdp_table->battery_power_limit * 256);
1245
1246         ci_set_power_limit(rdev, power_limit);
1247
1248         if (pi->caps_automatic_dc_transition) {
1249                 if (ac_power)
1250                         ci_send_msg_to_smc(rdev, PPSMC_MSG_RunningOnAC);
1251                 else
1252                         ci_send_msg_to_smc(rdev, PPSMC_MSG_Remove_DC_Clamp);
1253         }
1254
1255         return 0;
1256 }
1257 #endif
1258
1259 static PPSMC_Result ci_send_msg_to_smc_with_parameter(struct radeon_device *rdev,
1260                                                       PPSMC_Msg msg, u32 parameter)
1261 {
1262         WREG32(SMC_MSG_ARG_0, parameter);
1263         return ci_send_msg_to_smc(rdev, msg);
1264 }
1265
1266 static PPSMC_Result ci_send_msg_to_smc_return_parameter(struct radeon_device *rdev,
1267                                                         PPSMC_Msg msg, u32 *parameter)
1268 {
1269         PPSMC_Result smc_result;
1270
1271         smc_result = ci_send_msg_to_smc(rdev, msg);
1272
1273         if ((smc_result == PPSMC_Result_OK) && parameter)
1274                 *parameter = RREG32(SMC_MSG_ARG_0);
1275
1276         return smc_result;
1277 }
1278
1279 static int ci_dpm_force_state_sclk(struct radeon_device *rdev, u32 n)
1280 {
1281         struct ci_power_info *pi = ci_get_pi(rdev);
1282
1283         if (!pi->sclk_dpm_key_disabled) {
1284                 PPSMC_Result smc_result =
1285                         ci_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SCLKDPM_SetEnabledMask, 1 << n);
1286                 if (smc_result != PPSMC_Result_OK)
1287                         return -EINVAL;
1288         }
1289
1290         return 0;
1291 }
1292
1293 static int ci_dpm_force_state_mclk(struct radeon_device *rdev, u32 n)
1294 {
1295         struct ci_power_info *pi = ci_get_pi(rdev);
1296
1297         if (!pi->mclk_dpm_key_disabled) {
1298                 PPSMC_Result smc_result =
1299                         ci_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_MCLKDPM_SetEnabledMask, 1 << n);
1300                 if (smc_result != PPSMC_Result_OK)
1301                         return -EINVAL;
1302         }
1303
1304         return 0;
1305 }
1306
1307 static int ci_dpm_force_state_pcie(struct radeon_device *rdev, u32 n)
1308 {
1309         struct ci_power_info *pi = ci_get_pi(rdev);
1310
1311         if (!pi->pcie_dpm_key_disabled) {
1312                 PPSMC_Result smc_result =
1313                         ci_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_PCIeDPM_ForceLevel, n);
1314                 if (smc_result != PPSMC_Result_OK)
1315                         return -EINVAL;
1316         }
1317
1318         return 0;
1319 }
1320
1321 static int ci_set_power_limit(struct radeon_device *rdev, u32 n)
1322 {
1323         struct ci_power_info *pi = ci_get_pi(rdev);
1324
1325         if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_PkgPwrLimit) {
1326                 PPSMC_Result smc_result =
1327                         ci_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_PkgPwrSetLimit, n);
1328                 if (smc_result != PPSMC_Result_OK)
1329                         return -EINVAL;
1330         }
1331
1332         return 0;
1333 }
1334
1335 static int ci_set_overdrive_target_tdp(struct radeon_device *rdev,
1336                                        u32 target_tdp)
1337 {
1338         PPSMC_Result smc_result =
1339                 ci_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_OverDriveSetTargetTdp, target_tdp);
1340         if (smc_result != PPSMC_Result_OK)
1341                 return -EINVAL;
1342         return 0;
1343 }
1344
1345 static int ci_set_boot_state(struct radeon_device *rdev)
1346 {
1347         return ci_enable_sclk_mclk_dpm(rdev, false);
1348 }
1349
1350 static u32 ci_get_average_sclk_freq(struct radeon_device *rdev)
1351 {
1352         u32 sclk_freq;
1353         PPSMC_Result smc_result =
1354                 ci_send_msg_to_smc_return_parameter(rdev,
1355                                                     PPSMC_MSG_API_GetSclkFrequency,
1356                                                     &sclk_freq);
1357         if (smc_result != PPSMC_Result_OK)
1358                 sclk_freq = 0;
1359
1360         return sclk_freq;
1361 }
1362
1363 static u32 ci_get_average_mclk_freq(struct radeon_device *rdev)
1364 {
1365         u32 mclk_freq;
1366         PPSMC_Result smc_result =
1367                 ci_send_msg_to_smc_return_parameter(rdev,
1368                                                     PPSMC_MSG_API_GetMclkFrequency,
1369                                                     &mclk_freq);
1370         if (smc_result != PPSMC_Result_OK)
1371                 mclk_freq = 0;
1372
1373         return mclk_freq;
1374 }
1375
1376 static void ci_dpm_start_smc(struct radeon_device *rdev)
1377 {
1378         int i;
1379
1380         ci_program_jump_on_start(rdev);
1381         ci_start_smc_clock(rdev);
1382         ci_start_smc(rdev);
1383         for (i = 0; i < rdev->usec_timeout; i++) {
1384                 if (RREG32_SMC(FIRMWARE_FLAGS) & INTERRUPTS_ENABLED)
1385                         break;
1386         }
1387 }
1388
1389 static void ci_dpm_stop_smc(struct radeon_device *rdev)
1390 {
1391         ci_reset_smc(rdev);
1392         ci_stop_smc_clock(rdev);
1393 }
1394
1395 static int ci_process_firmware_header(struct radeon_device *rdev)
1396 {
1397         struct ci_power_info *pi = ci_get_pi(rdev);
1398         u32 tmp;
1399         int ret;
1400
1401         ret = ci_read_smc_sram_dword(rdev,
1402                                      SMU7_FIRMWARE_HEADER_LOCATION +
1403                                      offsetof(SMU7_Firmware_Header, DpmTable),
1404                                      &tmp, pi->sram_end);
1405         if (ret)
1406                 return ret;
1407
1408         pi->dpm_table_start = tmp;
1409
1410         ret = ci_read_smc_sram_dword(rdev,
1411                                      SMU7_FIRMWARE_HEADER_LOCATION +
1412                                      offsetof(SMU7_Firmware_Header, SoftRegisters),
1413                                      &tmp, pi->sram_end);
1414         if (ret)
1415                 return ret;
1416
1417         pi->soft_regs_start = tmp;
1418
1419         ret = ci_read_smc_sram_dword(rdev,
1420                                      SMU7_FIRMWARE_HEADER_LOCATION +
1421                                      offsetof(SMU7_Firmware_Header, mcRegisterTable),
1422                                      &tmp, pi->sram_end);
1423         if (ret)
1424                 return ret;
1425
1426         pi->mc_reg_table_start = tmp;
1427
1428         ret = ci_read_smc_sram_dword(rdev,
1429                                      SMU7_FIRMWARE_HEADER_LOCATION +
1430                                      offsetof(SMU7_Firmware_Header, FanTable),
1431                                      &tmp, pi->sram_end);
1432         if (ret)
1433                 return ret;
1434
1435         pi->fan_table_start = tmp;
1436
1437         ret = ci_read_smc_sram_dword(rdev,
1438                                      SMU7_FIRMWARE_HEADER_LOCATION +
1439                                      offsetof(SMU7_Firmware_Header, mcArbDramTimingTable),
1440                                      &tmp, pi->sram_end);
1441         if (ret)
1442                 return ret;
1443
1444         pi->arb_table_start = tmp;
1445
1446         return 0;
1447 }
1448
1449 static void ci_read_clock_registers(struct radeon_device *rdev)
1450 {
1451         struct ci_power_info *pi = ci_get_pi(rdev);
1452
1453         pi->clock_registers.cg_spll_func_cntl =
1454                 RREG32_SMC(CG_SPLL_FUNC_CNTL);
1455         pi->clock_registers.cg_spll_func_cntl_2 =
1456                 RREG32_SMC(CG_SPLL_FUNC_CNTL_2);
1457         pi->clock_registers.cg_spll_func_cntl_3 =
1458                 RREG32_SMC(CG_SPLL_FUNC_CNTL_3);
1459         pi->clock_registers.cg_spll_func_cntl_4 =
1460                 RREG32_SMC(CG_SPLL_FUNC_CNTL_4);
1461         pi->clock_registers.cg_spll_spread_spectrum =
1462                 RREG32_SMC(CG_SPLL_SPREAD_SPECTRUM);
1463         pi->clock_registers.cg_spll_spread_spectrum_2 =
1464                 RREG32_SMC(CG_SPLL_SPREAD_SPECTRUM_2);
1465         pi->clock_registers.dll_cntl = RREG32(DLL_CNTL);
1466         pi->clock_registers.mclk_pwrmgt_cntl = RREG32(MCLK_PWRMGT_CNTL);
1467         pi->clock_registers.mpll_ad_func_cntl = RREG32(MPLL_AD_FUNC_CNTL);
1468         pi->clock_registers.mpll_dq_func_cntl = RREG32(MPLL_DQ_FUNC_CNTL);
1469         pi->clock_registers.mpll_func_cntl = RREG32(MPLL_FUNC_CNTL);
1470         pi->clock_registers.mpll_func_cntl_1 = RREG32(MPLL_FUNC_CNTL_1);
1471         pi->clock_registers.mpll_func_cntl_2 = RREG32(MPLL_FUNC_CNTL_2);
1472         pi->clock_registers.mpll_ss1 = RREG32(MPLL_SS1);
1473         pi->clock_registers.mpll_ss2 = RREG32(MPLL_SS2);
1474 }
1475
1476 static void ci_init_sclk_t(struct radeon_device *rdev)
1477 {
1478         struct ci_power_info *pi = ci_get_pi(rdev);
1479
1480         pi->low_sclk_interrupt_t = 0;
1481 }
1482
1483 static void ci_enable_thermal_protection(struct radeon_device *rdev,
1484                                          bool enable)
1485 {
1486         u32 tmp = RREG32_SMC(GENERAL_PWRMGT);
1487
1488         if (enable)
1489                 tmp &= ~THERMAL_PROTECTION_DIS;
1490         else
1491                 tmp |= THERMAL_PROTECTION_DIS;
1492         WREG32_SMC(GENERAL_PWRMGT, tmp);
1493 }
1494
1495 static void ci_enable_acpi_power_management(struct radeon_device *rdev)
1496 {
1497         u32 tmp = RREG32_SMC(GENERAL_PWRMGT);
1498
1499         tmp |= STATIC_PM_EN;
1500
1501         WREG32_SMC(GENERAL_PWRMGT, tmp);
1502 }
1503
1504 #if 0
1505 static int ci_enter_ulp_state(struct radeon_device *rdev)
1506 {
1507
1508         WREG32(SMC_MESSAGE_0, PPSMC_MSG_SwitchToMinimumPower);
1509
1510         udelay(25000);
1511
1512         return 0;
1513 }
1514
1515 static int ci_exit_ulp_state(struct radeon_device *rdev)
1516 {
1517         int i;
1518
1519         WREG32(SMC_MESSAGE_0, PPSMC_MSG_ResumeFromMinimumPower);
1520
1521         udelay(7000);
1522
1523         for (i = 0; i < rdev->usec_timeout; i++) {
1524                 if (RREG32(SMC_RESP_0) == 1)
1525                         break;
1526                 udelay(1000);
1527         }
1528
1529         return 0;
1530 }
1531 #endif
1532
1533 static int ci_notify_smc_display_change(struct radeon_device *rdev,
1534                                         bool has_display)
1535 {
1536         PPSMC_Msg msg = has_display ? PPSMC_MSG_HasDisplay : PPSMC_MSG_NoDisplay;
1537
1538         return (ci_send_msg_to_smc(rdev, msg) == PPSMC_Result_OK) ?  0 : -EINVAL;
1539 }
1540
1541 static int ci_enable_ds_master_switch(struct radeon_device *rdev,
1542                                       bool enable)
1543 {
1544         struct ci_power_info *pi = ci_get_pi(rdev);
1545
1546         if (enable) {
1547                 if (pi->caps_sclk_ds) {
1548                         if (ci_send_msg_to_smc(rdev, PPSMC_MSG_MASTER_DeepSleep_ON) != PPSMC_Result_OK)
1549                                 return -EINVAL;
1550                 } else {
1551                         if (ci_send_msg_to_smc(rdev, PPSMC_MSG_MASTER_DeepSleep_OFF) != PPSMC_Result_OK)
1552                                 return -EINVAL;
1553                 }
1554         } else {
1555                 if (pi->caps_sclk_ds) {
1556                         if (ci_send_msg_to_smc(rdev, PPSMC_MSG_MASTER_DeepSleep_OFF) != PPSMC_Result_OK)
1557                                 return -EINVAL;
1558                 }
1559         }
1560
1561         return 0;
1562 }
1563
1564 static void ci_program_display_gap(struct radeon_device *rdev)
1565 {
1566         u32 tmp = RREG32_SMC(CG_DISPLAY_GAP_CNTL);
1567         u32 pre_vbi_time_in_us;
1568         u32 frame_time_in_us;
1569         u32 ref_clock = rdev->clock.spll.reference_freq;
1570         u32 refresh_rate = r600_dpm_get_vrefresh(rdev);
1571         u32 vblank_time = r600_dpm_get_vblank_time(rdev);
1572
1573         tmp &= ~DISP_GAP_MASK;
1574         if (rdev->pm.dpm.new_active_crtc_count > 0)
1575                 tmp |= DISP_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM);
1576         else
1577                 tmp |= DISP_GAP(R600_PM_DISPLAY_GAP_IGNORE);
1578         WREG32_SMC(CG_DISPLAY_GAP_CNTL, tmp);
1579
1580         if (refresh_rate == 0)
1581                 refresh_rate = 60;
1582         if (vblank_time == 0xffffffff)
1583                 vblank_time = 500;
1584         frame_time_in_us = 1000000 / refresh_rate;
1585         pre_vbi_time_in_us =
1586                 frame_time_in_us - 200 - vblank_time;
1587         tmp = pre_vbi_time_in_us * (ref_clock / 100);
1588
1589         WREG32_SMC(CG_DISPLAY_GAP_CNTL2, tmp);
1590         ci_write_smc_soft_register(rdev, offsetof(SMU7_SoftRegisters, PreVBlankGap), 0x64);
1591         ci_write_smc_soft_register(rdev, offsetof(SMU7_SoftRegisters, VBlankTimeout), (frame_time_in_us - pre_vbi_time_in_us));
1592
1593
1594         ci_notify_smc_display_change(rdev, (rdev->pm.dpm.new_active_crtc_count == 1));
1595
1596 }
1597
1598 static void ci_enable_spread_spectrum(struct radeon_device *rdev, bool enable)
1599 {
1600         struct ci_power_info *pi = ci_get_pi(rdev);
1601         u32 tmp;
1602
1603         if (enable) {
1604                 if (pi->caps_sclk_ss_support) {
1605                         tmp = RREG32_SMC(GENERAL_PWRMGT);
1606                         tmp |= DYN_SPREAD_SPECTRUM_EN;
1607                         WREG32_SMC(GENERAL_PWRMGT, tmp);
1608                 }
1609         } else {
1610                 tmp = RREG32_SMC(CG_SPLL_SPREAD_SPECTRUM);
1611                 tmp &= ~SSEN;
1612                 WREG32_SMC(CG_SPLL_SPREAD_SPECTRUM, tmp);
1613
1614                 tmp = RREG32_SMC(GENERAL_PWRMGT);
1615                 tmp &= ~DYN_SPREAD_SPECTRUM_EN;
1616                 WREG32_SMC(GENERAL_PWRMGT, tmp);
1617         }
1618 }
1619
1620 static void ci_program_sstp(struct radeon_device *rdev)
1621 {
1622         WREG32_SMC(CG_SSP, (SSTU(R600_SSTU_DFLT) | SST(R600_SST_DFLT)));
1623 }
1624
1625 static void ci_enable_display_gap(struct radeon_device *rdev)
1626 {
1627         u32 tmp = RREG32_SMC(CG_DISPLAY_GAP_CNTL);
1628
1629         tmp &= ~(DISP_GAP_MASK | DISP_GAP_MCHG_MASK);
1630         tmp |= (DISP_GAP(R600_PM_DISPLAY_GAP_IGNORE) |
1631                 DISP_GAP_MCHG(R600_PM_DISPLAY_GAP_VBLANK));
1632
1633         WREG32_SMC(CG_DISPLAY_GAP_CNTL, tmp);
1634 }
1635
1636 static void ci_program_vc(struct radeon_device *rdev)
1637 {
1638         u32 tmp;
1639
1640         tmp = RREG32_SMC(SCLK_PWRMGT_CNTL);
1641         tmp &= ~(RESET_SCLK_CNT | RESET_BUSY_CNT);
1642         WREG32_SMC(SCLK_PWRMGT_CNTL, tmp);
1643
1644         WREG32_SMC(CG_FTV_0, CISLANDS_VRC_DFLT0);
1645         WREG32_SMC(CG_FTV_1, CISLANDS_VRC_DFLT1);
1646         WREG32_SMC(CG_FTV_2, CISLANDS_VRC_DFLT2);
1647         WREG32_SMC(CG_FTV_3, CISLANDS_VRC_DFLT3);
1648         WREG32_SMC(CG_FTV_4, CISLANDS_VRC_DFLT4);
1649         WREG32_SMC(CG_FTV_5, CISLANDS_VRC_DFLT5);
1650         WREG32_SMC(CG_FTV_6, CISLANDS_VRC_DFLT6);
1651         WREG32_SMC(CG_FTV_7, CISLANDS_VRC_DFLT7);
1652 }
1653
1654 static void ci_clear_vc(struct radeon_device *rdev)
1655 {
1656         u32 tmp;
1657
1658         tmp = RREG32_SMC(SCLK_PWRMGT_CNTL);
1659         tmp |= (RESET_SCLK_CNT | RESET_BUSY_CNT);
1660         WREG32_SMC(SCLK_PWRMGT_CNTL, tmp);
1661
1662         WREG32_SMC(CG_FTV_0, 0);
1663         WREG32_SMC(CG_FTV_1, 0);
1664         WREG32_SMC(CG_FTV_2, 0);
1665         WREG32_SMC(CG_FTV_3, 0);
1666         WREG32_SMC(CG_FTV_4, 0);
1667         WREG32_SMC(CG_FTV_5, 0);
1668         WREG32_SMC(CG_FTV_6, 0);
1669         WREG32_SMC(CG_FTV_7, 0);
1670 }
1671
1672 static int ci_upload_firmware(struct radeon_device *rdev)
1673 {
1674         struct ci_power_info *pi = ci_get_pi(rdev);
1675         int i, ret;
1676
1677         for (i = 0; i < rdev->usec_timeout; i++) {
1678                 if (RREG32_SMC(RCU_UC_EVENTS) & BOOT_SEQ_DONE)
1679                         break;
1680         }
1681         WREG32_SMC(SMC_SYSCON_MISC_CNTL, 1);
1682
1683         ci_stop_smc_clock(rdev);
1684         ci_reset_smc(rdev);
1685
1686         ret = ci_load_smc_ucode(rdev, pi->sram_end);
1687
1688         return ret;
1689
1690 }
1691
1692 static int ci_get_svi2_voltage_table(struct radeon_device *rdev,
1693                                      struct radeon_clock_voltage_dependency_table *voltage_dependency_table,
1694                                      struct atom_voltage_table *voltage_table)
1695 {
1696         u32 i;
1697
1698         if (voltage_dependency_table == NULL)
1699                 return -EINVAL;
1700
1701         voltage_table->mask_low = 0;
1702         voltage_table->phase_delay = 0;
1703
1704         voltage_table->count = voltage_dependency_table->count;
1705         for (i = 0; i < voltage_table->count; i++) {
1706                 voltage_table->entries[i].value = voltage_dependency_table->entries[i].v;
1707                 voltage_table->entries[i].smio_low = 0;
1708         }
1709
1710         return 0;
1711 }
1712
1713 static int ci_construct_voltage_tables(struct radeon_device *rdev)
1714 {
1715         struct ci_power_info *pi = ci_get_pi(rdev);
1716         int ret;
1717
1718         if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) {
1719                 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDC,
1720                                                     VOLTAGE_OBJ_GPIO_LUT,
1721                                                     &pi->vddc_voltage_table);
1722                 if (ret)
1723                         return ret;
1724         } else if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2) {
1725                 ret = ci_get_svi2_voltage_table(rdev,
1726                                                 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
1727                                                 &pi->vddc_voltage_table);
1728                 if (ret)
1729                         return ret;
1730         }
1731
1732         if (pi->vddc_voltage_table.count > SMU7_MAX_LEVELS_VDDC)
1733                 si_trim_voltage_table_to_fit_state_table(rdev, SMU7_MAX_LEVELS_VDDC,
1734                                                          &pi->vddc_voltage_table);
1735
1736         if (pi->vddci_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) {
1737                 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDCI,
1738                                                     VOLTAGE_OBJ_GPIO_LUT,
1739                                                     &pi->vddci_voltage_table);
1740                 if (ret)
1741                         return ret;
1742         } else if (pi->vddci_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2) {
1743                 ret = ci_get_svi2_voltage_table(rdev,
1744                                                 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
1745                                                 &pi->vddci_voltage_table);
1746                 if (ret)
1747                         return ret;
1748         }
1749
1750         if (pi->vddci_voltage_table.count > SMU7_MAX_LEVELS_VDDCI)
1751                 si_trim_voltage_table_to_fit_state_table(rdev, SMU7_MAX_LEVELS_VDDCI,
1752                                                          &pi->vddci_voltage_table);
1753
1754         if (pi->mvdd_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) {
1755                 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_MVDDC,
1756                                                     VOLTAGE_OBJ_GPIO_LUT,
1757                                                     &pi->mvdd_voltage_table);
1758                 if (ret)
1759                         return ret;
1760         } else if (pi->mvdd_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2) {
1761                 ret = ci_get_svi2_voltage_table(rdev,
1762                                                 &rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk,
1763                                                 &pi->mvdd_voltage_table);
1764                 if (ret)
1765                         return ret;
1766         }
1767
1768         if (pi->mvdd_voltage_table.count > SMU7_MAX_LEVELS_MVDD)
1769                 si_trim_voltage_table_to_fit_state_table(rdev, SMU7_MAX_LEVELS_MVDD,
1770                                                          &pi->mvdd_voltage_table);
1771
1772         return 0;
1773 }
1774
1775 static void ci_populate_smc_voltage_table(struct radeon_device *rdev,
1776                                           struct atom_voltage_table_entry *voltage_table,
1777                                           SMU7_Discrete_VoltageLevel *smc_voltage_table)
1778 {
1779         int ret;
1780
1781         ret = ci_get_std_voltage_value_sidd(rdev, voltage_table,
1782                                             &smc_voltage_table->StdVoltageHiSidd,
1783                                             &smc_voltage_table->StdVoltageLoSidd);
1784
1785         if (ret) {
1786                 smc_voltage_table->StdVoltageHiSidd = voltage_table->value * VOLTAGE_SCALE;
1787                 smc_voltage_table->StdVoltageLoSidd = voltage_table->value * VOLTAGE_SCALE;
1788         }
1789
1790         smc_voltage_table->Voltage = cpu_to_be16(voltage_table->value * VOLTAGE_SCALE);
1791         smc_voltage_table->StdVoltageHiSidd =
1792                 cpu_to_be16(smc_voltage_table->StdVoltageHiSidd);
1793         smc_voltage_table->StdVoltageLoSidd =
1794                 cpu_to_be16(smc_voltage_table->StdVoltageLoSidd);
1795 }
1796
1797 static int ci_populate_smc_vddc_table(struct radeon_device *rdev,
1798                                       SMU7_Discrete_DpmTable *table)
1799 {
1800         struct ci_power_info *pi = ci_get_pi(rdev);
1801         unsigned int count;
1802
1803         table->VddcLevelCount = pi->vddc_voltage_table.count;
1804         for (count = 0; count < table->VddcLevelCount; count++) {
1805                 ci_populate_smc_voltage_table(rdev,
1806                                               &pi->vddc_voltage_table.entries[count],
1807                                               &table->VddcLevel[count]);
1808
1809                 if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO)
1810                         table->VddcLevel[count].Smio |=
1811                                 pi->vddc_voltage_table.entries[count].smio_low;
1812                 else
1813                         table->VddcLevel[count].Smio = 0;
1814         }
1815         table->VddcLevelCount = cpu_to_be32(table->VddcLevelCount);
1816
1817         return 0;
1818 }
1819
1820 static int ci_populate_smc_vddci_table(struct radeon_device *rdev,
1821                                        SMU7_Discrete_DpmTable *table)
1822 {
1823         unsigned int count;
1824         struct ci_power_info *pi = ci_get_pi(rdev);
1825
1826         table->VddciLevelCount = pi->vddci_voltage_table.count;
1827         for (count = 0; count < table->VddciLevelCount; count++) {
1828                 ci_populate_smc_voltage_table(rdev,
1829                                               &pi->vddci_voltage_table.entries[count],
1830                                               &table->VddciLevel[count]);
1831
1832                 if (pi->vddci_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO)
1833                         table->VddciLevel[count].Smio |=
1834                                 pi->vddci_voltage_table.entries[count].smio_low;
1835                 else
1836                         table->VddciLevel[count].Smio = 0;
1837         }
1838         table->VddciLevelCount = cpu_to_be32(table->VddciLevelCount);
1839
1840         return 0;
1841 }
1842
1843 static int ci_populate_smc_mvdd_table(struct radeon_device *rdev,
1844                                       SMU7_Discrete_DpmTable *table)
1845 {
1846         struct ci_power_info *pi = ci_get_pi(rdev);
1847         unsigned int count;
1848
1849         table->MvddLevelCount = pi->mvdd_voltage_table.count;
1850         for (count = 0; count < table->MvddLevelCount; count++) {
1851                 ci_populate_smc_voltage_table(rdev,
1852                                               &pi->mvdd_voltage_table.entries[count],
1853                                               &table->MvddLevel[count]);
1854
1855                 if (pi->mvdd_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO)
1856                         table->MvddLevel[count].Smio |=
1857                                 pi->mvdd_voltage_table.entries[count].smio_low;
1858                 else
1859                         table->MvddLevel[count].Smio = 0;
1860         }
1861         table->MvddLevelCount = cpu_to_be32(table->MvddLevelCount);
1862
1863         return 0;
1864 }
1865
1866 static int ci_populate_smc_voltage_tables(struct radeon_device *rdev,
1867                                           SMU7_Discrete_DpmTable *table)
1868 {
1869         int ret;
1870
1871         ret = ci_populate_smc_vddc_table(rdev, table);
1872         if (ret)
1873                 return ret;
1874
1875         ret = ci_populate_smc_vddci_table(rdev, table);
1876         if (ret)
1877                 return ret;
1878
1879         ret = ci_populate_smc_mvdd_table(rdev, table);
1880         if (ret)
1881                 return ret;
1882
1883         return 0;
1884 }
1885
1886 static int ci_populate_mvdd_value(struct radeon_device *rdev, u32 mclk,
1887                                   SMU7_Discrete_VoltageLevel *voltage)
1888 {
1889         struct ci_power_info *pi = ci_get_pi(rdev);
1890         u32 i = 0;
1891
1892         if (pi->mvdd_control != CISLANDS_VOLTAGE_CONTROL_NONE) {
1893                 for (i = 0; i < rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.count; i++) {
1894                         if (mclk <= rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.entries[i].clk) {
1895                                 voltage->Voltage = pi->mvdd_voltage_table.entries[i].value;
1896                                 break;
1897                         }
1898                 }
1899
1900                 if (i >= rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.count)
1901                         return -EINVAL;
1902         }
1903
1904         return -EINVAL;
1905 }
1906
1907 static int ci_get_std_voltage_value_sidd(struct radeon_device *rdev,
1908                                          struct atom_voltage_table_entry *voltage_table,
1909                                          u16 *std_voltage_hi_sidd, u16 *std_voltage_lo_sidd)
1910 {
1911         u16 v_index, idx;
1912         bool voltage_found = false;
1913         *std_voltage_hi_sidd = voltage_table->value * VOLTAGE_SCALE;
1914         *std_voltage_lo_sidd = voltage_table->value * VOLTAGE_SCALE;
1915
1916         if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries == NULL)
1917                 return -EINVAL;
1918
1919         if (rdev->pm.dpm.dyn_state.cac_leakage_table.entries) {
1920                 for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {
1921                         if (voltage_table->value ==
1922                             rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) {
1923                                 voltage_found = true;
1924                                 if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count)
1925                                         idx = v_index;
1926                                 else
1927                                         idx = rdev->pm.dpm.dyn_state.cac_leakage_table.count - 1;
1928                                 *std_voltage_lo_sidd =
1929                                         rdev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].vddc * VOLTAGE_SCALE;
1930                                 *std_voltage_hi_sidd =
1931                                         rdev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].leakage * VOLTAGE_SCALE;
1932                                 break;
1933                         }
1934                 }
1935
1936                 if (!voltage_found) {
1937                         for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {
1938                                 if (voltage_table->value <=
1939                                     rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) {
1940                                         voltage_found = true;
1941                                         if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count)
1942                                                 idx = v_index;
1943                                         else
1944                                                 idx = rdev->pm.dpm.dyn_state.cac_leakage_table.count - 1;
1945                                         *std_voltage_lo_sidd =
1946                                                 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].vddc * VOLTAGE_SCALE;
1947                                         *std_voltage_hi_sidd =
1948                                                 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].leakage * VOLTAGE_SCALE;
1949                                         break;
1950                                 }
1951                         }
1952                 }
1953         }
1954
1955         return 0;
1956 }
1957
1958 static void ci_populate_phase_value_based_on_sclk(struct radeon_device *rdev,
1959                                                   const struct radeon_phase_shedding_limits_table *limits,
1960                                                   u32 sclk,
1961                                                   u32 *phase_shedding)
1962 {
1963         unsigned int i;
1964
1965         *phase_shedding = 1;
1966
1967         for (i = 0; i < limits->count; i++) {
1968                 if (sclk < limits->entries[i].sclk) {
1969                         *phase_shedding = i;
1970                         break;
1971                 }
1972         }
1973 }
1974
1975 static void ci_populate_phase_value_based_on_mclk(struct radeon_device *rdev,
1976                                                   const struct radeon_phase_shedding_limits_table *limits,
1977                                                   u32 mclk,
1978                                                   u32 *phase_shedding)
1979 {
1980         unsigned int i;
1981
1982         *phase_shedding = 1;
1983
1984         for (i = 0; i < limits->count; i++) {
1985                 if (mclk < limits->entries[i].mclk) {
1986                         *phase_shedding = i;
1987                         break;
1988                 }
1989         }
1990 }
1991
1992 static int ci_init_arb_table_index(struct radeon_device *rdev)
1993 {
1994         struct ci_power_info *pi = ci_get_pi(rdev);
1995         u32 tmp;
1996         int ret;
1997
1998         ret = ci_read_smc_sram_dword(rdev, pi->arb_table_start,
1999                                      &tmp, pi->sram_end);
2000         if (ret)
2001                 return ret;
2002
2003         tmp &= 0x00FFFFFF;
2004         tmp |= MC_CG_ARB_FREQ_F1 << 24;
2005
2006         return ci_write_smc_sram_dword(rdev, pi->arb_table_start,
2007                                        tmp, pi->sram_end);
2008 }
2009
2010 static int ci_get_dependency_volt_by_clk(struct radeon_device *rdev,
2011                                          struct radeon_clock_voltage_dependency_table *allowed_clock_voltage_table,
2012                                          u32 clock, u32 *voltage)
2013 {
2014         u32 i = 0;
2015
2016         if (allowed_clock_voltage_table->count == 0)
2017                 return -EINVAL;
2018
2019         for (i = 0; i < allowed_clock_voltage_table->count; i++) {
2020                 if (allowed_clock_voltage_table->entries[i].clk >= clock) {
2021                         *voltage = allowed_clock_voltage_table->entries[i].v;
2022                         return 0;
2023                 }
2024         }
2025
2026         *voltage = allowed_clock_voltage_table->entries[i-1].v;
2027
2028         return 0;
2029 }
2030
2031 static u8 ci_get_sleep_divider_id_from_clock(struct radeon_device *rdev,
2032                                              u32 sclk, u32 min_sclk_in_sr)
2033 {
2034         u32 i;
2035         u32 tmp;
2036         u32 min = (min_sclk_in_sr > CISLAND_MINIMUM_ENGINE_CLOCK) ?
2037                 min_sclk_in_sr : CISLAND_MINIMUM_ENGINE_CLOCK;
2038
2039         if (sclk < min)
2040                 return 0;
2041
2042         for (i = CISLAND_MAX_DEEPSLEEP_DIVIDER_ID;  ; i--) {
2043                 tmp = sclk / (1 << i);
2044                 if (tmp >= min || i == 0)
2045                         break;
2046         }
2047
2048         return (u8)i;
2049 }
2050
2051 static int ci_initial_switch_from_arb_f0_to_f1(struct radeon_device *rdev)
2052 {
2053         return ni_copy_and_switch_arb_sets(rdev, MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1);
2054 }
2055
2056 static int ci_reset_to_default(struct radeon_device *rdev)
2057 {
2058         return (ci_send_msg_to_smc(rdev, PPSMC_MSG_ResetToDefaults) == PPSMC_Result_OK) ?
2059                 0 : -EINVAL;
2060 }
2061
2062 static int ci_force_switch_to_arb_f0(struct radeon_device *rdev)
2063 {
2064         u32 tmp;
2065
2066         tmp = (RREG32_SMC(SMC_SCRATCH9) & 0x0000ff00) >> 8;
2067
2068         if (tmp == MC_CG_ARB_FREQ_F0)
2069                 return 0;
2070
2071         return ni_copy_and_switch_arb_sets(rdev, tmp, MC_CG_ARB_FREQ_F0);
2072 }
2073
2074 static void ci_register_patching_mc_arb(struct radeon_device *rdev,
2075                                         const u32 engine_clock,
2076                                         const u32 memory_clock,
2077                                         u32 *dram_timimg2)
2078 {
2079         bool patch;
2080         u32 tmp, tmp2;
2081
2082         tmp = RREG32(MC_SEQ_MISC0);
2083         patch = ((tmp & 0x0000f00) == 0x300) ? true : false;
2084
2085         if (patch &&
2086             ((rdev->pdev->device == 0x67B0) ||
2087              (rdev->pdev->device == 0x67B1))) {
2088                 if ((memory_clock > 100000) && (memory_clock <= 125000)) {
2089                         tmp2 = (((0x31 * engine_clock) / 125000) - 1) & 0xff;
2090                         *dram_timimg2 &= ~0x00ff0000;
2091                         *dram_timimg2 |= tmp2 << 16;
2092                 } else if ((memory_clock > 125000) && (memory_clock <= 137500)) {
2093                         tmp2 = (((0x36 * engine_clock) / 137500) - 1) & 0xff;
2094                         *dram_timimg2 &= ~0x00ff0000;
2095                         *dram_timimg2 |= tmp2 << 16;
2096                 }
2097         }
2098 }
2099
2100
2101 static int ci_populate_memory_timing_parameters(struct radeon_device *rdev,
2102                                                 u32 sclk,
2103                                                 u32 mclk,
2104                                                 SMU7_Discrete_MCArbDramTimingTableEntry *arb_regs)
2105 {
2106         u32 dram_timing;
2107         u32 dram_timing2;
2108         u32 burst_time;
2109
2110         radeon_atom_set_engine_dram_timings(rdev, sclk, mclk);
2111
2112         dram_timing  = RREG32(MC_ARB_DRAM_TIMING);
2113         dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2);
2114         burst_time = RREG32(MC_ARB_BURST_TIME) & STATE0_MASK;
2115
2116         ci_register_patching_mc_arb(rdev, sclk, mclk, &dram_timing2);
2117
2118         arb_regs->McArbDramTiming  = cpu_to_be32(dram_timing);
2119         arb_regs->McArbDramTiming2 = cpu_to_be32(dram_timing2);
2120         arb_regs->McArbBurstTime = (u8)burst_time;
2121
2122         return 0;
2123 }
2124
2125 static int ci_do_program_memory_timing_parameters(struct radeon_device *rdev)
2126 {
2127         struct ci_power_info *pi = ci_get_pi(rdev);
2128         SMU7_Discrete_MCArbDramTimingTable arb_regs;
2129         u32 i, j;
2130         int ret =  0;
2131
2132         memset(&arb_regs, 0, sizeof(SMU7_Discrete_MCArbDramTimingTable));
2133
2134         for (i = 0; i < pi->dpm_table.sclk_table.count; i++) {
2135                 for (j = 0; j < pi->dpm_table.mclk_table.count; j++) {
2136                         ret = ci_populate_memory_timing_parameters(rdev,
2137                                                                    pi->dpm_table.sclk_table.dpm_levels[i].value,
2138                                                                    pi->dpm_table.mclk_table.dpm_levels[j].value,
2139                                                                    &arb_regs.entries[i][j]);
2140                         if (ret)
2141                                 break;
2142                 }
2143         }
2144
2145         if (ret == 0)
2146                 ret = ci_copy_bytes_to_smc(rdev,
2147                                            pi->arb_table_start,
2148                                            (u8 *)&arb_regs,
2149                                            sizeof(SMU7_Discrete_MCArbDramTimingTable),
2150                                            pi->sram_end);
2151
2152         return ret;
2153 }
2154
2155 static int ci_program_memory_timing_parameters(struct radeon_device *rdev)
2156 {
2157         struct ci_power_info *pi = ci_get_pi(rdev);
2158
2159         if (pi->need_update_smu7_dpm_table == 0)
2160                 return 0;
2161
2162         return ci_do_program_memory_timing_parameters(rdev);
2163 }
2164
2165 static void ci_populate_smc_initial_state(struct radeon_device *rdev,
2166                                           struct radeon_ps *radeon_boot_state)
2167 {
2168         struct ci_ps *boot_state = ci_get_ps(radeon_boot_state);
2169         struct ci_power_info *pi = ci_get_pi(rdev);
2170         u32 level = 0;
2171
2172         for (level = 0; level < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; level++) {
2173                 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[level].clk >=
2174                     boot_state->performance_levels[0].sclk) {
2175                         pi->smc_state_table.GraphicsBootLevel = level;
2176                         break;
2177                 }
2178         }
2179
2180         for (level = 0; level < rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk.count; level++) {
2181                 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk.entries[level].clk >=
2182                     boot_state->performance_levels[0].mclk) {
2183                         pi->smc_state_table.MemoryBootLevel = level;
2184                         break;
2185                 }
2186         }
2187 }
2188
2189 static u32 ci_get_dpm_level_enable_mask_value(struct ci_single_dpm_table *dpm_table)
2190 {
2191         u32 i;
2192         u32 mask_value = 0;
2193
2194         for (i = dpm_table->count; i > 0; i--) {
2195                 mask_value = mask_value << 1;
2196                 if (dpm_table->dpm_levels[i-1].enabled)
2197                         mask_value |= 0x1;
2198                 else
2199                         mask_value &= 0xFFFFFFFE;
2200         }
2201
2202         return mask_value;
2203 }
2204
2205 static void ci_populate_smc_link_level(struct radeon_device *rdev,
2206                                        SMU7_Discrete_DpmTable *table)
2207 {
2208         struct ci_power_info *pi = ci_get_pi(rdev);
2209         struct ci_dpm_table *dpm_table = &pi->dpm_table;
2210         u32 i;
2211
2212         for (i = 0; i < dpm_table->pcie_speed_table.count; i++) {
2213                 table->LinkLevel[i].PcieGenSpeed =
2214                         (u8)dpm_table->pcie_speed_table.dpm_levels[i].value;
2215                 table->LinkLevel[i].PcieLaneCount =
2216                         r600_encode_pci_lane_width(dpm_table->pcie_speed_table.dpm_levels[i].param1);
2217                 table->LinkLevel[i].EnabledForActivity = 1;
2218                 table->LinkLevel[i].DownT = cpu_to_be32(5);
2219                 table->LinkLevel[i].UpT = cpu_to_be32(30);
2220         }
2221
2222         pi->smc_state_table.LinkLevelCount = (u8)dpm_table->pcie_speed_table.count;
2223         pi->dpm_level_enable_mask.pcie_dpm_enable_mask =
2224                 ci_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table);
2225 }
2226
2227 static int ci_populate_smc_uvd_level(struct radeon_device *rdev,
2228                                      SMU7_Discrete_DpmTable *table)
2229 {
2230         u32 count;
2231         struct atom_clock_dividers dividers;
2232         int ret = -EINVAL;
2233
2234         table->UvdLevelCount =
2235                 rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count;
2236
2237         for (count = 0; count < table->UvdLevelCount; count++) {
2238                 table->UvdLevel[count].VclkFrequency =
2239                         rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[count].vclk;
2240                 table->UvdLevel[count].DclkFrequency =
2241                         rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[count].dclk;
2242                 table->UvdLevel[count].MinVddc =
2243                         rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[count].v * VOLTAGE_SCALE;
2244                 table->UvdLevel[count].MinVddcPhases = 1;
2245
2246                 ret = radeon_atom_get_clock_dividers(rdev,
2247                                                      COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
2248                                                      table->UvdLevel[count].VclkFrequency, false, &dividers);
2249                 if (ret)
2250                         return ret;
2251
2252                 table->UvdLevel[count].VclkDivider = (u8)dividers.post_divider;
2253
2254                 ret = radeon_atom_get_clock_dividers(rdev,
2255                                                      COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
2256                                                      table->UvdLevel[count].DclkFrequency, false, &dividers);
2257                 if (ret)
2258                         return ret;
2259
2260                 table->UvdLevel[count].DclkDivider = (u8)dividers.post_divider;
2261
2262                 table->UvdLevel[count].VclkFrequency = cpu_to_be32(table->UvdLevel[count].VclkFrequency);
2263                 table->UvdLevel[count].DclkFrequency = cpu_to_be32(table->UvdLevel[count].DclkFrequency);
2264                 table->UvdLevel[count].MinVddc = cpu_to_be16(table->UvdLevel[count].MinVddc);
2265         }
2266
2267         return ret;
2268 }
2269
2270 static int ci_populate_smc_vce_level(struct radeon_device *rdev,
2271                                      SMU7_Discrete_DpmTable *table)
2272 {
2273         u32 count;
2274         struct atom_clock_dividers dividers;
2275         int ret = -EINVAL;
2276
2277         table->VceLevelCount =
2278                 rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.count;
2279
2280         for (count = 0; count < table->VceLevelCount; count++) {
2281                 table->VceLevel[count].Frequency =
2282                         rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[count].evclk;
2283                 table->VceLevel[count].MinVoltage =
2284                         (u16)rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[count].v * VOLTAGE_SCALE;
2285                 table->VceLevel[count].MinPhases = 1;
2286
2287                 ret = radeon_atom_get_clock_dividers(rdev,
2288                                                      COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
2289                                                      table->VceLevel[count].Frequency, false, &dividers);
2290                 if (ret)
2291                         return ret;
2292
2293                 table->VceLevel[count].Divider = (u8)dividers.post_divider;
2294
2295                 table->VceLevel[count].Frequency = cpu_to_be32(table->VceLevel[count].Frequency);
2296                 table->VceLevel[count].MinVoltage = cpu_to_be16(table->VceLevel[count].MinVoltage);
2297         }
2298
2299         return ret;
2300
2301 }
2302
2303 static int ci_populate_smc_acp_level(struct radeon_device *rdev,
2304                                      SMU7_Discrete_DpmTable *table)
2305 {
2306         u32 count;
2307         struct atom_clock_dividers dividers;
2308         int ret = -EINVAL;
2309
2310         table->AcpLevelCount = (u8)
2311                 (rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.count);
2312
2313         for (count = 0; count < table->AcpLevelCount; count++) {
2314                 table->AcpLevel[count].Frequency =
2315                         rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries[count].clk;
2316                 table->AcpLevel[count].MinVoltage =
2317                         rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries[count].v;
2318                 table->AcpLevel[count].MinPhases = 1;
2319
2320                 ret = radeon_atom_get_clock_dividers(rdev,
2321                                                      COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
2322                                                      table->AcpLevel[count].Frequency, false, &dividers);
2323                 if (ret)
2324                         return ret;
2325
2326                 table->AcpLevel[count].Divider = (u8)dividers.post_divider;
2327
2328                 table->AcpLevel[count].Frequency = cpu_to_be32(table->AcpLevel[count].Frequency);
2329                 table->AcpLevel[count].MinVoltage = cpu_to_be16(table->AcpLevel[count].MinVoltage);
2330         }
2331
2332         return ret;
2333 }
2334
2335 static int ci_populate_smc_samu_level(struct radeon_device *rdev,
2336                                       SMU7_Discrete_DpmTable *table)
2337 {
2338         u32 count;
2339         struct atom_clock_dividers dividers;
2340         int ret = -EINVAL;
2341
2342         table->SamuLevelCount =
2343                 rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.count;
2344
2345         for (count = 0; count < table->SamuLevelCount; count++) {
2346                 table->SamuLevel[count].Frequency =
2347                         rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries[count].clk;
2348                 table->SamuLevel[count].MinVoltage =
2349                         rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries[count].v * VOLTAGE_SCALE;
2350                 table->SamuLevel[count].MinPhases = 1;
2351
2352                 ret = radeon_atom_get_clock_dividers(rdev,
2353                                                      COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
2354                                                      table->SamuLevel[count].Frequency, false, &dividers);
2355                 if (ret)
2356                         return ret;
2357
2358                 table->SamuLevel[count].Divider = (u8)dividers.post_divider;
2359
2360                 table->SamuLevel[count].Frequency = cpu_to_be32(table->SamuLevel[count].Frequency);
2361                 table->SamuLevel[count].MinVoltage = cpu_to_be16(table->SamuLevel[count].MinVoltage);
2362         }
2363
2364         return ret;
2365 }
2366
2367 static int ci_calculate_mclk_params(struct radeon_device *rdev,
2368                                     u32 memory_clock,
2369                                     SMU7_Discrete_MemoryLevel *mclk,
2370                                     bool strobe_mode,
2371                                     bool dll_state_on)
2372 {
2373         struct ci_power_info *pi = ci_get_pi(rdev);
2374         u32  dll_cntl = pi->clock_registers.dll_cntl;
2375         u32  mclk_pwrmgt_cntl = pi->clock_registers.mclk_pwrmgt_cntl;
2376         u32  mpll_ad_func_cntl = pi->clock_registers.mpll_ad_func_cntl;
2377         u32  mpll_dq_func_cntl = pi->clock_registers.mpll_dq_func_cntl;
2378         u32  mpll_func_cntl = pi->clock_registers.mpll_func_cntl;
2379         u32  mpll_func_cntl_1 = pi->clock_registers.mpll_func_cntl_1;
2380         u32  mpll_func_cntl_2 = pi->clock_registers.mpll_func_cntl_2;
2381         u32  mpll_ss1 = pi->clock_registers.mpll_ss1;
2382         u32  mpll_ss2 = pi->clock_registers.mpll_ss2;
2383         struct atom_mpll_param mpll_param;
2384         int ret;
2385
2386         ret = radeon_atom_get_memory_pll_dividers(rdev, memory_clock, strobe_mode, &mpll_param);
2387         if (ret)
2388                 return ret;
2389
2390         mpll_func_cntl &= ~BWCTRL_MASK;
2391         mpll_func_cntl |= BWCTRL(mpll_param.bwcntl);
2392
2393         mpll_func_cntl_1 &= ~(CLKF_MASK | CLKFRAC_MASK | VCO_MODE_MASK);
2394         mpll_func_cntl_1 |= CLKF(mpll_param.clkf) |
2395                 CLKFRAC(mpll_param.clkfrac) | VCO_MODE(mpll_param.vco_mode);
2396
2397         mpll_ad_func_cntl &= ~YCLK_POST_DIV_MASK;
2398         mpll_ad_func_cntl |= YCLK_POST_DIV(mpll_param.post_div);
2399
2400         if (pi->mem_gddr5) {
2401                 mpll_dq_func_cntl &= ~(YCLK_SEL_MASK | YCLK_POST_DIV_MASK);
2402                 mpll_dq_func_cntl |= YCLK_SEL(mpll_param.yclk_sel) |
2403                         YCLK_POST_DIV(mpll_param.post_div);
2404         }
2405
2406         if (pi->caps_mclk_ss_support) {
2407                 struct radeon_atom_ss ss;
2408                 u32 freq_nom;
2409                 u32 tmp;
2410                 u32 reference_clock = rdev->clock.mpll.reference_freq;
2411
2412                 if (mpll_param.qdr == 1)
2413                         freq_nom = memory_clock * 4 * (1 << mpll_param.post_div);
2414                 else
2415                         freq_nom = memory_clock * 2 * (1 << mpll_param.post_div);
2416
2417                 tmp = (freq_nom / reference_clock);
2418                 tmp = tmp * tmp;
2419                 if (radeon_atombios_get_asic_ss_info(rdev, &ss,
2420                                                      ASIC_INTERNAL_MEMORY_SS, freq_nom)) {
2421                         u32 clks = reference_clock * 5 / ss.rate;
2422                         u32 clkv = (u32)((((131 * ss.percentage * ss.rate) / 100) * tmp) / freq_nom);
2423
2424                         mpll_ss1 &= ~CLKV_MASK;
2425                         mpll_ss1 |= CLKV(clkv);
2426
2427                         mpll_ss2 &= ~CLKS_MASK;
2428                         mpll_ss2 |= CLKS(clks);
2429                 }
2430         }
2431
2432         mclk_pwrmgt_cntl &= ~DLL_SPEED_MASK;
2433         mclk_pwrmgt_cntl |= DLL_SPEED(mpll_param.dll_speed);
2434
2435         if (dll_state_on)
2436                 mclk_pwrmgt_cntl |= MRDCK0_PDNB | MRDCK1_PDNB;
2437         else
2438                 mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB);
2439
2440         mclk->MclkFrequency = memory_clock;
2441         mclk->MpllFuncCntl = mpll_func_cntl;
2442         mclk->MpllFuncCntl_1 = mpll_func_cntl_1;
2443         mclk->MpllFuncCntl_2 = mpll_func_cntl_2;
2444         mclk->MpllAdFuncCntl = mpll_ad_func_cntl;
2445         mclk->MpllDqFuncCntl = mpll_dq_func_cntl;
2446         mclk->MclkPwrmgtCntl = mclk_pwrmgt_cntl;
2447         mclk->DllCntl = dll_cntl;
2448         mclk->MpllSs1 = mpll_ss1;
2449         mclk->MpllSs2 = mpll_ss2;
2450
2451         return 0;
2452 }
2453
2454 static int ci_populate_single_memory_level(struct radeon_device *rdev,
2455                                            u32 memory_clock,
2456                                            SMU7_Discrete_MemoryLevel *memory_level)
2457 {
2458         struct ci_power_info *pi = ci_get_pi(rdev);
2459         int ret;
2460         bool dll_state_on;
2461
2462         if (rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk.entries) {
2463                 ret = ci_get_dependency_volt_by_clk(rdev,
2464                                                     &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
2465                                                     memory_clock, &memory_level->MinVddc);
2466                 if (ret)
2467                         return ret;
2468         }
2469
2470         if (rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk.entries) {
2471                 ret = ci_get_dependency_volt_by_clk(rdev,
2472                                                     &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
2473                                                     memory_clock, &memory_level->MinVddci);
2474                 if (ret)
2475                         return ret;
2476         }
2477
2478         if (rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.entries) {
2479                 ret = ci_get_dependency_volt_by_clk(rdev,
2480                                                     &rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk,
2481                                                     memory_clock, &memory_level->MinMvdd);
2482                 if (ret)
2483                         return ret;
2484         }
2485
2486         memory_level->MinVddcPhases = 1;
2487
2488         if (pi->vddc_phase_shed_control)
2489                 ci_populate_phase_value_based_on_mclk(rdev,
2490                                                       &rdev->pm.dpm.dyn_state.phase_shedding_limits_table,
2491                                                       memory_clock,
2492                                                       &memory_level->MinVddcPhases);
2493
2494         memory_level->EnabledForThrottle = 1;
2495         memory_level->UpH = 0;
2496         memory_level->DownH = 100;
2497         memory_level->VoltageDownH = 0;
2498         memory_level->ActivityLevel = (u16)pi->mclk_activity_target;
2499
2500         memory_level->StutterEnable = false;
2501         memory_level->StrobeEnable = false;
2502         memory_level->EdcReadEnable = false;
2503         memory_level->EdcWriteEnable = false;
2504         memory_level->RttEnable = false;
2505
2506         memory_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
2507
2508         if (pi->mclk_stutter_mode_threshold &&
2509             (memory_clock <= pi->mclk_stutter_mode_threshold) &&
2510             (pi->uvd_enabled == false) &&
2511             (RREG32(DPG_PIPE_STUTTER_CONTROL) & STUTTER_ENABLE) &&
2512             (rdev->pm.dpm.new_active_crtc_count <= 2))
2513                 memory_level->StutterEnable = true;
2514
2515         if (pi->mclk_strobe_mode_threshold &&
2516             (memory_clock <= pi->mclk_strobe_mode_threshold))
2517                 memory_level->StrobeEnable = 1;
2518
2519         if (pi->mem_gddr5) {
2520                 memory_level->StrobeRatio =
2521                         si_get_mclk_frequency_ratio(memory_clock, memory_level->StrobeEnable);
2522                 if (pi->mclk_edc_enable_threshold &&
2523                     (memory_clock > pi->mclk_edc_enable_threshold))
2524                         memory_level->EdcReadEnable = true;
2525
2526                 if (pi->mclk_edc_wr_enable_threshold &&
2527                     (memory_clock > pi->mclk_edc_wr_enable_threshold))
2528                         memory_level->EdcWriteEnable = true;
2529
2530                 if (memory_level->StrobeEnable) {
2531                         if (si_get_mclk_frequency_ratio(memory_clock, true) >=
2532                             ((RREG32(MC_SEQ_MISC7) >> 16) & 0xf))
2533                                 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
2534                         else
2535                                 dll_state_on = ((RREG32(MC_SEQ_MISC6) >> 1) & 0x1) ? true : false;
2536                 } else {
2537                         dll_state_on = pi->dll_default_on;
2538                 }
2539         } else {
2540                 memory_level->StrobeRatio = si_get_ddr3_mclk_frequency_ratio(memory_clock);
2541                 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
2542         }
2543
2544         ret = ci_calculate_mclk_params(rdev, memory_clock, memory_level, memory_level->StrobeEnable, dll_state_on);
2545         if (ret)
2546                 return ret;
2547
2548         memory_level->MinVddc = cpu_to_be32(memory_level->MinVddc * VOLTAGE_SCALE);
2549         memory_level->MinVddcPhases = cpu_to_be32(memory_level->MinVddcPhases);
2550         memory_level->MinVddci = cpu_to_be32(memory_level->MinVddci * VOLTAGE_SCALE);
2551         memory_level->MinMvdd = cpu_to_be32(memory_level->MinMvdd * VOLTAGE_SCALE);
2552
2553         memory_level->MclkFrequency = cpu_to_be32(memory_level->MclkFrequency);
2554         memory_level->ActivityLevel = cpu_to_be16(memory_level->ActivityLevel);
2555         memory_level->MpllFuncCntl = cpu_to_be32(memory_level->MpllFuncCntl);
2556         memory_level->MpllFuncCntl_1 = cpu_to_be32(memory_level->MpllFuncCntl_1);
2557         memory_level->MpllFuncCntl_2 = cpu_to_be32(memory_level->MpllFuncCntl_2);
2558         memory_level->MpllAdFuncCntl = cpu_to_be32(memory_level->MpllAdFuncCntl);
2559         memory_level->MpllDqFuncCntl = cpu_to_be32(memory_level->MpllDqFuncCntl);
2560         memory_level->MclkPwrmgtCntl = cpu_to_be32(memory_level->MclkPwrmgtCntl);
2561         memory_level->DllCntl = cpu_to_be32(memory_level->DllCntl);
2562         memory_level->MpllSs1 = cpu_to_be32(memory_level->MpllSs1);
2563         memory_level->MpllSs2 = cpu_to_be32(memory_level->MpllSs2);
2564
2565         return 0;
2566 }
2567
2568 static int ci_populate_smc_acpi_level(struct radeon_device *rdev,
2569                                       SMU7_Discrete_DpmTable *table)
2570 {
2571         struct ci_power_info *pi = ci_get_pi(rdev);
2572         struct atom_clock_dividers dividers;
2573         SMU7_Discrete_VoltageLevel voltage_level;
2574         u32 spll_func_cntl = pi->clock_registers.cg_spll_func_cntl;
2575         u32 spll_func_cntl_2 = pi->clock_registers.cg_spll_func_cntl_2;
2576         u32 dll_cntl = pi->clock_registers.dll_cntl;
2577         u32 mclk_pwrmgt_cntl = pi->clock_registers.mclk_pwrmgt_cntl;
2578         int ret;
2579
2580         table->ACPILevel.Flags &= ~PPSMC_SWSTATE_FLAG_DC;
2581
2582         if (pi->acpi_vddc)
2583                 table->ACPILevel.MinVddc = cpu_to_be32(pi->acpi_vddc * VOLTAGE_SCALE);
2584         else
2585                 table->ACPILevel.MinVddc = cpu_to_be32(pi->min_vddc_in_pp_table * VOLTAGE_SCALE);
2586
2587         table->ACPILevel.MinVddcPhases = pi->vddc_phase_shed_control ? 0 : 1;
2588
2589         table->ACPILevel.SclkFrequency = rdev->clock.spll.reference_freq;
2590
2591         ret = radeon_atom_get_clock_dividers(rdev,
2592                                              COMPUTE_GPUCLK_INPUT_FLAG_SCLK,
2593                                              table->ACPILevel.SclkFrequency, false, &dividers);
2594         if (ret)
2595                 return ret;
2596
2597         table->ACPILevel.SclkDid = (u8)dividers.post_divider;
2598         table->ACPILevel.DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
2599         table->ACPILevel.DeepSleepDivId = 0;
2600
2601         spll_func_cntl &= ~SPLL_PWRON;
2602         spll_func_cntl |= SPLL_RESET;
2603
2604         spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK;
2605         spll_func_cntl_2 |= SCLK_MUX_SEL(4);
2606
2607         table->ACPILevel.CgSpllFuncCntl = spll_func_cntl;
2608         table->ACPILevel.CgSpllFuncCntl2 = spll_func_cntl_2;
2609         table->ACPILevel.CgSpllFuncCntl3 = pi->clock_registers.cg_spll_func_cntl_3;
2610         table->ACPILevel.CgSpllFuncCntl4 = pi->clock_registers.cg_spll_func_cntl_4;
2611         table->ACPILevel.SpllSpreadSpectrum = pi->clock_registers.cg_spll_spread_spectrum;
2612         table->ACPILevel.SpllSpreadSpectrum2 = pi->clock_registers.cg_spll_spread_spectrum_2;
2613         table->ACPILevel.CcPwrDynRm = 0;
2614         table->ACPILevel.CcPwrDynRm1 = 0;
2615
2616         table->ACPILevel.Flags = cpu_to_be32(table->ACPILevel.Flags);
2617         table->ACPILevel.MinVddcPhases = cpu_to_be32(table->ACPILevel.MinVddcPhases);
2618         table->ACPILevel.SclkFrequency = cpu_to_be32(table->ACPILevel.SclkFrequency);
2619         table->ACPILevel.CgSpllFuncCntl = cpu_to_be32(table->ACPILevel.CgSpllFuncCntl);
2620         table->ACPILevel.CgSpllFuncCntl2 = cpu_to_be32(table->ACPILevel.CgSpllFuncCntl2);
2621         table->ACPILevel.CgSpllFuncCntl3 = cpu_to_be32(table->ACPILevel.CgSpllFuncCntl3);
2622         table->ACPILevel.CgSpllFuncCntl4 = cpu_to_be32(table->ACPILevel.CgSpllFuncCntl4);
2623         table->ACPILevel.SpllSpreadSpectrum = cpu_to_be32(table->ACPILevel.SpllSpreadSpectrum);
2624         table->ACPILevel.SpllSpreadSpectrum2 = cpu_to_be32(table->ACPILevel.SpllSpreadSpectrum2);
2625         table->ACPILevel.CcPwrDynRm = cpu_to_be32(table->ACPILevel.CcPwrDynRm);
2626         table->ACPILevel.CcPwrDynRm1 = cpu_to_be32(table->ACPILevel.CcPwrDynRm1);
2627
2628         table->MemoryACPILevel.MinVddc = table->ACPILevel.MinVddc;
2629         table->MemoryACPILevel.MinVddcPhases = table->ACPILevel.MinVddcPhases;
2630
2631         if (pi->vddci_control != CISLANDS_VOLTAGE_CONTROL_NONE) {
2632                 if (pi->acpi_vddci)
2633                         table->MemoryACPILevel.MinVddci =
2634                                 cpu_to_be32(pi->acpi_vddci * VOLTAGE_SCALE);
2635                 else
2636                         table->MemoryACPILevel.MinVddci =
2637                                 cpu_to_be32(pi->min_vddci_in_pp_table * VOLTAGE_SCALE);
2638         }
2639
2640         if (ci_populate_mvdd_value(rdev, 0, &voltage_level))
2641                 table->MemoryACPILevel.MinMvdd = 0;
2642         else
2643                 table->MemoryACPILevel.MinMvdd =
2644                         cpu_to_be32(voltage_level.Voltage * VOLTAGE_SCALE);
2645
2646         mclk_pwrmgt_cntl |= MRDCK0_RESET | MRDCK1_RESET;
2647         mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB);
2648
2649         dll_cntl &= ~(MRDCK0_BYPASS | MRDCK1_BYPASS);
2650
2651         table->MemoryACPILevel.DllCntl = cpu_to_be32(dll_cntl);
2652         table->MemoryACPILevel.MclkPwrmgtCntl = cpu_to_be32(mclk_pwrmgt_cntl);
2653         table->MemoryACPILevel.MpllAdFuncCntl =
2654                 cpu_to_be32(pi->clock_registers.mpll_ad_func_cntl);
2655         table->MemoryACPILevel.MpllDqFuncCntl =
2656                 cpu_to_be32(pi->clock_registers.mpll_dq_func_cntl);
2657         table->MemoryACPILevel.MpllFuncCntl =
2658                 cpu_to_be32(pi->clock_registers.mpll_func_cntl);
2659         table->MemoryACPILevel.MpllFuncCntl_1 =
2660                 cpu_to_be32(pi->clock_registers.mpll_func_cntl_1);
2661         table->MemoryACPILevel.MpllFuncCntl_2 =
2662                 cpu_to_be32(pi->clock_registers.mpll_func_cntl_2);
2663         table->MemoryACPILevel.MpllSs1 = cpu_to_be32(pi->clock_registers.mpll_ss1);
2664         table->MemoryACPILevel.MpllSs2 = cpu_to_be32(pi->clock_registers.mpll_ss2);
2665
2666         table->MemoryACPILevel.EnabledForThrottle = 0;
2667         table->MemoryACPILevel.EnabledForActivity = 0;
2668         table->MemoryACPILevel.UpH = 0;
2669         table->MemoryACPILevel.DownH = 100;
2670         table->MemoryACPILevel.VoltageDownH = 0;
2671         table->MemoryACPILevel.ActivityLevel =
2672                 cpu_to_be16((u16)pi->mclk_activity_target);
2673
2674         table->MemoryACPILevel.StutterEnable = false;
2675         table->MemoryACPILevel.StrobeEnable = false;
2676         table->MemoryACPILevel.EdcReadEnable = false;
2677         table->MemoryACPILevel.EdcWriteEnable = false;
2678         table->MemoryACPILevel.RttEnable = false;
2679
2680         return 0;
2681 }
2682
2683
2684 static int ci_enable_ulv(struct radeon_device *rdev, bool enable)
2685 {
2686         struct ci_power_info *pi = ci_get_pi(rdev);
2687         struct ci_ulv_parm *ulv = &pi->ulv;
2688
2689         if (ulv->supported) {
2690                 if (enable)
2691                         return (ci_send_msg_to_smc(rdev, PPSMC_MSG_EnableULV) == PPSMC_Result_OK) ?
2692                                 0 : -EINVAL;
2693                 else
2694                         return (ci_send_msg_to_smc(rdev, PPSMC_MSG_DisableULV) == PPSMC_Result_OK) ?
2695                                 0 : -EINVAL;
2696         }
2697
2698         return 0;
2699 }
2700
2701 static int ci_populate_ulv_level(struct radeon_device *rdev,
2702                                  SMU7_Discrete_Ulv *state)
2703 {
2704         struct ci_power_info *pi = ci_get_pi(rdev);
2705         u16 ulv_voltage = rdev->pm.dpm.backbias_response_time;
2706
2707         state->CcPwrDynRm = 0;
2708         state->CcPwrDynRm1 = 0;
2709
2710         if (ulv_voltage == 0) {
2711                 pi->ulv.supported = false;
2712                 return 0;
2713         }
2714
2715         if (pi->voltage_control != CISLANDS_VOLTAGE_CONTROL_BY_SVID2) {
2716                 if (ulv_voltage > rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v)
2717                         state->VddcOffset = 0;
2718                 else
2719                         state->VddcOffset =
2720                                 rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v - ulv_voltage;
2721         } else {
2722                 if (ulv_voltage > rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v)
2723                         state->VddcOffsetVid = 0;
2724                 else
2725                         state->VddcOffsetVid = (u8)
2726                                 ((rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v - ulv_voltage) *
2727                                  VOLTAGE_VID_OFFSET_SCALE2 / VOLTAGE_VID_OFFSET_SCALE1);
2728         }
2729         state->VddcPhase = pi->vddc_phase_shed_control ? 0 : 1;
2730
2731         state->CcPwrDynRm = cpu_to_be32(state->CcPwrDynRm);
2732         state->CcPwrDynRm1 = cpu_to_be32(state->CcPwrDynRm1);
2733         state->VddcOffset = cpu_to_be16(state->VddcOffset);
2734
2735         return 0;
2736 }
2737
2738 static int ci_calculate_sclk_params(struct radeon_device *rdev,
2739                                     u32 engine_clock,
2740                                     SMU7_Discrete_GraphicsLevel *sclk)
2741 {
2742         struct ci_power_info *pi = ci_get_pi(rdev);
2743         struct atom_clock_dividers dividers;
2744         u32 spll_func_cntl_3 = pi->clock_registers.cg_spll_func_cntl_3;
2745         u32 spll_func_cntl_4 = pi->clock_registers.cg_spll_func_cntl_4;
2746         u32 cg_spll_spread_spectrum = pi->clock_registers.cg_spll_spread_spectrum;
2747         u32 cg_spll_spread_spectrum_2 = pi->clock_registers.cg_spll_spread_spectrum_2;
2748         u32 reference_clock = rdev->clock.spll.reference_freq;
2749         u32 reference_divider;
2750         u32 fbdiv;
2751         int ret;
2752
2753         ret = radeon_atom_get_clock_dividers(rdev,
2754                                              COMPUTE_GPUCLK_INPUT_FLAG_SCLK,
2755                                              engine_clock, false, &dividers);
2756         if (ret)
2757                 return ret;
2758
2759         reference_divider = 1 + dividers.ref_div;
2760         fbdiv = dividers.fb_div & 0x3FFFFFF;
2761
2762         spll_func_cntl_3 &= ~SPLL_FB_DIV_MASK;
2763         spll_func_cntl_3 |= SPLL_FB_DIV(fbdiv);
2764         spll_func_cntl_3 |= SPLL_DITHEN;
2765
2766         if (pi->caps_sclk_ss_support) {
2767                 struct radeon_atom_ss ss;
2768                 u32 vco_freq = engine_clock * dividers.post_div;
2769
2770                 if (radeon_atombios_get_asic_ss_info(rdev, &ss,
2771                                                      ASIC_INTERNAL_ENGINE_SS, vco_freq)) {
2772                         u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate);
2773                         u32 clk_v = 4 * ss.percentage * fbdiv / (clk_s * 10000);
2774
2775                         cg_spll_spread_spectrum &= ~CLK_S_MASK;
2776                         cg_spll_spread_spectrum |= CLK_S(clk_s);
2777                         cg_spll_spread_spectrum |= SSEN;
2778
2779                         cg_spll_spread_spectrum_2 &= ~CLK_V_MASK;
2780                         cg_spll_spread_spectrum_2 |= CLK_V(clk_v);
2781                 }
2782         }
2783
2784         sclk->SclkFrequency = engine_clock;
2785         sclk->CgSpllFuncCntl3 = spll_func_cntl_3;
2786         sclk->CgSpllFuncCntl4 = spll_func_cntl_4;
2787         sclk->SpllSpreadSpectrum = cg_spll_spread_spectrum;
2788         sclk->SpllSpreadSpectrum2  = cg_spll_spread_spectrum_2;
2789         sclk->SclkDid = (u8)dividers.post_divider;
2790
2791         return 0;
2792 }
2793
2794 static int ci_populate_single_graphic_level(struct radeon_device *rdev,
2795                                             u32 engine_clock,
2796                                             u16 sclk_activity_level_t,
2797                                             SMU7_Discrete_GraphicsLevel *graphic_level)
2798 {
2799         struct ci_power_info *pi = ci_get_pi(rdev);
2800         int ret;
2801
2802         ret = ci_calculate_sclk_params(rdev, engine_clock, graphic_level);
2803         if (ret)
2804                 return ret;
2805
2806         ret = ci_get_dependency_volt_by_clk(rdev,
2807                                             &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk,
2808                                             engine_clock, &graphic_level->MinVddc);
2809         if (ret)
2810                 return ret;
2811
2812         graphic_level->SclkFrequency = engine_clock;
2813
2814         graphic_level->Flags =  0;
2815         graphic_level->MinVddcPhases = 1;
2816
2817         if (pi->vddc_phase_shed_control)
2818                 ci_populate_phase_value_based_on_sclk(rdev,
2819                                                       &rdev->pm.dpm.dyn_state.phase_shedding_limits_table,
2820                                                       engine_clock,
2821                                                       &graphic_level->MinVddcPhases);
2822
2823         graphic_level->ActivityLevel = sclk_activity_level_t;
2824
2825         graphic_level->CcPwrDynRm = 0;
2826         graphic_level->CcPwrDynRm1 = 0;
2827         graphic_level->EnabledForThrottle = 1;
2828         graphic_level->UpH = 0;
2829         graphic_level->DownH = 0;
2830         graphic_level->VoltageDownH = 0;
2831         graphic_level->PowerThrottle = 0;
2832
2833         if (pi->caps_sclk_ds)
2834                 graphic_level->DeepSleepDivId = ci_get_sleep_divider_id_from_clock(rdev,
2835                                                                                    engine_clock,
2836                                                                                    CISLAND_MINIMUM_ENGINE_CLOCK);
2837
2838         graphic_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
2839
2840         graphic_level->Flags = cpu_to_be32(graphic_level->Flags);
2841         graphic_level->MinVddc = cpu_to_be32(graphic_level->MinVddc * VOLTAGE_SCALE);
2842         graphic_level->MinVddcPhases = cpu_to_be32(graphic_level->MinVddcPhases);
2843         graphic_level->SclkFrequency = cpu_to_be32(graphic_level->SclkFrequency);
2844         graphic_level->ActivityLevel = cpu_to_be16(graphic_level->ActivityLevel);
2845         graphic_level->CgSpllFuncCntl3 = cpu_to_be32(graphic_level->CgSpllFuncCntl3);
2846         graphic_level->CgSpllFuncCntl4 = cpu_to_be32(graphic_level->CgSpllFuncCntl4);
2847         graphic_level->SpllSpreadSpectrum = cpu_to_be32(graphic_level->SpllSpreadSpectrum);
2848         graphic_level->SpllSpreadSpectrum2 = cpu_to_be32(graphic_level->SpllSpreadSpectrum2);
2849         graphic_level->CcPwrDynRm = cpu_to_be32(graphic_level->CcPwrDynRm);
2850         graphic_level->CcPwrDynRm1 = cpu_to_be32(graphic_level->CcPwrDynRm1);
2851
2852         return 0;
2853 }
2854
2855 static int ci_populate_all_graphic_levels(struct radeon_device *rdev)
2856 {
2857         struct ci_power_info *pi = ci_get_pi(rdev);
2858         struct ci_dpm_table *dpm_table = &pi->dpm_table;
2859         u32 level_array_address = pi->dpm_table_start +
2860                 offsetof(SMU7_Discrete_DpmTable, GraphicsLevel);
2861         u32 level_array_size = sizeof(SMU7_Discrete_GraphicsLevel) *
2862                 SMU7_MAX_LEVELS_GRAPHICS;
2863         SMU7_Discrete_GraphicsLevel *levels = pi->smc_state_table.GraphicsLevel;
2864         u32 i, ret;
2865
2866         memset(levels, 0, level_array_size);
2867
2868         for (i = 0; i < dpm_table->sclk_table.count; i++) {
2869                 ret = ci_populate_single_graphic_level(rdev,
2870                                                        dpm_table->sclk_table.dpm_levels[i].value,
2871                                                        (u16)pi->activity_target[i],
2872                                                        &pi->smc_state_table.GraphicsLevel[i]);
2873                 if (ret)
2874                         return ret;
2875                 if (i > 1)
2876                         pi->smc_state_table.GraphicsLevel[i].DeepSleepDivId = 0;
2877                 if (i == (dpm_table->sclk_table.count - 1))
2878                         pi->smc_state_table.GraphicsLevel[i].DisplayWatermark =
2879                                 PPSMC_DISPLAY_WATERMARK_HIGH;
2880         }
2881         pi->smc_state_table.GraphicsLevel[0].EnabledForActivity = 1;
2882
2883         pi->smc_state_table.GraphicsDpmLevelCount = (u8)dpm_table->sclk_table.count;
2884         pi->dpm_level_enable_mask.sclk_dpm_enable_mask =
2885                 ci_get_dpm_level_enable_mask_value(&dpm_table->sclk_table);
2886
2887         ret = ci_copy_bytes_to_smc(rdev, level_array_address,
2888                                    (u8 *)levels, level_array_size,
2889                                    pi->sram_end);
2890         if (ret)
2891                 return ret;
2892
2893         return 0;
2894 }
2895
2896 static int ci_populate_ulv_state(struct radeon_device *rdev,
2897                                  SMU7_Discrete_Ulv *ulv_level)
2898 {
2899         return ci_populate_ulv_level(rdev, ulv_level);
2900 }
2901
2902 static int ci_populate_all_memory_levels(struct radeon_device *rdev)
2903 {
2904         struct ci_power_info *pi = ci_get_pi(rdev);
2905         struct ci_dpm_table *dpm_table = &pi->dpm_table;
2906         u32 level_array_address = pi->dpm_table_start +
2907                 offsetof(SMU7_Discrete_DpmTable, MemoryLevel);
2908         u32 level_array_size = sizeof(SMU7_Discrete_MemoryLevel) *
2909                 SMU7_MAX_LEVELS_MEMORY;
2910         SMU7_Discrete_MemoryLevel *levels = pi->smc_state_table.MemoryLevel;
2911         u32 i, ret;
2912
2913         memset(levels, 0, level_array_size);
2914
2915         for (i = 0; i < dpm_table->mclk_table.count; i++) {
2916                 if (dpm_table->mclk_table.dpm_levels[i].value == 0)
2917                         return -EINVAL;
2918                 ret = ci_populate_single_memory_level(rdev,
2919                                                       dpm_table->mclk_table.dpm_levels[i].value,
2920                                                       &pi->smc_state_table.MemoryLevel[i]);
2921                 if (ret)
2922                         return ret;
2923         }
2924
2925         pi->smc_state_table.MemoryLevel[0].EnabledForActivity = 1;
2926
2927         if ((dpm_table->mclk_table.count >= 2) &&
2928             ((rdev->pdev->device == 0x67B0) || (rdev->pdev->device == 0x67B1))) {
2929                 pi->smc_state_table.MemoryLevel[1].MinVddc =
2930                         pi->smc_state_table.MemoryLevel[0].MinVddc;
2931                 pi->smc_state_table.MemoryLevel[1].MinVddcPhases =
2932                         pi->smc_state_table.MemoryLevel[0].MinVddcPhases;
2933         }
2934
2935         pi->smc_state_table.MemoryLevel[0].ActivityLevel = cpu_to_be16(0x1F);
2936
2937         pi->smc_state_table.MemoryDpmLevelCount = (u8)dpm_table->mclk_table.count;
2938         pi->dpm_level_enable_mask.mclk_dpm_enable_mask =
2939                 ci_get_dpm_level_enable_mask_value(&dpm_table->mclk_table);
2940
2941         pi->smc_state_table.MemoryLevel[dpm_table->mclk_table.count - 1].DisplayWatermark =
2942                 PPSMC_DISPLAY_WATERMARK_HIGH;
2943
2944         ret = ci_copy_bytes_to_smc(rdev, level_array_address,
2945                                    (u8 *)levels, level_array_size,
2946                                    pi->sram_end);
2947         if (ret)
2948                 return ret;
2949
2950         return 0;
2951 }
2952
2953 static void ci_reset_single_dpm_table(struct radeon_device *rdev,
2954                                       struct ci_single_dpm_table* dpm_table,
2955                                       u32 count)
2956 {
2957         u32 i;
2958
2959         dpm_table->count = count;
2960         for (i = 0; i < MAX_REGULAR_DPM_NUMBER; i++)
2961                 dpm_table->dpm_levels[i].enabled = false;
2962 }
2963
2964 static void ci_setup_pcie_table_entry(struct ci_single_dpm_table* dpm_table,
2965                                       u32 index, u32 pcie_gen, u32 pcie_lanes)
2966 {
2967         dpm_table->dpm_levels[index].value = pcie_gen;
2968         dpm_table->dpm_levels[index].param1 = pcie_lanes;
2969         dpm_table->dpm_levels[index].enabled = true;
2970 }
2971
2972 static int ci_setup_default_pcie_tables(struct radeon_device *rdev)
2973 {
2974         struct ci_power_info *pi = ci_get_pi(rdev);
2975
2976         if (!pi->use_pcie_performance_levels && !pi->use_pcie_powersaving_levels)
2977                 return -EINVAL;
2978
2979         if (pi->use_pcie_performance_levels && !pi->use_pcie_powersaving_levels) {
2980                 pi->pcie_gen_powersaving = pi->pcie_gen_performance;
2981                 pi->pcie_lane_powersaving = pi->pcie_lane_performance;
2982         } else if (!pi->use_pcie_performance_levels && pi->use_pcie_powersaving_levels) {
2983                 pi->pcie_gen_performance = pi->pcie_gen_powersaving;
2984                 pi->pcie_lane_performance = pi->pcie_lane_powersaving;
2985         }
2986
2987         ci_reset_single_dpm_table(rdev,
2988                                   &pi->dpm_table.pcie_speed_table,
2989                                   SMU7_MAX_LEVELS_LINK);
2990
2991         if (rdev->family == CHIP_BONAIRE)
2992                 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 0,
2993                                           pi->pcie_gen_powersaving.min,
2994                                           pi->pcie_lane_powersaving.max);
2995         else
2996                 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 0,
2997                                           pi->pcie_gen_powersaving.min,
2998                                           pi->pcie_lane_powersaving.min);
2999         ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 1,
3000                                   pi->pcie_gen_performance.min,
3001                                   pi->pcie_lane_performance.min);
3002         ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 2,
3003                                   pi->pcie_gen_powersaving.min,
3004                                   pi->pcie_lane_powersaving.max);
3005         ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 3,
3006                                   pi->pcie_gen_performance.min,
3007                                   pi->pcie_lane_performance.max);
3008         ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 4,
3009                                   pi->pcie_gen_powersaving.max,
3010                                   pi->pcie_lane_powersaving.max);
3011         ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 5,
3012                                   pi->pcie_gen_performance.max,
3013                                   pi->pcie_lane_performance.max);
3014
3015         pi->dpm_table.pcie_speed_table.count = 6;
3016
3017         return 0;
3018 }
3019
3020 static int ci_setup_default_dpm_tables(struct radeon_device *rdev)
3021 {
3022         struct ci_power_info *pi = ci_get_pi(rdev);
3023         struct radeon_clock_voltage_dependency_table *allowed_sclk_vddc_table =
3024                 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
3025         struct radeon_clock_voltage_dependency_table *allowed_mclk_table =
3026                 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk;
3027         struct radeon_cac_leakage_table *std_voltage_table =
3028                 &rdev->pm.dpm.dyn_state.cac_leakage_table;
3029         u32 i;
3030
3031         if (allowed_sclk_vddc_table == NULL)
3032                 return -EINVAL;
3033         if (allowed_sclk_vddc_table->count < 1)
3034                 return -EINVAL;
3035         if (allowed_mclk_table == NULL)
3036                 return -EINVAL;
3037         if (allowed_mclk_table->count < 1)
3038                 return -EINVAL;
3039
3040         memset(&pi->dpm_table, 0, sizeof(struct ci_dpm_table));
3041
3042         ci_reset_single_dpm_table(rdev,
3043                                   &pi->dpm_table.sclk_table,
3044                                   SMU7_MAX_LEVELS_GRAPHICS);
3045         ci_reset_single_dpm_table(rdev,
3046                                   &pi->dpm_table.mclk_table,
3047                                   SMU7_MAX_LEVELS_MEMORY);
3048         ci_reset_single_dpm_table(rdev,
3049                                   &pi->dpm_table.vddc_table,
3050                                   SMU7_MAX_LEVELS_VDDC);
3051         ci_reset_single_dpm_table(rdev,
3052                                   &pi->dpm_table.vddci_table,
3053                                   SMU7_MAX_LEVELS_VDDCI);
3054         ci_reset_single_dpm_table(rdev,
3055                                   &pi->dpm_table.mvdd_table,
3056                                   SMU7_MAX_LEVELS_MVDD);
3057
3058         pi->dpm_table.sclk_table.count = 0;
3059         for (i = 0; i < allowed_sclk_vddc_table->count; i++) {
3060                 if ((i == 0) ||
3061                     (pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count-1].value !=
3062                      allowed_sclk_vddc_table->entries[i].clk)) {
3063                         pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count].value =
3064                                 allowed_sclk_vddc_table->entries[i].clk;
3065                         pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count].enabled =
3066                                 (i == 0) ? true : false;
3067                         pi->dpm_table.sclk_table.count++;
3068                 }
3069         }
3070
3071         pi->dpm_table.mclk_table.count = 0;
3072         for (i = 0; i < allowed_mclk_table->count; i++) {
3073                 if ((i == 0) ||
3074                     (pi->dpm_table.mclk_table.dpm_levels[pi->dpm_table.mclk_table.count-1].value !=
3075                      allowed_mclk_table->entries[i].clk)) {
3076                         pi->dpm_table.mclk_table.dpm_levels[pi->dpm_table.mclk_table.count].value =
3077                                 allowed_mclk_table->entries[i].clk;
3078                         pi->dpm_table.mclk_table.dpm_levels[pi->dpm_table.mclk_table.count].enabled =
3079                                 (i == 0) ? true : false;
3080                         pi->dpm_table.mclk_table.count++;
3081                 }
3082         }
3083
3084         for (i = 0; i < allowed_sclk_vddc_table->count; i++) {
3085                 pi->dpm_table.vddc_table.dpm_levels[i].value =
3086                         allowed_sclk_vddc_table->entries[i].v;
3087                 pi->dpm_table.vddc_table.dpm_levels[i].param1 =
3088                         std_voltage_table->entries[i].leakage;
3089                 pi->dpm_table.vddc_table.dpm_levels[i].enabled = true;
3090         }
3091         pi->dpm_table.vddc_table.count = allowed_sclk_vddc_table->count;
3092
3093         allowed_mclk_table = &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk;
3094         if (allowed_mclk_table) {
3095                 for (i = 0; i < allowed_mclk_table->count; i++) {
3096                         pi->dpm_table.vddci_table.dpm_levels[i].value =
3097                                 allowed_mclk_table->entries[i].v;
3098                         pi->dpm_table.vddci_table.dpm_levels[i].enabled = true;
3099                 }
3100                 pi->dpm_table.vddci_table.count = allowed_mclk_table->count;
3101         }
3102
3103         allowed_mclk_table = &rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk;
3104         if (allowed_mclk_table) {
3105                 for (i = 0; i < allowed_mclk_table->count; i++) {
3106                         pi->dpm_table.mvdd_table.dpm_levels[i].value =
3107                                 allowed_mclk_table->entries[i].v;
3108                         pi->dpm_table.mvdd_table.dpm_levels[i].enabled = true;
3109                 }
3110                 pi->dpm_table.mvdd_table.count = allowed_mclk_table->count;
3111         }
3112
3113         ci_setup_default_pcie_tables(rdev);
3114
3115         return 0;
3116 }
3117
3118 static int ci_find_boot_level(struct ci_single_dpm_table *table,
3119                               u32 value, u32 *boot_level)
3120 {
3121         u32 i;
3122         int ret = -EINVAL;
3123
3124         for(i = 0; i < table->count; i++) {
3125                 if (value == table->dpm_levels[i].value) {
3126                         *boot_level = i;
3127                         ret = 0;
3128                 }
3129         }
3130
3131         return ret;
3132 }
3133
3134 static int ci_init_smc_table(struct radeon_device *rdev)
3135 {
3136         struct ci_power_info *pi = ci_get_pi(rdev);
3137         struct ci_ulv_parm *ulv = &pi->ulv;
3138         struct radeon_ps *radeon_boot_state = rdev->pm.dpm.boot_ps;
3139         SMU7_Discrete_DpmTable *table = &pi->smc_state_table;
3140         int ret;
3141
3142         ret = ci_setup_default_dpm_tables(rdev);
3143         if (ret)
3144                 return ret;
3145
3146         if (pi->voltage_control != CISLANDS_VOLTAGE_CONTROL_NONE)
3147                 ci_populate_smc_voltage_tables(rdev, table);
3148
3149         ci_init_fps_limits(rdev);
3150
3151         if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC)
3152                 table->SystemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC;
3153
3154         if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC)
3155                 table->SystemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;
3156
3157         if (pi->mem_gddr5)
3158                 table->SystemFlags |= PPSMC_SYSTEMFLAG_GDDR5;
3159
3160         if (ulv->supported) {
3161                 ret = ci_populate_ulv_state(rdev, &pi->smc_state_table.Ulv);
3162                 if (ret)
3163                         return ret;
3164                 WREG32_SMC(CG_ULV_PARAMETER, ulv->cg_ulv_parameter);
3165         }
3166
3167         ret = ci_populate_all_graphic_levels(rdev);
3168         if (ret)
3169                 return ret;
3170
3171         ret = ci_populate_all_memory_levels(rdev);
3172         if (ret)
3173                 return ret;
3174
3175         ci_populate_smc_link_level(rdev, table);
3176
3177         ret = ci_populate_smc_acpi_level(rdev, table);
3178         if (ret)
3179                 return ret;
3180
3181         ret = ci_populate_smc_vce_level(rdev, table);
3182         if (ret)
3183                 return ret;
3184
3185         ret = ci_populate_smc_acp_level(rdev, table);
3186         if (ret)
3187                 return ret;
3188
3189         ret = ci_populate_smc_samu_level(rdev, table);
3190         if (ret)
3191                 return ret;
3192
3193         ret = ci_do_program_memory_timing_parameters(rdev);
3194         if (ret)
3195                 return ret;
3196
3197         ret = ci_populate_smc_uvd_level(rdev, table);
3198         if (ret)
3199                 return ret;
3200
3201         table->UvdBootLevel  = 0;
3202         table->VceBootLevel  = 0;
3203         table->AcpBootLevel  = 0;
3204         table->SamuBootLevel  = 0;
3205         table->GraphicsBootLevel  = 0;
3206         table->MemoryBootLevel  = 0;
3207
3208         ret = ci_find_boot_level(&pi->dpm_table.sclk_table,
3209                                  pi->vbios_boot_state.sclk_bootup_value,
3210                                  (u32 *)&pi->smc_state_table.GraphicsBootLevel);
3211
3212         ret = ci_find_boot_level(&pi->dpm_table.mclk_table,
3213                                  pi->vbios_boot_state.mclk_bootup_value,
3214                                  (u32 *)&pi->smc_state_table.MemoryBootLevel);
3215
3216         table->BootVddc = pi->vbios_boot_state.vddc_bootup_value;
3217         table->BootVddci = pi->vbios_boot_state.vddci_bootup_value;
3218         table->BootMVdd = pi->vbios_boot_state.mvdd_bootup_value;
3219
3220         ci_populate_smc_initial_state(rdev, radeon_boot_state);
3221
3222         ret = ci_populate_bapm_parameters_in_dpm_table(rdev);
3223         if (ret)
3224                 return ret;
3225
3226         table->UVDInterval = 1;
3227         table->VCEInterval = 1;
3228         table->ACPInterval = 1;
3229         table->SAMUInterval = 1;
3230         table->GraphicsVoltageChangeEnable = 1;
3231         table->GraphicsThermThrottleEnable = 1;
3232         table->GraphicsInterval = 1;
3233         table->VoltageInterval = 1;
3234         table->ThermalInterval = 1;
3235         table->TemperatureLimitHigh = (u16)((pi->thermal_temp_setting.temperature_high *
3236                                              CISLANDS_Q88_FORMAT_CONVERSION_UNIT) / 1000);
3237         table->TemperatureLimitLow = (u16)((pi->thermal_temp_setting.temperature_low *
3238                                             CISLANDS_Q88_FORMAT_CONVERSION_UNIT) / 1000);
3239         table->MemoryVoltageChangeEnable = 1;
3240         table->MemoryInterval = 1;
3241         table->VoltageResponseTime = 0;
3242         table->VddcVddciDelta = 4000;
3243         table->PhaseResponseTime = 0;
3244         table->MemoryThermThrottleEnable = 1;
3245         table->PCIeBootLinkLevel = pi->dpm_table.pcie_speed_table.count - 1;
3246         table->PCIeGenInterval = 1;
3247         if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2)
3248                 table->SVI2Enable  = 1;
3249         else
3250                 table->SVI2Enable  = 0;
3251
3252         table->ThermGpio = 17;
3253         table->SclkStepSize = 0x4000;
3254
3255         table->SystemFlags = cpu_to_be32(table->SystemFlags);
3256         table->SmioMaskVddcVid = cpu_to_be32(table->SmioMaskVddcVid);
3257         table->SmioMaskVddcPhase = cpu_to_be32(table->SmioMaskVddcPhase);
3258         table->SmioMaskVddciVid = cpu_to_be32(table->SmioMaskVddciVid);
3259         table->SmioMaskMvddVid = cpu_to_be32(table->SmioMaskMvddVid);
3260         table->SclkStepSize = cpu_to_be32(table->SclkStepSize);
3261         table->TemperatureLimitHigh = cpu_to_be16(table->TemperatureLimitHigh);
3262         table->TemperatureLimitLow = cpu_to_be16(table->TemperatureLimitLow);
3263         table->VddcVddciDelta = cpu_to_be16(table->VddcVddciDelta);
3264         table->VoltageResponseTime = cpu_to_be16(table->VoltageResponseTime);
3265         table->PhaseResponseTime = cpu_to_be16(table->PhaseResponseTime);
3266         table->BootVddc = cpu_to_be16(table->BootVddc * VOLTAGE_SCALE);
3267         table->BootVddci = cpu_to_be16(table->BootVddci * VOLTAGE_SCALE);
3268         table->BootMVdd = cpu_to_be16(table->BootMVdd * VOLTAGE_SCALE);
3269
3270         ret = ci_copy_bytes_to_smc(rdev,
3271                                    pi->dpm_table_start +
3272                                    offsetof(SMU7_Discrete_DpmTable, SystemFlags),
3273                                    (u8 *)&table->SystemFlags,
3274                                    sizeof(SMU7_Discrete_DpmTable) - 3 * sizeof(SMU7_PIDController),
3275                                    pi->sram_end);
3276         if (ret)
3277                 return ret;
3278
3279         return 0;
3280 }
3281
3282 static void ci_trim_single_dpm_states(struct radeon_device *rdev,
3283                                       struct ci_single_dpm_table *dpm_table,
3284                                       u32 low_limit, u32 high_limit)
3285 {
3286         u32 i;
3287
3288         for (i = 0; i < dpm_table->count; i++) {
3289                 if ((dpm_table->dpm_levels[i].value < low_limit) ||
3290                     (dpm_table->dpm_levels[i].value > high_limit))
3291                         dpm_table->dpm_levels[i].enabled = false;
3292                 else
3293                         dpm_table->dpm_levels[i].enabled = true;
3294         }
3295 }
3296
3297 static void ci_trim_pcie_dpm_states(struct radeon_device *rdev,
3298                                     u32 speed_low, u32 lanes_low,
3299                                     u32 speed_high, u32 lanes_high)
3300 {
3301         struct ci_power_info *pi = ci_get_pi(rdev);
3302         struct ci_single_dpm_table *pcie_table = &pi->dpm_table.pcie_speed_table;
3303         u32 i, j;
3304
3305         for (i = 0; i < pcie_table->count; i++) {
3306                 if ((pcie_table->dpm_levels[i].value < speed_low) ||
3307                     (pcie_table->dpm_levels[i].param1 < lanes_low) ||
3308                     (pcie_table->dpm_levels[i].value > speed_high) ||
3309                     (pcie_table->dpm_levels[i].param1 > lanes_high))
3310                         pcie_table->dpm_levels[i].enabled = false;
3311                 else
3312                         pcie_table->dpm_levels[i].enabled = true;
3313         }
3314
3315         for (i = 0; i < pcie_table->count; i++) {
3316                 if (pcie_table->dpm_levels[i].enabled) {
3317                         for (j = i + 1; j < pcie_table->count; j++) {
3318                                 if (pcie_table->dpm_levels[j].enabled) {
3319                                         if ((pcie_table->dpm_levels[i].value == pcie_table->dpm_levels[j].value) &&
3320                                             (pcie_table->dpm_levels[i].param1 == pcie_table->dpm_levels[j].param1))
3321                                                 pcie_table->dpm_levels[j].enabled = false;
3322                                 }
3323                         }
3324                 }
3325         }
3326 }
3327
3328 static int ci_trim_dpm_states(struct radeon_device *rdev,
3329                               struct radeon_ps *radeon_state)
3330 {
3331         struct ci_ps *state = ci_get_ps(radeon_state);
3332         struct ci_power_info *pi = ci_get_pi(rdev);
3333         u32 high_limit_count;
3334
3335         if (state->performance_level_count < 1)
3336                 return -EINVAL;
3337
3338         if (state->performance_level_count == 1)
3339                 high_limit_count = 0;
3340         else
3341                 high_limit_count = 1;
3342
3343         ci_trim_single_dpm_states(rdev,
3344                                   &pi->dpm_table.sclk_table,
3345                                   state->performance_levels[0].sclk,
3346                                   state->performance_levels[high_limit_count].sclk);
3347
3348         ci_trim_single_dpm_states(rdev,
3349                                   &pi->dpm_table.mclk_table,
3350                                   state->performance_levels[0].mclk,
3351                                   state->performance_levels[high_limit_count].mclk);
3352
3353         ci_trim_pcie_dpm_states(rdev,
3354                                 state->performance_levels[0].pcie_gen,
3355                                 state->performance_levels[0].pcie_lane,
3356                                 state->performance_levels[high_limit_count].pcie_gen,
3357                                 state->performance_levels[high_limit_count].pcie_lane);
3358
3359         return 0;
3360 }
3361
3362 static int ci_apply_disp_minimum_voltage_request(struct radeon_device *rdev)
3363 {
3364         struct radeon_clock_voltage_dependency_table *disp_voltage_table =
3365                 &rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk;
3366         struct radeon_clock_voltage_dependency_table *vddc_table =
3367                 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
3368         u32 requested_voltage = 0;
3369         u32 i;
3370
3371         if (disp_voltage_table == NULL)
3372                 return -EINVAL;
3373         if (!disp_voltage_table->count)
3374                 return -EINVAL;
3375
3376         for (i = 0; i < disp_voltage_table->count; i++) {
3377                 if (rdev->clock.current_dispclk == disp_voltage_table->entries[i].clk)
3378                         requested_voltage = disp_voltage_table->entries[i].v;
3379         }
3380
3381         for (i = 0; i < vddc_table->count; i++) {
3382                 if (requested_voltage <= vddc_table->entries[i].v) {
3383                         requested_voltage = vddc_table->entries[i].v;
3384                         return (ci_send_msg_to_smc_with_parameter(rdev,
3385                                                                   PPSMC_MSG_VddC_Request,
3386                                                                   requested_voltage * VOLTAGE_SCALE) == PPSMC_Result_OK) ?
3387                                 0 : -EINVAL;
3388                 }
3389         }
3390
3391         return -EINVAL;
3392 }
3393
3394 static int ci_upload_dpm_level_enable_mask(struct radeon_device *rdev)
3395 {
3396         struct ci_power_info *pi = ci_get_pi(rdev);
3397         PPSMC_Result result;
3398
3399         if (!pi->sclk_dpm_key_disabled) {
3400                 if (pi->dpm_level_enable_mask.sclk_dpm_enable_mask) {
3401                         result = ci_send_msg_to_smc_with_parameter(rdev,
3402                                                                    PPSMC_MSG_SCLKDPM_SetEnabledMask,
3403                                                                    pi->dpm_level_enable_mask.sclk_dpm_enable_mask);
3404                         if (result != PPSMC_Result_OK)
3405                                 return -EINVAL;
3406                 }
3407         }
3408
3409         if (!pi->mclk_dpm_key_disabled) {
3410                 if (pi->dpm_level_enable_mask.mclk_dpm_enable_mask) {
3411                         result = ci_send_msg_to_smc_with_parameter(rdev,
3412                                                                    PPSMC_MSG_MCLKDPM_SetEnabledMask,
3413                                                                    pi->dpm_level_enable_mask.mclk_dpm_enable_mask);
3414                         if (result != PPSMC_Result_OK)
3415                                 return -EINVAL;
3416                 }
3417         }
3418
3419         if (!pi->pcie_dpm_key_disabled) {
3420                 if (pi->dpm_level_enable_mask.pcie_dpm_enable_mask) {
3421                         result = ci_send_msg_to_smc_with_parameter(rdev,
3422                                                                    PPSMC_MSG_PCIeDPM_SetEnabledMask,
3423                                                                    pi->dpm_level_enable_mask.pcie_dpm_enable_mask);
3424                         if (result != PPSMC_Result_OK)
3425                                 return -EINVAL;
3426                 }
3427         }
3428
3429         ci_apply_disp_minimum_voltage_request(rdev);
3430
3431         return 0;
3432 }
3433
3434 static void ci_find_dpm_states_clocks_in_dpm_table(struct radeon_device *rdev,
3435                                                    struct radeon_ps *radeon_state)
3436 {
3437         struct ci_power_info *pi = ci_get_pi(rdev);
3438         struct ci_ps *state = ci_get_ps(radeon_state);
3439         struct ci_single_dpm_table *sclk_table = &pi->dpm_table.sclk_table;
3440         u32 sclk = state->performance_levels[state->performance_level_count-1].sclk;
3441         struct ci_single_dpm_table *mclk_table = &pi->dpm_table.mclk_table;
3442         u32 mclk = state->performance_levels[state->performance_level_count-1].mclk;
3443         u32 i;
3444
3445         pi->need_update_smu7_dpm_table = 0;
3446
3447         for (i = 0; i < sclk_table->count; i++) {
3448                 if (sclk == sclk_table->dpm_levels[i].value)
3449                         break;
3450         }
3451
3452         if (i >= sclk_table->count) {
3453                 pi->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_SCLK;
3454         } else {
3455                 /* XXX check display min clock requirements */
3456                 if (0 != CISLAND_MINIMUM_ENGINE_CLOCK)
3457                         pi->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_SCLK;
3458         }
3459
3460         for (i = 0; i < mclk_table->count; i++) {
3461                 if (mclk == mclk_table->dpm_levels[i].value)
3462                         break;
3463         }
3464
3465         if (i >= mclk_table->count)
3466                 pi->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_MCLK;
3467
3468         if (rdev->pm.dpm.current_active_crtc_count !=
3469             rdev->pm.dpm.new_active_crtc_count)
3470                 pi->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_MCLK;
3471 }
3472
3473 static int ci_populate_and_upload_sclk_mclk_dpm_levels(struct radeon_device *rdev,
3474                                                        struct radeon_ps *radeon_state)
3475 {
3476         struct ci_power_info *pi = ci_get_pi(rdev);
3477         struct ci_ps *state = ci_get_ps(radeon_state);
3478         u32 sclk = state->performance_levels[state->performance_level_count-1].sclk;
3479         u32 mclk = state->performance_levels[state->performance_level_count-1].mclk;
3480         struct ci_dpm_table *dpm_table = &pi->dpm_table;
3481         int ret;
3482
3483         if (!pi->need_update_smu7_dpm_table)
3484                 return 0;
3485
3486         if (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_SCLK)
3487                 dpm_table->sclk_table.dpm_levels[dpm_table->sclk_table.count-1].value = sclk;
3488
3489         if (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)
3490                 dpm_table->mclk_table.dpm_levels[dpm_table->mclk_table.count-1].value = mclk;
3491
3492         if (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK)) {
3493                 ret = ci_populate_all_graphic_levels(rdev);
3494                 if (ret)
3495                         return ret;
3496         }
3497
3498         if (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_MCLK | DPMTABLE_UPDATE_MCLK)) {
3499                 ret = ci_populate_all_memory_levels(rdev);
3500                 if (ret)
3501                         return ret;
3502         }
3503
3504         return 0;
3505 }
3506
3507 static int ci_enable_uvd_dpm(struct radeon_device *rdev, bool enable)
3508 {
3509         struct ci_power_info *pi = ci_get_pi(rdev);
3510         const struct radeon_clock_and_voltage_limits *max_limits;
3511         int i;
3512
3513         if (rdev->pm.dpm.ac_power)
3514                 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
3515         else
3516                 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
3517
3518         if (enable) {
3519                 pi->dpm_level_enable_mask.uvd_dpm_enable_mask = 0;
3520
3521                 for (i = rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count - 1; i >= 0; i--) {
3522                         if (rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) {
3523                                 pi->dpm_level_enable_mask.uvd_dpm_enable_mask |= 1 << i;
3524
3525                                 if (!pi->caps_uvd_dpm)
3526                                         break;
3527                         }
3528                 }
3529
3530                 ci_send_msg_to_smc_with_parameter(rdev,
3531                                                   PPSMC_MSG_UVDDPM_SetEnabledMask,
3532                                                   pi->dpm_level_enable_mask.uvd_dpm_enable_mask);
3533
3534                 if (pi->last_mclk_dpm_enable_mask & 0x1) {
3535                         pi->uvd_enabled = true;
3536                         pi->dpm_level_enable_mask.mclk_dpm_enable_mask &= 0xFFFFFFFE;
3537                         ci_send_msg_to_smc_with_parameter(rdev,
3538                                                           PPSMC_MSG_MCLKDPM_SetEnabledMask,
3539                                                           pi->dpm_level_enable_mask.mclk_dpm_enable_mask);
3540                 }
3541         } else {
3542                 if (pi->last_mclk_dpm_enable_mask & 0x1) {
3543                         pi->uvd_enabled = false;
3544                         pi->dpm_level_enable_mask.mclk_dpm_enable_mask |= 1;
3545                         ci_send_msg_to_smc_with_parameter(rdev,
3546                                                           PPSMC_MSG_MCLKDPM_SetEnabledMask,
3547                                                           pi->dpm_level_enable_mask.mclk_dpm_enable_mask);
3548                 }
3549         }
3550
3551         return (ci_send_msg_to_smc(rdev, enable ?
3552                                    PPSMC_MSG_UVDDPM_Enable : PPSMC_MSG_UVDDPM_Disable) == PPSMC_Result_OK) ?
3553                 0 : -EINVAL;
3554 }
3555
3556 static int ci_enable_vce_dpm(struct radeon_device *rdev, bool enable)
3557 {
3558         struct ci_power_info *pi = ci_get_pi(rdev);
3559         const struct radeon_clock_and_voltage_limits *max_limits;
3560         int i;
3561
3562         if (rdev->pm.dpm.ac_power)
3563                 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
3564         else
3565                 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
3566
3567         if (enable) {
3568                 pi->dpm_level_enable_mask.vce_dpm_enable_mask = 0;
3569                 for (i = rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.count - 1; i >= 0; i--) {
3570                         if (rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) {
3571                                 pi->dpm_level_enable_mask.vce_dpm_enable_mask |= 1 << i;
3572
3573                                 if (!pi->caps_vce_dpm)
3574                                         break;
3575                         }
3576                 }
3577
3578                 ci_send_msg_to_smc_with_parameter(rdev,
3579                                                   PPSMC_MSG_VCEDPM_SetEnabledMask,
3580                                                   pi->dpm_level_enable_mask.vce_dpm_enable_mask);
3581         }
3582
3583         return (ci_send_msg_to_smc(rdev, enable ?
3584                                    PPSMC_MSG_VCEDPM_Enable : PPSMC_MSG_VCEDPM_Disable) == PPSMC_Result_OK) ?
3585                 0 : -EINVAL;
3586 }
3587
3588 #if 0
3589 static int ci_enable_samu_dpm(struct radeon_device *rdev, bool enable)
3590 {
3591         struct ci_power_info *pi = ci_get_pi(rdev);
3592         const struct radeon_clock_and_voltage_limits *max_limits;
3593         int i;
3594
3595         if (rdev->pm.dpm.ac_power)
3596                 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
3597         else
3598                 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
3599
3600         if (enable) {
3601                 pi->dpm_level_enable_mask.samu_dpm_enable_mask = 0;
3602                 for (i = rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.count - 1; i >= 0; i--) {
3603                         if (rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) {
3604                                 pi->dpm_level_enable_mask.samu_dpm_enable_mask |= 1 << i;
3605
3606                                 if (!pi->caps_samu_dpm)
3607                                         break;
3608                         }
3609                 }
3610
3611                 ci_send_msg_to_smc_with_parameter(rdev,
3612                                                   PPSMC_MSG_SAMUDPM_SetEnabledMask,
3613                                                   pi->dpm_level_enable_mask.samu_dpm_enable_mask);
3614         }
3615         return (ci_send_msg_to_smc(rdev, enable ?
3616                                    PPSMC_MSG_SAMUDPM_Enable : PPSMC_MSG_SAMUDPM_Disable) == PPSMC_Result_OK) ?
3617                 0 : -EINVAL;
3618 }
3619
3620 static int ci_enable_acp_dpm(struct radeon_device *rdev, bool enable)
3621 {
3622         struct ci_power_info *pi = ci_get_pi(rdev);
3623         const struct radeon_clock_and_voltage_limits *max_limits;
3624         int i;
3625
3626         if (rdev->pm.dpm.ac_power)
3627                 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
3628         else
3629                 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
3630
3631         if (enable) {
3632                 pi->dpm_level_enable_mask.acp_dpm_enable_mask = 0;
3633                 for (i = rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.count - 1; i >= 0; i--) {
3634                         if (rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) {
3635                                 pi->dpm_level_enable_mask.acp_dpm_enable_mask |= 1 << i;
3636
3637                                 if (!pi->caps_acp_dpm)
3638                                         break;
3639                         }
3640                 }
3641
3642                 ci_send_msg_to_smc_with_parameter(rdev,
3643                                                   PPSMC_MSG_ACPDPM_SetEnabledMask,
3644                                                   pi->dpm_level_enable_mask.acp_dpm_enable_mask);
3645         }
3646
3647         return (ci_send_msg_to_smc(rdev, enable ?
3648                                    PPSMC_MSG_ACPDPM_Enable : PPSMC_MSG_ACPDPM_Disable) == PPSMC_Result_OK) ?
3649                 0 : -EINVAL;
3650 }
3651 #endif
3652
3653 static int ci_update_uvd_dpm(struct radeon_device *rdev, bool gate)
3654 {
3655         struct ci_power_info *pi = ci_get_pi(rdev);
3656         u32 tmp;
3657
3658         if (!gate) {
3659                 if (pi->caps_uvd_dpm ||
3660                     (rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count <= 0))
3661                         pi->smc_state_table.UvdBootLevel = 0;
3662                 else
3663                         pi->smc_state_table.UvdBootLevel =
3664                                 rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count - 1;
3665
3666                 tmp = RREG32_SMC(DPM_TABLE_475);
3667                 tmp &= ~UvdBootLevel_MASK;
3668                 tmp |= UvdBootLevel(pi->smc_state_table.UvdBootLevel);
3669                 WREG32_SMC(DPM_TABLE_475, tmp);
3670         }
3671
3672         return ci_enable_uvd_dpm(rdev, !gate);
3673 }
3674
3675 static u8 ci_get_vce_boot_level(struct radeon_device *rdev)
3676 {
3677         u8 i;
3678         u32 min_evclk = 30000; /* ??? */
3679         struct radeon_vce_clock_voltage_dependency_table *table =
3680                 &rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
3681
3682         for (i = 0; i < table->count; i++) {
3683                 if (table->entries[i].evclk >= min_evclk)
3684                         return i;
3685         }
3686
3687         return table->count - 1;
3688 }
3689
3690 static int ci_update_vce_dpm(struct radeon_device *rdev,
3691                              struct radeon_ps *radeon_new_state,
3692                              struct radeon_ps *radeon_current_state)
3693 {
3694         struct ci_power_info *pi = ci_get_pi(rdev);
3695         int ret = 0;
3696         u32 tmp;
3697
3698         if (radeon_current_state->evclk != radeon_new_state->evclk) {
3699                 if (radeon_new_state->evclk) {
3700                         /* turn the clocks on when encoding */
3701                         cik_update_cg(rdev, RADEON_CG_BLOCK_VCE, false);
3702
3703                         pi->smc_state_table.VceBootLevel = ci_get_vce_boot_level(rdev);
3704                         tmp = RREG32_SMC(DPM_TABLE_475);
3705                         tmp &= ~VceBootLevel_MASK;
3706                         tmp |= VceBootLevel(pi->smc_state_table.VceBootLevel);
3707                         WREG32_SMC(DPM_TABLE_475, tmp);
3708
3709                         ret = ci_enable_vce_dpm(rdev, true);
3710                 } else {
3711                         /* turn the clocks off when not encoding */
3712                         cik_update_cg(rdev, RADEON_CG_BLOCK_VCE, true);
3713
3714                         ret = ci_enable_vce_dpm(rdev, false);
3715                 }
3716         }
3717         return ret;
3718 }
3719
3720 #if 0
3721 static int ci_update_samu_dpm(struct radeon_device *rdev, bool gate)
3722 {
3723         return ci_enable_samu_dpm(rdev, gate);
3724 }
3725
3726 static int ci_update_acp_dpm(struct radeon_device *rdev, bool gate)
3727 {
3728         struct ci_power_info *pi = ci_get_pi(rdev);
3729         u32 tmp;
3730
3731         if (!gate) {
3732                 pi->smc_state_table.AcpBootLevel = 0;
3733
3734                 tmp = RREG32_SMC(DPM_TABLE_475);
3735                 tmp &= ~AcpBootLevel_MASK;
3736                 tmp |= AcpBootLevel(pi->smc_state_table.AcpBootLevel);
3737                 WREG32_SMC(DPM_TABLE_475, tmp);
3738         }
3739
3740         return ci_enable_acp_dpm(rdev, !gate);
3741 }
3742 #endif
3743
3744 static int ci_generate_dpm_level_enable_mask(struct radeon_device *rdev,
3745                                              struct radeon_ps *radeon_state)
3746 {
3747         struct ci_power_info *pi = ci_get_pi(rdev);
3748         int ret;
3749
3750         ret = ci_trim_dpm_states(rdev, radeon_state);
3751         if (ret)
3752                 return ret;
3753
3754         pi->dpm_level_enable_mask.sclk_dpm_enable_mask =
3755                 ci_get_dpm_level_enable_mask_value(&pi->dpm_table.sclk_table);
3756         pi->dpm_level_enable_mask.mclk_dpm_enable_mask =
3757                 ci_get_dpm_level_enable_mask_value(&pi->dpm_table.mclk_table);
3758         pi->last_mclk_dpm_enable_mask =
3759                 pi->dpm_level_enable_mask.mclk_dpm_enable_mask;
3760         if (pi->uvd_enabled) {
3761                 if (pi->dpm_level_enable_mask.mclk_dpm_enable_mask & 1)
3762                         pi->dpm_level_enable_mask.mclk_dpm_enable_mask &= 0xFFFFFFFE;
3763         }
3764         pi->dpm_level_enable_mask.pcie_dpm_enable_mask =
3765                 ci_get_dpm_level_enable_mask_value(&pi->dpm_table.pcie_speed_table);
3766
3767         return 0;
3768 }
3769
3770 static u32 ci_get_lowest_enabled_level(struct radeon_device *rdev,
3771                                        u32 level_mask)
3772 {
3773         u32 level = 0;
3774
3775         while ((level_mask & (1 << level)) == 0)
3776                 level++;
3777
3778         return level;
3779 }
3780
3781
3782 int ci_dpm_force_performance_level(struct radeon_device *rdev,
3783                                    enum radeon_dpm_forced_level level)
3784 {
3785         struct ci_power_info *pi = ci_get_pi(rdev);
3786         u32 tmp, levels, i;
3787         int ret;
3788
3789         if (level == RADEON_DPM_FORCED_LEVEL_HIGH) {
3790                 if ((!pi->sclk_dpm_key_disabled) &&
3791                     pi->dpm_level_enable_mask.sclk_dpm_enable_mask) {
3792                         levels = 0;
3793                         tmp = pi->dpm_level_enable_mask.sclk_dpm_enable_mask;
3794                         while (tmp >>= 1)
3795                                 levels++;
3796                         if (levels) {
3797                                 ret = ci_dpm_force_state_sclk(rdev, levels);
3798                                 if (ret)
3799                                         return ret;
3800                                 for (i = 0; i < rdev->usec_timeout; i++) {
3801                                         tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX) &
3802                                                CURR_SCLK_INDEX_MASK) >> CURR_SCLK_INDEX_SHIFT;
3803                                         if (tmp == levels)
3804                                                 break;
3805                                         udelay(1);
3806                                 }
3807                         }
3808                 }
3809                 if ((!pi->mclk_dpm_key_disabled) &&
3810                     pi->dpm_level_enable_mask.mclk_dpm_enable_mask) {
3811                         levels = 0;
3812                         tmp = pi->dpm_level_enable_mask.mclk_dpm_enable_mask;
3813                         while (tmp >>= 1)
3814                                 levels++;
3815                         if (levels) {
3816                                 ret = ci_dpm_force_state_mclk(rdev, levels);
3817                                 if (ret)
3818                                         return ret;
3819                                 for (i = 0; i < rdev->usec_timeout; i++) {
3820                                         tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX) &
3821                                                CURR_MCLK_INDEX_MASK) >> CURR_MCLK_INDEX_SHIFT;
3822                                         if (tmp == levels)
3823                                                 break;
3824                                         udelay(1);
3825                                 }
3826                         }
3827                 }
3828                 if ((!pi->pcie_dpm_key_disabled) &&
3829                     pi->dpm_level_enable_mask.pcie_dpm_enable_mask) {
3830                         levels = 0;
3831                         tmp = pi->dpm_level_enable_mask.pcie_dpm_enable_mask;
3832                         while (tmp >>= 1)
3833                                 levels++;
3834                         if (levels) {
3835                                 ret = ci_dpm_force_state_pcie(rdev, level);
3836                                 if (ret)
3837                                         return ret;
3838                                 for (i = 0; i < rdev->usec_timeout; i++) {
3839                                         tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX_1) &
3840                                                CURR_PCIE_INDEX_MASK) >> CURR_PCIE_INDEX_SHIFT;
3841                                         if (tmp == levels)
3842                                                 break;
3843                                         udelay(1);
3844                                 }
3845                         }
3846                 }
3847         } else if (level == RADEON_DPM_FORCED_LEVEL_LOW) {
3848                 if ((!pi->sclk_dpm_key_disabled) &&
3849                     pi->dpm_level_enable_mask.sclk_dpm_enable_mask) {
3850                         levels = ci_get_lowest_enabled_level(rdev,
3851                                                              pi->dpm_level_enable_mask.sclk_dpm_enable_mask);
3852                         ret = ci_dpm_force_state_sclk(rdev, levels);
3853                         if (ret)
3854                                 return ret;
3855                         for (i = 0; i < rdev->usec_timeout; i++) {
3856                                 tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX) &
3857                                        CURR_SCLK_INDEX_MASK) >> CURR_SCLK_INDEX_SHIFT;
3858                                 if (tmp == levels)
3859                                         break;
3860                                 udelay(1);
3861                         }
3862                 }
3863                 if ((!pi->mclk_dpm_key_disabled) &&
3864                     pi->dpm_level_enable_mask.mclk_dpm_enable_mask) {
3865                         levels = ci_get_lowest_enabled_level(rdev,
3866                                                              pi->dpm_level_enable_mask.mclk_dpm_enable_mask);
3867                         ret = ci_dpm_force_state_mclk(rdev, levels);
3868                         if (ret)
3869                                 return ret;
3870                         for (i = 0; i < rdev->usec_timeout; i++) {
3871                                 tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX) &
3872                                        CURR_MCLK_INDEX_MASK) >> CURR_MCLK_INDEX_SHIFT;
3873                                 if (tmp == levels)
3874                                         break;
3875                                 udelay(1);
3876                         }
3877                 }
3878                 if ((!pi->pcie_dpm_key_disabled) &&
3879                     pi->dpm_level_enable_mask.pcie_dpm_enable_mask) {
3880                         levels = ci_get_lowest_enabled_level(rdev,
3881                                                              pi->dpm_level_enable_mask.pcie_dpm_enable_mask);
3882                         ret = ci_dpm_force_state_pcie(rdev, levels);
3883                         if (ret)
3884                                 return ret;
3885                         for (i = 0; i < rdev->usec_timeout; i++) {
3886                                 tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX_1) &
3887                                        CURR_PCIE_INDEX_MASK) >> CURR_PCIE_INDEX_SHIFT;
3888                                 if (tmp == levels)
3889                                         break;
3890                                 udelay(1);
3891                         }
3892                 }
3893         } else if (level == RADEON_DPM_FORCED_LEVEL_AUTO) {
3894                 ret = ci_upload_dpm_level_enable_mask(rdev);
3895                 if (ret)
3896                         return ret;
3897         }
3898
3899         rdev->pm.dpm.forced_level = level;
3900
3901         return 0;
3902 }
3903
3904 static int ci_set_mc_special_registers(struct radeon_device *rdev,
3905                                        struct ci_mc_reg_table *table)
3906 {
3907         struct ci_power_info *pi = ci_get_pi(rdev);
3908         u8 i, j, k;
3909         u32 temp_reg;
3910
3911         for (i = 0, j = table->last; i < table->last; i++) {
3912                 if (j >= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
3913                         return -EINVAL;
3914                 switch(table->mc_reg_address[i].s1 << 2) {
3915                 case MC_SEQ_MISC1:
3916                         temp_reg = RREG32(MC_PMG_CMD_EMRS);
3917                         table->mc_reg_address[j].s1 = MC_PMG_CMD_EMRS >> 2;
3918                         table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_EMRS_LP >> 2;
3919                         for (k = 0; k < table->num_entries; k++) {
3920                                 table->mc_reg_table_entry[k].mc_data[j] =
3921                                         ((temp_reg & 0xffff0000)) | ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16);
3922                         }
3923                         j++;
3924                         if (j >= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
3925                                 return -EINVAL;
3926
3927                         temp_reg = RREG32(MC_PMG_CMD_MRS);
3928                         table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS >> 2;
3929                         table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS_LP >> 2;
3930                         for (k = 0; k < table->num_entries; k++) {
3931                                 table->mc_reg_table_entry[k].mc_data[j] =
3932                                         (temp_reg & 0xffff0000) | (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
3933                                 if (!pi->mem_gddr5)
3934                                         table->mc_reg_table_entry[k].mc_data[j] |= 0x100;
3935                         }
3936                         j++;
3937                         if (j > SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
3938                                 return -EINVAL;
3939
3940                         if (!pi->mem_gddr5) {
3941                                 table->mc_reg_address[j].s1 = MC_PMG_AUTO_CMD >> 2;
3942                                 table->mc_reg_address[j].s0 = MC_PMG_AUTO_CMD >> 2;
3943                                 for (k = 0; k < table->num_entries; k++) {
3944                                         table->mc_reg_table_entry[k].mc_data[j] =
3945                                                 (table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16;
3946                                 }
3947                                 j++;
3948                                 if (j > SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
3949                                         return -EINVAL;
3950                         }
3951                         break;
3952                 case MC_SEQ_RESERVE_M:
3953                         temp_reg = RREG32(MC_PMG_CMD_MRS1);
3954                         table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS1 >> 2;
3955                         table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS1_LP >> 2;
3956                         for (k = 0; k < table->num_entries; k++) {
3957                                 table->mc_reg_table_entry[k].mc_data[j] =
3958                                         (temp_reg & 0xffff0000) | (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
3959                         }
3960                         j++;
3961                         if (j > SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
3962                                 return -EINVAL;
3963                         break;
3964                 default:
3965                         break;
3966                 }
3967
3968         }
3969
3970         table->last = j;
3971
3972         return 0;
3973 }
3974
3975 static bool ci_check_s0_mc_reg_index(u16 in_reg, u16 *out_reg)
3976 {
3977         bool result = true;
3978
3979         switch(in_reg) {
3980         case MC_SEQ_RAS_TIMING >> 2:
3981                 *out_reg = MC_SEQ_RAS_TIMING_LP >> 2;
3982                 break;
3983         case MC_SEQ_DLL_STBY >> 2:
3984                 *out_reg = MC_SEQ_DLL_STBY_LP >> 2;
3985                 break;
3986         case MC_SEQ_G5PDX_CMD0 >> 2:
3987                 *out_reg = MC_SEQ_G5PDX_CMD0_LP >> 2;
3988                 break;
3989         case MC_SEQ_G5PDX_CMD1 >> 2:
3990                 *out_reg = MC_SEQ_G5PDX_CMD1_LP >> 2;
3991                 break;
3992         case MC_SEQ_G5PDX_CTRL >> 2:
3993                 *out_reg = MC_SEQ_G5PDX_CTRL_LP >> 2;
3994                 break;
3995         case MC_SEQ_CAS_TIMING >> 2:
3996                 *out_reg = MC_SEQ_CAS_TIMING_LP >> 2;
3997             break;
3998         case MC_SEQ_MISC_TIMING >> 2:
3999                 *out_reg = MC_SEQ_MISC_TIMING_LP >> 2;
4000                 break;
4001         case MC_SEQ_MISC_TIMING2 >> 2:
4002                 *out_reg = MC_SEQ_MISC_TIMING2_LP >> 2;
4003                 break;
4004         case MC_SEQ_PMG_DVS_CMD >> 2:
4005                 *out_reg = MC_SEQ_PMG_DVS_CMD_LP >> 2;
4006                 break;
4007         case MC_SEQ_PMG_DVS_CTL >> 2:
4008                 *out_reg = MC_SEQ_PMG_DVS_CTL_LP >> 2;
4009                 break;
4010         case MC_SEQ_RD_CTL_D0 >> 2:
4011                 *out_reg = MC_SEQ_RD_CTL_D0_LP >> 2;
4012                 break;
4013         case MC_SEQ_RD_CTL_D1 >> 2:
4014                 *out_reg = MC_SEQ_RD_CTL_D1_LP >> 2;
4015                 break;
4016         case MC_SEQ_WR_CTL_D0 >> 2:
4017                 *out_reg = MC_SEQ_WR_CTL_D0_LP >> 2;
4018                 break;
4019         case MC_SEQ_WR_CTL_D1 >> 2:
4020                 *out_reg = MC_SEQ_WR_CTL_D1_LP >> 2;
4021                 break;
4022         case MC_PMG_CMD_EMRS >> 2:
4023                 *out_reg = MC_SEQ_PMG_CMD_EMRS_LP >> 2;
4024                 break;
4025         case MC_PMG_CMD_MRS >> 2:
4026                 *out_reg = MC_SEQ_PMG_CMD_MRS_LP >> 2;
4027                 break;
4028         case MC_PMG_CMD_MRS1 >> 2:
4029                 *out_reg = MC_SEQ_PMG_CMD_MRS1_LP >> 2;
4030                 break;
4031         case MC_SEQ_PMG_TIMING >> 2:
4032                 *out_reg = MC_SEQ_PMG_TIMING_LP >> 2;
4033                 break;
4034         case MC_PMG_CMD_MRS2 >> 2:
4035                 *out_reg = MC_SEQ_PMG_CMD_MRS2_LP >> 2;
4036                 break;
4037         case MC_SEQ_WR_CTL_2 >> 2:
4038                 *out_reg = MC_SEQ_WR_CTL_2_LP >> 2;
4039                 break;
4040         default:
4041                 result = false;
4042                 break;
4043         }
4044
4045         return result;
4046 }
4047
4048 static void ci_set_valid_flag(struct ci_mc_reg_table *table)
4049 {
4050         u8 i, j;
4051
4052         for (i = 0; i < table->last; i++) {
4053                 for (j = 1; j < table->num_entries; j++) {
4054                         if (table->mc_reg_table_entry[j-1].mc_data[i] !=
4055                             table->mc_reg_table_entry[j].mc_data[i]) {
4056                                 table->valid_flag |= 1 << i;
4057                                 break;
4058                         }
4059                 }
4060         }
4061 }
4062
4063 static void ci_set_s0_mc_reg_index(struct ci_mc_reg_table *table)
4064 {
4065         u32 i;
4066         u16 address;
4067
4068         for (i = 0; i < table->last; i++) {
4069                 table->mc_reg_address[i].s0 =
4070                         ci_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address) ?
4071                         address : table->mc_reg_address[i].s1;
4072         }
4073 }
4074
4075 static int ci_copy_vbios_mc_reg_table(const struct atom_mc_reg_table *table,
4076                                       struct ci_mc_reg_table *ci_table)
4077 {
4078         u8 i, j;
4079
4080         if (table->last > SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
4081                 return -EINVAL;
4082         if (table->num_entries > MAX_AC_TIMING_ENTRIES)
4083                 return -EINVAL;
4084
4085         for (i = 0; i < table->last; i++)
4086                 ci_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1;
4087
4088         ci_table->last = table->last;
4089
4090         for (i = 0; i < table->num_entries; i++) {
4091                 ci_table->mc_reg_table_entry[i].mclk_max =
4092                         table->mc_reg_table_entry[i].mclk_max;
4093                 for (j = 0; j < table->last; j++)
4094                         ci_table->mc_reg_table_entry[i].mc_data[j] =
4095                                 table->mc_reg_table_entry[i].mc_data[j];
4096         }
4097         ci_table->num_entries = table->num_entries;
4098
4099         return 0;
4100 }
4101
4102 static int ci_register_patching_mc_seq(struct radeon_device *rdev,
4103                                        struct ci_mc_reg_table *table)
4104 {
4105         u8 i, k;
4106         u32 tmp;
4107         bool patch;
4108
4109         tmp = RREG32(MC_SEQ_MISC0);
4110         patch = ((tmp & 0x0000f00) == 0x300) ? true : false;
4111
4112         if (patch &&
4113             ((rdev->pdev->device == 0x67B0) ||
4114              (rdev->pdev->device == 0x67B1))) {
4115                 for (i = 0; i < table->last; i++) {
4116                         if (table->last >= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
4117                                 return -EINVAL;
4118                         switch(table->mc_reg_address[i].s1 >> 2) {
4119                         case MC_SEQ_MISC1:
4120                                 for (k = 0; k < table->num_entries; k++) {
4121                                         if ((table->mc_reg_table_entry[k].mclk_max == 125000) ||
4122                                             (table->mc_reg_table_entry[k].mclk_max == 137500))
4123                                                 table->mc_reg_table_entry[k].mc_data[i] =
4124                                                         (table->mc_reg_table_entry[k].mc_data[i] & 0xFFFFFFF8) |
4125                                                         0x00000007;
4126                                 }
4127                                 break;
4128                         case MC_SEQ_WR_CTL_D0:
4129                                 for (k = 0; k < table->num_entries; k++) {
4130                                         if ((table->mc_reg_table_entry[k].mclk_max == 125000) ||
4131                                             (table->mc_reg_table_entry[k].mclk_max == 137500))
4132                                                 table->mc_reg_table_entry[k].mc_data[i] =
4133                                                         (table->mc_reg_table_entry[k].mc_data[i] & 0xFFFF0F00) |
4134                                                         0x0000D0DD;
4135                                 }
4136                                 break;
4137                         case MC_SEQ_WR_CTL_D1:
4138                                 for (k = 0; k < table->num_entries; k++) {
4139                                         if ((table->mc_reg_table_entry[k].mclk_max == 125000) ||
4140                                             (table->mc_reg_table_entry[k].mclk_max == 137500))
4141                                                 table->mc_reg_table_entry[k].mc_data[i] =
4142                                                         (table->mc_reg_table_entry[k].mc_data[i] & 0xFFFF0F00) |
4143                                                         0x0000D0DD;
4144                                 }
4145                                 break;
4146                         case MC_SEQ_WR_CTL_2:
4147                                 for (k = 0; k < table->num_entries; k++) {
4148                                         if ((table->mc_reg_table_entry[k].mclk_max == 125000) ||
4149                                             (table->mc_reg_table_entry[k].mclk_max == 137500))
4150                                                 table->mc_reg_table_entry[k].mc_data[i] = 0;
4151                                 }
4152                                 break;
4153                         case MC_SEQ_CAS_TIMING:
4154                                 for (k = 0; k < table->num_entries; k++) {
4155                                         if (table->mc_reg_table_entry[k].mclk_max == 125000)
4156                                                 table->mc_reg_table_entry[k].mc_data[i] =
4157                                                         (table->mc_reg_table_entry[k].mc_data[i] & 0xFFE0FE0F) |
4158                                                         0x000C0140;
4159                                         else if (table->mc_reg_table_entry[k].mclk_max == 137500)
4160                                                 table->mc_reg_table_entry[k].mc_data[i] =
4161                                                         (table->mc_reg_table_entry[k].mc_data[i] & 0xFFE0FE0F) |
4162                                                         0x000C0150;
4163                                 }
4164                                 break;
4165                         case MC_SEQ_MISC_TIMING:
4166                                 for (k = 0; k < table->num_entries; k++) {
4167                                         if (table->mc_reg_table_entry[k].mclk_max == 125000)
4168                                                 table->mc_reg_table_entry[k].mc_data[i] =
4169                                                         (table->mc_reg_table_entry[k].mc_data[i] & 0xFFFFFFE0) |
4170                                                         0x00000030;
4171                                         else if (table->mc_reg_table_entry[k].mclk_max == 137500)
4172                                                 table->mc_reg_table_entry[k].mc_data[i] =
4173                                                         (table->mc_reg_table_entry[k].mc_data[i] & 0xFFFFFFE0) |
4174                                                         0x00000035;
4175                                 }
4176                                 break;
4177                         default:
4178                                 break;
4179                         }
4180                 }
4181
4182                 WREG32(MC_SEQ_IO_DEBUG_INDEX, 3);
4183                 tmp = RREG32(MC_SEQ_IO_DEBUG_DATA);
4184                 tmp = (tmp & 0xFFF8FFFF) | (1 << 16);
4185                 WREG32(MC_SEQ_IO_DEBUG_INDEX, 3);
4186                 WREG32(MC_SEQ_IO_DEBUG_DATA, tmp);
4187         }
4188
4189         return 0;
4190 }
4191
4192 static int ci_initialize_mc_reg_table(struct radeon_device *rdev)
4193 {
4194         struct ci_power_info *pi = ci_get_pi(rdev);
4195         struct atom_mc_reg_table *table;
4196         struct ci_mc_reg_table *ci_table = &pi->mc_reg_table;
4197         u8 module_index = rv770_get_memory_module_index(rdev);
4198         int ret;
4199
4200         table = kzalloc(sizeof(struct atom_mc_reg_table), GFP_KERNEL);
4201         if (!table)
4202                 return -ENOMEM;
4203
4204         WREG32(MC_SEQ_RAS_TIMING_LP, RREG32(MC_SEQ_RAS_TIMING));
4205         WREG32(MC_SEQ_CAS_TIMING_LP, RREG32(MC_SEQ_CAS_TIMING));
4206         WREG32(MC_SEQ_DLL_STBY_LP, RREG32(MC_SEQ_DLL_STBY));
4207         WREG32(MC_SEQ_G5PDX_CMD0_LP, RREG32(MC_SEQ_G5PDX_CMD0));
4208         WREG32(MC_SEQ_G5PDX_CMD1_LP, RREG32(MC_SEQ_G5PDX_CMD1));
4209         WREG32(MC_SEQ_G5PDX_CTRL_LP, RREG32(MC_SEQ_G5PDX_CTRL));
4210         WREG32(MC_SEQ_PMG_DVS_CMD_LP, RREG32(MC_SEQ_PMG_DVS_CMD));
4211         WREG32(MC_SEQ_PMG_DVS_CTL_LP, RREG32(MC_SEQ_PMG_DVS_CTL));
4212         WREG32(MC_SEQ_MISC_TIMING_LP, RREG32(MC_SEQ_MISC_TIMING));
4213         WREG32(MC_SEQ_MISC_TIMING2_LP, RREG32(MC_SEQ_MISC_TIMING2));
4214         WREG32(MC_SEQ_PMG_CMD_EMRS_LP, RREG32(MC_PMG_CMD_EMRS));
4215         WREG32(MC_SEQ_PMG_CMD_MRS_LP, RREG32(MC_PMG_CMD_MRS));
4216         WREG32(MC_SEQ_PMG_CMD_MRS1_LP, RREG32(MC_PMG_CMD_MRS1));
4217         WREG32(MC_SEQ_WR_CTL_D0_LP, RREG32(MC_SEQ_WR_CTL_D0));
4218         WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1));
4219         WREG32(MC_SEQ_RD_CTL_D0_LP, RREG32(MC_SEQ_RD_CTL_D0));
4220         WREG32(MC_SEQ_RD_CTL_D1_LP, RREG32(MC_SEQ_RD_CTL_D1));
4221         WREG32(MC_SEQ_PMG_TIMING_LP, RREG32(MC_SEQ_PMG_TIMING));
4222         WREG32(MC_SEQ_PMG_CMD_MRS2_LP, RREG32(MC_PMG_CMD_MRS2));
4223         WREG32(MC_SEQ_WR_CTL_2_LP, RREG32(MC_SEQ_WR_CTL_2));
4224
4225         ret = radeon_atom_init_mc_reg_table(rdev, module_index, table);
4226         if (ret)
4227                 goto init_mc_done;
4228
4229         ret = ci_copy_vbios_mc_reg_table(table, ci_table);
4230         if (ret)
4231                 goto init_mc_done;
4232
4233         ci_set_s0_mc_reg_index(ci_table);
4234
4235         ret = ci_register_patching_mc_seq(rdev, ci_table);
4236         if (ret)
4237                 goto init_mc_done;
4238
4239         ret = ci_set_mc_special_registers(rdev, ci_table);
4240         if (ret)
4241                 goto init_mc_done;
4242
4243         ci_set_valid_flag(ci_table);
4244
4245 init_mc_done:
4246         kfree(table);
4247
4248         return ret;
4249 }
4250
4251 static int ci_populate_mc_reg_addresses(struct radeon_device *rdev,
4252                                         SMU7_Discrete_MCRegisters *mc_reg_table)
4253 {
4254         struct ci_power_info *pi = ci_get_pi(rdev);
4255         u32 i, j;
4256
4257         for (i = 0, j = 0; j < pi->mc_reg_table.last; j++) {
4258                 if (pi->mc_reg_table.valid_flag & (1 << j)) {
4259                         if (i >= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
4260                                 return -EINVAL;
4261                         mc_reg_table->address[i].s0 = cpu_to_be16(pi->mc_reg_table.mc_reg_address[j].s0);
4262                         mc_reg_table->address[i].s1 = cpu_to_be16(pi->mc_reg_table.mc_reg_address[j].s1);
4263                         i++;
4264                 }
4265         }
4266
4267         mc_reg_table->last = (u8)i;
4268
4269         return 0;
4270 }
4271
4272 static void ci_convert_mc_registers(const struct ci_mc_reg_entry *entry,
4273                                     SMU7_Discrete_MCRegisterSet *data,
4274                                     u32 num_entries, u32 valid_flag)
4275 {
4276         u32 i, j;
4277
4278         for (i = 0, j = 0; j < num_entries; j++) {
4279                 if (valid_flag & (1 << j)) {
4280                         data->value[i] = cpu_to_be32(entry->mc_data[j]);
4281                         i++;
4282                 }
4283         }
4284 }
4285
4286 static void ci_convert_mc_reg_table_entry_to_smc(struct radeon_device *rdev,
4287                                                  const u32 memory_clock,
4288                                                  SMU7_Discrete_MCRegisterSet *mc_reg_table_data)
4289 {
4290         struct ci_power_info *pi = ci_get_pi(rdev);
4291         u32 i = 0;
4292
4293         for(i = 0; i < pi->mc_reg_table.num_entries; i++) {
4294                 if (memory_clock <= pi->mc_reg_table.mc_reg_table_entry[i].mclk_max)
4295                         break;
4296         }
4297
4298         if ((i == pi->mc_reg_table.num_entries) && (i > 0))
4299                 --i;
4300
4301         ci_convert_mc_registers(&pi->mc_reg_table.mc_reg_table_entry[i],
4302                                 mc_reg_table_data, pi->mc_reg_table.last,
4303                                 pi->mc_reg_table.valid_flag);
4304 }
4305
4306 static void ci_convert_mc_reg_table_to_smc(struct radeon_device *rdev,
4307                                            SMU7_Discrete_MCRegisters *mc_reg_table)
4308 {
4309         struct ci_power_info *pi = ci_get_pi(rdev);
4310         u32 i;
4311
4312         for (i = 0; i < pi->dpm_table.mclk_table.count; i++)
4313                 ci_convert_mc_reg_table_entry_to_smc(rdev,
4314                                                      pi->dpm_table.mclk_table.dpm_levels[i].value,
4315                                                      &mc_reg_table->data[i]);
4316 }
4317
4318 static int ci_populate_initial_mc_reg_table(struct radeon_device *rdev)
4319 {
4320         struct ci_power_info *pi = ci_get_pi(rdev);
4321         int ret;
4322
4323         memset(&pi->smc_mc_reg_table, 0, sizeof(SMU7_Discrete_MCRegisters));
4324
4325         ret = ci_populate_mc_reg_addresses(rdev, &pi->smc_mc_reg_table);
4326         if (ret)
4327                 return ret;
4328         ci_convert_mc_reg_table_to_smc(rdev, &pi->smc_mc_reg_table);
4329
4330         return ci_copy_bytes_to_smc(rdev,
4331                                     pi->mc_reg_table_start,
4332                                     (u8 *)&pi->smc_mc_reg_table,
4333                                     sizeof(SMU7_Discrete_MCRegisters),
4334                                     pi->sram_end);
4335 }
4336
4337 static int ci_update_and_upload_mc_reg_table(struct radeon_device *rdev)
4338 {
4339         struct ci_power_info *pi = ci_get_pi(rdev);
4340
4341         if (!(pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK))
4342                 return 0;
4343
4344         memset(&pi->smc_mc_reg_table, 0, sizeof(SMU7_Discrete_MCRegisters));
4345
4346         ci_convert_mc_reg_table_to_smc(rdev, &pi->smc_mc_reg_table);
4347
4348         return ci_copy_bytes_to_smc(rdev,
4349                                     pi->mc_reg_table_start +
4350                                     offsetof(SMU7_Discrete_MCRegisters, data[0]),
4351                                     (u8 *)&pi->smc_mc_reg_table.data[0],
4352                                     sizeof(SMU7_Discrete_MCRegisterSet) *
4353                                     pi->dpm_table.mclk_table.count,
4354                                     pi->sram_end);
4355 }
4356
4357 static void ci_enable_voltage_control(struct radeon_device *rdev)
4358 {
4359         u32 tmp = RREG32_SMC(GENERAL_PWRMGT);
4360
4361         tmp |= VOLT_PWRMGT_EN;
4362         WREG32_SMC(GENERAL_PWRMGT, tmp);
4363 }
4364
4365 static enum radeon_pcie_gen ci_get_maximum_link_speed(struct radeon_device *rdev,
4366                                                       struct radeon_ps *radeon_state)
4367 {
4368         struct ci_ps *state = ci_get_ps(radeon_state);
4369         int i;
4370         u16 pcie_speed, max_speed = 0;
4371
4372         for (i = 0; i < state->performance_level_count; i++) {
4373                 pcie_speed = state->performance_levels[i].pcie_gen;
4374                 if (max_speed < pcie_speed)
4375                         max_speed = pcie_speed;
4376         }
4377
4378         return max_speed;
4379 }
4380
4381 static u16 ci_get_current_pcie_speed(struct radeon_device *rdev)
4382 {
4383         u32 speed_cntl = 0;
4384
4385         speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL) & LC_CURRENT_DATA_RATE_MASK;
4386         speed_cntl >>= LC_CURRENT_DATA_RATE_SHIFT;
4387
4388         return (u16)speed_cntl;
4389 }
4390
4391 static int ci_get_current_pcie_lane_number(struct radeon_device *rdev)
4392 {
4393         u32 link_width = 0;
4394
4395         link_width = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL) & LC_LINK_WIDTH_RD_MASK;
4396         link_width >>= LC_LINK_WIDTH_RD_SHIFT;
4397
4398         switch (link_width) {
4399         case RADEON_PCIE_LC_LINK_WIDTH_X1:
4400                 return 1;
4401         case RADEON_PCIE_LC_LINK_WIDTH_X2:
4402                 return 2;
4403         case RADEON_PCIE_LC_LINK_WIDTH_X4:
4404                 return 4;
4405         case RADEON_PCIE_LC_LINK_WIDTH_X8:
4406                 return 8;
4407         case RADEON_PCIE_LC_LINK_WIDTH_X12:
4408                 /* not actually supported */
4409                 return 12;
4410         case RADEON_PCIE_LC_LINK_WIDTH_X0:
4411         case RADEON_PCIE_LC_LINK_WIDTH_X16:
4412         default:
4413                 return 16;
4414         }
4415 }
4416
4417 static void ci_request_link_speed_change_before_state_change(struct radeon_device *rdev,
4418                                                              struct radeon_ps *radeon_new_state,
4419                                                              struct radeon_ps *radeon_current_state)
4420 {
4421         struct ci_power_info *pi = ci_get_pi(rdev);
4422         enum radeon_pcie_gen target_link_speed =
4423                 ci_get_maximum_link_speed(rdev, radeon_new_state);
4424         enum radeon_pcie_gen current_link_speed;
4425
4426         if (pi->force_pcie_gen == RADEON_PCIE_GEN_INVALID)
4427                 current_link_speed = ci_get_maximum_link_speed(rdev, radeon_current_state);
4428         else
4429                 current_link_speed = pi->force_pcie_gen;
4430
4431         pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID;
4432         pi->pspp_notify_required = false;
4433         if (target_link_speed > current_link_speed) {
4434                 switch (target_link_speed) {
4435 #ifdef CONFIG_ACPI
4436                 case RADEON_PCIE_GEN3:
4437                         if (radeon_acpi_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN3, false) == 0)
4438                                 break;
4439                         pi->force_pcie_gen = RADEON_PCIE_GEN2;
4440                         if (current_link_speed == RADEON_PCIE_GEN2)
4441                                 break;
4442                 case RADEON_PCIE_GEN2:
4443                         if (radeon_acpi_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN2, false) == 0)
4444                                 break;
4445 #endif
4446                 default:
4447                         pi->force_pcie_gen = ci_get_current_pcie_speed(rdev);
4448                         break;
4449                 }
4450         } else {
4451                 if (target_link_speed < current_link_speed)
4452                         pi->pspp_notify_required = true;
4453         }
4454 }
4455
4456 static void ci_notify_link_speed_change_after_state_change(struct radeon_device *rdev,
4457                                                            struct radeon_ps *radeon_new_state,
4458                                                            struct radeon_ps *radeon_current_state)
4459 {
4460         struct ci_power_info *pi = ci_get_pi(rdev);
4461         enum radeon_pcie_gen target_link_speed =
4462                 ci_get_maximum_link_speed(rdev, radeon_new_state);
4463         u8 request;
4464
4465         if (pi->pspp_notify_required) {
4466                 if (target_link_speed == RADEON_PCIE_GEN3)
4467                         request = PCIE_PERF_REQ_PECI_GEN3;
4468                 else if (target_link_speed == RADEON_PCIE_GEN2)
4469                         request = PCIE_PERF_REQ_PECI_GEN2;
4470                 else
4471                         request = PCIE_PERF_REQ_PECI_GEN1;
4472
4473                 if ((request == PCIE_PERF_REQ_PECI_GEN1) &&
4474                     (ci_get_current_pcie_speed(rdev) > 0))
4475                         return;
4476
4477 #ifdef CONFIG_ACPI
4478                 radeon_acpi_pcie_performance_request(rdev, request, false);
4479 #endif
4480         }
4481 }
4482
4483 static int ci_set_private_data_variables_based_on_pptable(struct radeon_device *rdev)
4484 {
4485         struct ci_power_info *pi = ci_get_pi(rdev);
4486         struct radeon_clock_voltage_dependency_table *allowed_sclk_vddc_table =
4487                 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
4488         struct radeon_clock_voltage_dependency_table *allowed_mclk_vddc_table =
4489                 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk;
4490         struct radeon_clock_voltage_dependency_table *allowed_mclk_vddci_table =
4491                 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk;
4492
4493         if (allowed_sclk_vddc_table == NULL)
4494                 return -EINVAL;
4495         if (allowed_sclk_vddc_table->count < 1)
4496                 return -EINVAL;
4497         if (allowed_mclk_vddc_table == NULL)
4498                 return -EINVAL;
4499         if (allowed_mclk_vddc_table->count < 1)
4500                 return -EINVAL;
4501         if (allowed_mclk_vddci_table == NULL)
4502                 return -EINVAL;
4503         if (allowed_mclk_vddci_table->count < 1)
4504                 return -EINVAL;
4505
4506         pi->min_vddc_in_pp_table = allowed_sclk_vddc_table->entries[0].v;
4507         pi->max_vddc_in_pp_table =
4508                 allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].v;
4509
4510         pi->min_vddci_in_pp_table = allowed_mclk_vddci_table->entries[0].v;
4511         pi->max_vddci_in_pp_table =
4512                 allowed_mclk_vddci_table->entries[allowed_mclk_vddci_table->count - 1].v;
4513
4514         rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk =
4515                 allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].clk;
4516         rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk =
4517                 allowed_mclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].clk;
4518         rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc =
4519                 allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].v;
4520         rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddci =
4521                 allowed_mclk_vddci_table->entries[allowed_mclk_vddci_table->count - 1].v;
4522
4523         return 0;
4524 }
4525
4526 static void ci_patch_with_vddc_leakage(struct radeon_device *rdev, u16 *vddc)
4527 {
4528         struct ci_power_info *pi = ci_get_pi(rdev);
4529         struct ci_leakage_voltage *leakage_table = &pi->vddc_leakage;
4530         u32 leakage_index;
4531
4532         for (leakage_index = 0; leakage_index < leakage_table->count; leakage_index++) {
4533                 if (leakage_table->leakage_id[leakage_index] == *vddc) {
4534                         *vddc = leakage_table->actual_voltage[leakage_index];
4535                         break;
4536                 }
4537         }
4538 }
4539
4540 static void ci_patch_with_vddci_leakage(struct radeon_device *rdev, u16 *vddci)
4541 {
4542         struct ci_power_info *pi = ci_get_pi(rdev);
4543         struct ci_leakage_voltage *leakage_table = &pi->vddci_leakage;
4544         u32 leakage_index;
4545
4546         for (leakage_index = 0; leakage_index < leakage_table->count; leakage_index++) {
4547                 if (leakage_table->leakage_id[leakage_index] == *vddci) {
4548                         *vddci = leakage_table->actual_voltage[leakage_index];
4549                         break;
4550                 }
4551         }
4552 }
4553
4554 static void ci_patch_clock_voltage_dependency_table_with_vddc_leakage(struct radeon_device *rdev,
4555                                                                       struct radeon_clock_voltage_dependency_table *table)
4556 {
4557         u32 i;
4558
4559         if (table) {
4560                 for (i = 0; i < table->count; i++)
4561                         ci_patch_with_vddc_leakage(rdev, &table->entries[i].v);
4562         }
4563 }
4564
4565 static void ci_patch_clock_voltage_dependency_table_with_vddci_leakage(struct radeon_device *rdev,
4566                                                                        struct radeon_clock_voltage_dependency_table *table)
4567 {
4568         u32 i;
4569
4570         if (table) {
4571                 for (i = 0; i < table->count; i++)
4572                         ci_patch_with_vddci_leakage(rdev, &table->entries[i].v);
4573         }
4574 }
4575
4576 static void ci_patch_vce_clock_voltage_dependency_table_with_vddc_leakage(struct radeon_device *rdev,
4577                                                                           struct radeon_vce_clock_voltage_dependency_table *table)
4578 {
4579         u32 i;
4580
4581         if (table) {
4582                 for (i = 0; i < table->count; i++)
4583                         ci_patch_with_vddc_leakage(rdev, &table->entries[i].v);
4584         }
4585 }
4586
4587 static void ci_patch_uvd_clock_voltage_dependency_table_with_vddc_leakage(struct radeon_device *rdev,
4588                                                                           struct radeon_uvd_clock_voltage_dependency_table *table)
4589 {
4590         u32 i;
4591
4592         if (table) {
4593                 for (i = 0; i < table->count; i++)
4594                         ci_patch_with_vddc_leakage(rdev, &table->entries[i].v);
4595         }
4596 }
4597
4598 static void ci_patch_vddc_phase_shed_limit_table_with_vddc_leakage(struct radeon_device *rdev,
4599                                                                    struct radeon_phase_shedding_limits_table *table)
4600 {
4601         u32 i;
4602
4603         if (table) {
4604                 for (i = 0; i < table->count; i++)
4605                         ci_patch_with_vddc_leakage(rdev, &table->entries[i].voltage);
4606         }
4607 }
4608
4609 static void ci_patch_clock_voltage_limits_with_vddc_leakage(struct radeon_device *rdev,
4610                                                             struct radeon_clock_and_voltage_limits *table)
4611 {
4612         if (table) {
4613                 ci_patch_with_vddc_leakage(rdev, (u16 *)&table->vddc);
4614                 ci_patch_with_vddci_leakage(rdev, (u16 *)&table->vddci);
4615         }
4616 }
4617
4618 static void ci_patch_cac_leakage_table_with_vddc_leakage(struct radeon_device *rdev,
4619                                                          struct radeon_cac_leakage_table *table)
4620 {
4621         u32 i;
4622
4623         if (table) {
4624                 for (i = 0; i < table->count; i++)
4625                         ci_patch_with_vddc_leakage(rdev, &table->entries[i].vddc);
4626         }
4627 }
4628
4629 static void ci_patch_dependency_tables_with_leakage(struct radeon_device *rdev)
4630 {
4631
4632         ci_patch_clock_voltage_dependency_table_with_vddc_leakage(rdev,
4633                                                                   &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk);
4634         ci_patch_clock_voltage_dependency_table_with_vddc_leakage(rdev,
4635                                                                   &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk);
4636         ci_patch_clock_voltage_dependency_table_with_vddc_leakage(rdev,
4637                                                                   &rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk);
4638         ci_patch_clock_voltage_dependency_table_with_vddci_leakage(rdev,
4639                                                                    &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk);
4640         ci_patch_vce_clock_voltage_dependency_table_with_vddc_leakage(rdev,
4641                                                                       &rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table);
4642         ci_patch_uvd_clock_voltage_dependency_table_with_vddc_leakage(rdev,
4643                                                                       &rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table);
4644         ci_patch_clock_voltage_dependency_table_with_vddc_leakage(rdev,
4645                                                                   &rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table);
4646         ci_patch_clock_voltage_dependency_table_with_vddc_leakage(rdev,
4647                                                                   &rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table);
4648         ci_patch_vddc_phase_shed_limit_table_with_vddc_leakage(rdev,
4649                                                                &rdev->pm.dpm.dyn_state.phase_shedding_limits_table);
4650         ci_patch_clock_voltage_limits_with_vddc_leakage(rdev,
4651                                                         &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac);
4652         ci_patch_clock_voltage_limits_with_vddc_leakage(rdev,
4653                                                         &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc);
4654         ci_patch_cac_leakage_table_with_vddc_leakage(rdev,
4655                                                      &rdev->pm.dpm.dyn_state.cac_leakage_table);
4656
4657 }
4658
4659 static void ci_get_memory_type(struct radeon_device *rdev)
4660 {
4661         struct ci_power_info *pi = ci_get_pi(rdev);
4662         u32 tmp;
4663
4664         tmp = RREG32(MC_SEQ_MISC0);
4665
4666         if (((tmp & MC_SEQ_MISC0_GDDR5_MASK) >> MC_SEQ_MISC0_GDDR5_SHIFT) ==
4667             MC_SEQ_MISC0_GDDR5_VALUE)
4668                 pi->mem_gddr5 = true;
4669         else
4670                 pi->mem_gddr5 = false;
4671
4672 }
4673
4674 static void ci_update_current_ps(struct radeon_device *rdev,
4675                                  struct radeon_ps *rps)
4676 {
4677         struct ci_ps *new_ps = ci_get_ps(rps);
4678         struct ci_power_info *pi = ci_get_pi(rdev);
4679
4680         pi->current_rps = *rps;
4681         pi->current_ps = *new_ps;
4682         pi->current_rps.ps_priv = &pi->current_ps;
4683 }
4684
4685 static void ci_update_requested_ps(struct radeon_device *rdev,
4686                                    struct radeon_ps *rps)
4687 {
4688         struct ci_ps *new_ps = ci_get_ps(rps);
4689         struct ci_power_info *pi = ci_get_pi(rdev);
4690
4691         pi->requested_rps = *rps;
4692         pi->requested_ps = *new_ps;
4693         pi->requested_rps.ps_priv = &pi->requested_ps;
4694 }
4695
4696 int ci_dpm_pre_set_power_state(struct radeon_device *rdev)
4697 {
4698         struct ci_power_info *pi = ci_get_pi(rdev);
4699         struct radeon_ps requested_ps = *rdev->pm.dpm.requested_ps;
4700         struct radeon_ps *new_ps = &requested_ps;
4701
4702         ci_update_requested_ps(rdev, new_ps);
4703
4704         ci_apply_state_adjust_rules(rdev, &pi->requested_rps);
4705
4706         return 0;
4707 }
4708
4709 void ci_dpm_post_set_power_state(struct radeon_device *rdev)
4710 {
4711         struct ci_power_info *pi = ci_get_pi(rdev);
4712         struct radeon_ps *new_ps = &pi->requested_rps;
4713
4714         ci_update_current_ps(rdev, new_ps);
4715 }
4716
4717
4718 void ci_dpm_setup_asic(struct radeon_device *rdev)
4719 {
4720         int r;
4721
4722         r = ci_mc_load_microcode(rdev);
4723         if (r)
4724                 DRM_ERROR("Failed to load MC firmware!\n");
4725         ci_read_clock_registers(rdev);
4726         ci_get_memory_type(rdev);
4727         ci_enable_acpi_power_management(rdev);
4728         ci_init_sclk_t(rdev);
4729 }
4730
4731 int ci_dpm_enable(struct radeon_device *rdev)
4732 {
4733         struct ci_power_info *pi = ci_get_pi(rdev);
4734         struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;
4735         int ret;
4736
4737         if (ci_is_smc_running(rdev))
4738                 return -EINVAL;
4739         if (pi->voltage_control != CISLANDS_VOLTAGE_CONTROL_NONE) {
4740                 ci_enable_voltage_control(rdev);
4741                 ret = ci_construct_voltage_tables(rdev);
4742                 if (ret) {
4743                         DRM_ERROR("ci_construct_voltage_tables failed\n");
4744                         return ret;
4745                 }
4746         }
4747         if (pi->caps_dynamic_ac_timing) {
4748                 ret = ci_initialize_mc_reg_table(rdev);
4749                 if (ret)
4750                         pi->caps_dynamic_ac_timing = false;
4751         }
4752         if (pi->dynamic_ss)
4753                 ci_enable_spread_spectrum(rdev, true);
4754         if (pi->thermal_protection)
4755                 ci_enable_thermal_protection(rdev, true);
4756         ci_program_sstp(rdev);
4757         ci_enable_display_gap(rdev);
4758         ci_program_vc(rdev);
4759         ret = ci_upload_firmware(rdev);
4760         if (ret) {
4761                 DRM_ERROR("ci_upload_firmware failed\n");
4762                 return ret;
4763         }
4764         ret = ci_process_firmware_header(rdev);
4765         if (ret) {
4766                 DRM_ERROR("ci_process_firmware_header failed\n");
4767                 return ret;
4768         }
4769         ret = ci_initial_switch_from_arb_f0_to_f1(rdev);
4770         if (ret) {
4771                 DRM_ERROR("ci_initial_switch_from_arb_f0_to_f1 failed\n");
4772                 return ret;
4773         }
4774         ret = ci_init_smc_table(rdev);
4775         if (ret) {
4776                 DRM_ERROR("ci_init_smc_table failed\n");
4777                 return ret;
4778         }
4779         ret = ci_init_arb_table_index(rdev);
4780         if (ret) {
4781                 DRM_ERROR("ci_init_arb_table_index failed\n");
4782                 return ret;
4783         }
4784         if (pi->caps_dynamic_ac_timing) {
4785                 ret = ci_populate_initial_mc_reg_table(rdev);
4786                 if (ret) {
4787                         DRM_ERROR("ci_populate_initial_mc_reg_table failed\n");
4788                         return ret;
4789                 }
4790         }
4791         ret = ci_populate_pm_base(rdev);
4792         if (ret) {
4793                 DRM_ERROR("ci_populate_pm_base failed\n");
4794                 return ret;
4795         }
4796         ci_dpm_start_smc(rdev);
4797         ci_enable_vr_hot_gpio_interrupt(rdev);
4798         ret = ci_notify_smc_display_change(rdev, false);
4799         if (ret) {
4800                 DRM_ERROR("ci_notify_smc_display_change failed\n");
4801                 return ret;
4802         }
4803         ci_enable_sclk_control(rdev, true);
4804         ret = ci_enable_ulv(rdev, true);
4805         if (ret) {
4806                 DRM_ERROR("ci_enable_ulv failed\n");
4807                 return ret;
4808         }
4809         ret = ci_enable_ds_master_switch(rdev, true);
4810         if (ret) {
4811                 DRM_ERROR("ci_enable_ds_master_switch failed\n");
4812                 return ret;
4813         }
4814         ret = ci_start_dpm(rdev);
4815         if (ret) {
4816                 DRM_ERROR("ci_start_dpm failed\n");
4817                 return ret;
4818         }
4819         ret = ci_enable_didt(rdev, true);
4820         if (ret) {
4821                 DRM_ERROR("ci_enable_didt failed\n");
4822                 return ret;
4823         }
4824         ret = ci_enable_smc_cac(rdev, true);
4825         if (ret) {
4826                 DRM_ERROR("ci_enable_smc_cac failed\n");
4827                 return ret;
4828         }
4829         ret = ci_enable_power_containment(rdev, true);
4830         if (ret) {
4831                 DRM_ERROR("ci_enable_power_containment failed\n");
4832                 return ret;
4833         }
4834
4835         ci_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, true);
4836
4837         ci_update_current_ps(rdev, boot_ps);
4838
4839         return 0;
4840 }
4841
4842 static int ci_set_temperature_range(struct radeon_device *rdev)
4843 {
4844         int ret;
4845
4846         ret = ci_thermal_enable_alert(rdev, false);
4847         if (ret)
4848                 return ret;
4849         ret = ci_thermal_set_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
4850         if (ret)
4851                 return ret;
4852         ret = ci_thermal_enable_alert(rdev, true);
4853         if (ret)
4854                 return ret;
4855
4856         return ret;
4857 }
4858
4859 int ci_dpm_late_enable(struct radeon_device *rdev)
4860 {
4861         int ret;
4862
4863         ret = ci_set_temperature_range(rdev);
4864         if (ret)
4865                 return ret;
4866
4867         ci_dpm_powergate_uvd(rdev, true);
4868
4869         return 0;
4870 }
4871
4872 void ci_dpm_disable(struct radeon_device *rdev)
4873 {
4874         struct ci_power_info *pi = ci_get_pi(rdev);
4875         struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;
4876
4877         ci_dpm_powergate_uvd(rdev, false);
4878
4879         if (!ci_is_smc_running(rdev))
4880                 return;
4881
4882         if (pi->thermal_protection)
4883                 ci_enable_thermal_protection(rdev, false);
4884         ci_enable_power_containment(rdev, false);
4885         ci_enable_smc_cac(rdev, false);
4886         ci_enable_didt(rdev, false);
4887         ci_enable_spread_spectrum(rdev, false);
4888         ci_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, false);
4889         ci_stop_dpm(rdev);
4890         ci_enable_ds_master_switch(rdev, false);
4891         ci_enable_ulv(rdev, false);
4892         ci_clear_vc(rdev);
4893         ci_reset_to_default(rdev);
4894         ci_dpm_stop_smc(rdev);
4895         ci_force_switch_to_arb_f0(rdev);
4896
4897         ci_update_current_ps(rdev, boot_ps);
4898 }
4899
4900 int ci_dpm_set_power_state(struct radeon_device *rdev)
4901 {
4902         struct ci_power_info *pi = ci_get_pi(rdev);
4903         struct radeon_ps *new_ps = &pi->requested_rps;
4904         struct radeon_ps *old_ps = &pi->current_rps;
4905         int ret;
4906
4907         ci_find_dpm_states_clocks_in_dpm_table(rdev, new_ps);
4908         if (pi->pcie_performance_request)
4909                 ci_request_link_speed_change_before_state_change(rdev, new_ps, old_ps);
4910         ret = ci_freeze_sclk_mclk_dpm(rdev);
4911         if (ret) {
4912                 DRM_ERROR("ci_freeze_sclk_mclk_dpm failed\n");
4913                 return ret;
4914         }
4915         ret = ci_populate_and_upload_sclk_mclk_dpm_levels(rdev, new_ps);
4916         if (ret) {
4917                 DRM_ERROR("ci_populate_and_upload_sclk_mclk_dpm_levels failed\n");
4918                 return ret;
4919         }
4920         ret = ci_generate_dpm_level_enable_mask(rdev, new_ps);
4921         if (ret) {
4922                 DRM_ERROR("ci_generate_dpm_level_enable_mask failed\n");
4923                 return ret;
4924         }
4925
4926         ret = ci_update_vce_dpm(rdev, new_ps, old_ps);
4927         if (ret) {
4928                 DRM_ERROR("ci_update_vce_dpm failed\n");
4929                 return ret;
4930         }
4931
4932         ret = ci_update_sclk_t(rdev);
4933         if (ret) {
4934                 DRM_ERROR("ci_update_sclk_t failed\n");
4935                 return ret;
4936         }
4937         if (pi->caps_dynamic_ac_timing) {
4938                 ret = ci_update_and_upload_mc_reg_table(rdev);
4939                 if (ret) {
4940                         DRM_ERROR("ci_update_and_upload_mc_reg_table failed\n");
4941                         return ret;
4942                 }
4943         }
4944         ret = ci_program_memory_timing_parameters(rdev);
4945         if (ret) {
4946                 DRM_ERROR("ci_program_memory_timing_parameters failed\n");
4947                 return ret;
4948         }
4949         ret = ci_unfreeze_sclk_mclk_dpm(rdev);
4950         if (ret) {
4951                 DRM_ERROR("ci_unfreeze_sclk_mclk_dpm failed\n");
4952                 return ret;
4953         }
4954         ret = ci_upload_dpm_level_enable_mask(rdev);
4955         if (ret) {
4956                 DRM_ERROR("ci_upload_dpm_level_enable_mask failed\n");
4957                 return ret;
4958         }
4959         if (pi->pcie_performance_request)
4960                 ci_notify_link_speed_change_after_state_change(rdev, new_ps, old_ps);
4961
4962         return 0;
4963 }
4964
4965 int ci_dpm_power_control_set_level(struct radeon_device *rdev)
4966 {
4967         return ci_power_control_set_level(rdev);
4968 }
4969
4970 void ci_dpm_reset_asic(struct radeon_device *rdev)
4971 {
4972         ci_set_boot_state(rdev);
4973 }
4974
4975 void ci_dpm_display_configuration_changed(struct radeon_device *rdev)
4976 {
4977         ci_program_display_gap(rdev);
4978 }
4979
4980 union power_info {
4981         struct _ATOM_POWERPLAY_INFO info;
4982         struct _ATOM_POWERPLAY_INFO_V2 info_2;
4983         struct _ATOM_POWERPLAY_INFO_V3 info_3;
4984         struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
4985         struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
4986         struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
4987 };
4988
4989 union pplib_clock_info {
4990         struct _ATOM_PPLIB_R600_CLOCK_INFO r600;
4991         struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780;
4992         struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
4993         struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo;
4994         struct _ATOM_PPLIB_SI_CLOCK_INFO si;
4995         struct _ATOM_PPLIB_CI_CLOCK_INFO ci;
4996 };
4997
4998 union pplib_power_state {
4999         struct _ATOM_PPLIB_STATE v1;
5000         struct _ATOM_PPLIB_STATE_V2 v2;
5001 };
5002
5003 static void ci_parse_pplib_non_clock_info(struct radeon_device *rdev,
5004                                           struct radeon_ps *rps,
5005                                           struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info,
5006                                           u8 table_rev)
5007 {
5008         rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings);
5009         rps->class = le16_to_cpu(non_clock_info->usClassification);
5010         rps->class2 = le16_to_cpu(non_clock_info->usClassification2);
5011
5012         if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) {
5013                 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK);
5014                 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK);
5015         } else {
5016                 rps->vclk = 0;
5017                 rps->dclk = 0;
5018         }
5019
5020         if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT)
5021                 rdev->pm.dpm.boot_ps = rps;
5022         if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE)
5023                 rdev->pm.dpm.uvd_ps = rps;
5024 }
5025
5026 static void ci_parse_pplib_clock_info(struct radeon_device *rdev,
5027                                       struct radeon_ps *rps, int index,
5028                                       union pplib_clock_info *clock_info)
5029 {
5030         struct ci_power_info *pi = ci_get_pi(rdev);
5031         struct ci_ps *ps = ci_get_ps(rps);
5032         struct ci_pl *pl = &ps->performance_levels[index];
5033
5034         ps->performance_level_count = index + 1;
5035
5036         pl->sclk = le16_to_cpu(clock_info->ci.usEngineClockLow);
5037         pl->sclk |= clock_info->ci.ucEngineClockHigh << 16;
5038         pl->mclk = le16_to_cpu(clock_info->ci.usMemoryClockLow);
5039         pl->mclk |= clock_info->ci.ucMemoryClockHigh << 16;
5040
5041         pl->pcie_gen = r600_get_pcie_gen_support(rdev,
5042                                                  pi->sys_pcie_mask,
5043                                                  pi->vbios_boot_state.pcie_gen_bootup_value,
5044                                                  clock_info->ci.ucPCIEGen);
5045         pl->pcie_lane = r600_get_pcie_lane_support(rdev,
5046                                                    pi->vbios_boot_state.pcie_lane_bootup_value,
5047                                                    le16_to_cpu(clock_info->ci.usPCIELane));
5048
5049         if (rps->class & ATOM_PPLIB_CLASSIFICATION_ACPI) {
5050                 pi->acpi_pcie_gen = pl->pcie_gen;
5051         }
5052
5053         if (rps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV) {
5054                 pi->ulv.supported = true;
5055                 pi->ulv.pl = *pl;
5056                 pi->ulv.cg_ulv_parameter = CISLANDS_CGULVPARAMETER_DFLT;
5057         }
5058
5059         /* patch up boot state */
5060         if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) {
5061                 pl->mclk = pi->vbios_boot_state.mclk_bootup_value;
5062                 pl->sclk = pi->vbios_boot_state.sclk_bootup_value;
5063                 pl->pcie_gen = pi->vbios_boot_state.pcie_gen_bootup_value;
5064                 pl->pcie_lane = pi->vbios_boot_state.pcie_lane_bootup_value;
5065         }
5066
5067         switch (rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) {
5068         case ATOM_PPLIB_CLASSIFICATION_UI_BATTERY:
5069                 pi->use_pcie_powersaving_levels = true;
5070                 if (pi->pcie_gen_powersaving.max < pl->pcie_gen)
5071                         pi->pcie_gen_powersaving.max = pl->pcie_gen;
5072                 if (pi->pcie_gen_powersaving.min > pl->pcie_gen)
5073                         pi->pcie_gen_powersaving.min = pl->pcie_gen;
5074                 if (pi->pcie_lane_powersaving.max < pl->pcie_lane)
5075                         pi->pcie_lane_powersaving.max = pl->pcie_lane;
5076                 if (pi->pcie_lane_powersaving.min > pl->pcie_lane)
5077                         pi->pcie_lane_powersaving.min = pl->pcie_lane;
5078                 break;
5079         case ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE:
5080                 pi->use_pcie_performance_levels = true;
5081                 if (pi->pcie_gen_performance.max < pl->pcie_gen)
5082                         pi->pcie_gen_performance.max = pl->pcie_gen;
5083                 if (pi->pcie_gen_performance.min > pl->pcie_gen)
5084                         pi->pcie_gen_performance.min = pl->pcie_gen;
5085                 if (pi->pcie_lane_performance.max < pl->pcie_lane)
5086                         pi->pcie_lane_performance.max = pl->pcie_lane;
5087                 if (pi->pcie_lane_performance.min > pl->pcie_lane)
5088                         pi->pcie_lane_performance.min = pl->pcie_lane;
5089                 break;
5090         default:
5091                 break;
5092         }
5093 }
5094
5095 static int ci_parse_power_table(struct radeon_device *rdev)
5096 {
5097         struct radeon_mode_info *mode_info = &rdev->mode_info;
5098         struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
5099         union pplib_power_state *power_state;
5100         int i, j, k, non_clock_array_index, clock_array_index;
5101         union pplib_clock_info *clock_info;
5102         struct _StateArray *state_array;
5103         struct _ClockInfoArray *clock_info_array;
5104         struct _NonClockInfoArray *non_clock_info_array;
5105         union power_info *power_info;
5106         int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
5107         u16 data_offset;
5108         u8 frev, crev;
5109         u8 *power_state_offset;
5110         struct ci_ps *ps;
5111
5112         if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
5113                                    &frev, &crev, &data_offset))
5114                 return -EINVAL;
5115         power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
5116
5117         state_array = (struct _StateArray *)
5118                 (mode_info->atom_context->bios + data_offset +
5119                  le16_to_cpu(power_info->pplib.usStateArrayOffset));
5120         clock_info_array = (struct _ClockInfoArray *)
5121                 (mode_info->atom_context->bios + data_offset +
5122                  le16_to_cpu(power_info->pplib.usClockInfoArrayOffset));
5123         non_clock_info_array = (struct _NonClockInfoArray *)
5124                 (mode_info->atom_context->bios + data_offset +
5125                  le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset));
5126
5127         rdev->pm.dpm.ps = kzalloc(sizeof(struct radeon_ps) *
5128                                   state_array->ucNumEntries, GFP_KERNEL);
5129         if (!rdev->pm.dpm.ps)
5130                 return -ENOMEM;
5131         power_state_offset = (u8 *)state_array->states;
5132         for (i = 0; i < state_array->ucNumEntries; i++) {
5133                 u8 *idx;
5134                 power_state = (union pplib_power_state *)power_state_offset;
5135                 non_clock_array_index = power_state->v2.nonClockInfoIndex;
5136                 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
5137                         &non_clock_info_array->nonClockInfo[non_clock_array_index];
5138                 if (!rdev->pm.power_state[i].clock_info)
5139                         return -EINVAL;
5140                 ps = kzalloc(sizeof(struct ci_ps), GFP_KERNEL);
5141                 if (ps == NULL) {
5142                         kfree(rdev->pm.dpm.ps);
5143                         return -ENOMEM;
5144                 }
5145                 rdev->pm.dpm.ps[i].ps_priv = ps;
5146                 ci_parse_pplib_non_clock_info(rdev, &rdev->pm.dpm.ps[i],
5147                                               non_clock_info,
5148                                               non_clock_info_array->ucEntrySize);
5149                 k = 0;
5150                 idx = (u8 *)&power_state->v2.clockInfoIndex[0];
5151                 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) {
5152                         clock_array_index = idx[j];
5153                         if (clock_array_index >= clock_info_array->ucNumEntries)
5154                                 continue;
5155                         if (k >= CISLANDS_MAX_HARDWARE_POWERLEVELS)
5156                                 break;
5157                         clock_info = (union pplib_clock_info *)
5158                                 ((u8 *)&clock_info_array->clockInfo[0] +
5159                                  (clock_array_index * clock_info_array->ucEntrySize));
5160                         ci_parse_pplib_clock_info(rdev,
5161                                                   &rdev->pm.dpm.ps[i], k,
5162                                                   clock_info);
5163                         k++;
5164                 }
5165                 power_state_offset += 2 + power_state->v2.ucNumDPMLevels;
5166         }
5167         rdev->pm.dpm.num_ps = state_array->ucNumEntries;
5168
5169         /* fill in the vce power states */
5170         for (i = 0; i < RADEON_MAX_VCE_LEVELS; i++) {
5171                 u32 sclk, mclk;
5172                 clock_array_index = rdev->pm.dpm.vce_states[i].clk_idx;
5173                 clock_info = (union pplib_clock_info *)
5174                         &clock_info_array->clockInfo[clock_array_index * clock_info_array->ucEntrySize];
5175                 sclk = le16_to_cpu(clock_info->ci.usEngineClockLow);
5176                 sclk |= clock_info->ci.ucEngineClockHigh << 16;
5177                 mclk = le16_to_cpu(clock_info->ci.usMemoryClockLow);
5178                 mclk |= clock_info->ci.ucMemoryClockHigh << 16;
5179                 rdev->pm.dpm.vce_states[i].sclk = sclk;
5180                 rdev->pm.dpm.vce_states[i].mclk = mclk;
5181         }
5182
5183         return 0;
5184 }
5185
5186 static int ci_get_vbios_boot_values(struct radeon_device *rdev,
5187                                     struct ci_vbios_boot_state *boot_state)
5188 {
5189         struct radeon_mode_info *mode_info = &rdev->mode_info;
5190         int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
5191         ATOM_FIRMWARE_INFO_V2_2 *firmware_info;
5192         u8 frev, crev;
5193         u16 data_offset;
5194
5195         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
5196                                    &frev, &crev, &data_offset)) {
5197                 firmware_info =
5198                         (ATOM_FIRMWARE_INFO_V2_2 *)(mode_info->atom_context->bios +
5199                                                     data_offset);
5200                 boot_state->mvdd_bootup_value = le16_to_cpu(firmware_info->usBootUpMVDDCVoltage);
5201                 boot_state->vddc_bootup_value = le16_to_cpu(firmware_info->usBootUpVDDCVoltage);
5202                 boot_state->vddci_bootup_value = le16_to_cpu(firmware_info->usBootUpVDDCIVoltage);
5203                 boot_state->pcie_gen_bootup_value = ci_get_current_pcie_speed(rdev);
5204                 boot_state->pcie_lane_bootup_value = ci_get_current_pcie_lane_number(rdev);
5205                 boot_state->sclk_bootup_value = le32_to_cpu(firmware_info->ulDefaultEngineClock);
5206                 boot_state->mclk_bootup_value = le32_to_cpu(firmware_info->ulDefaultMemoryClock);
5207
5208                 return 0;
5209         }
5210         return -EINVAL;
5211 }
5212
5213 void ci_dpm_fini(struct radeon_device *rdev)
5214 {
5215         int i;
5216
5217         for (i = 0; i < rdev->pm.dpm.num_ps; i++) {
5218                 kfree(rdev->pm.dpm.ps[i].ps_priv);
5219         }
5220         kfree(rdev->pm.dpm.ps);
5221         kfree(rdev->pm.dpm.priv);
5222         kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries);
5223         r600_free_extended_power_table(rdev);
5224 }
5225
5226 int ci_dpm_init(struct radeon_device *rdev)
5227 {
5228         int index = GetIndexIntoMasterTable(DATA, ASIC_InternalSS_Info);
5229         SMU7_Discrete_DpmTable  *dpm_table;
5230         struct radeon_gpio_rec gpio;
5231         u16 data_offset, size;
5232         u8 frev, crev;
5233         struct ci_power_info *pi;
5234         int ret;
5235         u32 mask;
5236
5237         pi = kzalloc(sizeof(struct ci_power_info), GFP_KERNEL);
5238         if (pi == NULL)
5239                 return -ENOMEM;
5240         rdev->pm.dpm.priv = pi;
5241
5242         ret = drm_pcie_get_speed_cap_mask(rdev->ddev, &mask);
5243         if (ret)
5244                 pi->sys_pcie_mask = 0;
5245         else
5246                 pi->sys_pcie_mask = mask;
5247         pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID;
5248
5249         pi->pcie_gen_performance.max = RADEON_PCIE_GEN1;
5250         pi->pcie_gen_performance.min = RADEON_PCIE_GEN3;
5251         pi->pcie_gen_powersaving.max = RADEON_PCIE_GEN1;
5252         pi->pcie_gen_powersaving.min = RADEON_PCIE_GEN3;
5253
5254         pi->pcie_lane_performance.max = 0;
5255         pi->pcie_lane_performance.min = 16;
5256         pi->pcie_lane_powersaving.max = 0;
5257         pi->pcie_lane_powersaving.min = 16;
5258
5259         ret = ci_get_vbios_boot_values(rdev, &pi->vbios_boot_state);
5260         if (ret) {
5261                 ci_dpm_fini(rdev);
5262                 return ret;
5263         }
5264
5265         ret = r600_get_platform_caps(rdev);
5266         if (ret) {
5267                 ci_dpm_fini(rdev);
5268                 return ret;
5269         }
5270
5271         ret = r600_parse_extended_power_table(rdev);
5272         if (ret) {
5273                 ci_dpm_fini(rdev);
5274                 return ret;
5275         }
5276
5277         ret = ci_parse_power_table(rdev);
5278         if (ret) {
5279                 ci_dpm_fini(rdev);
5280                 return ret;
5281         }
5282
5283         pi->dll_default_on = false;
5284         pi->sram_end = SMC_RAM_END;
5285
5286         pi->activity_target[0] = CISLAND_TARGETACTIVITY_DFLT;
5287         pi->activity_target[1] = CISLAND_TARGETACTIVITY_DFLT;
5288         pi->activity_target[2] = CISLAND_TARGETACTIVITY_DFLT;
5289         pi->activity_target[3] = CISLAND_TARGETACTIVITY_DFLT;
5290         pi->activity_target[4] = CISLAND_TARGETACTIVITY_DFLT;
5291         pi->activity_target[5] = CISLAND_TARGETACTIVITY_DFLT;
5292         pi->activity_target[6] = CISLAND_TARGETACTIVITY_DFLT;
5293         pi->activity_target[7] = CISLAND_TARGETACTIVITY_DFLT;
5294
5295         pi->mclk_activity_target = CISLAND_MCLK_TARGETACTIVITY_DFLT;
5296
5297         pi->sclk_dpm_key_disabled = 0;
5298         pi->mclk_dpm_key_disabled = 0;
5299         pi->pcie_dpm_key_disabled = 0;
5300
5301         /* mclk dpm is unstable on some R7 260X cards with the old mc ucode */
5302         if ((rdev->pdev->device == 0x6658) &&
5303             (rdev->mc_fw->size == (BONAIRE_MC_UCODE_SIZE * 4))) {
5304                 pi->mclk_dpm_key_disabled = 1;
5305         }
5306
5307         pi->caps_sclk_ds = true;
5308
5309         pi->mclk_strobe_mode_threshold = 40000;
5310         pi->mclk_stutter_mode_threshold = 40000;
5311         pi->mclk_edc_enable_threshold = 40000;
5312         pi->mclk_edc_wr_enable_threshold = 40000;
5313
5314         ci_initialize_powertune_defaults(rdev);
5315
5316         pi->caps_fps = false;
5317
5318         pi->caps_sclk_throttle_low_notification = false;
5319
5320         pi->caps_uvd_dpm = true;
5321         pi->caps_vce_dpm = true;
5322
5323         ci_get_leakage_voltages(rdev);
5324         ci_patch_dependency_tables_with_leakage(rdev);
5325         ci_set_private_data_variables_based_on_pptable(rdev);
5326
5327         rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries =
5328                 kzalloc(4 * sizeof(struct radeon_clock_voltage_dependency_entry), GFP_KERNEL);
5329         if (!rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries) {
5330                 ci_dpm_fini(rdev);
5331                 return -ENOMEM;
5332         }
5333         rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count = 4;
5334         rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].clk = 0;
5335         rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].v = 0;
5336         rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].clk = 36000;
5337         rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].v = 720;
5338         rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].clk = 54000;
5339         rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].v = 810;
5340         rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].clk = 72000;
5341         rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].v = 900;
5342
5343         rdev->pm.dpm.dyn_state.mclk_sclk_ratio = 4;
5344         rdev->pm.dpm.dyn_state.sclk_mclk_delta = 15000;
5345         rdev->pm.dpm.dyn_state.vddc_vddci_delta = 200;
5346
5347         rdev->pm.dpm.dyn_state.valid_sclk_values.count = 0;
5348         rdev->pm.dpm.dyn_state.valid_sclk_values.values = NULL;
5349         rdev->pm.dpm.dyn_state.valid_mclk_values.count = 0;
5350         rdev->pm.dpm.dyn_state.valid_mclk_values.values = NULL;
5351
5352         if (rdev->family == CHIP_HAWAII) {
5353                 pi->thermal_temp_setting.temperature_low = 94500;
5354                 pi->thermal_temp_setting.temperature_high = 95000;
5355                 pi->thermal_temp_setting.temperature_shutdown = 104000;
5356         } else {
5357                 pi->thermal_temp_setting.temperature_low = 99500;
5358                 pi->thermal_temp_setting.temperature_high = 100000;
5359                 pi->thermal_temp_setting.temperature_shutdown = 104000;
5360         }
5361
5362         pi->uvd_enabled = false;
5363
5364         dpm_table = &pi->smc_state_table;
5365
5366         gpio = radeon_atombios_lookup_gpio(rdev, VDDC_VRHOT_GPIO_PINID);
5367         if (gpio.valid) {
5368                 dpm_table->VRHotGpio = gpio.shift;
5369                 rdev->pm.dpm.platform_caps |= ATOM_PP_PLATFORM_CAP_REGULATOR_HOT;
5370         } else {
5371                 dpm_table->VRHotGpio = CISLANDS_UNUSED_GPIO_PIN;
5372                 rdev->pm.dpm.platform_caps &= ~ATOM_PP_PLATFORM_CAP_REGULATOR_HOT;
5373         }
5374
5375         gpio = radeon_atombios_lookup_gpio(rdev, PP_AC_DC_SWITCH_GPIO_PINID);
5376         if (gpio.valid) {
5377                 dpm_table->AcDcGpio = gpio.shift;
5378                 rdev->pm.dpm.platform_caps |= ATOM_PP_PLATFORM_CAP_HARDWAREDC;
5379         } else {
5380                 dpm_table->AcDcGpio = CISLANDS_UNUSED_GPIO_PIN;
5381                 rdev->pm.dpm.platform_caps &= ~ATOM_PP_PLATFORM_CAP_HARDWAREDC;
5382         }
5383
5384         gpio = radeon_atombios_lookup_gpio(rdev, VDDC_PCC_GPIO_PINID);
5385         if (gpio.valid) {
5386                 u32 tmp = RREG32_SMC(CNB_PWRMGT_CNTL);
5387
5388                 switch (gpio.shift) {
5389                 case 0:
5390                         tmp &= ~GNB_SLOW_MODE_MASK;
5391                         tmp |= GNB_SLOW_MODE(1);
5392                         break;
5393                 case 1:
5394                         tmp &= ~GNB_SLOW_MODE_MASK;
5395                         tmp |= GNB_SLOW_MODE(2);
5396                         break;
5397                 case 2:
5398                         tmp |= GNB_SLOW;
5399                         break;
5400                 case 3:
5401                         tmp |= FORCE_NB_PS1;
5402                         break;
5403                 case 4:
5404                         tmp |= DPM_ENABLED;
5405                         break;
5406                 default:
5407                         DRM_ERROR("Invalid PCC GPIO!");
5408                         break;
5409                 }
5410                 WREG32_SMC(CNB_PWRMGT_CNTL, tmp);
5411         }
5412
5413         pi->voltage_control = CISLANDS_VOLTAGE_CONTROL_NONE;
5414         pi->vddci_control = CISLANDS_VOLTAGE_CONTROL_NONE;
5415         pi->mvdd_control = CISLANDS_VOLTAGE_CONTROL_NONE;
5416         if (radeon_atom_is_voltage_gpio(rdev, VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_GPIO_LUT))
5417                 pi->voltage_control = CISLANDS_VOLTAGE_CONTROL_BY_GPIO;
5418         else if (radeon_atom_is_voltage_gpio(rdev, VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_SVID2))
5419                 pi->voltage_control = CISLANDS_VOLTAGE_CONTROL_BY_SVID2;
5420
5421         if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_VDDCI_CONTROL) {
5422                 if (radeon_atom_is_voltage_gpio(rdev, VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT))
5423                         pi->vddci_control = CISLANDS_VOLTAGE_CONTROL_BY_GPIO;
5424                 else if (radeon_atom_is_voltage_gpio(rdev, VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_SVID2))
5425                         pi->vddci_control = CISLANDS_VOLTAGE_CONTROL_BY_SVID2;
5426                 else
5427                         rdev->pm.dpm.platform_caps &= ~ATOM_PP_PLATFORM_CAP_VDDCI_CONTROL;
5428         }
5429
5430         if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_MVDDCONTROL) {
5431                 if (radeon_atom_is_voltage_gpio(rdev, VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_GPIO_LUT))
5432                         pi->mvdd_control = CISLANDS_VOLTAGE_CONTROL_BY_GPIO;
5433                 else if (radeon_atom_is_voltage_gpio(rdev, VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_SVID2))
5434                         pi->mvdd_control = CISLANDS_VOLTAGE_CONTROL_BY_SVID2;
5435                 else
5436                         rdev->pm.dpm.platform_caps &= ~ATOM_PP_PLATFORM_CAP_MVDDCONTROL;
5437         }
5438
5439         pi->vddc_phase_shed_control = true;
5440
5441 #if defined(CONFIG_ACPI)
5442         pi->pcie_performance_request =
5443                 radeon_acpi_is_pcie_performance_request_supported(rdev);
5444 #else
5445         pi->pcie_performance_request = false;
5446 #endif
5447
5448         if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
5449                                    &frev, &crev, &data_offset)) {
5450                 pi->caps_sclk_ss_support = true;
5451                 pi->caps_mclk_ss_support = true;
5452                 pi->dynamic_ss = true;
5453         } else {
5454                 pi->caps_sclk_ss_support = false;
5455                 pi->caps_mclk_ss_support = false;
5456                 pi->dynamic_ss = true;
5457         }
5458
5459         if (rdev->pm.int_thermal_type != THERMAL_TYPE_NONE)
5460                 pi->thermal_protection = true;
5461         else
5462                 pi->thermal_protection = false;
5463
5464         pi->caps_dynamic_ac_timing = true;
5465
5466         pi->uvd_power_gated = false;
5467
5468         /* make sure dc limits are valid */
5469         if ((rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk == 0) ||
5470             (rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk == 0))
5471                 rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc =
5472                         rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
5473
5474         return 0;
5475 }
5476
5477 void ci_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
5478                                                     struct seq_file *m)
5479 {
5480         struct ci_power_info *pi = ci_get_pi(rdev);
5481         struct radeon_ps *rps = &pi->current_rps;
5482         u32 sclk = ci_get_average_sclk_freq(rdev);
5483         u32 mclk = ci_get_average_mclk_freq(rdev);
5484
5485         seq_printf(m, "uvd    %sabled\n", pi->uvd_enabled ? "en" : "dis");
5486         seq_printf(m, "vce    %sabled\n", rps->vce_active ? "en" : "dis");
5487         seq_printf(m, "power level avg    sclk: %u mclk: %u\n",
5488                    sclk, mclk);
5489 }
5490
5491 void ci_dpm_print_power_state(struct radeon_device *rdev,
5492                               struct radeon_ps *rps)
5493 {
5494         struct ci_ps *ps = ci_get_ps(rps);
5495         struct ci_pl *pl;
5496         int i;
5497
5498         r600_dpm_print_class_info(rps->class, rps->class2);
5499         r600_dpm_print_cap_info(rps->caps);
5500         printk("\tuvd    vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
5501         for (i = 0; i < ps->performance_level_count; i++) {
5502                 pl = &ps->performance_levels[i];
5503                 printk("\t\tpower level %d    sclk: %u mclk: %u pcie gen: %u pcie lanes: %u\n",
5504                        i, pl->sclk, pl->mclk, pl->pcie_gen + 1, pl->pcie_lane);
5505         }
5506         r600_dpm_print_ps_status(rdev, rps);
5507 }
5508
5509 u32 ci_dpm_get_sclk(struct radeon_device *rdev, bool low)
5510 {
5511         struct ci_power_info *pi = ci_get_pi(rdev);
5512         struct ci_ps *requested_state = ci_get_ps(&pi->requested_rps);
5513
5514         if (low)
5515                 return requested_state->performance_levels[0].sclk;
5516         else
5517                 return requested_state->performance_levels[requested_state->performance_level_count - 1].sclk;
5518 }
5519
5520 u32 ci_dpm_get_mclk(struct radeon_device *rdev, bool low)
5521 {
5522         struct ci_power_info *pi = ci_get_pi(rdev);
5523         struct ci_ps *requested_state = ci_get_ps(&pi->requested_rps);
5524
5525         if (low)
5526                 return requested_state->performance_levels[0].mclk;
5527         else
5528                 return requested_state->performance_levels[requested_state->performance_level_count - 1].mclk;
5529 }