2 * Copyright 2013 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
24 #include <linux/firmware.h>
27 #include "radeon_asic.h"
28 #include "radeon_ucode.h"
33 #include <linux/seq_file.h>
35 #define MC_CG_ARB_FREQ_F0 0x0a
36 #define MC_CG_ARB_FREQ_F1 0x0b
37 #define MC_CG_ARB_FREQ_F2 0x0c
38 #define MC_CG_ARB_FREQ_F3 0x0d
40 #define SMC_RAM_END 0x40000
42 #define VOLTAGE_SCALE 4
43 #define VOLTAGE_VID_OFFSET_SCALE1 625
44 #define VOLTAGE_VID_OFFSET_SCALE2 100
46 static const struct ci_pt_defaults defaults_hawaii_xt =
48 1, 0xF, 0xFD, 0x19, 5, 0x14, 0, 0xB0000,
49 { 0x84, 0x0, 0x0, 0x7F, 0x0, 0x0, 0x5A, 0x60, 0x51, 0x8E, 0x79, 0x6B, 0x5F, 0x90, 0x79 },
50 { 0x1EA, 0x1EA, 0x1EA, 0x224, 0x224, 0x224, 0x24F, 0x24F, 0x24F, 0x28E, 0x28E, 0x28E, 0x2BC, 0x2BC, 0x2BC }
53 static const struct ci_pt_defaults defaults_hawaii_pro =
55 1, 0xF, 0xFD, 0x19, 5, 0x14, 0, 0x65062,
56 { 0x93, 0x0, 0x0, 0x97, 0x0, 0x0, 0x6B, 0x60, 0x51, 0x95, 0x79, 0x6B, 0x5F, 0x90, 0x79 },
57 { 0x1EA, 0x1EA, 0x1EA, 0x224, 0x224, 0x224, 0x24F, 0x24F, 0x24F, 0x28E, 0x28E, 0x28E, 0x2BC, 0x2BC, 0x2BC }
60 static const struct ci_pt_defaults defaults_bonaire_xt =
62 1, 0xF, 0xFD, 0x19, 5, 45, 0, 0xB0000,
63 { 0x79, 0x253, 0x25D, 0xAE, 0x72, 0x80, 0x83, 0x86, 0x6F, 0xC8, 0xC9, 0xC9, 0x2F, 0x4D, 0x61 },
64 { 0x17C, 0x172, 0x180, 0x1BC, 0x1B3, 0x1BD, 0x206, 0x200, 0x203, 0x25D, 0x25A, 0x255, 0x2C3, 0x2C5, 0x2B4 }
67 static const struct ci_pt_defaults defaults_bonaire_pro =
69 1, 0xF, 0xFD, 0x19, 5, 45, 0, 0x65062,
70 { 0x8C, 0x23F, 0x244, 0xA6, 0x83, 0x85, 0x86, 0x86, 0x83, 0xDB, 0xDB, 0xDA, 0x67, 0x60, 0x5F },
71 { 0x187, 0x193, 0x193, 0x1C7, 0x1D1, 0x1D1, 0x210, 0x219, 0x219, 0x266, 0x26C, 0x26C, 0x2C9, 0x2CB, 0x2CB }
74 static const struct ci_pt_defaults defaults_saturn_xt =
76 1, 0xF, 0xFD, 0x19, 5, 55, 0, 0x70000,
77 { 0x8C, 0x247, 0x249, 0xA6, 0x80, 0x81, 0x8B, 0x89, 0x86, 0xC9, 0xCA, 0xC9, 0x4D, 0x4D, 0x4D },
78 { 0x187, 0x187, 0x187, 0x1C7, 0x1C7, 0x1C7, 0x210, 0x210, 0x210, 0x266, 0x266, 0x266, 0x2C9, 0x2C9, 0x2C9 }
81 static const struct ci_pt_defaults defaults_saturn_pro =
83 1, 0xF, 0xFD, 0x19, 5, 55, 0, 0x30000,
84 { 0x96, 0x21D, 0x23B, 0xA1, 0x85, 0x87, 0x83, 0x84, 0x81, 0xE6, 0xE6, 0xE6, 0x71, 0x6A, 0x6A },
85 { 0x193, 0x19E, 0x19E, 0x1D2, 0x1DC, 0x1DC, 0x21A, 0x223, 0x223, 0x26E, 0x27E, 0x274, 0x2CF, 0x2D2, 0x2D2 }
88 static const struct ci_pt_config_reg didt_config_ci[] =
90 { 0x10, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
91 { 0x10, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
92 { 0x10, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
93 { 0x10, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
94 { 0x11, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
95 { 0x11, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
96 { 0x11, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
97 { 0x11, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
98 { 0x12, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
99 { 0x12, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
100 { 0x12, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
101 { 0x12, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
102 { 0x2, 0x00003fff, 0, 0x4, CISLANDS_CONFIGREG_DIDT_IND },
103 { 0x2, 0x03ff0000, 16, 0x80, CISLANDS_CONFIGREG_DIDT_IND },
104 { 0x2, 0x78000000, 27, 0x3, CISLANDS_CONFIGREG_DIDT_IND },
105 { 0x1, 0x0000ffff, 0, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
106 { 0x1, 0xffff0000, 16, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
107 { 0x0, 0x00000001, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
108 { 0x30, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
109 { 0x30, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
110 { 0x30, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
111 { 0x30, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
112 { 0x31, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
113 { 0x31, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
114 { 0x31, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
115 { 0x31, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
116 { 0x32, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
117 { 0x32, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
118 { 0x32, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
119 { 0x32, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
120 { 0x22, 0x00003fff, 0, 0x4, CISLANDS_CONFIGREG_DIDT_IND },
121 { 0x22, 0x03ff0000, 16, 0x80, CISLANDS_CONFIGREG_DIDT_IND },
122 { 0x22, 0x78000000, 27, 0x3, CISLANDS_CONFIGREG_DIDT_IND },
123 { 0x21, 0x0000ffff, 0, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
124 { 0x21, 0xffff0000, 16, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
125 { 0x20, 0x00000001, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
126 { 0x50, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
127 { 0x50, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
128 { 0x50, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
129 { 0x50, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
130 { 0x51, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
131 { 0x51, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
132 { 0x51, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
133 { 0x51, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
134 { 0x52, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
135 { 0x52, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
136 { 0x52, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
137 { 0x52, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
138 { 0x42, 0x00003fff, 0, 0x4, CISLANDS_CONFIGREG_DIDT_IND },
139 { 0x42, 0x03ff0000, 16, 0x80, CISLANDS_CONFIGREG_DIDT_IND },
140 { 0x42, 0x78000000, 27, 0x3, CISLANDS_CONFIGREG_DIDT_IND },
141 { 0x41, 0x0000ffff, 0, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
142 { 0x41, 0xffff0000, 16, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
143 { 0x40, 0x00000001, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
144 { 0x70, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
145 { 0x70, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
146 { 0x70, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
147 { 0x70, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
148 { 0x71, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
149 { 0x71, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
150 { 0x71, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
151 { 0x71, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
152 { 0x72, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
153 { 0x72, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
154 { 0x72, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
155 { 0x72, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
156 { 0x62, 0x00003fff, 0, 0x4, CISLANDS_CONFIGREG_DIDT_IND },
157 { 0x62, 0x03ff0000, 16, 0x80, CISLANDS_CONFIGREG_DIDT_IND },
158 { 0x62, 0x78000000, 27, 0x3, CISLANDS_CONFIGREG_DIDT_IND },
159 { 0x61, 0x0000ffff, 0, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
160 { 0x61, 0xffff0000, 16, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
161 { 0x60, 0x00000001, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
165 extern u8 rv770_get_memory_module_index(struct radeon_device *rdev);
166 extern int ni_copy_and_switch_arb_sets(struct radeon_device *rdev,
167 u32 arb_freq_src, u32 arb_freq_dest);
168 extern u8 si_get_ddr3_mclk_frequency_ratio(u32 memory_clock);
169 extern u8 si_get_mclk_frequency_ratio(u32 memory_clock, bool strobe_mode);
170 extern void si_trim_voltage_table_to_fit_state_table(struct radeon_device *rdev,
171 u32 max_voltage_steps,
172 struct atom_voltage_table *voltage_table);
173 extern void cik_enter_rlc_safe_mode(struct radeon_device *rdev);
174 extern void cik_exit_rlc_safe_mode(struct radeon_device *rdev);
175 extern int ci_mc_load_microcode(struct radeon_device *rdev);
176 extern void cik_update_cg(struct radeon_device *rdev,
177 u32 block, bool enable);
179 static int ci_get_std_voltage_value_sidd(struct radeon_device *rdev,
180 struct atom_voltage_table_entry *voltage_table,
181 u16 *std_voltage_hi_sidd, u16 *std_voltage_lo_sidd);
182 static int ci_set_power_limit(struct radeon_device *rdev, u32 n);
183 static int ci_set_overdrive_target_tdp(struct radeon_device *rdev,
185 static int ci_update_uvd_dpm(struct radeon_device *rdev, bool gate);
187 static struct ci_power_info *ci_get_pi(struct radeon_device *rdev)
189 struct ci_power_info *pi = rdev->pm.dpm.priv;
194 static struct ci_ps *ci_get_ps(struct radeon_ps *rps)
196 struct ci_ps *ps = rps->ps_priv;
201 static void ci_initialize_powertune_defaults(struct radeon_device *rdev)
203 struct ci_power_info *pi = ci_get_pi(rdev);
205 switch (rdev->pdev->device) {
213 pi->powertune_defaults = &defaults_bonaire_xt;
219 pi->powertune_defaults = &defaults_saturn_xt;
223 pi->powertune_defaults = &defaults_hawaii_xt;
227 pi->powertune_defaults = &defaults_hawaii_pro;
237 pi->powertune_defaults = &defaults_bonaire_xt;
241 pi->dte_tj_offset = 0;
243 pi->caps_power_containment = true;
244 pi->caps_cac = false;
245 pi->caps_sq_ramping = false;
246 pi->caps_db_ramping = false;
247 pi->caps_td_ramping = false;
248 pi->caps_tcp_ramping = false;
250 if (pi->caps_power_containment) {
252 pi->enable_bapm_feature = true;
253 pi->enable_tdc_limit_feature = true;
254 pi->enable_pkg_pwr_tracking_feature = true;
258 static u8 ci_convert_to_vid(u16 vddc)
260 return (6200 - (vddc * VOLTAGE_SCALE)) / 25;
263 static int ci_populate_bapm_vddc_vid_sidd(struct radeon_device *rdev)
265 struct ci_power_info *pi = ci_get_pi(rdev);
266 u8 *hi_vid = pi->smc_powertune_table.BapmVddCVidHiSidd;
267 u8 *lo_vid = pi->smc_powertune_table.BapmVddCVidLoSidd;
268 u8 *hi2_vid = pi->smc_powertune_table.BapmVddCVidHiSidd2;
271 if (rdev->pm.dpm.dyn_state.cac_leakage_table.entries == NULL)
273 if (rdev->pm.dpm.dyn_state.cac_leakage_table.count > 8)
275 if (rdev->pm.dpm.dyn_state.cac_leakage_table.count !=
276 rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count)
279 for (i = 0; i < rdev->pm.dpm.dyn_state.cac_leakage_table.count; i++) {
280 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_EVV) {
281 lo_vid[i] = ci_convert_to_vid(rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc1);
282 hi_vid[i] = ci_convert_to_vid(rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc2);
283 hi2_vid[i] = ci_convert_to_vid(rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc3);
285 lo_vid[i] = ci_convert_to_vid(rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc);
286 hi_vid[i] = ci_convert_to_vid((u16)rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].leakage);
292 static int ci_populate_vddc_vid(struct radeon_device *rdev)
294 struct ci_power_info *pi = ci_get_pi(rdev);
295 u8 *vid = pi->smc_powertune_table.VddCVid;
298 if (pi->vddc_voltage_table.count > 8)
301 for (i = 0; i < pi->vddc_voltage_table.count; i++)
302 vid[i] = ci_convert_to_vid(pi->vddc_voltage_table.entries[i].value);
307 static int ci_populate_svi_load_line(struct radeon_device *rdev)
309 struct ci_power_info *pi = ci_get_pi(rdev);
310 const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults;
312 pi->smc_powertune_table.SviLoadLineEn = pt_defaults->svi_load_line_en;
313 pi->smc_powertune_table.SviLoadLineVddC = pt_defaults->svi_load_line_vddc;
314 pi->smc_powertune_table.SviLoadLineTrimVddC = 3;
315 pi->smc_powertune_table.SviLoadLineOffsetVddC = 0;
320 static int ci_populate_tdc_limit(struct radeon_device *rdev)
322 struct ci_power_info *pi = ci_get_pi(rdev);
323 const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults;
326 tdc_limit = rdev->pm.dpm.dyn_state.cac_tdp_table->tdc * 256;
327 pi->smc_powertune_table.TDC_VDDC_PkgLimit = cpu_to_be16(tdc_limit);
328 pi->smc_powertune_table.TDC_VDDC_ThrottleReleaseLimitPerc =
329 pt_defaults->tdc_vddc_throttle_release_limit_perc;
330 pi->smc_powertune_table.TDC_MAWt = pt_defaults->tdc_mawt;
335 static int ci_populate_dw8(struct radeon_device *rdev)
337 struct ci_power_info *pi = ci_get_pi(rdev);
338 const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults;
341 ret = ci_read_smc_sram_dword(rdev,
342 SMU7_FIRMWARE_HEADER_LOCATION +
343 offsetof(SMU7_Firmware_Header, PmFuseTable) +
344 offsetof(SMU7_Discrete_PmFuses, TdcWaterfallCtl),
345 (u32 *)&pi->smc_powertune_table.TdcWaterfallCtl,
350 pi->smc_powertune_table.TdcWaterfallCtl = pt_defaults->tdc_waterfall_ctl;
355 static int ci_min_max_v_gnbl_pm_lid_from_bapm_vddc(struct radeon_device *rdev)
357 struct ci_power_info *pi = ci_get_pi(rdev);
358 u8 *hi_vid = pi->smc_powertune_table.BapmVddCVidHiSidd;
359 u8 *lo_vid = pi->smc_powertune_table.BapmVddCVidLoSidd;
362 min = max = hi_vid[0];
363 for (i = 0; i < 8; i++) {
364 if (0 != hi_vid[i]) {
371 if (0 != lo_vid[i]) {
379 if ((min == 0) || (max == 0))
381 pi->smc_powertune_table.GnbLPMLMaxVid = (u8)max;
382 pi->smc_powertune_table.GnbLPMLMinVid = (u8)min;
387 static int ci_populate_bapm_vddc_base_leakage_sidd(struct radeon_device *rdev)
389 struct ci_power_info *pi = ci_get_pi(rdev);
390 u16 hi_sidd = pi->smc_powertune_table.BapmVddCBaseLeakageHiSidd;
391 u16 lo_sidd = pi->smc_powertune_table.BapmVddCBaseLeakageLoSidd;
392 struct radeon_cac_tdp_table *cac_tdp_table =
393 rdev->pm.dpm.dyn_state.cac_tdp_table;
395 hi_sidd = cac_tdp_table->high_cac_leakage / 100 * 256;
396 lo_sidd = cac_tdp_table->low_cac_leakage / 100 * 256;
398 pi->smc_powertune_table.BapmVddCBaseLeakageHiSidd = cpu_to_be16(hi_sidd);
399 pi->smc_powertune_table.BapmVddCBaseLeakageLoSidd = cpu_to_be16(lo_sidd);
404 static int ci_populate_bapm_parameters_in_dpm_table(struct radeon_device *rdev)
406 struct ci_power_info *pi = ci_get_pi(rdev);
407 const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults;
408 SMU7_Discrete_DpmTable *dpm_table = &pi->smc_state_table;
409 struct radeon_cac_tdp_table *cac_tdp_table =
410 rdev->pm.dpm.dyn_state.cac_tdp_table;
411 struct radeon_ppm_table *ppm = rdev->pm.dpm.dyn_state.ppm_table;
416 dpm_table->DefaultTdp = cac_tdp_table->tdp * 256;
417 dpm_table->TargetTdp = cac_tdp_table->configurable_tdp * 256;
419 dpm_table->DTETjOffset = (u8)pi->dte_tj_offset;
420 dpm_table->GpuTjMax =
421 (u8)(pi->thermal_temp_setting.temperature_high / 1000);
422 dpm_table->GpuTjHyst = 8;
424 dpm_table->DTEAmbientTempBase = pt_defaults->dte_ambient_temp_base;
427 dpm_table->PPM_PkgPwrLimit = cpu_to_be16((u16)ppm->dgpu_tdp * 256 / 1000);
428 dpm_table->PPM_TemperatureLimit = cpu_to_be16((u16)ppm->tj_max * 256);
430 dpm_table->PPM_PkgPwrLimit = cpu_to_be16(0);
431 dpm_table->PPM_TemperatureLimit = cpu_to_be16(0);
434 dpm_table->BAPM_TEMP_GRADIENT = cpu_to_be32(pt_defaults->bapm_temp_gradient);
435 def1 = pt_defaults->bapmti_r;
436 def2 = pt_defaults->bapmti_rc;
438 for (i = 0; i < SMU7_DTE_ITERATIONS; i++) {
439 for (j = 0; j < SMU7_DTE_SOURCES; j++) {
440 for (k = 0; k < SMU7_DTE_SINKS; k++) {
441 dpm_table->BAPMTI_R[i][j][k] = cpu_to_be16(*def1);
442 dpm_table->BAPMTI_RC[i][j][k] = cpu_to_be16(*def2);
452 static int ci_populate_pm_base(struct radeon_device *rdev)
454 struct ci_power_info *pi = ci_get_pi(rdev);
455 u32 pm_fuse_table_offset;
458 if (pi->caps_power_containment) {
459 ret = ci_read_smc_sram_dword(rdev,
460 SMU7_FIRMWARE_HEADER_LOCATION +
461 offsetof(SMU7_Firmware_Header, PmFuseTable),
462 &pm_fuse_table_offset, pi->sram_end);
465 ret = ci_populate_bapm_vddc_vid_sidd(rdev);
468 ret = ci_populate_vddc_vid(rdev);
471 ret = ci_populate_svi_load_line(rdev);
474 ret = ci_populate_tdc_limit(rdev);
477 ret = ci_populate_dw8(rdev);
480 ret = ci_min_max_v_gnbl_pm_lid_from_bapm_vddc(rdev);
483 ret = ci_populate_bapm_vddc_base_leakage_sidd(rdev);
486 ret = ci_copy_bytes_to_smc(rdev, pm_fuse_table_offset,
487 (u8 *)&pi->smc_powertune_table,
488 sizeof(SMU7_Discrete_PmFuses), pi->sram_end);
496 static void ci_do_enable_didt(struct radeon_device *rdev, const bool enable)
498 struct ci_power_info *pi = ci_get_pi(rdev);
501 if (pi->caps_sq_ramping) {
502 data = RREG32_DIDT(DIDT_SQ_CTRL0);
504 data |= DIDT_CTRL_EN;
506 data &= ~DIDT_CTRL_EN;
507 WREG32_DIDT(DIDT_SQ_CTRL0, data);
510 if (pi->caps_db_ramping) {
511 data = RREG32_DIDT(DIDT_DB_CTRL0);
513 data |= DIDT_CTRL_EN;
515 data &= ~DIDT_CTRL_EN;
516 WREG32_DIDT(DIDT_DB_CTRL0, data);
519 if (pi->caps_td_ramping) {
520 data = RREG32_DIDT(DIDT_TD_CTRL0);
522 data |= DIDT_CTRL_EN;
524 data &= ~DIDT_CTRL_EN;
525 WREG32_DIDT(DIDT_TD_CTRL0, data);
528 if (pi->caps_tcp_ramping) {
529 data = RREG32_DIDT(DIDT_TCP_CTRL0);
531 data |= DIDT_CTRL_EN;
533 data &= ~DIDT_CTRL_EN;
534 WREG32_DIDT(DIDT_TCP_CTRL0, data);
538 static int ci_program_pt_config_registers(struct radeon_device *rdev,
539 const struct ci_pt_config_reg *cac_config_regs)
541 const struct ci_pt_config_reg *config_regs = cac_config_regs;
545 if (config_regs == NULL)
548 while (config_regs->offset != 0xFFFFFFFF) {
549 if (config_regs->type == CISLANDS_CONFIGREG_CACHE) {
550 cache |= ((config_regs->value << config_regs->shift) & config_regs->mask);
552 switch (config_regs->type) {
553 case CISLANDS_CONFIGREG_SMC_IND:
554 data = RREG32_SMC(config_regs->offset);
556 case CISLANDS_CONFIGREG_DIDT_IND:
557 data = RREG32_DIDT(config_regs->offset);
560 data = RREG32(config_regs->offset << 2);
564 data &= ~config_regs->mask;
565 data |= ((config_regs->value << config_regs->shift) & config_regs->mask);
568 switch (config_regs->type) {
569 case CISLANDS_CONFIGREG_SMC_IND:
570 WREG32_SMC(config_regs->offset, data);
572 case CISLANDS_CONFIGREG_DIDT_IND:
573 WREG32_DIDT(config_regs->offset, data);
576 WREG32(config_regs->offset << 2, data);
586 static int ci_enable_didt(struct radeon_device *rdev, bool enable)
588 struct ci_power_info *pi = ci_get_pi(rdev);
591 if (pi->caps_sq_ramping || pi->caps_db_ramping ||
592 pi->caps_td_ramping || pi->caps_tcp_ramping) {
593 cik_enter_rlc_safe_mode(rdev);
596 ret = ci_program_pt_config_registers(rdev, didt_config_ci);
598 cik_exit_rlc_safe_mode(rdev);
603 ci_do_enable_didt(rdev, enable);
605 cik_exit_rlc_safe_mode(rdev);
611 static int ci_enable_power_containment(struct radeon_device *rdev, bool enable)
613 struct ci_power_info *pi = ci_get_pi(rdev);
614 PPSMC_Result smc_result;
618 pi->power_containment_features = 0;
619 if (pi->caps_power_containment) {
620 if (pi->enable_bapm_feature) {
621 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_EnableDTE);
622 if (smc_result != PPSMC_Result_OK)
625 pi->power_containment_features |= POWERCONTAINMENT_FEATURE_BAPM;
628 if (pi->enable_tdc_limit_feature) {
629 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_TDCLimitEnable);
630 if (smc_result != PPSMC_Result_OK)
633 pi->power_containment_features |= POWERCONTAINMENT_FEATURE_TDCLimit;
636 if (pi->enable_pkg_pwr_tracking_feature) {
637 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_PkgPwrLimitEnable);
638 if (smc_result != PPSMC_Result_OK) {
641 struct radeon_cac_tdp_table *cac_tdp_table =
642 rdev->pm.dpm.dyn_state.cac_tdp_table;
643 u32 default_pwr_limit =
644 (u32)(cac_tdp_table->maximum_power_delivery_limit * 256);
646 pi->power_containment_features |= POWERCONTAINMENT_FEATURE_PkgPwrLimit;
648 ci_set_power_limit(rdev, default_pwr_limit);
653 if (pi->caps_power_containment && pi->power_containment_features) {
654 if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_TDCLimit)
655 ci_send_msg_to_smc(rdev, PPSMC_MSG_TDCLimitDisable);
657 if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_BAPM)
658 ci_send_msg_to_smc(rdev, PPSMC_MSG_DisableDTE);
660 if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_PkgPwrLimit)
661 ci_send_msg_to_smc(rdev, PPSMC_MSG_PkgPwrLimitDisable);
662 pi->power_containment_features = 0;
669 static int ci_enable_smc_cac(struct radeon_device *rdev, bool enable)
671 struct ci_power_info *pi = ci_get_pi(rdev);
672 PPSMC_Result smc_result;
677 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_EnableCac);
678 if (smc_result != PPSMC_Result_OK) {
680 pi->cac_enabled = false;
682 pi->cac_enabled = true;
684 } else if (pi->cac_enabled) {
685 ci_send_msg_to_smc(rdev, PPSMC_MSG_DisableCac);
686 pi->cac_enabled = false;
693 static int ci_power_control_set_level(struct radeon_device *rdev)
695 struct ci_power_info *pi = ci_get_pi(rdev);
696 struct radeon_cac_tdp_table *cac_tdp_table =
697 rdev->pm.dpm.dyn_state.cac_tdp_table;
701 bool adjust_polarity = false; /* ??? */
703 if (pi->caps_power_containment &&
704 (pi->power_containment_features & POWERCONTAINMENT_FEATURE_BAPM)) {
705 adjust_percent = adjust_polarity ?
706 rdev->pm.dpm.tdp_adjustment : (-1 * rdev->pm.dpm.tdp_adjustment);
707 target_tdp = ((100 + adjust_percent) *
708 (s32)cac_tdp_table->configurable_tdp) / 100;
711 ret = ci_set_overdrive_target_tdp(rdev, (u32)target_tdp);
717 void ci_dpm_powergate_uvd(struct radeon_device *rdev, bool gate)
719 struct ci_power_info *pi = ci_get_pi(rdev);
721 if (pi->uvd_power_gated == gate)
724 pi->uvd_power_gated = gate;
726 ci_update_uvd_dpm(rdev, gate);
729 bool ci_dpm_vblank_too_short(struct radeon_device *rdev)
731 struct ci_power_info *pi = ci_get_pi(rdev);
732 u32 vblank_time = r600_dpm_get_vblank_time(rdev);
733 u32 switch_limit = pi->mem_gddr5 ? 450 : 300;
735 if (vblank_time < switch_limit)
742 static void ci_apply_state_adjust_rules(struct radeon_device *rdev,
743 struct radeon_ps *rps)
745 struct ci_ps *ps = ci_get_ps(rps);
746 struct ci_power_info *pi = ci_get_pi(rdev);
747 struct radeon_clock_and_voltage_limits *max_limits;
748 bool disable_mclk_switching;
752 if (rps->vce_active) {
753 rps->evclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].evclk;
754 rps->ecclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].ecclk;
760 if ((rdev->pm.dpm.new_active_crtc_count > 1) ||
761 ci_dpm_vblank_too_short(rdev))
762 disable_mclk_switching = true;
764 disable_mclk_switching = false;
766 if ((rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) == ATOM_PPLIB_CLASSIFICATION_UI_BATTERY)
767 pi->battery_state = true;
769 pi->battery_state = false;
771 if (rdev->pm.dpm.ac_power)
772 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
774 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
776 if (rdev->pm.dpm.ac_power == false) {
777 for (i = 0; i < ps->performance_level_count; i++) {
778 if (ps->performance_levels[i].mclk > max_limits->mclk)
779 ps->performance_levels[i].mclk = max_limits->mclk;
780 if (ps->performance_levels[i].sclk > max_limits->sclk)
781 ps->performance_levels[i].sclk = max_limits->sclk;
785 /* XXX validate the min clocks required for display */
787 if (disable_mclk_switching) {
788 mclk = ps->performance_levels[ps->performance_level_count - 1].mclk;
789 sclk = ps->performance_levels[0].sclk;
791 mclk = ps->performance_levels[0].mclk;
792 sclk = ps->performance_levels[0].sclk;
795 if (rps->vce_active) {
796 if (sclk < rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].sclk)
797 sclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].sclk;
798 if (mclk < rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].mclk)
799 mclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].mclk;
802 ps->performance_levels[0].sclk = sclk;
803 ps->performance_levels[0].mclk = mclk;
805 if (ps->performance_levels[1].sclk < ps->performance_levels[0].sclk)
806 ps->performance_levels[1].sclk = ps->performance_levels[0].sclk;
808 if (disable_mclk_switching) {
809 if (ps->performance_levels[0].mclk < ps->performance_levels[1].mclk)
810 ps->performance_levels[0].mclk = ps->performance_levels[1].mclk;
812 if (ps->performance_levels[1].mclk < ps->performance_levels[0].mclk)
813 ps->performance_levels[1].mclk = ps->performance_levels[0].mclk;
817 static int ci_thermal_set_temperature_range(struct radeon_device *rdev,
818 int min_temp, int max_temp)
820 int low_temp = 0 * 1000;
821 int high_temp = 255 * 1000;
824 if (low_temp < min_temp)
826 if (high_temp > max_temp)
827 high_temp = max_temp;
828 if (high_temp < low_temp) {
829 DRM_ERROR("invalid thermal range: %d - %d\n", low_temp, high_temp);
833 tmp = RREG32_SMC(CG_THERMAL_INT);
834 tmp &= ~(CI_DIG_THERM_INTH_MASK | CI_DIG_THERM_INTL_MASK);
835 tmp |= CI_DIG_THERM_INTH(high_temp / 1000) |
836 CI_DIG_THERM_INTL(low_temp / 1000);
837 WREG32_SMC(CG_THERMAL_INT, tmp);
840 /* XXX: need to figure out how to handle this properly */
841 tmp = RREG32_SMC(CG_THERMAL_CTRL);
842 tmp &= DIG_THERM_DPM_MASK;
843 tmp |= DIG_THERM_DPM(high_temp / 1000);
844 WREG32_SMC(CG_THERMAL_CTRL, tmp);
847 rdev->pm.dpm.thermal.min_temp = low_temp;
848 rdev->pm.dpm.thermal.max_temp = high_temp;
853 static int ci_thermal_enable_alert(struct radeon_device *rdev,
856 u32 thermal_int = RREG32_SMC(CG_THERMAL_INT);
860 thermal_int &= ~(THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW);
861 rdev->irq.dpm_thermal = false;
862 result = ci_send_msg_to_smc(rdev, PPSMC_MSG_Thermal_Cntl_Enable);
863 if (result != PPSMC_Result_OK) {
864 DRM_DEBUG_KMS("Could not enable thermal interrupts.\n");
868 thermal_int |= THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW;
869 rdev->irq.dpm_thermal = true;
870 result = ci_send_msg_to_smc(rdev, PPSMC_MSG_Thermal_Cntl_Disable);
871 if (result != PPSMC_Result_OK) {
872 DRM_DEBUG_KMS("Could not disable thermal interrupts.\n");
877 WREG32_SMC(CG_THERMAL_INT, thermal_int);
883 static int ci_read_smc_soft_register(struct radeon_device *rdev,
884 u16 reg_offset, u32 *value)
886 struct ci_power_info *pi = ci_get_pi(rdev);
888 return ci_read_smc_sram_dword(rdev,
889 pi->soft_regs_start + reg_offset,
890 value, pi->sram_end);
894 static int ci_write_smc_soft_register(struct radeon_device *rdev,
895 u16 reg_offset, u32 value)
897 struct ci_power_info *pi = ci_get_pi(rdev);
899 return ci_write_smc_sram_dword(rdev,
900 pi->soft_regs_start + reg_offset,
901 value, pi->sram_end);
904 static void ci_init_fps_limits(struct radeon_device *rdev)
906 struct ci_power_info *pi = ci_get_pi(rdev);
907 SMU7_Discrete_DpmTable *table = &pi->smc_state_table;
913 table->FpsHighT = cpu_to_be16(tmp);
916 table->FpsLowT = cpu_to_be16(tmp);
920 static int ci_update_sclk_t(struct radeon_device *rdev)
922 struct ci_power_info *pi = ci_get_pi(rdev);
924 u32 low_sclk_interrupt_t = 0;
926 if (pi->caps_sclk_throttle_low_notification) {
927 low_sclk_interrupt_t = cpu_to_be32(pi->low_sclk_interrupt_t);
929 ret = ci_copy_bytes_to_smc(rdev,
930 pi->dpm_table_start +
931 offsetof(SMU7_Discrete_DpmTable, LowSclkInterruptT),
932 (u8 *)&low_sclk_interrupt_t,
933 sizeof(u32), pi->sram_end);
940 static void ci_get_leakage_voltages(struct radeon_device *rdev)
942 struct ci_power_info *pi = ci_get_pi(rdev);
943 u16 leakage_id, virtual_voltage_id;
947 pi->vddc_leakage.count = 0;
948 pi->vddci_leakage.count = 0;
950 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_EVV) {
951 for (i = 0; i < CISLANDS_MAX_LEAKAGE_COUNT; i++) {
952 virtual_voltage_id = ATOM_VIRTUAL_VOLTAGE_ID0 + i;
953 if (radeon_atom_get_voltage_evv(rdev, virtual_voltage_id, &vddc) != 0)
955 if (vddc != 0 && vddc != virtual_voltage_id) {
956 pi->vddc_leakage.actual_voltage[pi->vddc_leakage.count] = vddc;
957 pi->vddc_leakage.leakage_id[pi->vddc_leakage.count] = virtual_voltage_id;
958 pi->vddc_leakage.count++;
961 } else if (radeon_atom_get_leakage_id_from_vbios(rdev, &leakage_id) == 0) {
962 for (i = 0; i < CISLANDS_MAX_LEAKAGE_COUNT; i++) {
963 virtual_voltage_id = ATOM_VIRTUAL_VOLTAGE_ID0 + i;
964 if (radeon_atom_get_leakage_vddc_based_on_leakage_params(rdev, &vddc, &vddci,
967 if (vddc != 0 && vddc != virtual_voltage_id) {
968 pi->vddc_leakage.actual_voltage[pi->vddc_leakage.count] = vddc;
969 pi->vddc_leakage.leakage_id[pi->vddc_leakage.count] = virtual_voltage_id;
970 pi->vddc_leakage.count++;
972 if (vddci != 0 && vddci != virtual_voltage_id) {
973 pi->vddci_leakage.actual_voltage[pi->vddci_leakage.count] = vddci;
974 pi->vddci_leakage.leakage_id[pi->vddci_leakage.count] = virtual_voltage_id;
975 pi->vddci_leakage.count++;
982 static void ci_set_dpm_event_sources(struct radeon_device *rdev, u32 sources)
984 struct ci_power_info *pi = ci_get_pi(rdev);
985 bool want_thermal_protection;
986 enum radeon_dpm_event_src dpm_event_src;
992 want_thermal_protection = false;
994 case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL):
995 want_thermal_protection = true;
996 dpm_event_src = RADEON_DPM_EVENT_SRC_DIGITAL;
998 case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL):
999 want_thermal_protection = true;
1000 dpm_event_src = RADEON_DPM_EVENT_SRC_EXTERNAL;
1002 case ((1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL) |
1003 (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL)):
1004 want_thermal_protection = true;
1005 dpm_event_src = RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL;
1009 if (want_thermal_protection) {
1011 /* XXX: need to figure out how to handle this properly */
1012 tmp = RREG32_SMC(CG_THERMAL_CTRL);
1013 tmp &= DPM_EVENT_SRC_MASK;
1014 tmp |= DPM_EVENT_SRC(dpm_event_src);
1015 WREG32_SMC(CG_THERMAL_CTRL, tmp);
1018 tmp = RREG32_SMC(GENERAL_PWRMGT);
1019 if (pi->thermal_protection)
1020 tmp &= ~THERMAL_PROTECTION_DIS;
1022 tmp |= THERMAL_PROTECTION_DIS;
1023 WREG32_SMC(GENERAL_PWRMGT, tmp);
1025 tmp = RREG32_SMC(GENERAL_PWRMGT);
1026 tmp |= THERMAL_PROTECTION_DIS;
1027 WREG32_SMC(GENERAL_PWRMGT, tmp);
1031 static void ci_enable_auto_throttle_source(struct radeon_device *rdev,
1032 enum radeon_dpm_auto_throttle_src source,
1035 struct ci_power_info *pi = ci_get_pi(rdev);
1038 if (!(pi->active_auto_throttle_sources & (1 << source))) {
1039 pi->active_auto_throttle_sources |= 1 << source;
1040 ci_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources);
1043 if (pi->active_auto_throttle_sources & (1 << source)) {
1044 pi->active_auto_throttle_sources &= ~(1 << source);
1045 ci_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources);
1050 static void ci_enable_vr_hot_gpio_interrupt(struct radeon_device *rdev)
1052 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REGULATOR_HOT)
1053 ci_send_msg_to_smc(rdev, PPSMC_MSG_EnableVRHotGPIOInterrupt);
1056 static int ci_unfreeze_sclk_mclk_dpm(struct radeon_device *rdev)
1058 struct ci_power_info *pi = ci_get_pi(rdev);
1059 PPSMC_Result smc_result;
1061 if (!pi->need_update_smu7_dpm_table)
1064 if ((!pi->sclk_dpm_key_disabled) &&
1065 (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK))) {
1066 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_SCLKDPM_UnfreezeLevel);
1067 if (smc_result != PPSMC_Result_OK)
1071 if ((!pi->mclk_dpm_key_disabled) &&
1072 (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) {
1073 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_MCLKDPM_UnfreezeLevel);
1074 if (smc_result != PPSMC_Result_OK)
1078 pi->need_update_smu7_dpm_table = 0;
1082 static int ci_enable_sclk_mclk_dpm(struct radeon_device *rdev, bool enable)
1084 struct ci_power_info *pi = ci_get_pi(rdev);
1085 PPSMC_Result smc_result;
1088 if (!pi->sclk_dpm_key_disabled) {
1089 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_DPM_Enable);
1090 if (smc_result != PPSMC_Result_OK)
1094 if (!pi->mclk_dpm_key_disabled) {
1095 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_MCLKDPM_Enable);
1096 if (smc_result != PPSMC_Result_OK)
1099 WREG32_P(MC_SEQ_CNTL_3, CAC_EN, ~CAC_EN);
1101 WREG32_SMC(LCAC_MC0_CNTL, 0x05);
1102 WREG32_SMC(LCAC_MC1_CNTL, 0x05);
1103 WREG32_SMC(LCAC_CPL_CNTL, 0x100005);
1107 WREG32_SMC(LCAC_MC0_CNTL, 0x400005);
1108 WREG32_SMC(LCAC_MC1_CNTL, 0x400005);
1109 WREG32_SMC(LCAC_CPL_CNTL, 0x500005);
1112 if (!pi->sclk_dpm_key_disabled) {
1113 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_DPM_Disable);
1114 if (smc_result != PPSMC_Result_OK)
1118 if (!pi->mclk_dpm_key_disabled) {
1119 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_MCLKDPM_Disable);
1120 if (smc_result != PPSMC_Result_OK)
1128 static int ci_start_dpm(struct radeon_device *rdev)
1130 struct ci_power_info *pi = ci_get_pi(rdev);
1131 PPSMC_Result smc_result;
1135 tmp = RREG32_SMC(GENERAL_PWRMGT);
1136 tmp |= GLOBAL_PWRMGT_EN;
1137 WREG32_SMC(GENERAL_PWRMGT, tmp);
1139 tmp = RREG32_SMC(SCLK_PWRMGT_CNTL);
1140 tmp |= DYNAMIC_PM_EN;
1141 WREG32_SMC(SCLK_PWRMGT_CNTL, tmp);
1143 ci_write_smc_soft_register(rdev, offsetof(SMU7_SoftRegisters, VoltageChangeTimeout), 0x1000);
1145 WREG32_P(BIF_LNCNT_RESET, 0, ~RESET_LNCNT_EN);
1147 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_Voltage_Cntl_Enable);
1148 if (smc_result != PPSMC_Result_OK)
1151 ret = ci_enable_sclk_mclk_dpm(rdev, true);
1155 if (!pi->pcie_dpm_key_disabled) {
1156 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_PCIeDPM_Enable);
1157 if (smc_result != PPSMC_Result_OK)
1164 static int ci_freeze_sclk_mclk_dpm(struct radeon_device *rdev)
1166 struct ci_power_info *pi = ci_get_pi(rdev);
1167 PPSMC_Result smc_result;
1169 if (!pi->need_update_smu7_dpm_table)
1172 if ((!pi->sclk_dpm_key_disabled) &&
1173 (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK))) {
1174 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_SCLKDPM_FreezeLevel);
1175 if (smc_result != PPSMC_Result_OK)
1179 if ((!pi->mclk_dpm_key_disabled) &&
1180 (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) {
1181 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_MCLKDPM_FreezeLevel);
1182 if (smc_result != PPSMC_Result_OK)
1189 static int ci_stop_dpm(struct radeon_device *rdev)
1191 struct ci_power_info *pi = ci_get_pi(rdev);
1192 PPSMC_Result smc_result;
1196 tmp = RREG32_SMC(GENERAL_PWRMGT);
1197 tmp &= ~GLOBAL_PWRMGT_EN;
1198 WREG32_SMC(GENERAL_PWRMGT, tmp);
1200 tmp = RREG32_SMC(SCLK_PWRMGT_CNTL);
1201 tmp &= ~DYNAMIC_PM_EN;
1202 WREG32_SMC(SCLK_PWRMGT_CNTL, tmp);
1204 if (!pi->pcie_dpm_key_disabled) {
1205 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_PCIeDPM_Disable);
1206 if (smc_result != PPSMC_Result_OK)
1210 ret = ci_enable_sclk_mclk_dpm(rdev, false);
1214 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_Voltage_Cntl_Disable);
1215 if (smc_result != PPSMC_Result_OK)
1221 static void ci_enable_sclk_control(struct radeon_device *rdev, bool enable)
1223 u32 tmp = RREG32_SMC(SCLK_PWRMGT_CNTL);
1226 tmp &= ~SCLK_PWRMGT_OFF;
1228 tmp |= SCLK_PWRMGT_OFF;
1229 WREG32_SMC(SCLK_PWRMGT_CNTL, tmp);
1233 static int ci_notify_hw_of_power_source(struct radeon_device *rdev,
1236 struct ci_power_info *pi = ci_get_pi(rdev);
1237 struct radeon_cac_tdp_table *cac_tdp_table =
1238 rdev->pm.dpm.dyn_state.cac_tdp_table;
1242 power_limit = (u32)(cac_tdp_table->maximum_power_delivery_limit * 256);
1244 power_limit = (u32)(cac_tdp_table->battery_power_limit * 256);
1246 ci_set_power_limit(rdev, power_limit);
1248 if (pi->caps_automatic_dc_transition) {
1250 ci_send_msg_to_smc(rdev, PPSMC_MSG_RunningOnAC);
1252 ci_send_msg_to_smc(rdev, PPSMC_MSG_Remove_DC_Clamp);
1259 static PPSMC_Result ci_send_msg_to_smc_with_parameter(struct radeon_device *rdev,
1260 PPSMC_Msg msg, u32 parameter)
1262 WREG32(SMC_MSG_ARG_0, parameter);
1263 return ci_send_msg_to_smc(rdev, msg);
1266 static PPSMC_Result ci_send_msg_to_smc_return_parameter(struct radeon_device *rdev,
1267 PPSMC_Msg msg, u32 *parameter)
1269 PPSMC_Result smc_result;
1271 smc_result = ci_send_msg_to_smc(rdev, msg);
1273 if ((smc_result == PPSMC_Result_OK) && parameter)
1274 *parameter = RREG32(SMC_MSG_ARG_0);
1279 static int ci_dpm_force_state_sclk(struct radeon_device *rdev, u32 n)
1281 struct ci_power_info *pi = ci_get_pi(rdev);
1283 if (!pi->sclk_dpm_key_disabled) {
1284 PPSMC_Result smc_result =
1285 ci_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SCLKDPM_SetEnabledMask, 1 << n);
1286 if (smc_result != PPSMC_Result_OK)
1293 static int ci_dpm_force_state_mclk(struct radeon_device *rdev, u32 n)
1295 struct ci_power_info *pi = ci_get_pi(rdev);
1297 if (!pi->mclk_dpm_key_disabled) {
1298 PPSMC_Result smc_result =
1299 ci_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_MCLKDPM_SetEnabledMask, 1 << n);
1300 if (smc_result != PPSMC_Result_OK)
1307 static int ci_dpm_force_state_pcie(struct radeon_device *rdev, u32 n)
1309 struct ci_power_info *pi = ci_get_pi(rdev);
1311 if (!pi->pcie_dpm_key_disabled) {
1312 PPSMC_Result smc_result =
1313 ci_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_PCIeDPM_ForceLevel, n);
1314 if (smc_result != PPSMC_Result_OK)
1321 static int ci_set_power_limit(struct radeon_device *rdev, u32 n)
1323 struct ci_power_info *pi = ci_get_pi(rdev);
1325 if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_PkgPwrLimit) {
1326 PPSMC_Result smc_result =
1327 ci_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_PkgPwrSetLimit, n);
1328 if (smc_result != PPSMC_Result_OK)
1335 static int ci_set_overdrive_target_tdp(struct radeon_device *rdev,
1338 PPSMC_Result smc_result =
1339 ci_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_OverDriveSetTargetTdp, target_tdp);
1340 if (smc_result != PPSMC_Result_OK)
1345 static int ci_set_boot_state(struct radeon_device *rdev)
1347 return ci_enable_sclk_mclk_dpm(rdev, false);
1350 static u32 ci_get_average_sclk_freq(struct radeon_device *rdev)
1353 PPSMC_Result smc_result =
1354 ci_send_msg_to_smc_return_parameter(rdev,
1355 PPSMC_MSG_API_GetSclkFrequency,
1357 if (smc_result != PPSMC_Result_OK)
1363 static u32 ci_get_average_mclk_freq(struct radeon_device *rdev)
1366 PPSMC_Result smc_result =
1367 ci_send_msg_to_smc_return_parameter(rdev,
1368 PPSMC_MSG_API_GetMclkFrequency,
1370 if (smc_result != PPSMC_Result_OK)
1376 static void ci_dpm_start_smc(struct radeon_device *rdev)
1380 ci_program_jump_on_start(rdev);
1381 ci_start_smc_clock(rdev);
1383 for (i = 0; i < rdev->usec_timeout; i++) {
1384 if (RREG32_SMC(FIRMWARE_FLAGS) & INTERRUPTS_ENABLED)
1389 static void ci_dpm_stop_smc(struct radeon_device *rdev)
1392 ci_stop_smc_clock(rdev);
1395 static int ci_process_firmware_header(struct radeon_device *rdev)
1397 struct ci_power_info *pi = ci_get_pi(rdev);
1401 ret = ci_read_smc_sram_dword(rdev,
1402 SMU7_FIRMWARE_HEADER_LOCATION +
1403 offsetof(SMU7_Firmware_Header, DpmTable),
1404 &tmp, pi->sram_end);
1408 pi->dpm_table_start = tmp;
1410 ret = ci_read_smc_sram_dword(rdev,
1411 SMU7_FIRMWARE_HEADER_LOCATION +
1412 offsetof(SMU7_Firmware_Header, SoftRegisters),
1413 &tmp, pi->sram_end);
1417 pi->soft_regs_start = tmp;
1419 ret = ci_read_smc_sram_dword(rdev,
1420 SMU7_FIRMWARE_HEADER_LOCATION +
1421 offsetof(SMU7_Firmware_Header, mcRegisterTable),
1422 &tmp, pi->sram_end);
1426 pi->mc_reg_table_start = tmp;
1428 ret = ci_read_smc_sram_dword(rdev,
1429 SMU7_FIRMWARE_HEADER_LOCATION +
1430 offsetof(SMU7_Firmware_Header, FanTable),
1431 &tmp, pi->sram_end);
1435 pi->fan_table_start = tmp;
1437 ret = ci_read_smc_sram_dword(rdev,
1438 SMU7_FIRMWARE_HEADER_LOCATION +
1439 offsetof(SMU7_Firmware_Header, mcArbDramTimingTable),
1440 &tmp, pi->sram_end);
1444 pi->arb_table_start = tmp;
1449 static void ci_read_clock_registers(struct radeon_device *rdev)
1451 struct ci_power_info *pi = ci_get_pi(rdev);
1453 pi->clock_registers.cg_spll_func_cntl =
1454 RREG32_SMC(CG_SPLL_FUNC_CNTL);
1455 pi->clock_registers.cg_spll_func_cntl_2 =
1456 RREG32_SMC(CG_SPLL_FUNC_CNTL_2);
1457 pi->clock_registers.cg_spll_func_cntl_3 =
1458 RREG32_SMC(CG_SPLL_FUNC_CNTL_3);
1459 pi->clock_registers.cg_spll_func_cntl_4 =
1460 RREG32_SMC(CG_SPLL_FUNC_CNTL_4);
1461 pi->clock_registers.cg_spll_spread_spectrum =
1462 RREG32_SMC(CG_SPLL_SPREAD_SPECTRUM);
1463 pi->clock_registers.cg_spll_spread_spectrum_2 =
1464 RREG32_SMC(CG_SPLL_SPREAD_SPECTRUM_2);
1465 pi->clock_registers.dll_cntl = RREG32(DLL_CNTL);
1466 pi->clock_registers.mclk_pwrmgt_cntl = RREG32(MCLK_PWRMGT_CNTL);
1467 pi->clock_registers.mpll_ad_func_cntl = RREG32(MPLL_AD_FUNC_CNTL);
1468 pi->clock_registers.mpll_dq_func_cntl = RREG32(MPLL_DQ_FUNC_CNTL);
1469 pi->clock_registers.mpll_func_cntl = RREG32(MPLL_FUNC_CNTL);
1470 pi->clock_registers.mpll_func_cntl_1 = RREG32(MPLL_FUNC_CNTL_1);
1471 pi->clock_registers.mpll_func_cntl_2 = RREG32(MPLL_FUNC_CNTL_2);
1472 pi->clock_registers.mpll_ss1 = RREG32(MPLL_SS1);
1473 pi->clock_registers.mpll_ss2 = RREG32(MPLL_SS2);
1476 static void ci_init_sclk_t(struct radeon_device *rdev)
1478 struct ci_power_info *pi = ci_get_pi(rdev);
1480 pi->low_sclk_interrupt_t = 0;
1483 static void ci_enable_thermal_protection(struct radeon_device *rdev,
1486 u32 tmp = RREG32_SMC(GENERAL_PWRMGT);
1489 tmp &= ~THERMAL_PROTECTION_DIS;
1491 tmp |= THERMAL_PROTECTION_DIS;
1492 WREG32_SMC(GENERAL_PWRMGT, tmp);
1495 static void ci_enable_acpi_power_management(struct radeon_device *rdev)
1497 u32 tmp = RREG32_SMC(GENERAL_PWRMGT);
1499 tmp |= STATIC_PM_EN;
1501 WREG32_SMC(GENERAL_PWRMGT, tmp);
1505 static int ci_enter_ulp_state(struct radeon_device *rdev)
1508 WREG32(SMC_MESSAGE_0, PPSMC_MSG_SwitchToMinimumPower);
1515 static int ci_exit_ulp_state(struct radeon_device *rdev)
1519 WREG32(SMC_MESSAGE_0, PPSMC_MSG_ResumeFromMinimumPower);
1523 for (i = 0; i < rdev->usec_timeout; i++) {
1524 if (RREG32(SMC_RESP_0) == 1)
1533 static int ci_notify_smc_display_change(struct radeon_device *rdev,
1536 PPSMC_Msg msg = has_display ? PPSMC_MSG_HasDisplay : PPSMC_MSG_NoDisplay;
1538 return (ci_send_msg_to_smc(rdev, msg) == PPSMC_Result_OK) ? 0 : -EINVAL;
1541 static int ci_enable_ds_master_switch(struct radeon_device *rdev,
1544 struct ci_power_info *pi = ci_get_pi(rdev);
1547 if (pi->caps_sclk_ds) {
1548 if (ci_send_msg_to_smc(rdev, PPSMC_MSG_MASTER_DeepSleep_ON) != PPSMC_Result_OK)
1551 if (ci_send_msg_to_smc(rdev, PPSMC_MSG_MASTER_DeepSleep_OFF) != PPSMC_Result_OK)
1555 if (pi->caps_sclk_ds) {
1556 if (ci_send_msg_to_smc(rdev, PPSMC_MSG_MASTER_DeepSleep_OFF) != PPSMC_Result_OK)
1564 static void ci_program_display_gap(struct radeon_device *rdev)
1566 u32 tmp = RREG32_SMC(CG_DISPLAY_GAP_CNTL);
1567 u32 pre_vbi_time_in_us;
1568 u32 frame_time_in_us;
1569 u32 ref_clock = rdev->clock.spll.reference_freq;
1570 u32 refresh_rate = r600_dpm_get_vrefresh(rdev);
1571 u32 vblank_time = r600_dpm_get_vblank_time(rdev);
1573 tmp &= ~DISP_GAP_MASK;
1574 if (rdev->pm.dpm.new_active_crtc_count > 0)
1575 tmp |= DISP_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM);
1577 tmp |= DISP_GAP(R600_PM_DISPLAY_GAP_IGNORE);
1578 WREG32_SMC(CG_DISPLAY_GAP_CNTL, tmp);
1580 if (refresh_rate == 0)
1582 if (vblank_time == 0xffffffff)
1584 frame_time_in_us = 1000000 / refresh_rate;
1585 pre_vbi_time_in_us =
1586 frame_time_in_us - 200 - vblank_time;
1587 tmp = pre_vbi_time_in_us * (ref_clock / 100);
1589 WREG32_SMC(CG_DISPLAY_GAP_CNTL2, tmp);
1590 ci_write_smc_soft_register(rdev, offsetof(SMU7_SoftRegisters, PreVBlankGap), 0x64);
1591 ci_write_smc_soft_register(rdev, offsetof(SMU7_SoftRegisters, VBlankTimeout), (frame_time_in_us - pre_vbi_time_in_us));
1594 ci_notify_smc_display_change(rdev, (rdev->pm.dpm.new_active_crtc_count == 1));
1598 static void ci_enable_spread_spectrum(struct radeon_device *rdev, bool enable)
1600 struct ci_power_info *pi = ci_get_pi(rdev);
1604 if (pi->caps_sclk_ss_support) {
1605 tmp = RREG32_SMC(GENERAL_PWRMGT);
1606 tmp |= DYN_SPREAD_SPECTRUM_EN;
1607 WREG32_SMC(GENERAL_PWRMGT, tmp);
1610 tmp = RREG32_SMC(CG_SPLL_SPREAD_SPECTRUM);
1612 WREG32_SMC(CG_SPLL_SPREAD_SPECTRUM, tmp);
1614 tmp = RREG32_SMC(GENERAL_PWRMGT);
1615 tmp &= ~DYN_SPREAD_SPECTRUM_EN;
1616 WREG32_SMC(GENERAL_PWRMGT, tmp);
1620 static void ci_program_sstp(struct radeon_device *rdev)
1622 WREG32_SMC(CG_SSP, (SSTU(R600_SSTU_DFLT) | SST(R600_SST_DFLT)));
1625 static void ci_enable_display_gap(struct radeon_device *rdev)
1627 u32 tmp = RREG32_SMC(CG_DISPLAY_GAP_CNTL);
1629 tmp &= ~(DISP_GAP_MASK | DISP_GAP_MCHG_MASK);
1630 tmp |= (DISP_GAP(R600_PM_DISPLAY_GAP_IGNORE) |
1631 DISP_GAP_MCHG(R600_PM_DISPLAY_GAP_VBLANK));
1633 WREG32_SMC(CG_DISPLAY_GAP_CNTL, tmp);
1636 static void ci_program_vc(struct radeon_device *rdev)
1640 tmp = RREG32_SMC(SCLK_PWRMGT_CNTL);
1641 tmp &= ~(RESET_SCLK_CNT | RESET_BUSY_CNT);
1642 WREG32_SMC(SCLK_PWRMGT_CNTL, tmp);
1644 WREG32_SMC(CG_FTV_0, CISLANDS_VRC_DFLT0);
1645 WREG32_SMC(CG_FTV_1, CISLANDS_VRC_DFLT1);
1646 WREG32_SMC(CG_FTV_2, CISLANDS_VRC_DFLT2);
1647 WREG32_SMC(CG_FTV_3, CISLANDS_VRC_DFLT3);
1648 WREG32_SMC(CG_FTV_4, CISLANDS_VRC_DFLT4);
1649 WREG32_SMC(CG_FTV_5, CISLANDS_VRC_DFLT5);
1650 WREG32_SMC(CG_FTV_6, CISLANDS_VRC_DFLT6);
1651 WREG32_SMC(CG_FTV_7, CISLANDS_VRC_DFLT7);
1654 static void ci_clear_vc(struct radeon_device *rdev)
1658 tmp = RREG32_SMC(SCLK_PWRMGT_CNTL);
1659 tmp |= (RESET_SCLK_CNT | RESET_BUSY_CNT);
1660 WREG32_SMC(SCLK_PWRMGT_CNTL, tmp);
1662 WREG32_SMC(CG_FTV_0, 0);
1663 WREG32_SMC(CG_FTV_1, 0);
1664 WREG32_SMC(CG_FTV_2, 0);
1665 WREG32_SMC(CG_FTV_3, 0);
1666 WREG32_SMC(CG_FTV_4, 0);
1667 WREG32_SMC(CG_FTV_5, 0);
1668 WREG32_SMC(CG_FTV_6, 0);
1669 WREG32_SMC(CG_FTV_7, 0);
1672 static int ci_upload_firmware(struct radeon_device *rdev)
1674 struct ci_power_info *pi = ci_get_pi(rdev);
1677 for (i = 0; i < rdev->usec_timeout; i++) {
1678 if (RREG32_SMC(RCU_UC_EVENTS) & BOOT_SEQ_DONE)
1681 WREG32_SMC(SMC_SYSCON_MISC_CNTL, 1);
1683 ci_stop_smc_clock(rdev);
1686 ret = ci_load_smc_ucode(rdev, pi->sram_end);
1692 static int ci_get_svi2_voltage_table(struct radeon_device *rdev,
1693 struct radeon_clock_voltage_dependency_table *voltage_dependency_table,
1694 struct atom_voltage_table *voltage_table)
1698 if (voltage_dependency_table == NULL)
1701 voltage_table->mask_low = 0;
1702 voltage_table->phase_delay = 0;
1704 voltage_table->count = voltage_dependency_table->count;
1705 for (i = 0; i < voltage_table->count; i++) {
1706 voltage_table->entries[i].value = voltage_dependency_table->entries[i].v;
1707 voltage_table->entries[i].smio_low = 0;
1713 static int ci_construct_voltage_tables(struct radeon_device *rdev)
1715 struct ci_power_info *pi = ci_get_pi(rdev);
1718 if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) {
1719 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDC,
1720 VOLTAGE_OBJ_GPIO_LUT,
1721 &pi->vddc_voltage_table);
1724 } else if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2) {
1725 ret = ci_get_svi2_voltage_table(rdev,
1726 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
1727 &pi->vddc_voltage_table);
1732 if (pi->vddc_voltage_table.count > SMU7_MAX_LEVELS_VDDC)
1733 si_trim_voltage_table_to_fit_state_table(rdev, SMU7_MAX_LEVELS_VDDC,
1734 &pi->vddc_voltage_table);
1736 if (pi->vddci_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) {
1737 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDCI,
1738 VOLTAGE_OBJ_GPIO_LUT,
1739 &pi->vddci_voltage_table);
1742 } else if (pi->vddci_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2) {
1743 ret = ci_get_svi2_voltage_table(rdev,
1744 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
1745 &pi->vddci_voltage_table);
1750 if (pi->vddci_voltage_table.count > SMU7_MAX_LEVELS_VDDCI)
1751 si_trim_voltage_table_to_fit_state_table(rdev, SMU7_MAX_LEVELS_VDDCI,
1752 &pi->vddci_voltage_table);
1754 if (pi->mvdd_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) {
1755 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_MVDDC,
1756 VOLTAGE_OBJ_GPIO_LUT,
1757 &pi->mvdd_voltage_table);
1760 } else if (pi->mvdd_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2) {
1761 ret = ci_get_svi2_voltage_table(rdev,
1762 &rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk,
1763 &pi->mvdd_voltage_table);
1768 if (pi->mvdd_voltage_table.count > SMU7_MAX_LEVELS_MVDD)
1769 si_trim_voltage_table_to_fit_state_table(rdev, SMU7_MAX_LEVELS_MVDD,
1770 &pi->mvdd_voltage_table);
1775 static void ci_populate_smc_voltage_table(struct radeon_device *rdev,
1776 struct atom_voltage_table_entry *voltage_table,
1777 SMU7_Discrete_VoltageLevel *smc_voltage_table)
1781 ret = ci_get_std_voltage_value_sidd(rdev, voltage_table,
1782 &smc_voltage_table->StdVoltageHiSidd,
1783 &smc_voltage_table->StdVoltageLoSidd);
1786 smc_voltage_table->StdVoltageHiSidd = voltage_table->value * VOLTAGE_SCALE;
1787 smc_voltage_table->StdVoltageLoSidd = voltage_table->value * VOLTAGE_SCALE;
1790 smc_voltage_table->Voltage = cpu_to_be16(voltage_table->value * VOLTAGE_SCALE);
1791 smc_voltage_table->StdVoltageHiSidd =
1792 cpu_to_be16(smc_voltage_table->StdVoltageHiSidd);
1793 smc_voltage_table->StdVoltageLoSidd =
1794 cpu_to_be16(smc_voltage_table->StdVoltageLoSidd);
1797 static int ci_populate_smc_vddc_table(struct radeon_device *rdev,
1798 SMU7_Discrete_DpmTable *table)
1800 struct ci_power_info *pi = ci_get_pi(rdev);
1803 table->VddcLevelCount = pi->vddc_voltage_table.count;
1804 for (count = 0; count < table->VddcLevelCount; count++) {
1805 ci_populate_smc_voltage_table(rdev,
1806 &pi->vddc_voltage_table.entries[count],
1807 &table->VddcLevel[count]);
1809 if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO)
1810 table->VddcLevel[count].Smio |=
1811 pi->vddc_voltage_table.entries[count].smio_low;
1813 table->VddcLevel[count].Smio = 0;
1815 table->VddcLevelCount = cpu_to_be32(table->VddcLevelCount);
1820 static int ci_populate_smc_vddci_table(struct radeon_device *rdev,
1821 SMU7_Discrete_DpmTable *table)
1824 struct ci_power_info *pi = ci_get_pi(rdev);
1826 table->VddciLevelCount = pi->vddci_voltage_table.count;
1827 for (count = 0; count < table->VddciLevelCount; count++) {
1828 ci_populate_smc_voltage_table(rdev,
1829 &pi->vddci_voltage_table.entries[count],
1830 &table->VddciLevel[count]);
1832 if (pi->vddci_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO)
1833 table->VddciLevel[count].Smio |=
1834 pi->vddci_voltage_table.entries[count].smio_low;
1836 table->VddciLevel[count].Smio = 0;
1838 table->VddciLevelCount = cpu_to_be32(table->VddciLevelCount);
1843 static int ci_populate_smc_mvdd_table(struct radeon_device *rdev,
1844 SMU7_Discrete_DpmTable *table)
1846 struct ci_power_info *pi = ci_get_pi(rdev);
1849 table->MvddLevelCount = pi->mvdd_voltage_table.count;
1850 for (count = 0; count < table->MvddLevelCount; count++) {
1851 ci_populate_smc_voltage_table(rdev,
1852 &pi->mvdd_voltage_table.entries[count],
1853 &table->MvddLevel[count]);
1855 if (pi->mvdd_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO)
1856 table->MvddLevel[count].Smio |=
1857 pi->mvdd_voltage_table.entries[count].smio_low;
1859 table->MvddLevel[count].Smio = 0;
1861 table->MvddLevelCount = cpu_to_be32(table->MvddLevelCount);
1866 static int ci_populate_smc_voltage_tables(struct radeon_device *rdev,
1867 SMU7_Discrete_DpmTable *table)
1871 ret = ci_populate_smc_vddc_table(rdev, table);
1875 ret = ci_populate_smc_vddci_table(rdev, table);
1879 ret = ci_populate_smc_mvdd_table(rdev, table);
1886 static int ci_populate_mvdd_value(struct radeon_device *rdev, u32 mclk,
1887 SMU7_Discrete_VoltageLevel *voltage)
1889 struct ci_power_info *pi = ci_get_pi(rdev);
1892 if (pi->mvdd_control != CISLANDS_VOLTAGE_CONTROL_NONE) {
1893 for (i = 0; i < rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.count; i++) {
1894 if (mclk <= rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.entries[i].clk) {
1895 voltage->Voltage = pi->mvdd_voltage_table.entries[i].value;
1900 if (i >= rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.count)
1907 static int ci_get_std_voltage_value_sidd(struct radeon_device *rdev,
1908 struct atom_voltage_table_entry *voltage_table,
1909 u16 *std_voltage_hi_sidd, u16 *std_voltage_lo_sidd)
1912 bool voltage_found = false;
1913 *std_voltage_hi_sidd = voltage_table->value * VOLTAGE_SCALE;
1914 *std_voltage_lo_sidd = voltage_table->value * VOLTAGE_SCALE;
1916 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries == NULL)
1919 if (rdev->pm.dpm.dyn_state.cac_leakage_table.entries) {
1920 for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {
1921 if (voltage_table->value ==
1922 rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) {
1923 voltage_found = true;
1924 if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count)
1927 idx = rdev->pm.dpm.dyn_state.cac_leakage_table.count - 1;
1928 *std_voltage_lo_sidd =
1929 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].vddc * VOLTAGE_SCALE;
1930 *std_voltage_hi_sidd =
1931 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].leakage * VOLTAGE_SCALE;
1936 if (!voltage_found) {
1937 for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {
1938 if (voltage_table->value <=
1939 rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) {
1940 voltage_found = true;
1941 if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count)
1944 idx = rdev->pm.dpm.dyn_state.cac_leakage_table.count - 1;
1945 *std_voltage_lo_sidd =
1946 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].vddc * VOLTAGE_SCALE;
1947 *std_voltage_hi_sidd =
1948 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].leakage * VOLTAGE_SCALE;
1958 static void ci_populate_phase_value_based_on_sclk(struct radeon_device *rdev,
1959 const struct radeon_phase_shedding_limits_table *limits,
1961 u32 *phase_shedding)
1965 *phase_shedding = 1;
1967 for (i = 0; i < limits->count; i++) {
1968 if (sclk < limits->entries[i].sclk) {
1969 *phase_shedding = i;
1975 static void ci_populate_phase_value_based_on_mclk(struct radeon_device *rdev,
1976 const struct radeon_phase_shedding_limits_table *limits,
1978 u32 *phase_shedding)
1982 *phase_shedding = 1;
1984 for (i = 0; i < limits->count; i++) {
1985 if (mclk < limits->entries[i].mclk) {
1986 *phase_shedding = i;
1992 static int ci_init_arb_table_index(struct radeon_device *rdev)
1994 struct ci_power_info *pi = ci_get_pi(rdev);
1998 ret = ci_read_smc_sram_dword(rdev, pi->arb_table_start,
1999 &tmp, pi->sram_end);
2004 tmp |= MC_CG_ARB_FREQ_F1 << 24;
2006 return ci_write_smc_sram_dword(rdev, pi->arb_table_start,
2010 static int ci_get_dependency_volt_by_clk(struct radeon_device *rdev,
2011 struct radeon_clock_voltage_dependency_table *allowed_clock_voltage_table,
2012 u32 clock, u32 *voltage)
2016 if (allowed_clock_voltage_table->count == 0)
2019 for (i = 0; i < allowed_clock_voltage_table->count; i++) {
2020 if (allowed_clock_voltage_table->entries[i].clk >= clock) {
2021 *voltage = allowed_clock_voltage_table->entries[i].v;
2026 *voltage = allowed_clock_voltage_table->entries[i-1].v;
2031 static u8 ci_get_sleep_divider_id_from_clock(struct radeon_device *rdev,
2032 u32 sclk, u32 min_sclk_in_sr)
2036 u32 min = (min_sclk_in_sr > CISLAND_MINIMUM_ENGINE_CLOCK) ?
2037 min_sclk_in_sr : CISLAND_MINIMUM_ENGINE_CLOCK;
2042 for (i = CISLAND_MAX_DEEPSLEEP_DIVIDER_ID; ; i--) {
2043 tmp = sclk / (1 << i);
2044 if (tmp >= min || i == 0)
2051 static int ci_initial_switch_from_arb_f0_to_f1(struct radeon_device *rdev)
2053 return ni_copy_and_switch_arb_sets(rdev, MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1);
2056 static int ci_reset_to_default(struct radeon_device *rdev)
2058 return (ci_send_msg_to_smc(rdev, PPSMC_MSG_ResetToDefaults) == PPSMC_Result_OK) ?
2062 static int ci_force_switch_to_arb_f0(struct radeon_device *rdev)
2066 tmp = (RREG32_SMC(SMC_SCRATCH9) & 0x0000ff00) >> 8;
2068 if (tmp == MC_CG_ARB_FREQ_F0)
2071 return ni_copy_and_switch_arb_sets(rdev, tmp, MC_CG_ARB_FREQ_F0);
2074 static void ci_register_patching_mc_arb(struct radeon_device *rdev,
2075 const u32 engine_clock,
2076 const u32 memory_clock,
2082 tmp = RREG32(MC_SEQ_MISC0);
2083 patch = ((tmp & 0x0000f00) == 0x300) ? true : false;
2086 ((rdev->pdev->device == 0x67B0) ||
2087 (rdev->pdev->device == 0x67B1))) {
2088 if ((memory_clock > 100000) && (memory_clock <= 125000)) {
2089 tmp2 = (((0x31 * engine_clock) / 125000) - 1) & 0xff;
2090 *dram_timimg2 &= ~0x00ff0000;
2091 *dram_timimg2 |= tmp2 << 16;
2092 } else if ((memory_clock > 125000) && (memory_clock <= 137500)) {
2093 tmp2 = (((0x36 * engine_clock) / 137500) - 1) & 0xff;
2094 *dram_timimg2 &= ~0x00ff0000;
2095 *dram_timimg2 |= tmp2 << 16;
2101 static int ci_populate_memory_timing_parameters(struct radeon_device *rdev,
2104 SMU7_Discrete_MCArbDramTimingTableEntry *arb_regs)
2110 radeon_atom_set_engine_dram_timings(rdev, sclk, mclk);
2112 dram_timing = RREG32(MC_ARB_DRAM_TIMING);
2113 dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2);
2114 burst_time = RREG32(MC_ARB_BURST_TIME) & STATE0_MASK;
2116 ci_register_patching_mc_arb(rdev, sclk, mclk, &dram_timing2);
2118 arb_regs->McArbDramTiming = cpu_to_be32(dram_timing);
2119 arb_regs->McArbDramTiming2 = cpu_to_be32(dram_timing2);
2120 arb_regs->McArbBurstTime = (u8)burst_time;
2125 static int ci_do_program_memory_timing_parameters(struct radeon_device *rdev)
2127 struct ci_power_info *pi = ci_get_pi(rdev);
2128 SMU7_Discrete_MCArbDramTimingTable arb_regs;
2132 memset(&arb_regs, 0, sizeof(SMU7_Discrete_MCArbDramTimingTable));
2134 for (i = 0; i < pi->dpm_table.sclk_table.count; i++) {
2135 for (j = 0; j < pi->dpm_table.mclk_table.count; j++) {
2136 ret = ci_populate_memory_timing_parameters(rdev,
2137 pi->dpm_table.sclk_table.dpm_levels[i].value,
2138 pi->dpm_table.mclk_table.dpm_levels[j].value,
2139 &arb_regs.entries[i][j]);
2146 ret = ci_copy_bytes_to_smc(rdev,
2147 pi->arb_table_start,
2149 sizeof(SMU7_Discrete_MCArbDramTimingTable),
2155 static int ci_program_memory_timing_parameters(struct radeon_device *rdev)
2157 struct ci_power_info *pi = ci_get_pi(rdev);
2159 if (pi->need_update_smu7_dpm_table == 0)
2162 return ci_do_program_memory_timing_parameters(rdev);
2165 static void ci_populate_smc_initial_state(struct radeon_device *rdev,
2166 struct radeon_ps *radeon_boot_state)
2168 struct ci_ps *boot_state = ci_get_ps(radeon_boot_state);
2169 struct ci_power_info *pi = ci_get_pi(rdev);
2172 for (level = 0; level < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; level++) {
2173 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[level].clk >=
2174 boot_state->performance_levels[0].sclk) {
2175 pi->smc_state_table.GraphicsBootLevel = level;
2180 for (level = 0; level < rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk.count; level++) {
2181 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk.entries[level].clk >=
2182 boot_state->performance_levels[0].mclk) {
2183 pi->smc_state_table.MemoryBootLevel = level;
2189 static u32 ci_get_dpm_level_enable_mask_value(struct ci_single_dpm_table *dpm_table)
2194 for (i = dpm_table->count; i > 0; i--) {
2195 mask_value = mask_value << 1;
2196 if (dpm_table->dpm_levels[i-1].enabled)
2199 mask_value &= 0xFFFFFFFE;
2205 static void ci_populate_smc_link_level(struct radeon_device *rdev,
2206 SMU7_Discrete_DpmTable *table)
2208 struct ci_power_info *pi = ci_get_pi(rdev);
2209 struct ci_dpm_table *dpm_table = &pi->dpm_table;
2212 for (i = 0; i < dpm_table->pcie_speed_table.count; i++) {
2213 table->LinkLevel[i].PcieGenSpeed =
2214 (u8)dpm_table->pcie_speed_table.dpm_levels[i].value;
2215 table->LinkLevel[i].PcieLaneCount =
2216 r600_encode_pci_lane_width(dpm_table->pcie_speed_table.dpm_levels[i].param1);
2217 table->LinkLevel[i].EnabledForActivity = 1;
2218 table->LinkLevel[i].DownT = cpu_to_be32(5);
2219 table->LinkLevel[i].UpT = cpu_to_be32(30);
2222 pi->smc_state_table.LinkLevelCount = (u8)dpm_table->pcie_speed_table.count;
2223 pi->dpm_level_enable_mask.pcie_dpm_enable_mask =
2224 ci_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table);
2227 static int ci_populate_smc_uvd_level(struct radeon_device *rdev,
2228 SMU7_Discrete_DpmTable *table)
2231 struct atom_clock_dividers dividers;
2234 table->UvdLevelCount =
2235 rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count;
2237 for (count = 0; count < table->UvdLevelCount; count++) {
2238 table->UvdLevel[count].VclkFrequency =
2239 rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[count].vclk;
2240 table->UvdLevel[count].DclkFrequency =
2241 rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[count].dclk;
2242 table->UvdLevel[count].MinVddc =
2243 rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[count].v * VOLTAGE_SCALE;
2244 table->UvdLevel[count].MinVddcPhases = 1;
2246 ret = radeon_atom_get_clock_dividers(rdev,
2247 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
2248 table->UvdLevel[count].VclkFrequency, false, ÷rs);
2252 table->UvdLevel[count].VclkDivider = (u8)dividers.post_divider;
2254 ret = radeon_atom_get_clock_dividers(rdev,
2255 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
2256 table->UvdLevel[count].DclkFrequency, false, ÷rs);
2260 table->UvdLevel[count].DclkDivider = (u8)dividers.post_divider;
2262 table->UvdLevel[count].VclkFrequency = cpu_to_be32(table->UvdLevel[count].VclkFrequency);
2263 table->UvdLevel[count].DclkFrequency = cpu_to_be32(table->UvdLevel[count].DclkFrequency);
2264 table->UvdLevel[count].MinVddc = cpu_to_be16(table->UvdLevel[count].MinVddc);
2270 static int ci_populate_smc_vce_level(struct radeon_device *rdev,
2271 SMU7_Discrete_DpmTable *table)
2274 struct atom_clock_dividers dividers;
2277 table->VceLevelCount =
2278 rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.count;
2280 for (count = 0; count < table->VceLevelCount; count++) {
2281 table->VceLevel[count].Frequency =
2282 rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[count].evclk;
2283 table->VceLevel[count].MinVoltage =
2284 (u16)rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[count].v * VOLTAGE_SCALE;
2285 table->VceLevel[count].MinPhases = 1;
2287 ret = radeon_atom_get_clock_dividers(rdev,
2288 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
2289 table->VceLevel[count].Frequency, false, ÷rs);
2293 table->VceLevel[count].Divider = (u8)dividers.post_divider;
2295 table->VceLevel[count].Frequency = cpu_to_be32(table->VceLevel[count].Frequency);
2296 table->VceLevel[count].MinVoltage = cpu_to_be16(table->VceLevel[count].MinVoltage);
2303 static int ci_populate_smc_acp_level(struct radeon_device *rdev,
2304 SMU7_Discrete_DpmTable *table)
2307 struct atom_clock_dividers dividers;
2310 table->AcpLevelCount = (u8)
2311 (rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.count);
2313 for (count = 0; count < table->AcpLevelCount; count++) {
2314 table->AcpLevel[count].Frequency =
2315 rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries[count].clk;
2316 table->AcpLevel[count].MinVoltage =
2317 rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries[count].v;
2318 table->AcpLevel[count].MinPhases = 1;
2320 ret = radeon_atom_get_clock_dividers(rdev,
2321 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
2322 table->AcpLevel[count].Frequency, false, ÷rs);
2326 table->AcpLevel[count].Divider = (u8)dividers.post_divider;
2328 table->AcpLevel[count].Frequency = cpu_to_be32(table->AcpLevel[count].Frequency);
2329 table->AcpLevel[count].MinVoltage = cpu_to_be16(table->AcpLevel[count].MinVoltage);
2335 static int ci_populate_smc_samu_level(struct radeon_device *rdev,
2336 SMU7_Discrete_DpmTable *table)
2339 struct atom_clock_dividers dividers;
2342 table->SamuLevelCount =
2343 rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.count;
2345 for (count = 0; count < table->SamuLevelCount; count++) {
2346 table->SamuLevel[count].Frequency =
2347 rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries[count].clk;
2348 table->SamuLevel[count].MinVoltage =
2349 rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries[count].v * VOLTAGE_SCALE;
2350 table->SamuLevel[count].MinPhases = 1;
2352 ret = radeon_atom_get_clock_dividers(rdev,
2353 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
2354 table->SamuLevel[count].Frequency, false, ÷rs);
2358 table->SamuLevel[count].Divider = (u8)dividers.post_divider;
2360 table->SamuLevel[count].Frequency = cpu_to_be32(table->SamuLevel[count].Frequency);
2361 table->SamuLevel[count].MinVoltage = cpu_to_be16(table->SamuLevel[count].MinVoltage);
2367 static int ci_calculate_mclk_params(struct radeon_device *rdev,
2369 SMU7_Discrete_MemoryLevel *mclk,
2373 struct ci_power_info *pi = ci_get_pi(rdev);
2374 u32 dll_cntl = pi->clock_registers.dll_cntl;
2375 u32 mclk_pwrmgt_cntl = pi->clock_registers.mclk_pwrmgt_cntl;
2376 u32 mpll_ad_func_cntl = pi->clock_registers.mpll_ad_func_cntl;
2377 u32 mpll_dq_func_cntl = pi->clock_registers.mpll_dq_func_cntl;
2378 u32 mpll_func_cntl = pi->clock_registers.mpll_func_cntl;
2379 u32 mpll_func_cntl_1 = pi->clock_registers.mpll_func_cntl_1;
2380 u32 mpll_func_cntl_2 = pi->clock_registers.mpll_func_cntl_2;
2381 u32 mpll_ss1 = pi->clock_registers.mpll_ss1;
2382 u32 mpll_ss2 = pi->clock_registers.mpll_ss2;
2383 struct atom_mpll_param mpll_param;
2386 ret = radeon_atom_get_memory_pll_dividers(rdev, memory_clock, strobe_mode, &mpll_param);
2390 mpll_func_cntl &= ~BWCTRL_MASK;
2391 mpll_func_cntl |= BWCTRL(mpll_param.bwcntl);
2393 mpll_func_cntl_1 &= ~(CLKF_MASK | CLKFRAC_MASK | VCO_MODE_MASK);
2394 mpll_func_cntl_1 |= CLKF(mpll_param.clkf) |
2395 CLKFRAC(mpll_param.clkfrac) | VCO_MODE(mpll_param.vco_mode);
2397 mpll_ad_func_cntl &= ~YCLK_POST_DIV_MASK;
2398 mpll_ad_func_cntl |= YCLK_POST_DIV(mpll_param.post_div);
2400 if (pi->mem_gddr5) {
2401 mpll_dq_func_cntl &= ~(YCLK_SEL_MASK | YCLK_POST_DIV_MASK);
2402 mpll_dq_func_cntl |= YCLK_SEL(mpll_param.yclk_sel) |
2403 YCLK_POST_DIV(mpll_param.post_div);
2406 if (pi->caps_mclk_ss_support) {
2407 struct radeon_atom_ss ss;
2410 u32 reference_clock = rdev->clock.mpll.reference_freq;
2412 if (mpll_param.qdr == 1)
2413 freq_nom = memory_clock * 4 * (1 << mpll_param.post_div);
2415 freq_nom = memory_clock * 2 * (1 << mpll_param.post_div);
2417 tmp = (freq_nom / reference_clock);
2419 if (radeon_atombios_get_asic_ss_info(rdev, &ss,
2420 ASIC_INTERNAL_MEMORY_SS, freq_nom)) {
2421 u32 clks = reference_clock * 5 / ss.rate;
2422 u32 clkv = (u32)((((131 * ss.percentage * ss.rate) / 100) * tmp) / freq_nom);
2424 mpll_ss1 &= ~CLKV_MASK;
2425 mpll_ss1 |= CLKV(clkv);
2427 mpll_ss2 &= ~CLKS_MASK;
2428 mpll_ss2 |= CLKS(clks);
2432 mclk_pwrmgt_cntl &= ~DLL_SPEED_MASK;
2433 mclk_pwrmgt_cntl |= DLL_SPEED(mpll_param.dll_speed);
2436 mclk_pwrmgt_cntl |= MRDCK0_PDNB | MRDCK1_PDNB;
2438 mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB);
2440 mclk->MclkFrequency = memory_clock;
2441 mclk->MpllFuncCntl = mpll_func_cntl;
2442 mclk->MpllFuncCntl_1 = mpll_func_cntl_1;
2443 mclk->MpllFuncCntl_2 = mpll_func_cntl_2;
2444 mclk->MpllAdFuncCntl = mpll_ad_func_cntl;
2445 mclk->MpllDqFuncCntl = mpll_dq_func_cntl;
2446 mclk->MclkPwrmgtCntl = mclk_pwrmgt_cntl;
2447 mclk->DllCntl = dll_cntl;
2448 mclk->MpllSs1 = mpll_ss1;
2449 mclk->MpllSs2 = mpll_ss2;
2454 static int ci_populate_single_memory_level(struct radeon_device *rdev,
2456 SMU7_Discrete_MemoryLevel *memory_level)
2458 struct ci_power_info *pi = ci_get_pi(rdev);
2462 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk.entries) {
2463 ret = ci_get_dependency_volt_by_clk(rdev,
2464 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
2465 memory_clock, &memory_level->MinVddc);
2470 if (rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk.entries) {
2471 ret = ci_get_dependency_volt_by_clk(rdev,
2472 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
2473 memory_clock, &memory_level->MinVddci);
2478 if (rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.entries) {
2479 ret = ci_get_dependency_volt_by_clk(rdev,
2480 &rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk,
2481 memory_clock, &memory_level->MinMvdd);
2486 memory_level->MinVddcPhases = 1;
2488 if (pi->vddc_phase_shed_control)
2489 ci_populate_phase_value_based_on_mclk(rdev,
2490 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table,
2492 &memory_level->MinVddcPhases);
2494 memory_level->EnabledForThrottle = 1;
2495 memory_level->UpH = 0;
2496 memory_level->DownH = 100;
2497 memory_level->VoltageDownH = 0;
2498 memory_level->ActivityLevel = (u16)pi->mclk_activity_target;
2500 memory_level->StutterEnable = false;
2501 memory_level->StrobeEnable = false;
2502 memory_level->EdcReadEnable = false;
2503 memory_level->EdcWriteEnable = false;
2504 memory_level->RttEnable = false;
2506 memory_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
2508 if (pi->mclk_stutter_mode_threshold &&
2509 (memory_clock <= pi->mclk_stutter_mode_threshold) &&
2510 (pi->uvd_enabled == false) &&
2511 (RREG32(DPG_PIPE_STUTTER_CONTROL) & STUTTER_ENABLE) &&
2512 (rdev->pm.dpm.new_active_crtc_count <= 2))
2513 memory_level->StutterEnable = true;
2515 if (pi->mclk_strobe_mode_threshold &&
2516 (memory_clock <= pi->mclk_strobe_mode_threshold))
2517 memory_level->StrobeEnable = 1;
2519 if (pi->mem_gddr5) {
2520 memory_level->StrobeRatio =
2521 si_get_mclk_frequency_ratio(memory_clock, memory_level->StrobeEnable);
2522 if (pi->mclk_edc_enable_threshold &&
2523 (memory_clock > pi->mclk_edc_enable_threshold))
2524 memory_level->EdcReadEnable = true;
2526 if (pi->mclk_edc_wr_enable_threshold &&
2527 (memory_clock > pi->mclk_edc_wr_enable_threshold))
2528 memory_level->EdcWriteEnable = true;
2530 if (memory_level->StrobeEnable) {
2531 if (si_get_mclk_frequency_ratio(memory_clock, true) >=
2532 ((RREG32(MC_SEQ_MISC7) >> 16) & 0xf))
2533 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
2535 dll_state_on = ((RREG32(MC_SEQ_MISC6) >> 1) & 0x1) ? true : false;
2537 dll_state_on = pi->dll_default_on;
2540 memory_level->StrobeRatio = si_get_ddr3_mclk_frequency_ratio(memory_clock);
2541 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
2544 ret = ci_calculate_mclk_params(rdev, memory_clock, memory_level, memory_level->StrobeEnable, dll_state_on);
2548 memory_level->MinVddc = cpu_to_be32(memory_level->MinVddc * VOLTAGE_SCALE);
2549 memory_level->MinVddcPhases = cpu_to_be32(memory_level->MinVddcPhases);
2550 memory_level->MinVddci = cpu_to_be32(memory_level->MinVddci * VOLTAGE_SCALE);
2551 memory_level->MinMvdd = cpu_to_be32(memory_level->MinMvdd * VOLTAGE_SCALE);
2553 memory_level->MclkFrequency = cpu_to_be32(memory_level->MclkFrequency);
2554 memory_level->ActivityLevel = cpu_to_be16(memory_level->ActivityLevel);
2555 memory_level->MpllFuncCntl = cpu_to_be32(memory_level->MpllFuncCntl);
2556 memory_level->MpllFuncCntl_1 = cpu_to_be32(memory_level->MpllFuncCntl_1);
2557 memory_level->MpllFuncCntl_2 = cpu_to_be32(memory_level->MpllFuncCntl_2);
2558 memory_level->MpllAdFuncCntl = cpu_to_be32(memory_level->MpllAdFuncCntl);
2559 memory_level->MpllDqFuncCntl = cpu_to_be32(memory_level->MpllDqFuncCntl);
2560 memory_level->MclkPwrmgtCntl = cpu_to_be32(memory_level->MclkPwrmgtCntl);
2561 memory_level->DllCntl = cpu_to_be32(memory_level->DllCntl);
2562 memory_level->MpllSs1 = cpu_to_be32(memory_level->MpllSs1);
2563 memory_level->MpllSs2 = cpu_to_be32(memory_level->MpllSs2);
2568 static int ci_populate_smc_acpi_level(struct radeon_device *rdev,
2569 SMU7_Discrete_DpmTable *table)
2571 struct ci_power_info *pi = ci_get_pi(rdev);
2572 struct atom_clock_dividers dividers;
2573 SMU7_Discrete_VoltageLevel voltage_level;
2574 u32 spll_func_cntl = pi->clock_registers.cg_spll_func_cntl;
2575 u32 spll_func_cntl_2 = pi->clock_registers.cg_spll_func_cntl_2;
2576 u32 dll_cntl = pi->clock_registers.dll_cntl;
2577 u32 mclk_pwrmgt_cntl = pi->clock_registers.mclk_pwrmgt_cntl;
2580 table->ACPILevel.Flags &= ~PPSMC_SWSTATE_FLAG_DC;
2583 table->ACPILevel.MinVddc = cpu_to_be32(pi->acpi_vddc * VOLTAGE_SCALE);
2585 table->ACPILevel.MinVddc = cpu_to_be32(pi->min_vddc_in_pp_table * VOLTAGE_SCALE);
2587 table->ACPILevel.MinVddcPhases = pi->vddc_phase_shed_control ? 0 : 1;
2589 table->ACPILevel.SclkFrequency = rdev->clock.spll.reference_freq;
2591 ret = radeon_atom_get_clock_dividers(rdev,
2592 COMPUTE_GPUCLK_INPUT_FLAG_SCLK,
2593 table->ACPILevel.SclkFrequency, false, ÷rs);
2597 table->ACPILevel.SclkDid = (u8)dividers.post_divider;
2598 table->ACPILevel.DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
2599 table->ACPILevel.DeepSleepDivId = 0;
2601 spll_func_cntl &= ~SPLL_PWRON;
2602 spll_func_cntl |= SPLL_RESET;
2604 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK;
2605 spll_func_cntl_2 |= SCLK_MUX_SEL(4);
2607 table->ACPILevel.CgSpllFuncCntl = spll_func_cntl;
2608 table->ACPILevel.CgSpllFuncCntl2 = spll_func_cntl_2;
2609 table->ACPILevel.CgSpllFuncCntl3 = pi->clock_registers.cg_spll_func_cntl_3;
2610 table->ACPILevel.CgSpllFuncCntl4 = pi->clock_registers.cg_spll_func_cntl_4;
2611 table->ACPILevel.SpllSpreadSpectrum = pi->clock_registers.cg_spll_spread_spectrum;
2612 table->ACPILevel.SpllSpreadSpectrum2 = pi->clock_registers.cg_spll_spread_spectrum_2;
2613 table->ACPILevel.CcPwrDynRm = 0;
2614 table->ACPILevel.CcPwrDynRm1 = 0;
2616 table->ACPILevel.Flags = cpu_to_be32(table->ACPILevel.Flags);
2617 table->ACPILevel.MinVddcPhases = cpu_to_be32(table->ACPILevel.MinVddcPhases);
2618 table->ACPILevel.SclkFrequency = cpu_to_be32(table->ACPILevel.SclkFrequency);
2619 table->ACPILevel.CgSpllFuncCntl = cpu_to_be32(table->ACPILevel.CgSpllFuncCntl);
2620 table->ACPILevel.CgSpllFuncCntl2 = cpu_to_be32(table->ACPILevel.CgSpllFuncCntl2);
2621 table->ACPILevel.CgSpllFuncCntl3 = cpu_to_be32(table->ACPILevel.CgSpllFuncCntl3);
2622 table->ACPILevel.CgSpllFuncCntl4 = cpu_to_be32(table->ACPILevel.CgSpllFuncCntl4);
2623 table->ACPILevel.SpllSpreadSpectrum = cpu_to_be32(table->ACPILevel.SpllSpreadSpectrum);
2624 table->ACPILevel.SpllSpreadSpectrum2 = cpu_to_be32(table->ACPILevel.SpllSpreadSpectrum2);
2625 table->ACPILevel.CcPwrDynRm = cpu_to_be32(table->ACPILevel.CcPwrDynRm);
2626 table->ACPILevel.CcPwrDynRm1 = cpu_to_be32(table->ACPILevel.CcPwrDynRm1);
2628 table->MemoryACPILevel.MinVddc = table->ACPILevel.MinVddc;
2629 table->MemoryACPILevel.MinVddcPhases = table->ACPILevel.MinVddcPhases;
2631 if (pi->vddci_control != CISLANDS_VOLTAGE_CONTROL_NONE) {
2633 table->MemoryACPILevel.MinVddci =
2634 cpu_to_be32(pi->acpi_vddci * VOLTAGE_SCALE);
2636 table->MemoryACPILevel.MinVddci =
2637 cpu_to_be32(pi->min_vddci_in_pp_table * VOLTAGE_SCALE);
2640 if (ci_populate_mvdd_value(rdev, 0, &voltage_level))
2641 table->MemoryACPILevel.MinMvdd = 0;
2643 table->MemoryACPILevel.MinMvdd =
2644 cpu_to_be32(voltage_level.Voltage * VOLTAGE_SCALE);
2646 mclk_pwrmgt_cntl |= MRDCK0_RESET | MRDCK1_RESET;
2647 mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB);
2649 dll_cntl &= ~(MRDCK0_BYPASS | MRDCK1_BYPASS);
2651 table->MemoryACPILevel.DllCntl = cpu_to_be32(dll_cntl);
2652 table->MemoryACPILevel.MclkPwrmgtCntl = cpu_to_be32(mclk_pwrmgt_cntl);
2653 table->MemoryACPILevel.MpllAdFuncCntl =
2654 cpu_to_be32(pi->clock_registers.mpll_ad_func_cntl);
2655 table->MemoryACPILevel.MpllDqFuncCntl =
2656 cpu_to_be32(pi->clock_registers.mpll_dq_func_cntl);
2657 table->MemoryACPILevel.MpllFuncCntl =
2658 cpu_to_be32(pi->clock_registers.mpll_func_cntl);
2659 table->MemoryACPILevel.MpllFuncCntl_1 =
2660 cpu_to_be32(pi->clock_registers.mpll_func_cntl_1);
2661 table->MemoryACPILevel.MpllFuncCntl_2 =
2662 cpu_to_be32(pi->clock_registers.mpll_func_cntl_2);
2663 table->MemoryACPILevel.MpllSs1 = cpu_to_be32(pi->clock_registers.mpll_ss1);
2664 table->MemoryACPILevel.MpllSs2 = cpu_to_be32(pi->clock_registers.mpll_ss2);
2666 table->MemoryACPILevel.EnabledForThrottle = 0;
2667 table->MemoryACPILevel.EnabledForActivity = 0;
2668 table->MemoryACPILevel.UpH = 0;
2669 table->MemoryACPILevel.DownH = 100;
2670 table->MemoryACPILevel.VoltageDownH = 0;
2671 table->MemoryACPILevel.ActivityLevel =
2672 cpu_to_be16((u16)pi->mclk_activity_target);
2674 table->MemoryACPILevel.StutterEnable = false;
2675 table->MemoryACPILevel.StrobeEnable = false;
2676 table->MemoryACPILevel.EdcReadEnable = false;
2677 table->MemoryACPILevel.EdcWriteEnable = false;
2678 table->MemoryACPILevel.RttEnable = false;
2684 static int ci_enable_ulv(struct radeon_device *rdev, bool enable)
2686 struct ci_power_info *pi = ci_get_pi(rdev);
2687 struct ci_ulv_parm *ulv = &pi->ulv;
2689 if (ulv->supported) {
2691 return (ci_send_msg_to_smc(rdev, PPSMC_MSG_EnableULV) == PPSMC_Result_OK) ?
2694 return (ci_send_msg_to_smc(rdev, PPSMC_MSG_DisableULV) == PPSMC_Result_OK) ?
2701 static int ci_populate_ulv_level(struct radeon_device *rdev,
2702 SMU7_Discrete_Ulv *state)
2704 struct ci_power_info *pi = ci_get_pi(rdev);
2705 u16 ulv_voltage = rdev->pm.dpm.backbias_response_time;
2707 state->CcPwrDynRm = 0;
2708 state->CcPwrDynRm1 = 0;
2710 if (ulv_voltage == 0) {
2711 pi->ulv.supported = false;
2715 if (pi->voltage_control != CISLANDS_VOLTAGE_CONTROL_BY_SVID2) {
2716 if (ulv_voltage > rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v)
2717 state->VddcOffset = 0;
2720 rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v - ulv_voltage;
2722 if (ulv_voltage > rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v)
2723 state->VddcOffsetVid = 0;
2725 state->VddcOffsetVid = (u8)
2726 ((rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v - ulv_voltage) *
2727 VOLTAGE_VID_OFFSET_SCALE2 / VOLTAGE_VID_OFFSET_SCALE1);
2729 state->VddcPhase = pi->vddc_phase_shed_control ? 0 : 1;
2731 state->CcPwrDynRm = cpu_to_be32(state->CcPwrDynRm);
2732 state->CcPwrDynRm1 = cpu_to_be32(state->CcPwrDynRm1);
2733 state->VddcOffset = cpu_to_be16(state->VddcOffset);
2738 static int ci_calculate_sclk_params(struct radeon_device *rdev,
2740 SMU7_Discrete_GraphicsLevel *sclk)
2742 struct ci_power_info *pi = ci_get_pi(rdev);
2743 struct atom_clock_dividers dividers;
2744 u32 spll_func_cntl_3 = pi->clock_registers.cg_spll_func_cntl_3;
2745 u32 spll_func_cntl_4 = pi->clock_registers.cg_spll_func_cntl_4;
2746 u32 cg_spll_spread_spectrum = pi->clock_registers.cg_spll_spread_spectrum;
2747 u32 cg_spll_spread_spectrum_2 = pi->clock_registers.cg_spll_spread_spectrum_2;
2748 u32 reference_clock = rdev->clock.spll.reference_freq;
2749 u32 reference_divider;
2753 ret = radeon_atom_get_clock_dividers(rdev,
2754 COMPUTE_GPUCLK_INPUT_FLAG_SCLK,
2755 engine_clock, false, ÷rs);
2759 reference_divider = 1 + dividers.ref_div;
2760 fbdiv = dividers.fb_div & 0x3FFFFFF;
2762 spll_func_cntl_3 &= ~SPLL_FB_DIV_MASK;
2763 spll_func_cntl_3 |= SPLL_FB_DIV(fbdiv);
2764 spll_func_cntl_3 |= SPLL_DITHEN;
2766 if (pi->caps_sclk_ss_support) {
2767 struct radeon_atom_ss ss;
2768 u32 vco_freq = engine_clock * dividers.post_div;
2770 if (radeon_atombios_get_asic_ss_info(rdev, &ss,
2771 ASIC_INTERNAL_ENGINE_SS, vco_freq)) {
2772 u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate);
2773 u32 clk_v = 4 * ss.percentage * fbdiv / (clk_s * 10000);
2775 cg_spll_spread_spectrum &= ~CLK_S_MASK;
2776 cg_spll_spread_spectrum |= CLK_S(clk_s);
2777 cg_spll_spread_spectrum |= SSEN;
2779 cg_spll_spread_spectrum_2 &= ~CLK_V_MASK;
2780 cg_spll_spread_spectrum_2 |= CLK_V(clk_v);
2784 sclk->SclkFrequency = engine_clock;
2785 sclk->CgSpllFuncCntl3 = spll_func_cntl_3;
2786 sclk->CgSpllFuncCntl4 = spll_func_cntl_4;
2787 sclk->SpllSpreadSpectrum = cg_spll_spread_spectrum;
2788 sclk->SpllSpreadSpectrum2 = cg_spll_spread_spectrum_2;
2789 sclk->SclkDid = (u8)dividers.post_divider;
2794 static int ci_populate_single_graphic_level(struct radeon_device *rdev,
2796 u16 sclk_activity_level_t,
2797 SMU7_Discrete_GraphicsLevel *graphic_level)
2799 struct ci_power_info *pi = ci_get_pi(rdev);
2802 ret = ci_calculate_sclk_params(rdev, engine_clock, graphic_level);
2806 ret = ci_get_dependency_volt_by_clk(rdev,
2807 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk,
2808 engine_clock, &graphic_level->MinVddc);
2812 graphic_level->SclkFrequency = engine_clock;
2814 graphic_level->Flags = 0;
2815 graphic_level->MinVddcPhases = 1;
2817 if (pi->vddc_phase_shed_control)
2818 ci_populate_phase_value_based_on_sclk(rdev,
2819 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table,
2821 &graphic_level->MinVddcPhases);
2823 graphic_level->ActivityLevel = sclk_activity_level_t;
2825 graphic_level->CcPwrDynRm = 0;
2826 graphic_level->CcPwrDynRm1 = 0;
2827 graphic_level->EnabledForThrottle = 1;
2828 graphic_level->UpH = 0;
2829 graphic_level->DownH = 0;
2830 graphic_level->VoltageDownH = 0;
2831 graphic_level->PowerThrottle = 0;
2833 if (pi->caps_sclk_ds)
2834 graphic_level->DeepSleepDivId = ci_get_sleep_divider_id_from_clock(rdev,
2836 CISLAND_MINIMUM_ENGINE_CLOCK);
2838 graphic_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
2840 graphic_level->Flags = cpu_to_be32(graphic_level->Flags);
2841 graphic_level->MinVddc = cpu_to_be32(graphic_level->MinVddc * VOLTAGE_SCALE);
2842 graphic_level->MinVddcPhases = cpu_to_be32(graphic_level->MinVddcPhases);
2843 graphic_level->SclkFrequency = cpu_to_be32(graphic_level->SclkFrequency);
2844 graphic_level->ActivityLevel = cpu_to_be16(graphic_level->ActivityLevel);
2845 graphic_level->CgSpllFuncCntl3 = cpu_to_be32(graphic_level->CgSpllFuncCntl3);
2846 graphic_level->CgSpllFuncCntl4 = cpu_to_be32(graphic_level->CgSpllFuncCntl4);
2847 graphic_level->SpllSpreadSpectrum = cpu_to_be32(graphic_level->SpllSpreadSpectrum);
2848 graphic_level->SpllSpreadSpectrum2 = cpu_to_be32(graphic_level->SpllSpreadSpectrum2);
2849 graphic_level->CcPwrDynRm = cpu_to_be32(graphic_level->CcPwrDynRm);
2850 graphic_level->CcPwrDynRm1 = cpu_to_be32(graphic_level->CcPwrDynRm1);
2855 static int ci_populate_all_graphic_levels(struct radeon_device *rdev)
2857 struct ci_power_info *pi = ci_get_pi(rdev);
2858 struct ci_dpm_table *dpm_table = &pi->dpm_table;
2859 u32 level_array_address = pi->dpm_table_start +
2860 offsetof(SMU7_Discrete_DpmTable, GraphicsLevel);
2861 u32 level_array_size = sizeof(SMU7_Discrete_GraphicsLevel) *
2862 SMU7_MAX_LEVELS_GRAPHICS;
2863 SMU7_Discrete_GraphicsLevel *levels = pi->smc_state_table.GraphicsLevel;
2866 memset(levels, 0, level_array_size);
2868 for (i = 0; i < dpm_table->sclk_table.count; i++) {
2869 ret = ci_populate_single_graphic_level(rdev,
2870 dpm_table->sclk_table.dpm_levels[i].value,
2871 (u16)pi->activity_target[i],
2872 &pi->smc_state_table.GraphicsLevel[i]);
2876 pi->smc_state_table.GraphicsLevel[i].DeepSleepDivId = 0;
2877 if (i == (dpm_table->sclk_table.count - 1))
2878 pi->smc_state_table.GraphicsLevel[i].DisplayWatermark =
2879 PPSMC_DISPLAY_WATERMARK_HIGH;
2881 pi->smc_state_table.GraphicsLevel[0].EnabledForActivity = 1;
2883 pi->smc_state_table.GraphicsDpmLevelCount = (u8)dpm_table->sclk_table.count;
2884 pi->dpm_level_enable_mask.sclk_dpm_enable_mask =
2885 ci_get_dpm_level_enable_mask_value(&dpm_table->sclk_table);
2887 ret = ci_copy_bytes_to_smc(rdev, level_array_address,
2888 (u8 *)levels, level_array_size,
2896 static int ci_populate_ulv_state(struct radeon_device *rdev,
2897 SMU7_Discrete_Ulv *ulv_level)
2899 return ci_populate_ulv_level(rdev, ulv_level);
2902 static int ci_populate_all_memory_levels(struct radeon_device *rdev)
2904 struct ci_power_info *pi = ci_get_pi(rdev);
2905 struct ci_dpm_table *dpm_table = &pi->dpm_table;
2906 u32 level_array_address = pi->dpm_table_start +
2907 offsetof(SMU7_Discrete_DpmTable, MemoryLevel);
2908 u32 level_array_size = sizeof(SMU7_Discrete_MemoryLevel) *
2909 SMU7_MAX_LEVELS_MEMORY;
2910 SMU7_Discrete_MemoryLevel *levels = pi->smc_state_table.MemoryLevel;
2913 memset(levels, 0, level_array_size);
2915 for (i = 0; i < dpm_table->mclk_table.count; i++) {
2916 if (dpm_table->mclk_table.dpm_levels[i].value == 0)
2918 ret = ci_populate_single_memory_level(rdev,
2919 dpm_table->mclk_table.dpm_levels[i].value,
2920 &pi->smc_state_table.MemoryLevel[i]);
2925 pi->smc_state_table.MemoryLevel[0].EnabledForActivity = 1;
2927 if ((dpm_table->mclk_table.count >= 2) &&
2928 ((rdev->pdev->device == 0x67B0) || (rdev->pdev->device == 0x67B1))) {
2929 pi->smc_state_table.MemoryLevel[1].MinVddc =
2930 pi->smc_state_table.MemoryLevel[0].MinVddc;
2931 pi->smc_state_table.MemoryLevel[1].MinVddcPhases =
2932 pi->smc_state_table.MemoryLevel[0].MinVddcPhases;
2935 pi->smc_state_table.MemoryLevel[0].ActivityLevel = cpu_to_be16(0x1F);
2937 pi->smc_state_table.MemoryDpmLevelCount = (u8)dpm_table->mclk_table.count;
2938 pi->dpm_level_enable_mask.mclk_dpm_enable_mask =
2939 ci_get_dpm_level_enable_mask_value(&dpm_table->mclk_table);
2941 pi->smc_state_table.MemoryLevel[dpm_table->mclk_table.count - 1].DisplayWatermark =
2942 PPSMC_DISPLAY_WATERMARK_HIGH;
2944 ret = ci_copy_bytes_to_smc(rdev, level_array_address,
2945 (u8 *)levels, level_array_size,
2953 static void ci_reset_single_dpm_table(struct radeon_device *rdev,
2954 struct ci_single_dpm_table* dpm_table,
2959 dpm_table->count = count;
2960 for (i = 0; i < MAX_REGULAR_DPM_NUMBER; i++)
2961 dpm_table->dpm_levels[i].enabled = false;
2964 static void ci_setup_pcie_table_entry(struct ci_single_dpm_table* dpm_table,
2965 u32 index, u32 pcie_gen, u32 pcie_lanes)
2967 dpm_table->dpm_levels[index].value = pcie_gen;
2968 dpm_table->dpm_levels[index].param1 = pcie_lanes;
2969 dpm_table->dpm_levels[index].enabled = true;
2972 static int ci_setup_default_pcie_tables(struct radeon_device *rdev)
2974 struct ci_power_info *pi = ci_get_pi(rdev);
2976 if (!pi->use_pcie_performance_levels && !pi->use_pcie_powersaving_levels)
2979 if (pi->use_pcie_performance_levels && !pi->use_pcie_powersaving_levels) {
2980 pi->pcie_gen_powersaving = pi->pcie_gen_performance;
2981 pi->pcie_lane_powersaving = pi->pcie_lane_performance;
2982 } else if (!pi->use_pcie_performance_levels && pi->use_pcie_powersaving_levels) {
2983 pi->pcie_gen_performance = pi->pcie_gen_powersaving;
2984 pi->pcie_lane_performance = pi->pcie_lane_powersaving;
2987 ci_reset_single_dpm_table(rdev,
2988 &pi->dpm_table.pcie_speed_table,
2989 SMU7_MAX_LEVELS_LINK);
2991 if (rdev->family == CHIP_BONAIRE)
2992 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 0,
2993 pi->pcie_gen_powersaving.min,
2994 pi->pcie_lane_powersaving.max);
2996 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 0,
2997 pi->pcie_gen_powersaving.min,
2998 pi->pcie_lane_powersaving.min);
2999 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 1,
3000 pi->pcie_gen_performance.min,
3001 pi->pcie_lane_performance.min);
3002 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 2,
3003 pi->pcie_gen_powersaving.min,
3004 pi->pcie_lane_powersaving.max);
3005 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 3,
3006 pi->pcie_gen_performance.min,
3007 pi->pcie_lane_performance.max);
3008 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 4,
3009 pi->pcie_gen_powersaving.max,
3010 pi->pcie_lane_powersaving.max);
3011 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 5,
3012 pi->pcie_gen_performance.max,
3013 pi->pcie_lane_performance.max);
3015 pi->dpm_table.pcie_speed_table.count = 6;
3020 static int ci_setup_default_dpm_tables(struct radeon_device *rdev)
3022 struct ci_power_info *pi = ci_get_pi(rdev);
3023 struct radeon_clock_voltage_dependency_table *allowed_sclk_vddc_table =
3024 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
3025 struct radeon_clock_voltage_dependency_table *allowed_mclk_table =
3026 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk;
3027 struct radeon_cac_leakage_table *std_voltage_table =
3028 &rdev->pm.dpm.dyn_state.cac_leakage_table;
3031 if (allowed_sclk_vddc_table == NULL)
3033 if (allowed_sclk_vddc_table->count < 1)
3035 if (allowed_mclk_table == NULL)
3037 if (allowed_mclk_table->count < 1)
3040 memset(&pi->dpm_table, 0, sizeof(struct ci_dpm_table));
3042 ci_reset_single_dpm_table(rdev,
3043 &pi->dpm_table.sclk_table,
3044 SMU7_MAX_LEVELS_GRAPHICS);
3045 ci_reset_single_dpm_table(rdev,
3046 &pi->dpm_table.mclk_table,
3047 SMU7_MAX_LEVELS_MEMORY);
3048 ci_reset_single_dpm_table(rdev,
3049 &pi->dpm_table.vddc_table,
3050 SMU7_MAX_LEVELS_VDDC);
3051 ci_reset_single_dpm_table(rdev,
3052 &pi->dpm_table.vddci_table,
3053 SMU7_MAX_LEVELS_VDDCI);
3054 ci_reset_single_dpm_table(rdev,
3055 &pi->dpm_table.mvdd_table,
3056 SMU7_MAX_LEVELS_MVDD);
3058 pi->dpm_table.sclk_table.count = 0;
3059 for (i = 0; i < allowed_sclk_vddc_table->count; i++) {
3061 (pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count-1].value !=
3062 allowed_sclk_vddc_table->entries[i].clk)) {
3063 pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count].value =
3064 allowed_sclk_vddc_table->entries[i].clk;
3065 pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count].enabled =
3066 (i == 0) ? true : false;
3067 pi->dpm_table.sclk_table.count++;
3071 pi->dpm_table.mclk_table.count = 0;
3072 for (i = 0; i < allowed_mclk_table->count; i++) {
3074 (pi->dpm_table.mclk_table.dpm_levels[pi->dpm_table.mclk_table.count-1].value !=
3075 allowed_mclk_table->entries[i].clk)) {
3076 pi->dpm_table.mclk_table.dpm_levels[pi->dpm_table.mclk_table.count].value =
3077 allowed_mclk_table->entries[i].clk;
3078 pi->dpm_table.mclk_table.dpm_levels[pi->dpm_table.mclk_table.count].enabled =
3079 (i == 0) ? true : false;
3080 pi->dpm_table.mclk_table.count++;
3084 for (i = 0; i < allowed_sclk_vddc_table->count; i++) {
3085 pi->dpm_table.vddc_table.dpm_levels[i].value =
3086 allowed_sclk_vddc_table->entries[i].v;
3087 pi->dpm_table.vddc_table.dpm_levels[i].param1 =
3088 std_voltage_table->entries[i].leakage;
3089 pi->dpm_table.vddc_table.dpm_levels[i].enabled = true;
3091 pi->dpm_table.vddc_table.count = allowed_sclk_vddc_table->count;
3093 allowed_mclk_table = &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk;
3094 if (allowed_mclk_table) {
3095 for (i = 0; i < allowed_mclk_table->count; i++) {
3096 pi->dpm_table.vddci_table.dpm_levels[i].value =
3097 allowed_mclk_table->entries[i].v;
3098 pi->dpm_table.vddci_table.dpm_levels[i].enabled = true;
3100 pi->dpm_table.vddci_table.count = allowed_mclk_table->count;
3103 allowed_mclk_table = &rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk;
3104 if (allowed_mclk_table) {
3105 for (i = 0; i < allowed_mclk_table->count; i++) {
3106 pi->dpm_table.mvdd_table.dpm_levels[i].value =
3107 allowed_mclk_table->entries[i].v;
3108 pi->dpm_table.mvdd_table.dpm_levels[i].enabled = true;
3110 pi->dpm_table.mvdd_table.count = allowed_mclk_table->count;
3113 ci_setup_default_pcie_tables(rdev);
3118 static int ci_find_boot_level(struct ci_single_dpm_table *table,
3119 u32 value, u32 *boot_level)
3124 for(i = 0; i < table->count; i++) {
3125 if (value == table->dpm_levels[i].value) {
3134 static int ci_init_smc_table(struct radeon_device *rdev)
3136 struct ci_power_info *pi = ci_get_pi(rdev);
3137 struct ci_ulv_parm *ulv = &pi->ulv;
3138 struct radeon_ps *radeon_boot_state = rdev->pm.dpm.boot_ps;
3139 SMU7_Discrete_DpmTable *table = &pi->smc_state_table;
3142 ret = ci_setup_default_dpm_tables(rdev);
3146 if (pi->voltage_control != CISLANDS_VOLTAGE_CONTROL_NONE)
3147 ci_populate_smc_voltage_tables(rdev, table);
3149 ci_init_fps_limits(rdev);
3151 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC)
3152 table->SystemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC;
3154 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC)
3155 table->SystemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;
3158 table->SystemFlags |= PPSMC_SYSTEMFLAG_GDDR5;
3160 if (ulv->supported) {
3161 ret = ci_populate_ulv_state(rdev, &pi->smc_state_table.Ulv);
3164 WREG32_SMC(CG_ULV_PARAMETER, ulv->cg_ulv_parameter);
3167 ret = ci_populate_all_graphic_levels(rdev);
3171 ret = ci_populate_all_memory_levels(rdev);
3175 ci_populate_smc_link_level(rdev, table);
3177 ret = ci_populate_smc_acpi_level(rdev, table);
3181 ret = ci_populate_smc_vce_level(rdev, table);
3185 ret = ci_populate_smc_acp_level(rdev, table);
3189 ret = ci_populate_smc_samu_level(rdev, table);
3193 ret = ci_do_program_memory_timing_parameters(rdev);
3197 ret = ci_populate_smc_uvd_level(rdev, table);
3201 table->UvdBootLevel = 0;
3202 table->VceBootLevel = 0;
3203 table->AcpBootLevel = 0;
3204 table->SamuBootLevel = 0;
3205 table->GraphicsBootLevel = 0;
3206 table->MemoryBootLevel = 0;
3208 ret = ci_find_boot_level(&pi->dpm_table.sclk_table,
3209 pi->vbios_boot_state.sclk_bootup_value,
3210 (u32 *)&pi->smc_state_table.GraphicsBootLevel);
3212 ret = ci_find_boot_level(&pi->dpm_table.mclk_table,
3213 pi->vbios_boot_state.mclk_bootup_value,
3214 (u32 *)&pi->smc_state_table.MemoryBootLevel);
3216 table->BootVddc = pi->vbios_boot_state.vddc_bootup_value;
3217 table->BootVddci = pi->vbios_boot_state.vddci_bootup_value;
3218 table->BootMVdd = pi->vbios_boot_state.mvdd_bootup_value;
3220 ci_populate_smc_initial_state(rdev, radeon_boot_state);
3222 ret = ci_populate_bapm_parameters_in_dpm_table(rdev);
3226 table->UVDInterval = 1;
3227 table->VCEInterval = 1;
3228 table->ACPInterval = 1;
3229 table->SAMUInterval = 1;
3230 table->GraphicsVoltageChangeEnable = 1;
3231 table->GraphicsThermThrottleEnable = 1;
3232 table->GraphicsInterval = 1;
3233 table->VoltageInterval = 1;
3234 table->ThermalInterval = 1;
3235 table->TemperatureLimitHigh = (u16)((pi->thermal_temp_setting.temperature_high *
3236 CISLANDS_Q88_FORMAT_CONVERSION_UNIT) / 1000);
3237 table->TemperatureLimitLow = (u16)((pi->thermal_temp_setting.temperature_low *
3238 CISLANDS_Q88_FORMAT_CONVERSION_UNIT) / 1000);
3239 table->MemoryVoltageChangeEnable = 1;
3240 table->MemoryInterval = 1;
3241 table->VoltageResponseTime = 0;
3242 table->VddcVddciDelta = 4000;
3243 table->PhaseResponseTime = 0;
3244 table->MemoryThermThrottleEnable = 1;
3245 table->PCIeBootLinkLevel = 0;
3246 table->PCIeGenInterval = 1;
3247 if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2)
3248 table->SVI2Enable = 1;
3250 table->SVI2Enable = 0;
3252 table->ThermGpio = 17;
3253 table->SclkStepSize = 0x4000;
3255 table->SystemFlags = cpu_to_be32(table->SystemFlags);
3256 table->SmioMaskVddcVid = cpu_to_be32(table->SmioMaskVddcVid);
3257 table->SmioMaskVddcPhase = cpu_to_be32(table->SmioMaskVddcPhase);
3258 table->SmioMaskVddciVid = cpu_to_be32(table->SmioMaskVddciVid);
3259 table->SmioMaskMvddVid = cpu_to_be32(table->SmioMaskMvddVid);
3260 table->SclkStepSize = cpu_to_be32(table->SclkStepSize);
3261 table->TemperatureLimitHigh = cpu_to_be16(table->TemperatureLimitHigh);
3262 table->TemperatureLimitLow = cpu_to_be16(table->TemperatureLimitLow);
3263 table->VddcVddciDelta = cpu_to_be16(table->VddcVddciDelta);
3264 table->VoltageResponseTime = cpu_to_be16(table->VoltageResponseTime);
3265 table->PhaseResponseTime = cpu_to_be16(table->PhaseResponseTime);
3266 table->BootVddc = cpu_to_be16(table->BootVddc * VOLTAGE_SCALE);
3267 table->BootVddci = cpu_to_be16(table->BootVddci * VOLTAGE_SCALE);
3268 table->BootMVdd = cpu_to_be16(table->BootMVdd * VOLTAGE_SCALE);
3270 ret = ci_copy_bytes_to_smc(rdev,
3271 pi->dpm_table_start +
3272 offsetof(SMU7_Discrete_DpmTable, SystemFlags),
3273 (u8 *)&table->SystemFlags,
3274 sizeof(SMU7_Discrete_DpmTable) - 3 * sizeof(SMU7_PIDController),
3282 static void ci_trim_single_dpm_states(struct radeon_device *rdev,
3283 struct ci_single_dpm_table *dpm_table,
3284 u32 low_limit, u32 high_limit)
3288 for (i = 0; i < dpm_table->count; i++) {
3289 if ((dpm_table->dpm_levels[i].value < low_limit) ||
3290 (dpm_table->dpm_levels[i].value > high_limit))
3291 dpm_table->dpm_levels[i].enabled = false;
3293 dpm_table->dpm_levels[i].enabled = true;
3297 static void ci_trim_pcie_dpm_states(struct radeon_device *rdev,
3298 u32 speed_low, u32 lanes_low,
3299 u32 speed_high, u32 lanes_high)
3301 struct ci_power_info *pi = ci_get_pi(rdev);
3302 struct ci_single_dpm_table *pcie_table = &pi->dpm_table.pcie_speed_table;
3305 for (i = 0; i < pcie_table->count; i++) {
3306 if ((pcie_table->dpm_levels[i].value < speed_low) ||
3307 (pcie_table->dpm_levels[i].param1 < lanes_low) ||
3308 (pcie_table->dpm_levels[i].value > speed_high) ||
3309 (pcie_table->dpm_levels[i].param1 > lanes_high))
3310 pcie_table->dpm_levels[i].enabled = false;
3312 pcie_table->dpm_levels[i].enabled = true;
3315 for (i = 0; i < pcie_table->count; i++) {
3316 if (pcie_table->dpm_levels[i].enabled) {
3317 for (j = i + 1; j < pcie_table->count; j++) {
3318 if (pcie_table->dpm_levels[j].enabled) {
3319 if ((pcie_table->dpm_levels[i].value == pcie_table->dpm_levels[j].value) &&
3320 (pcie_table->dpm_levels[i].param1 == pcie_table->dpm_levels[j].param1))
3321 pcie_table->dpm_levels[j].enabled = false;
3328 static int ci_trim_dpm_states(struct radeon_device *rdev,
3329 struct radeon_ps *radeon_state)
3331 struct ci_ps *state = ci_get_ps(radeon_state);
3332 struct ci_power_info *pi = ci_get_pi(rdev);
3333 u32 high_limit_count;
3335 if (state->performance_level_count < 1)
3338 if (state->performance_level_count == 1)
3339 high_limit_count = 0;
3341 high_limit_count = 1;
3343 ci_trim_single_dpm_states(rdev,
3344 &pi->dpm_table.sclk_table,
3345 state->performance_levels[0].sclk,
3346 state->performance_levels[high_limit_count].sclk);
3348 ci_trim_single_dpm_states(rdev,
3349 &pi->dpm_table.mclk_table,
3350 state->performance_levels[0].mclk,
3351 state->performance_levels[high_limit_count].mclk);
3353 ci_trim_pcie_dpm_states(rdev,
3354 state->performance_levels[0].pcie_gen,
3355 state->performance_levels[0].pcie_lane,
3356 state->performance_levels[high_limit_count].pcie_gen,
3357 state->performance_levels[high_limit_count].pcie_lane);
3362 static int ci_apply_disp_minimum_voltage_request(struct radeon_device *rdev)
3364 struct radeon_clock_voltage_dependency_table *disp_voltage_table =
3365 &rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk;
3366 struct radeon_clock_voltage_dependency_table *vddc_table =
3367 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
3368 u32 requested_voltage = 0;
3371 if (disp_voltage_table == NULL)
3373 if (!disp_voltage_table->count)
3376 for (i = 0; i < disp_voltage_table->count; i++) {
3377 if (rdev->clock.current_dispclk == disp_voltage_table->entries[i].clk)
3378 requested_voltage = disp_voltage_table->entries[i].v;
3381 for (i = 0; i < vddc_table->count; i++) {
3382 if (requested_voltage <= vddc_table->entries[i].v) {
3383 requested_voltage = vddc_table->entries[i].v;
3384 return (ci_send_msg_to_smc_with_parameter(rdev,
3385 PPSMC_MSG_VddC_Request,
3386 requested_voltage * VOLTAGE_SCALE) == PPSMC_Result_OK) ?
3394 static int ci_upload_dpm_level_enable_mask(struct radeon_device *rdev)
3396 struct ci_power_info *pi = ci_get_pi(rdev);
3397 PPSMC_Result result;
3399 if (!pi->sclk_dpm_key_disabled) {
3400 if (pi->dpm_level_enable_mask.sclk_dpm_enable_mask) {
3401 result = ci_send_msg_to_smc_with_parameter(rdev,
3402 PPSMC_MSG_SCLKDPM_SetEnabledMask,
3403 pi->dpm_level_enable_mask.sclk_dpm_enable_mask);
3404 if (result != PPSMC_Result_OK)
3409 if (!pi->mclk_dpm_key_disabled) {
3410 if (pi->dpm_level_enable_mask.mclk_dpm_enable_mask) {
3411 result = ci_send_msg_to_smc_with_parameter(rdev,
3412 PPSMC_MSG_MCLKDPM_SetEnabledMask,
3413 pi->dpm_level_enable_mask.mclk_dpm_enable_mask);
3414 if (result != PPSMC_Result_OK)
3419 if (!pi->pcie_dpm_key_disabled) {
3420 if (pi->dpm_level_enable_mask.pcie_dpm_enable_mask) {
3421 result = ci_send_msg_to_smc_with_parameter(rdev,
3422 PPSMC_MSG_PCIeDPM_SetEnabledMask,
3423 pi->dpm_level_enable_mask.pcie_dpm_enable_mask);
3424 if (result != PPSMC_Result_OK)
3429 ci_apply_disp_minimum_voltage_request(rdev);
3434 static void ci_find_dpm_states_clocks_in_dpm_table(struct radeon_device *rdev,
3435 struct radeon_ps *radeon_state)
3437 struct ci_power_info *pi = ci_get_pi(rdev);
3438 struct ci_ps *state = ci_get_ps(radeon_state);
3439 struct ci_single_dpm_table *sclk_table = &pi->dpm_table.sclk_table;
3440 u32 sclk = state->performance_levels[state->performance_level_count-1].sclk;
3441 struct ci_single_dpm_table *mclk_table = &pi->dpm_table.mclk_table;
3442 u32 mclk = state->performance_levels[state->performance_level_count-1].mclk;
3445 pi->need_update_smu7_dpm_table = 0;
3447 for (i = 0; i < sclk_table->count; i++) {
3448 if (sclk == sclk_table->dpm_levels[i].value)
3452 if (i >= sclk_table->count) {
3453 pi->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_SCLK;
3455 /* XXX check display min clock requirements */
3456 if (0 != CISLAND_MINIMUM_ENGINE_CLOCK)
3457 pi->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_SCLK;
3460 for (i = 0; i < mclk_table->count; i++) {
3461 if (mclk == mclk_table->dpm_levels[i].value)
3465 if (i >= mclk_table->count)
3466 pi->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_MCLK;
3468 if (rdev->pm.dpm.current_active_crtc_count !=
3469 rdev->pm.dpm.new_active_crtc_count)
3470 pi->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_MCLK;
3473 static int ci_populate_and_upload_sclk_mclk_dpm_levels(struct radeon_device *rdev,
3474 struct radeon_ps *radeon_state)
3476 struct ci_power_info *pi = ci_get_pi(rdev);
3477 struct ci_ps *state = ci_get_ps(radeon_state);
3478 u32 sclk = state->performance_levels[state->performance_level_count-1].sclk;
3479 u32 mclk = state->performance_levels[state->performance_level_count-1].mclk;
3480 struct ci_dpm_table *dpm_table = &pi->dpm_table;
3483 if (!pi->need_update_smu7_dpm_table)
3486 if (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_SCLK)
3487 dpm_table->sclk_table.dpm_levels[dpm_table->sclk_table.count-1].value = sclk;
3489 if (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)
3490 dpm_table->mclk_table.dpm_levels[dpm_table->mclk_table.count-1].value = mclk;
3492 if (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK)) {
3493 ret = ci_populate_all_graphic_levels(rdev);
3498 if (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_MCLK | DPMTABLE_UPDATE_MCLK)) {
3499 ret = ci_populate_all_memory_levels(rdev);
3507 static int ci_enable_uvd_dpm(struct radeon_device *rdev, bool enable)
3509 struct ci_power_info *pi = ci_get_pi(rdev);
3510 const struct radeon_clock_and_voltage_limits *max_limits;
3513 if (rdev->pm.dpm.ac_power)
3514 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
3516 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
3519 pi->dpm_level_enable_mask.uvd_dpm_enable_mask = 0;
3521 for (i = rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count - 1; i >= 0; i--) {
3522 if (rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) {
3523 pi->dpm_level_enable_mask.uvd_dpm_enable_mask |= 1 << i;
3525 if (!pi->caps_uvd_dpm)
3530 ci_send_msg_to_smc_with_parameter(rdev,
3531 PPSMC_MSG_UVDDPM_SetEnabledMask,
3532 pi->dpm_level_enable_mask.uvd_dpm_enable_mask);
3534 if (pi->last_mclk_dpm_enable_mask & 0x1) {
3535 pi->uvd_enabled = true;
3536 pi->dpm_level_enable_mask.mclk_dpm_enable_mask &= 0xFFFFFFFE;
3537 ci_send_msg_to_smc_with_parameter(rdev,
3538 PPSMC_MSG_MCLKDPM_SetEnabledMask,
3539 pi->dpm_level_enable_mask.mclk_dpm_enable_mask);
3542 if (pi->last_mclk_dpm_enable_mask & 0x1) {
3543 pi->uvd_enabled = false;
3544 pi->dpm_level_enable_mask.mclk_dpm_enable_mask |= 1;
3545 ci_send_msg_to_smc_with_parameter(rdev,
3546 PPSMC_MSG_MCLKDPM_SetEnabledMask,
3547 pi->dpm_level_enable_mask.mclk_dpm_enable_mask);
3551 return (ci_send_msg_to_smc(rdev, enable ?
3552 PPSMC_MSG_UVDDPM_Enable : PPSMC_MSG_UVDDPM_Disable) == PPSMC_Result_OK) ?
3556 static int ci_enable_vce_dpm(struct radeon_device *rdev, bool enable)
3558 struct ci_power_info *pi = ci_get_pi(rdev);
3559 const struct radeon_clock_and_voltage_limits *max_limits;
3562 if (rdev->pm.dpm.ac_power)
3563 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
3565 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
3568 pi->dpm_level_enable_mask.vce_dpm_enable_mask = 0;
3569 for (i = rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.count - 1; i >= 0; i--) {
3570 if (rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) {
3571 pi->dpm_level_enable_mask.vce_dpm_enable_mask |= 1 << i;
3573 if (!pi->caps_vce_dpm)
3578 ci_send_msg_to_smc_with_parameter(rdev,
3579 PPSMC_MSG_VCEDPM_SetEnabledMask,
3580 pi->dpm_level_enable_mask.vce_dpm_enable_mask);
3583 return (ci_send_msg_to_smc(rdev, enable ?
3584 PPSMC_MSG_VCEDPM_Enable : PPSMC_MSG_VCEDPM_Disable) == PPSMC_Result_OK) ?
3589 static int ci_enable_samu_dpm(struct radeon_device *rdev, bool enable)
3591 struct ci_power_info *pi = ci_get_pi(rdev);
3592 const struct radeon_clock_and_voltage_limits *max_limits;
3595 if (rdev->pm.dpm.ac_power)
3596 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
3598 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
3601 pi->dpm_level_enable_mask.samu_dpm_enable_mask = 0;
3602 for (i = rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.count - 1; i >= 0; i--) {
3603 if (rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) {
3604 pi->dpm_level_enable_mask.samu_dpm_enable_mask |= 1 << i;
3606 if (!pi->caps_samu_dpm)
3611 ci_send_msg_to_smc_with_parameter(rdev,
3612 PPSMC_MSG_SAMUDPM_SetEnabledMask,
3613 pi->dpm_level_enable_mask.samu_dpm_enable_mask);
3615 return (ci_send_msg_to_smc(rdev, enable ?
3616 PPSMC_MSG_SAMUDPM_Enable : PPSMC_MSG_SAMUDPM_Disable) == PPSMC_Result_OK) ?
3620 static int ci_enable_acp_dpm(struct radeon_device *rdev, bool enable)
3622 struct ci_power_info *pi = ci_get_pi(rdev);
3623 const struct radeon_clock_and_voltage_limits *max_limits;
3626 if (rdev->pm.dpm.ac_power)
3627 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
3629 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
3632 pi->dpm_level_enable_mask.acp_dpm_enable_mask = 0;
3633 for (i = rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.count - 1; i >= 0; i--) {
3634 if (rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) {
3635 pi->dpm_level_enable_mask.acp_dpm_enable_mask |= 1 << i;
3637 if (!pi->caps_acp_dpm)
3642 ci_send_msg_to_smc_with_parameter(rdev,
3643 PPSMC_MSG_ACPDPM_SetEnabledMask,
3644 pi->dpm_level_enable_mask.acp_dpm_enable_mask);
3647 return (ci_send_msg_to_smc(rdev, enable ?
3648 PPSMC_MSG_ACPDPM_Enable : PPSMC_MSG_ACPDPM_Disable) == PPSMC_Result_OK) ?
3653 static int ci_update_uvd_dpm(struct radeon_device *rdev, bool gate)
3655 struct ci_power_info *pi = ci_get_pi(rdev);
3659 if (pi->caps_uvd_dpm ||
3660 (rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count <= 0))
3661 pi->smc_state_table.UvdBootLevel = 0;
3663 pi->smc_state_table.UvdBootLevel =
3664 rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count - 1;
3666 tmp = RREG32_SMC(DPM_TABLE_475);
3667 tmp &= ~UvdBootLevel_MASK;
3668 tmp |= UvdBootLevel(pi->smc_state_table.UvdBootLevel);
3669 WREG32_SMC(DPM_TABLE_475, tmp);
3672 return ci_enable_uvd_dpm(rdev, !gate);
3675 static u8 ci_get_vce_boot_level(struct radeon_device *rdev)
3678 u32 min_evclk = 30000; /* ??? */
3679 struct radeon_vce_clock_voltage_dependency_table *table =
3680 &rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
3682 for (i = 0; i < table->count; i++) {
3683 if (table->entries[i].evclk >= min_evclk)
3687 return table->count - 1;
3690 static int ci_update_vce_dpm(struct radeon_device *rdev,
3691 struct radeon_ps *radeon_new_state,
3692 struct radeon_ps *radeon_current_state)
3694 struct ci_power_info *pi = ci_get_pi(rdev);
3698 if (radeon_current_state->evclk != radeon_new_state->evclk) {
3699 if (radeon_new_state->evclk) {
3700 /* turn the clocks on when encoding */
3701 cik_update_cg(rdev, RADEON_CG_BLOCK_VCE, false);
3703 pi->smc_state_table.VceBootLevel = ci_get_vce_boot_level(rdev);
3704 tmp = RREG32_SMC(DPM_TABLE_475);
3705 tmp &= ~VceBootLevel_MASK;
3706 tmp |= VceBootLevel(pi->smc_state_table.VceBootLevel);
3707 WREG32_SMC(DPM_TABLE_475, tmp);
3709 ret = ci_enable_vce_dpm(rdev, true);
3711 /* turn the clocks off when not encoding */
3712 cik_update_cg(rdev, RADEON_CG_BLOCK_VCE, true);
3714 ret = ci_enable_vce_dpm(rdev, false);
3721 static int ci_update_samu_dpm(struct radeon_device *rdev, bool gate)
3723 return ci_enable_samu_dpm(rdev, gate);
3726 static int ci_update_acp_dpm(struct radeon_device *rdev, bool gate)
3728 struct ci_power_info *pi = ci_get_pi(rdev);
3732 pi->smc_state_table.AcpBootLevel = 0;
3734 tmp = RREG32_SMC(DPM_TABLE_475);
3735 tmp &= ~AcpBootLevel_MASK;
3736 tmp |= AcpBootLevel(pi->smc_state_table.AcpBootLevel);
3737 WREG32_SMC(DPM_TABLE_475, tmp);
3740 return ci_enable_acp_dpm(rdev, !gate);
3744 static int ci_generate_dpm_level_enable_mask(struct radeon_device *rdev,
3745 struct radeon_ps *radeon_state)
3747 struct ci_power_info *pi = ci_get_pi(rdev);
3750 ret = ci_trim_dpm_states(rdev, radeon_state);
3754 pi->dpm_level_enable_mask.sclk_dpm_enable_mask =
3755 ci_get_dpm_level_enable_mask_value(&pi->dpm_table.sclk_table);
3756 pi->dpm_level_enable_mask.mclk_dpm_enable_mask =
3757 ci_get_dpm_level_enable_mask_value(&pi->dpm_table.mclk_table);
3758 pi->last_mclk_dpm_enable_mask =
3759 pi->dpm_level_enable_mask.mclk_dpm_enable_mask;
3760 if (pi->uvd_enabled) {
3761 if (pi->dpm_level_enable_mask.mclk_dpm_enable_mask & 1)
3762 pi->dpm_level_enable_mask.mclk_dpm_enable_mask &= 0xFFFFFFFE;
3764 pi->dpm_level_enable_mask.pcie_dpm_enable_mask =
3765 ci_get_dpm_level_enable_mask_value(&pi->dpm_table.pcie_speed_table);
3770 static u32 ci_get_lowest_enabled_level(struct radeon_device *rdev,
3775 while ((level_mask & (1 << level)) == 0)
3782 int ci_dpm_force_performance_level(struct radeon_device *rdev,
3783 enum radeon_dpm_forced_level level)
3785 struct ci_power_info *pi = ci_get_pi(rdev);
3789 if (level == RADEON_DPM_FORCED_LEVEL_HIGH) {
3790 if ((!pi->sclk_dpm_key_disabled) &&
3791 pi->dpm_level_enable_mask.sclk_dpm_enable_mask) {
3793 tmp = pi->dpm_level_enable_mask.sclk_dpm_enable_mask;
3797 ret = ci_dpm_force_state_sclk(rdev, levels);
3800 for (i = 0; i < rdev->usec_timeout; i++) {
3801 tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX) &
3802 CURR_SCLK_INDEX_MASK) >> CURR_SCLK_INDEX_SHIFT;
3809 if ((!pi->mclk_dpm_key_disabled) &&
3810 pi->dpm_level_enable_mask.mclk_dpm_enable_mask) {
3812 tmp = pi->dpm_level_enable_mask.mclk_dpm_enable_mask;
3816 ret = ci_dpm_force_state_mclk(rdev, levels);
3819 for (i = 0; i < rdev->usec_timeout; i++) {
3820 tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX) &
3821 CURR_MCLK_INDEX_MASK) >> CURR_MCLK_INDEX_SHIFT;
3828 if ((!pi->pcie_dpm_key_disabled) &&
3829 pi->dpm_level_enable_mask.pcie_dpm_enable_mask) {
3831 tmp = pi->dpm_level_enable_mask.pcie_dpm_enable_mask;
3835 ret = ci_dpm_force_state_pcie(rdev, level);
3838 for (i = 0; i < rdev->usec_timeout; i++) {
3839 tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX_1) &
3840 CURR_PCIE_INDEX_MASK) >> CURR_PCIE_INDEX_SHIFT;
3847 } else if (level == RADEON_DPM_FORCED_LEVEL_LOW) {
3848 if ((!pi->sclk_dpm_key_disabled) &&
3849 pi->dpm_level_enable_mask.sclk_dpm_enable_mask) {
3850 levels = ci_get_lowest_enabled_level(rdev,
3851 pi->dpm_level_enable_mask.sclk_dpm_enable_mask);
3852 ret = ci_dpm_force_state_sclk(rdev, levels);
3855 for (i = 0; i < rdev->usec_timeout; i++) {
3856 tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX) &
3857 CURR_SCLK_INDEX_MASK) >> CURR_SCLK_INDEX_SHIFT;
3863 if ((!pi->mclk_dpm_key_disabled) &&
3864 pi->dpm_level_enable_mask.mclk_dpm_enable_mask) {
3865 levels = ci_get_lowest_enabled_level(rdev,
3866 pi->dpm_level_enable_mask.mclk_dpm_enable_mask);
3867 ret = ci_dpm_force_state_mclk(rdev, levels);
3870 for (i = 0; i < rdev->usec_timeout; i++) {
3871 tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX) &
3872 CURR_MCLK_INDEX_MASK) >> CURR_MCLK_INDEX_SHIFT;
3878 if ((!pi->pcie_dpm_key_disabled) &&
3879 pi->dpm_level_enable_mask.pcie_dpm_enable_mask) {
3880 levels = ci_get_lowest_enabled_level(rdev,
3881 pi->dpm_level_enable_mask.pcie_dpm_enable_mask);
3882 ret = ci_dpm_force_state_pcie(rdev, levels);
3885 for (i = 0; i < rdev->usec_timeout; i++) {
3886 tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX_1) &
3887 CURR_PCIE_INDEX_MASK) >> CURR_PCIE_INDEX_SHIFT;
3893 } else if (level == RADEON_DPM_FORCED_LEVEL_AUTO) {
3894 ret = ci_upload_dpm_level_enable_mask(rdev);
3899 rdev->pm.dpm.forced_level = level;
3904 static int ci_set_mc_special_registers(struct radeon_device *rdev,
3905 struct ci_mc_reg_table *table)
3907 struct ci_power_info *pi = ci_get_pi(rdev);
3911 for (i = 0, j = table->last; i < table->last; i++) {
3912 if (j >= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
3914 switch(table->mc_reg_address[i].s1 << 2) {
3916 temp_reg = RREG32(MC_PMG_CMD_EMRS);
3917 table->mc_reg_address[j].s1 = MC_PMG_CMD_EMRS >> 2;
3918 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_EMRS_LP >> 2;
3919 for (k = 0; k < table->num_entries; k++) {
3920 table->mc_reg_table_entry[k].mc_data[j] =
3921 ((temp_reg & 0xffff0000)) | ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16);
3924 if (j >= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
3927 temp_reg = RREG32(MC_PMG_CMD_MRS);
3928 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS >> 2;
3929 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS_LP >> 2;
3930 for (k = 0; k < table->num_entries; k++) {
3931 table->mc_reg_table_entry[k].mc_data[j] =
3932 (temp_reg & 0xffff0000) | (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
3934 table->mc_reg_table_entry[k].mc_data[j] |= 0x100;
3937 if (j > SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
3940 if (!pi->mem_gddr5) {
3941 table->mc_reg_address[j].s1 = MC_PMG_AUTO_CMD >> 2;
3942 table->mc_reg_address[j].s0 = MC_PMG_AUTO_CMD >> 2;
3943 for (k = 0; k < table->num_entries; k++) {
3944 table->mc_reg_table_entry[k].mc_data[j] =
3945 (table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16;
3948 if (j > SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
3952 case MC_SEQ_RESERVE_M:
3953 temp_reg = RREG32(MC_PMG_CMD_MRS1);
3954 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS1 >> 2;
3955 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS1_LP >> 2;
3956 for (k = 0; k < table->num_entries; k++) {
3957 table->mc_reg_table_entry[k].mc_data[j] =
3958 (temp_reg & 0xffff0000) | (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
3961 if (j > SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
3975 static bool ci_check_s0_mc_reg_index(u16 in_reg, u16 *out_reg)
3980 case MC_SEQ_RAS_TIMING >> 2:
3981 *out_reg = MC_SEQ_RAS_TIMING_LP >> 2;
3983 case MC_SEQ_DLL_STBY >> 2:
3984 *out_reg = MC_SEQ_DLL_STBY_LP >> 2;
3986 case MC_SEQ_G5PDX_CMD0 >> 2:
3987 *out_reg = MC_SEQ_G5PDX_CMD0_LP >> 2;
3989 case MC_SEQ_G5PDX_CMD1 >> 2:
3990 *out_reg = MC_SEQ_G5PDX_CMD1_LP >> 2;
3992 case MC_SEQ_G5PDX_CTRL >> 2:
3993 *out_reg = MC_SEQ_G5PDX_CTRL_LP >> 2;
3995 case MC_SEQ_CAS_TIMING >> 2:
3996 *out_reg = MC_SEQ_CAS_TIMING_LP >> 2;
3998 case MC_SEQ_MISC_TIMING >> 2:
3999 *out_reg = MC_SEQ_MISC_TIMING_LP >> 2;
4001 case MC_SEQ_MISC_TIMING2 >> 2:
4002 *out_reg = MC_SEQ_MISC_TIMING2_LP >> 2;
4004 case MC_SEQ_PMG_DVS_CMD >> 2:
4005 *out_reg = MC_SEQ_PMG_DVS_CMD_LP >> 2;
4007 case MC_SEQ_PMG_DVS_CTL >> 2:
4008 *out_reg = MC_SEQ_PMG_DVS_CTL_LP >> 2;
4010 case MC_SEQ_RD_CTL_D0 >> 2:
4011 *out_reg = MC_SEQ_RD_CTL_D0_LP >> 2;
4013 case MC_SEQ_RD_CTL_D1 >> 2:
4014 *out_reg = MC_SEQ_RD_CTL_D1_LP >> 2;
4016 case MC_SEQ_WR_CTL_D0 >> 2:
4017 *out_reg = MC_SEQ_WR_CTL_D0_LP >> 2;
4019 case MC_SEQ_WR_CTL_D1 >> 2:
4020 *out_reg = MC_SEQ_WR_CTL_D1_LP >> 2;
4022 case MC_PMG_CMD_EMRS >> 2:
4023 *out_reg = MC_SEQ_PMG_CMD_EMRS_LP >> 2;
4025 case MC_PMG_CMD_MRS >> 2:
4026 *out_reg = MC_SEQ_PMG_CMD_MRS_LP >> 2;
4028 case MC_PMG_CMD_MRS1 >> 2:
4029 *out_reg = MC_SEQ_PMG_CMD_MRS1_LP >> 2;
4031 case MC_SEQ_PMG_TIMING >> 2:
4032 *out_reg = MC_SEQ_PMG_TIMING_LP >> 2;
4034 case MC_PMG_CMD_MRS2 >> 2:
4035 *out_reg = MC_SEQ_PMG_CMD_MRS2_LP >> 2;
4037 case MC_SEQ_WR_CTL_2 >> 2:
4038 *out_reg = MC_SEQ_WR_CTL_2_LP >> 2;
4048 static void ci_set_valid_flag(struct ci_mc_reg_table *table)
4052 for (i = 0; i < table->last; i++) {
4053 for (j = 1; j < table->num_entries; j++) {
4054 if (table->mc_reg_table_entry[j-1].mc_data[i] !=
4055 table->mc_reg_table_entry[j].mc_data[i]) {
4056 table->valid_flag |= 1 << i;
4063 static void ci_set_s0_mc_reg_index(struct ci_mc_reg_table *table)
4068 for (i = 0; i < table->last; i++) {
4069 table->mc_reg_address[i].s0 =
4070 ci_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address) ?
4071 address : table->mc_reg_address[i].s1;
4075 static int ci_copy_vbios_mc_reg_table(const struct atom_mc_reg_table *table,
4076 struct ci_mc_reg_table *ci_table)
4080 if (table->last > SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
4082 if (table->num_entries > MAX_AC_TIMING_ENTRIES)
4085 for (i = 0; i < table->last; i++)
4086 ci_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1;
4088 ci_table->last = table->last;
4090 for (i = 0; i < table->num_entries; i++) {
4091 ci_table->mc_reg_table_entry[i].mclk_max =
4092 table->mc_reg_table_entry[i].mclk_max;
4093 for (j = 0; j < table->last; j++)
4094 ci_table->mc_reg_table_entry[i].mc_data[j] =
4095 table->mc_reg_table_entry[i].mc_data[j];
4097 ci_table->num_entries = table->num_entries;
4102 static int ci_initialize_mc_reg_table(struct radeon_device *rdev)
4104 struct ci_power_info *pi = ci_get_pi(rdev);
4105 struct atom_mc_reg_table *table;
4106 struct ci_mc_reg_table *ci_table = &pi->mc_reg_table;
4107 u8 module_index = rv770_get_memory_module_index(rdev);
4110 table = kzalloc(sizeof(struct atom_mc_reg_table), GFP_KERNEL);
4114 WREG32(MC_SEQ_RAS_TIMING_LP, RREG32(MC_SEQ_RAS_TIMING));
4115 WREG32(MC_SEQ_CAS_TIMING_LP, RREG32(MC_SEQ_CAS_TIMING));
4116 WREG32(MC_SEQ_DLL_STBY_LP, RREG32(MC_SEQ_DLL_STBY));
4117 WREG32(MC_SEQ_G5PDX_CMD0_LP, RREG32(MC_SEQ_G5PDX_CMD0));
4118 WREG32(MC_SEQ_G5PDX_CMD1_LP, RREG32(MC_SEQ_G5PDX_CMD1));
4119 WREG32(MC_SEQ_G5PDX_CTRL_LP, RREG32(MC_SEQ_G5PDX_CTRL));
4120 WREG32(MC_SEQ_PMG_DVS_CMD_LP, RREG32(MC_SEQ_PMG_DVS_CMD));
4121 WREG32(MC_SEQ_PMG_DVS_CTL_LP, RREG32(MC_SEQ_PMG_DVS_CTL));
4122 WREG32(MC_SEQ_MISC_TIMING_LP, RREG32(MC_SEQ_MISC_TIMING));
4123 WREG32(MC_SEQ_MISC_TIMING2_LP, RREG32(MC_SEQ_MISC_TIMING2));
4124 WREG32(MC_SEQ_PMG_CMD_EMRS_LP, RREG32(MC_PMG_CMD_EMRS));
4125 WREG32(MC_SEQ_PMG_CMD_MRS_LP, RREG32(MC_PMG_CMD_MRS));
4126 WREG32(MC_SEQ_PMG_CMD_MRS1_LP, RREG32(MC_PMG_CMD_MRS1));
4127 WREG32(MC_SEQ_WR_CTL_D0_LP, RREG32(MC_SEQ_WR_CTL_D0));
4128 WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1));
4129 WREG32(MC_SEQ_RD_CTL_D0_LP, RREG32(MC_SEQ_RD_CTL_D0));
4130 WREG32(MC_SEQ_RD_CTL_D1_LP, RREG32(MC_SEQ_RD_CTL_D1));
4131 WREG32(MC_SEQ_PMG_TIMING_LP, RREG32(MC_SEQ_PMG_TIMING));
4132 WREG32(MC_SEQ_PMG_CMD_MRS2_LP, RREG32(MC_PMG_CMD_MRS2));
4133 WREG32(MC_SEQ_WR_CTL_2_LP, RREG32(MC_SEQ_WR_CTL_2));
4135 ret = radeon_atom_init_mc_reg_table(rdev, module_index, table);
4139 ret = ci_copy_vbios_mc_reg_table(table, ci_table);
4143 ci_set_s0_mc_reg_index(ci_table);
4145 ret = ci_set_mc_special_registers(rdev, ci_table);
4149 ci_set_valid_flag(ci_table);
4157 static int ci_populate_mc_reg_addresses(struct radeon_device *rdev,
4158 SMU7_Discrete_MCRegisters *mc_reg_table)
4160 struct ci_power_info *pi = ci_get_pi(rdev);
4163 for (i = 0, j = 0; j < pi->mc_reg_table.last; j++) {
4164 if (pi->mc_reg_table.valid_flag & (1 << j)) {
4165 if (i >= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
4167 mc_reg_table->address[i].s0 = cpu_to_be16(pi->mc_reg_table.mc_reg_address[j].s0);
4168 mc_reg_table->address[i].s1 = cpu_to_be16(pi->mc_reg_table.mc_reg_address[j].s1);
4173 mc_reg_table->last = (u8)i;
4178 static void ci_convert_mc_registers(const struct ci_mc_reg_entry *entry,
4179 SMU7_Discrete_MCRegisterSet *data,
4180 u32 num_entries, u32 valid_flag)
4184 for (i = 0, j = 0; j < num_entries; j++) {
4185 if (valid_flag & (1 << j)) {
4186 data->value[i] = cpu_to_be32(entry->mc_data[j]);
4192 static void ci_convert_mc_reg_table_entry_to_smc(struct radeon_device *rdev,
4193 const u32 memory_clock,
4194 SMU7_Discrete_MCRegisterSet *mc_reg_table_data)
4196 struct ci_power_info *pi = ci_get_pi(rdev);
4199 for(i = 0; i < pi->mc_reg_table.num_entries; i++) {
4200 if (memory_clock <= pi->mc_reg_table.mc_reg_table_entry[i].mclk_max)
4204 if ((i == pi->mc_reg_table.num_entries) && (i > 0))
4207 ci_convert_mc_registers(&pi->mc_reg_table.mc_reg_table_entry[i],
4208 mc_reg_table_data, pi->mc_reg_table.last,
4209 pi->mc_reg_table.valid_flag);
4212 static void ci_convert_mc_reg_table_to_smc(struct radeon_device *rdev,
4213 SMU7_Discrete_MCRegisters *mc_reg_table)
4215 struct ci_power_info *pi = ci_get_pi(rdev);
4218 for (i = 0; i < pi->dpm_table.mclk_table.count; i++)
4219 ci_convert_mc_reg_table_entry_to_smc(rdev,
4220 pi->dpm_table.mclk_table.dpm_levels[i].value,
4221 &mc_reg_table->data[i]);
4224 static int ci_populate_initial_mc_reg_table(struct radeon_device *rdev)
4226 struct ci_power_info *pi = ci_get_pi(rdev);
4229 memset(&pi->smc_mc_reg_table, 0, sizeof(SMU7_Discrete_MCRegisters));
4231 ret = ci_populate_mc_reg_addresses(rdev, &pi->smc_mc_reg_table);
4234 ci_convert_mc_reg_table_to_smc(rdev, &pi->smc_mc_reg_table);
4236 return ci_copy_bytes_to_smc(rdev,
4237 pi->mc_reg_table_start,
4238 (u8 *)&pi->smc_mc_reg_table,
4239 sizeof(SMU7_Discrete_MCRegisters),
4243 static int ci_update_and_upload_mc_reg_table(struct radeon_device *rdev)
4245 struct ci_power_info *pi = ci_get_pi(rdev);
4247 if (!(pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK))
4250 memset(&pi->smc_mc_reg_table, 0, sizeof(SMU7_Discrete_MCRegisters));
4252 ci_convert_mc_reg_table_to_smc(rdev, &pi->smc_mc_reg_table);
4254 return ci_copy_bytes_to_smc(rdev,
4255 pi->mc_reg_table_start +
4256 offsetof(SMU7_Discrete_MCRegisters, data[0]),
4257 (u8 *)&pi->smc_mc_reg_table.data[0],
4258 sizeof(SMU7_Discrete_MCRegisterSet) *
4259 pi->dpm_table.mclk_table.count,
4263 static void ci_enable_voltage_control(struct radeon_device *rdev)
4265 u32 tmp = RREG32_SMC(GENERAL_PWRMGT);
4267 tmp |= VOLT_PWRMGT_EN;
4268 WREG32_SMC(GENERAL_PWRMGT, tmp);
4271 static enum radeon_pcie_gen ci_get_maximum_link_speed(struct radeon_device *rdev,
4272 struct radeon_ps *radeon_state)
4274 struct ci_ps *state = ci_get_ps(radeon_state);
4276 u16 pcie_speed, max_speed = 0;
4278 for (i = 0; i < state->performance_level_count; i++) {
4279 pcie_speed = state->performance_levels[i].pcie_gen;
4280 if (max_speed < pcie_speed)
4281 max_speed = pcie_speed;
4287 static u16 ci_get_current_pcie_speed(struct radeon_device *rdev)
4291 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL) & LC_CURRENT_DATA_RATE_MASK;
4292 speed_cntl >>= LC_CURRENT_DATA_RATE_SHIFT;
4294 return (u16)speed_cntl;
4297 static int ci_get_current_pcie_lane_number(struct radeon_device *rdev)
4301 link_width = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL) & LC_LINK_WIDTH_RD_MASK;
4302 link_width >>= LC_LINK_WIDTH_RD_SHIFT;
4304 switch (link_width) {
4305 case RADEON_PCIE_LC_LINK_WIDTH_X1:
4307 case RADEON_PCIE_LC_LINK_WIDTH_X2:
4309 case RADEON_PCIE_LC_LINK_WIDTH_X4:
4311 case RADEON_PCIE_LC_LINK_WIDTH_X8:
4313 case RADEON_PCIE_LC_LINK_WIDTH_X12:
4314 /* not actually supported */
4316 case RADEON_PCIE_LC_LINK_WIDTH_X0:
4317 case RADEON_PCIE_LC_LINK_WIDTH_X16:
4323 static void ci_request_link_speed_change_before_state_change(struct radeon_device *rdev,
4324 struct radeon_ps *radeon_new_state,
4325 struct radeon_ps *radeon_current_state)
4327 struct ci_power_info *pi = ci_get_pi(rdev);
4328 enum radeon_pcie_gen target_link_speed =
4329 ci_get_maximum_link_speed(rdev, radeon_new_state);
4330 enum radeon_pcie_gen current_link_speed;
4332 if (pi->force_pcie_gen == RADEON_PCIE_GEN_INVALID)
4333 current_link_speed = ci_get_maximum_link_speed(rdev, radeon_current_state);
4335 current_link_speed = pi->force_pcie_gen;
4337 pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID;
4338 pi->pspp_notify_required = false;
4339 if (target_link_speed > current_link_speed) {
4340 switch (target_link_speed) {
4342 case RADEON_PCIE_GEN3:
4343 if (radeon_acpi_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN3, false) == 0)
4345 pi->force_pcie_gen = RADEON_PCIE_GEN2;
4346 if (current_link_speed == RADEON_PCIE_GEN2)
4348 case RADEON_PCIE_GEN2:
4349 if (radeon_acpi_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN2, false) == 0)
4353 pi->force_pcie_gen = ci_get_current_pcie_speed(rdev);
4357 if (target_link_speed < current_link_speed)
4358 pi->pspp_notify_required = true;
4362 static void ci_notify_link_speed_change_after_state_change(struct radeon_device *rdev,
4363 struct radeon_ps *radeon_new_state,
4364 struct radeon_ps *radeon_current_state)
4366 struct ci_power_info *pi = ci_get_pi(rdev);
4367 enum radeon_pcie_gen target_link_speed =
4368 ci_get_maximum_link_speed(rdev, radeon_new_state);
4371 if (pi->pspp_notify_required) {
4372 if (target_link_speed == RADEON_PCIE_GEN3)
4373 request = PCIE_PERF_REQ_PECI_GEN3;
4374 else if (target_link_speed == RADEON_PCIE_GEN2)
4375 request = PCIE_PERF_REQ_PECI_GEN2;
4377 request = PCIE_PERF_REQ_PECI_GEN1;
4379 if ((request == PCIE_PERF_REQ_PECI_GEN1) &&
4380 (ci_get_current_pcie_speed(rdev) > 0))
4384 radeon_acpi_pcie_performance_request(rdev, request, false);
4389 static int ci_set_private_data_variables_based_on_pptable(struct radeon_device *rdev)
4391 struct ci_power_info *pi = ci_get_pi(rdev);
4392 struct radeon_clock_voltage_dependency_table *allowed_sclk_vddc_table =
4393 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
4394 struct radeon_clock_voltage_dependency_table *allowed_mclk_vddc_table =
4395 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk;
4396 struct radeon_clock_voltage_dependency_table *allowed_mclk_vddci_table =
4397 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk;
4399 if (allowed_sclk_vddc_table == NULL)
4401 if (allowed_sclk_vddc_table->count < 1)
4403 if (allowed_mclk_vddc_table == NULL)
4405 if (allowed_mclk_vddc_table->count < 1)
4407 if (allowed_mclk_vddci_table == NULL)
4409 if (allowed_mclk_vddci_table->count < 1)
4412 pi->min_vddc_in_pp_table = allowed_sclk_vddc_table->entries[0].v;
4413 pi->max_vddc_in_pp_table =
4414 allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].v;
4416 pi->min_vddci_in_pp_table = allowed_mclk_vddci_table->entries[0].v;
4417 pi->max_vddci_in_pp_table =
4418 allowed_mclk_vddci_table->entries[allowed_mclk_vddci_table->count - 1].v;
4420 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk =
4421 allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].clk;
4422 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk =
4423 allowed_mclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].clk;
4424 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc =
4425 allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].v;
4426 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddci =
4427 allowed_mclk_vddci_table->entries[allowed_mclk_vddci_table->count - 1].v;
4432 static void ci_patch_with_vddc_leakage(struct radeon_device *rdev, u16 *vddc)
4434 struct ci_power_info *pi = ci_get_pi(rdev);
4435 struct ci_leakage_voltage *leakage_table = &pi->vddc_leakage;
4438 for (leakage_index = 0; leakage_index < leakage_table->count; leakage_index++) {
4439 if (leakage_table->leakage_id[leakage_index] == *vddc) {
4440 *vddc = leakage_table->actual_voltage[leakage_index];
4446 static void ci_patch_with_vddci_leakage(struct radeon_device *rdev, u16 *vddci)
4448 struct ci_power_info *pi = ci_get_pi(rdev);
4449 struct ci_leakage_voltage *leakage_table = &pi->vddci_leakage;
4452 for (leakage_index = 0; leakage_index < leakage_table->count; leakage_index++) {
4453 if (leakage_table->leakage_id[leakage_index] == *vddci) {
4454 *vddci = leakage_table->actual_voltage[leakage_index];
4460 static void ci_patch_clock_voltage_dependency_table_with_vddc_leakage(struct radeon_device *rdev,
4461 struct radeon_clock_voltage_dependency_table *table)
4466 for (i = 0; i < table->count; i++)
4467 ci_patch_with_vddc_leakage(rdev, &table->entries[i].v);
4471 static void ci_patch_clock_voltage_dependency_table_with_vddci_leakage(struct radeon_device *rdev,
4472 struct radeon_clock_voltage_dependency_table *table)
4477 for (i = 0; i < table->count; i++)
4478 ci_patch_with_vddci_leakage(rdev, &table->entries[i].v);
4482 static void ci_patch_vce_clock_voltage_dependency_table_with_vddc_leakage(struct radeon_device *rdev,
4483 struct radeon_vce_clock_voltage_dependency_table *table)
4488 for (i = 0; i < table->count; i++)
4489 ci_patch_with_vddc_leakage(rdev, &table->entries[i].v);
4493 static void ci_patch_uvd_clock_voltage_dependency_table_with_vddc_leakage(struct radeon_device *rdev,
4494 struct radeon_uvd_clock_voltage_dependency_table *table)
4499 for (i = 0; i < table->count; i++)
4500 ci_patch_with_vddc_leakage(rdev, &table->entries[i].v);
4504 static void ci_patch_vddc_phase_shed_limit_table_with_vddc_leakage(struct radeon_device *rdev,
4505 struct radeon_phase_shedding_limits_table *table)
4510 for (i = 0; i < table->count; i++)
4511 ci_patch_with_vddc_leakage(rdev, &table->entries[i].voltage);
4515 static void ci_patch_clock_voltage_limits_with_vddc_leakage(struct radeon_device *rdev,
4516 struct radeon_clock_and_voltage_limits *table)
4519 ci_patch_with_vddc_leakage(rdev, (u16 *)&table->vddc);
4520 ci_patch_with_vddci_leakage(rdev, (u16 *)&table->vddci);
4524 static void ci_patch_cac_leakage_table_with_vddc_leakage(struct radeon_device *rdev,
4525 struct radeon_cac_leakage_table *table)
4530 for (i = 0; i < table->count; i++)
4531 ci_patch_with_vddc_leakage(rdev, &table->entries[i].vddc);
4535 static void ci_patch_dependency_tables_with_leakage(struct radeon_device *rdev)
4538 ci_patch_clock_voltage_dependency_table_with_vddc_leakage(rdev,
4539 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk);
4540 ci_patch_clock_voltage_dependency_table_with_vddc_leakage(rdev,
4541 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk);
4542 ci_patch_clock_voltage_dependency_table_with_vddc_leakage(rdev,
4543 &rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk);
4544 ci_patch_clock_voltage_dependency_table_with_vddci_leakage(rdev,
4545 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk);
4546 ci_patch_vce_clock_voltage_dependency_table_with_vddc_leakage(rdev,
4547 &rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table);
4548 ci_patch_uvd_clock_voltage_dependency_table_with_vddc_leakage(rdev,
4549 &rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table);
4550 ci_patch_clock_voltage_dependency_table_with_vddc_leakage(rdev,
4551 &rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table);
4552 ci_patch_clock_voltage_dependency_table_with_vddc_leakage(rdev,
4553 &rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table);
4554 ci_patch_vddc_phase_shed_limit_table_with_vddc_leakage(rdev,
4555 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table);
4556 ci_patch_clock_voltage_limits_with_vddc_leakage(rdev,
4557 &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac);
4558 ci_patch_clock_voltage_limits_with_vddc_leakage(rdev,
4559 &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc);
4560 ci_patch_cac_leakage_table_with_vddc_leakage(rdev,
4561 &rdev->pm.dpm.dyn_state.cac_leakage_table);
4565 static void ci_get_memory_type(struct radeon_device *rdev)
4567 struct ci_power_info *pi = ci_get_pi(rdev);
4570 tmp = RREG32(MC_SEQ_MISC0);
4572 if (((tmp & MC_SEQ_MISC0_GDDR5_MASK) >> MC_SEQ_MISC0_GDDR5_SHIFT) ==
4573 MC_SEQ_MISC0_GDDR5_VALUE)
4574 pi->mem_gddr5 = true;
4576 pi->mem_gddr5 = false;
4580 static void ci_update_current_ps(struct radeon_device *rdev,
4581 struct radeon_ps *rps)
4583 struct ci_ps *new_ps = ci_get_ps(rps);
4584 struct ci_power_info *pi = ci_get_pi(rdev);
4586 pi->current_rps = *rps;
4587 pi->current_ps = *new_ps;
4588 pi->current_rps.ps_priv = &pi->current_ps;
4591 static void ci_update_requested_ps(struct radeon_device *rdev,
4592 struct radeon_ps *rps)
4594 struct ci_ps *new_ps = ci_get_ps(rps);
4595 struct ci_power_info *pi = ci_get_pi(rdev);
4597 pi->requested_rps = *rps;
4598 pi->requested_ps = *new_ps;
4599 pi->requested_rps.ps_priv = &pi->requested_ps;
4602 int ci_dpm_pre_set_power_state(struct radeon_device *rdev)
4604 struct ci_power_info *pi = ci_get_pi(rdev);
4605 struct radeon_ps requested_ps = *rdev->pm.dpm.requested_ps;
4606 struct radeon_ps *new_ps = &requested_ps;
4608 ci_update_requested_ps(rdev, new_ps);
4610 ci_apply_state_adjust_rules(rdev, &pi->requested_rps);
4615 void ci_dpm_post_set_power_state(struct radeon_device *rdev)
4617 struct ci_power_info *pi = ci_get_pi(rdev);
4618 struct radeon_ps *new_ps = &pi->requested_rps;
4620 ci_update_current_ps(rdev, new_ps);
4624 void ci_dpm_setup_asic(struct radeon_device *rdev)
4628 r = ci_mc_load_microcode(rdev);
4630 DRM_ERROR("Failed to load MC firmware!\n");
4631 ci_read_clock_registers(rdev);
4632 ci_get_memory_type(rdev);
4633 ci_enable_acpi_power_management(rdev);
4634 ci_init_sclk_t(rdev);
4637 int ci_dpm_enable(struct radeon_device *rdev)
4639 struct ci_power_info *pi = ci_get_pi(rdev);
4640 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;
4643 if (ci_is_smc_running(rdev))
4645 if (pi->voltage_control != CISLANDS_VOLTAGE_CONTROL_NONE) {
4646 ci_enable_voltage_control(rdev);
4647 ret = ci_construct_voltage_tables(rdev);
4649 DRM_ERROR("ci_construct_voltage_tables failed\n");
4653 if (pi->caps_dynamic_ac_timing) {
4654 ret = ci_initialize_mc_reg_table(rdev);
4656 pi->caps_dynamic_ac_timing = false;
4659 ci_enable_spread_spectrum(rdev, true);
4660 if (pi->thermal_protection)
4661 ci_enable_thermal_protection(rdev, true);
4662 ci_program_sstp(rdev);
4663 ci_enable_display_gap(rdev);
4664 ci_program_vc(rdev);
4665 ret = ci_upload_firmware(rdev);
4667 DRM_ERROR("ci_upload_firmware failed\n");
4670 ret = ci_process_firmware_header(rdev);
4672 DRM_ERROR("ci_process_firmware_header failed\n");
4675 ret = ci_initial_switch_from_arb_f0_to_f1(rdev);
4677 DRM_ERROR("ci_initial_switch_from_arb_f0_to_f1 failed\n");
4680 ret = ci_init_smc_table(rdev);
4682 DRM_ERROR("ci_init_smc_table failed\n");
4685 ret = ci_init_arb_table_index(rdev);
4687 DRM_ERROR("ci_init_arb_table_index failed\n");
4690 if (pi->caps_dynamic_ac_timing) {
4691 ret = ci_populate_initial_mc_reg_table(rdev);
4693 DRM_ERROR("ci_populate_initial_mc_reg_table failed\n");
4697 ret = ci_populate_pm_base(rdev);
4699 DRM_ERROR("ci_populate_pm_base failed\n");
4702 ci_dpm_start_smc(rdev);
4703 ci_enable_vr_hot_gpio_interrupt(rdev);
4704 ret = ci_notify_smc_display_change(rdev, false);
4706 DRM_ERROR("ci_notify_smc_display_change failed\n");
4709 ci_enable_sclk_control(rdev, true);
4710 ret = ci_enable_ulv(rdev, true);
4712 DRM_ERROR("ci_enable_ulv failed\n");
4715 ret = ci_enable_ds_master_switch(rdev, true);
4717 DRM_ERROR("ci_enable_ds_master_switch failed\n");
4720 ret = ci_start_dpm(rdev);
4722 DRM_ERROR("ci_start_dpm failed\n");
4725 ret = ci_enable_didt(rdev, true);
4727 DRM_ERROR("ci_enable_didt failed\n");
4730 ret = ci_enable_smc_cac(rdev, true);
4732 DRM_ERROR("ci_enable_smc_cac failed\n");
4735 ret = ci_enable_power_containment(rdev, true);
4737 DRM_ERROR("ci_enable_power_containment failed\n");
4741 ci_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, true);
4743 ci_update_current_ps(rdev, boot_ps);
4748 static int ci_set_temperature_range(struct radeon_device *rdev)
4752 ret = ci_thermal_enable_alert(rdev, false);
4755 ret = ci_thermal_set_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
4758 ret = ci_thermal_enable_alert(rdev, true);
4765 int ci_dpm_late_enable(struct radeon_device *rdev)
4769 ret = ci_set_temperature_range(rdev);
4773 ci_dpm_powergate_uvd(rdev, true);
4778 void ci_dpm_disable(struct radeon_device *rdev)
4780 struct ci_power_info *pi = ci_get_pi(rdev);
4781 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;
4783 ci_dpm_powergate_uvd(rdev, false);
4785 if (!ci_is_smc_running(rdev))
4788 if (pi->thermal_protection)
4789 ci_enable_thermal_protection(rdev, false);
4790 ci_enable_power_containment(rdev, false);
4791 ci_enable_smc_cac(rdev, false);
4792 ci_enable_didt(rdev, false);
4793 ci_enable_spread_spectrum(rdev, false);
4794 ci_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, false);
4796 ci_enable_ds_master_switch(rdev, false);
4797 ci_enable_ulv(rdev, false);
4799 ci_reset_to_default(rdev);
4800 ci_dpm_stop_smc(rdev);
4801 ci_force_switch_to_arb_f0(rdev);
4803 ci_update_current_ps(rdev, boot_ps);
4806 int ci_dpm_set_power_state(struct radeon_device *rdev)
4808 struct ci_power_info *pi = ci_get_pi(rdev);
4809 struct radeon_ps *new_ps = &pi->requested_rps;
4810 struct radeon_ps *old_ps = &pi->current_rps;
4813 ci_find_dpm_states_clocks_in_dpm_table(rdev, new_ps);
4814 if (pi->pcie_performance_request)
4815 ci_request_link_speed_change_before_state_change(rdev, new_ps, old_ps);
4816 ret = ci_freeze_sclk_mclk_dpm(rdev);
4818 DRM_ERROR("ci_freeze_sclk_mclk_dpm failed\n");
4821 ret = ci_populate_and_upload_sclk_mclk_dpm_levels(rdev, new_ps);
4823 DRM_ERROR("ci_populate_and_upload_sclk_mclk_dpm_levels failed\n");
4826 ret = ci_generate_dpm_level_enable_mask(rdev, new_ps);
4828 DRM_ERROR("ci_generate_dpm_level_enable_mask failed\n");
4832 ret = ci_update_vce_dpm(rdev, new_ps, old_ps);
4834 DRM_ERROR("ci_update_vce_dpm failed\n");
4838 ret = ci_update_sclk_t(rdev);
4840 DRM_ERROR("ci_update_sclk_t failed\n");
4843 if (pi->caps_dynamic_ac_timing) {
4844 ret = ci_update_and_upload_mc_reg_table(rdev);
4846 DRM_ERROR("ci_update_and_upload_mc_reg_table failed\n");
4850 ret = ci_program_memory_timing_parameters(rdev);
4852 DRM_ERROR("ci_program_memory_timing_parameters failed\n");
4855 ret = ci_unfreeze_sclk_mclk_dpm(rdev);
4857 DRM_ERROR("ci_unfreeze_sclk_mclk_dpm failed\n");
4860 ret = ci_upload_dpm_level_enable_mask(rdev);
4862 DRM_ERROR("ci_upload_dpm_level_enable_mask failed\n");
4865 if (pi->pcie_performance_request)
4866 ci_notify_link_speed_change_after_state_change(rdev, new_ps, old_ps);
4871 int ci_dpm_power_control_set_level(struct radeon_device *rdev)
4873 return ci_power_control_set_level(rdev);
4876 void ci_dpm_reset_asic(struct radeon_device *rdev)
4878 ci_set_boot_state(rdev);
4881 void ci_dpm_display_configuration_changed(struct radeon_device *rdev)
4883 ci_program_display_gap(rdev);
4887 struct _ATOM_POWERPLAY_INFO info;
4888 struct _ATOM_POWERPLAY_INFO_V2 info_2;
4889 struct _ATOM_POWERPLAY_INFO_V3 info_3;
4890 struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
4891 struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
4892 struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
4895 union pplib_clock_info {
4896 struct _ATOM_PPLIB_R600_CLOCK_INFO r600;
4897 struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780;
4898 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
4899 struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo;
4900 struct _ATOM_PPLIB_SI_CLOCK_INFO si;
4901 struct _ATOM_PPLIB_CI_CLOCK_INFO ci;
4904 union pplib_power_state {
4905 struct _ATOM_PPLIB_STATE v1;
4906 struct _ATOM_PPLIB_STATE_V2 v2;
4909 static void ci_parse_pplib_non_clock_info(struct radeon_device *rdev,
4910 struct radeon_ps *rps,
4911 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info,
4914 rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings);
4915 rps->class = le16_to_cpu(non_clock_info->usClassification);
4916 rps->class2 = le16_to_cpu(non_clock_info->usClassification2);
4918 if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) {
4919 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK);
4920 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK);
4926 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT)
4927 rdev->pm.dpm.boot_ps = rps;
4928 if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE)
4929 rdev->pm.dpm.uvd_ps = rps;
4932 static void ci_parse_pplib_clock_info(struct radeon_device *rdev,
4933 struct radeon_ps *rps, int index,
4934 union pplib_clock_info *clock_info)
4936 struct ci_power_info *pi = ci_get_pi(rdev);
4937 struct ci_ps *ps = ci_get_ps(rps);
4938 struct ci_pl *pl = &ps->performance_levels[index];
4940 ps->performance_level_count = index + 1;
4942 pl->sclk = le16_to_cpu(clock_info->ci.usEngineClockLow);
4943 pl->sclk |= clock_info->ci.ucEngineClockHigh << 16;
4944 pl->mclk = le16_to_cpu(clock_info->ci.usMemoryClockLow);
4945 pl->mclk |= clock_info->ci.ucMemoryClockHigh << 16;
4947 pl->pcie_gen = r600_get_pcie_gen_support(rdev,
4949 pi->vbios_boot_state.pcie_gen_bootup_value,
4950 clock_info->ci.ucPCIEGen);
4951 pl->pcie_lane = r600_get_pcie_lane_support(rdev,
4952 pi->vbios_boot_state.pcie_lane_bootup_value,
4953 le16_to_cpu(clock_info->ci.usPCIELane));
4955 if (rps->class & ATOM_PPLIB_CLASSIFICATION_ACPI) {
4956 pi->acpi_pcie_gen = pl->pcie_gen;
4959 if (rps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV) {
4960 pi->ulv.supported = true;
4962 pi->ulv.cg_ulv_parameter = CISLANDS_CGULVPARAMETER_DFLT;
4965 /* patch up boot state */
4966 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) {
4967 pl->mclk = pi->vbios_boot_state.mclk_bootup_value;
4968 pl->sclk = pi->vbios_boot_state.sclk_bootup_value;
4969 pl->pcie_gen = pi->vbios_boot_state.pcie_gen_bootup_value;
4970 pl->pcie_lane = pi->vbios_boot_state.pcie_lane_bootup_value;
4973 switch (rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) {
4974 case ATOM_PPLIB_CLASSIFICATION_UI_BATTERY:
4975 pi->use_pcie_powersaving_levels = true;
4976 if (pi->pcie_gen_powersaving.max < pl->pcie_gen)
4977 pi->pcie_gen_powersaving.max = pl->pcie_gen;
4978 if (pi->pcie_gen_powersaving.min > pl->pcie_gen)
4979 pi->pcie_gen_powersaving.min = pl->pcie_gen;
4980 if (pi->pcie_lane_powersaving.max < pl->pcie_lane)
4981 pi->pcie_lane_powersaving.max = pl->pcie_lane;
4982 if (pi->pcie_lane_powersaving.min > pl->pcie_lane)
4983 pi->pcie_lane_powersaving.min = pl->pcie_lane;
4985 case ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE:
4986 pi->use_pcie_performance_levels = true;
4987 if (pi->pcie_gen_performance.max < pl->pcie_gen)
4988 pi->pcie_gen_performance.max = pl->pcie_gen;
4989 if (pi->pcie_gen_performance.min > pl->pcie_gen)
4990 pi->pcie_gen_performance.min = pl->pcie_gen;
4991 if (pi->pcie_lane_performance.max < pl->pcie_lane)
4992 pi->pcie_lane_performance.max = pl->pcie_lane;
4993 if (pi->pcie_lane_performance.min > pl->pcie_lane)
4994 pi->pcie_lane_performance.min = pl->pcie_lane;
5001 static int ci_parse_power_table(struct radeon_device *rdev)
5003 struct radeon_mode_info *mode_info = &rdev->mode_info;
5004 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
5005 union pplib_power_state *power_state;
5006 int i, j, k, non_clock_array_index, clock_array_index;
5007 union pplib_clock_info *clock_info;
5008 struct _StateArray *state_array;
5009 struct _ClockInfoArray *clock_info_array;
5010 struct _NonClockInfoArray *non_clock_info_array;
5011 union power_info *power_info;
5012 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
5015 u8 *power_state_offset;
5018 if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
5019 &frev, &crev, &data_offset))
5021 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
5023 state_array = (struct _StateArray *)
5024 (mode_info->atom_context->bios + data_offset +
5025 le16_to_cpu(power_info->pplib.usStateArrayOffset));
5026 clock_info_array = (struct _ClockInfoArray *)
5027 (mode_info->atom_context->bios + data_offset +
5028 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset));
5029 non_clock_info_array = (struct _NonClockInfoArray *)
5030 (mode_info->atom_context->bios + data_offset +
5031 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset));
5033 rdev->pm.dpm.ps = kzalloc(sizeof(struct radeon_ps) *
5034 state_array->ucNumEntries, GFP_KERNEL);
5035 if (!rdev->pm.dpm.ps)
5037 power_state_offset = (u8 *)state_array->states;
5038 for (i = 0; i < state_array->ucNumEntries; i++) {
5040 power_state = (union pplib_power_state *)power_state_offset;
5041 non_clock_array_index = power_state->v2.nonClockInfoIndex;
5042 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
5043 &non_clock_info_array->nonClockInfo[non_clock_array_index];
5044 if (!rdev->pm.power_state[i].clock_info)
5046 ps = kzalloc(sizeof(struct ci_ps), GFP_KERNEL);
5048 kfree(rdev->pm.dpm.ps);
5051 rdev->pm.dpm.ps[i].ps_priv = ps;
5052 ci_parse_pplib_non_clock_info(rdev, &rdev->pm.dpm.ps[i],
5054 non_clock_info_array->ucEntrySize);
5056 idx = (u8 *)&power_state->v2.clockInfoIndex[0];
5057 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) {
5058 clock_array_index = idx[j];
5059 if (clock_array_index >= clock_info_array->ucNumEntries)
5061 if (k >= CISLANDS_MAX_HARDWARE_POWERLEVELS)
5063 clock_info = (union pplib_clock_info *)
5064 ((u8 *)&clock_info_array->clockInfo[0] +
5065 (clock_array_index * clock_info_array->ucEntrySize));
5066 ci_parse_pplib_clock_info(rdev,
5067 &rdev->pm.dpm.ps[i], k,
5071 power_state_offset += 2 + power_state->v2.ucNumDPMLevels;
5073 rdev->pm.dpm.num_ps = state_array->ucNumEntries;
5075 /* fill in the vce power states */
5076 for (i = 0; i < RADEON_MAX_VCE_LEVELS; i++) {
5078 clock_array_index = rdev->pm.dpm.vce_states[i].clk_idx;
5079 clock_info = (union pplib_clock_info *)
5080 &clock_info_array->clockInfo[clock_array_index * clock_info_array->ucEntrySize];
5081 sclk = le16_to_cpu(clock_info->ci.usEngineClockLow);
5082 sclk |= clock_info->ci.ucEngineClockHigh << 16;
5083 mclk = le16_to_cpu(clock_info->ci.usMemoryClockLow);
5084 mclk |= clock_info->ci.ucMemoryClockHigh << 16;
5085 rdev->pm.dpm.vce_states[i].sclk = sclk;
5086 rdev->pm.dpm.vce_states[i].mclk = mclk;
5092 static int ci_get_vbios_boot_values(struct radeon_device *rdev,
5093 struct ci_vbios_boot_state *boot_state)
5095 struct radeon_mode_info *mode_info = &rdev->mode_info;
5096 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
5097 ATOM_FIRMWARE_INFO_V2_2 *firmware_info;
5101 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
5102 &frev, &crev, &data_offset)) {
5104 (ATOM_FIRMWARE_INFO_V2_2 *)(mode_info->atom_context->bios +
5106 boot_state->mvdd_bootup_value = le16_to_cpu(firmware_info->usBootUpMVDDCVoltage);
5107 boot_state->vddc_bootup_value = le16_to_cpu(firmware_info->usBootUpVDDCVoltage);
5108 boot_state->vddci_bootup_value = le16_to_cpu(firmware_info->usBootUpVDDCIVoltage);
5109 boot_state->pcie_gen_bootup_value = ci_get_current_pcie_speed(rdev);
5110 boot_state->pcie_lane_bootup_value = ci_get_current_pcie_lane_number(rdev);
5111 boot_state->sclk_bootup_value = le32_to_cpu(firmware_info->ulDefaultEngineClock);
5112 boot_state->mclk_bootup_value = le32_to_cpu(firmware_info->ulDefaultMemoryClock);
5119 void ci_dpm_fini(struct radeon_device *rdev)
5123 for (i = 0; i < rdev->pm.dpm.num_ps; i++) {
5124 kfree(rdev->pm.dpm.ps[i].ps_priv);
5126 kfree(rdev->pm.dpm.ps);
5127 kfree(rdev->pm.dpm.priv);
5128 kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries);
5129 r600_free_extended_power_table(rdev);
5132 int ci_dpm_init(struct radeon_device *rdev)
5134 int index = GetIndexIntoMasterTable(DATA, ASIC_InternalSS_Info);
5135 SMU7_Discrete_DpmTable *dpm_table;
5136 struct radeon_gpio_rec gpio;
5137 u16 data_offset, size;
5139 struct ci_power_info *pi;
5143 pi = kzalloc(sizeof(struct ci_power_info), GFP_KERNEL);
5146 rdev->pm.dpm.priv = pi;
5148 ret = drm_pcie_get_speed_cap_mask(rdev->ddev, &mask);
5150 pi->sys_pcie_mask = 0;
5152 pi->sys_pcie_mask = mask;
5153 pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID;
5155 pi->pcie_gen_performance.max = RADEON_PCIE_GEN1;
5156 pi->pcie_gen_performance.min = RADEON_PCIE_GEN3;
5157 pi->pcie_gen_powersaving.max = RADEON_PCIE_GEN1;
5158 pi->pcie_gen_powersaving.min = RADEON_PCIE_GEN3;
5160 pi->pcie_lane_performance.max = 0;
5161 pi->pcie_lane_performance.min = 16;
5162 pi->pcie_lane_powersaving.max = 0;
5163 pi->pcie_lane_powersaving.min = 16;
5165 ret = ci_get_vbios_boot_values(rdev, &pi->vbios_boot_state);
5171 ret = r600_get_platform_caps(rdev);
5177 ret = r600_parse_extended_power_table(rdev);
5183 ret = ci_parse_power_table(rdev);
5189 pi->dll_default_on = false;
5190 pi->sram_end = SMC_RAM_END;
5192 pi->activity_target[0] = CISLAND_TARGETACTIVITY_DFLT;
5193 pi->activity_target[1] = CISLAND_TARGETACTIVITY_DFLT;
5194 pi->activity_target[2] = CISLAND_TARGETACTIVITY_DFLT;
5195 pi->activity_target[3] = CISLAND_TARGETACTIVITY_DFLT;
5196 pi->activity_target[4] = CISLAND_TARGETACTIVITY_DFLT;
5197 pi->activity_target[5] = CISLAND_TARGETACTIVITY_DFLT;
5198 pi->activity_target[6] = CISLAND_TARGETACTIVITY_DFLT;
5199 pi->activity_target[7] = CISLAND_TARGETACTIVITY_DFLT;
5201 pi->mclk_activity_target = CISLAND_MCLK_TARGETACTIVITY_DFLT;
5203 pi->sclk_dpm_key_disabled = 0;
5204 pi->mclk_dpm_key_disabled = 0;
5205 pi->pcie_dpm_key_disabled = 0;
5207 /* mclk dpm is unstable on some R7 260X cards with the old mc ucode */
5208 if ((rdev->pdev->device == 0x6658) &&
5209 (rdev->mc_fw->size == (BONAIRE_MC_UCODE_SIZE * 4))) {
5210 pi->mclk_dpm_key_disabled = 1;
5213 pi->caps_sclk_ds = true;
5215 pi->mclk_strobe_mode_threshold = 40000;
5216 pi->mclk_stutter_mode_threshold = 40000;
5217 pi->mclk_edc_enable_threshold = 40000;
5218 pi->mclk_edc_wr_enable_threshold = 40000;
5220 ci_initialize_powertune_defaults(rdev);
5222 pi->caps_fps = false;
5224 pi->caps_sclk_throttle_low_notification = false;
5226 pi->caps_uvd_dpm = true;
5227 pi->caps_vce_dpm = true;
5229 ci_get_leakage_voltages(rdev);
5230 ci_patch_dependency_tables_with_leakage(rdev);
5231 ci_set_private_data_variables_based_on_pptable(rdev);
5233 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries =
5234 kzalloc(4 * sizeof(struct radeon_clock_voltage_dependency_entry), GFP_KERNEL);
5235 if (!rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries) {
5239 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count = 4;
5240 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].clk = 0;
5241 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].v = 0;
5242 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].clk = 36000;
5243 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].v = 720;
5244 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].clk = 54000;
5245 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].v = 810;
5246 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].clk = 72000;
5247 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].v = 900;
5249 rdev->pm.dpm.dyn_state.mclk_sclk_ratio = 4;
5250 rdev->pm.dpm.dyn_state.sclk_mclk_delta = 15000;
5251 rdev->pm.dpm.dyn_state.vddc_vddci_delta = 200;
5253 rdev->pm.dpm.dyn_state.valid_sclk_values.count = 0;
5254 rdev->pm.dpm.dyn_state.valid_sclk_values.values = NULL;
5255 rdev->pm.dpm.dyn_state.valid_mclk_values.count = 0;
5256 rdev->pm.dpm.dyn_state.valid_mclk_values.values = NULL;
5258 if (rdev->family == CHIP_HAWAII) {
5259 pi->thermal_temp_setting.temperature_low = 94500;
5260 pi->thermal_temp_setting.temperature_high = 95000;
5261 pi->thermal_temp_setting.temperature_shutdown = 104000;
5263 pi->thermal_temp_setting.temperature_low = 99500;
5264 pi->thermal_temp_setting.temperature_high = 100000;
5265 pi->thermal_temp_setting.temperature_shutdown = 104000;
5268 pi->uvd_enabled = false;
5270 dpm_table = &pi->smc_state_table;
5272 gpio = radeon_atombios_lookup_gpio(rdev, VDDC_VRHOT_GPIO_PINID);
5274 dpm_table->VRHotGpio = gpio.shift;
5275 rdev->pm.dpm.platform_caps |= ATOM_PP_PLATFORM_CAP_REGULATOR_HOT;
5277 dpm_table->VRHotGpio = CISLANDS_UNUSED_GPIO_PIN;
5278 rdev->pm.dpm.platform_caps &= ~ATOM_PP_PLATFORM_CAP_REGULATOR_HOT;
5281 gpio = radeon_atombios_lookup_gpio(rdev, PP_AC_DC_SWITCH_GPIO_PINID);
5283 dpm_table->AcDcGpio = gpio.shift;
5284 rdev->pm.dpm.platform_caps |= ATOM_PP_PLATFORM_CAP_HARDWAREDC;
5286 dpm_table->AcDcGpio = CISLANDS_UNUSED_GPIO_PIN;
5287 rdev->pm.dpm.platform_caps &= ~ATOM_PP_PLATFORM_CAP_HARDWAREDC;
5290 gpio = radeon_atombios_lookup_gpio(rdev, VDDC_PCC_GPIO_PINID);
5292 u32 tmp = RREG32_SMC(CNB_PWRMGT_CNTL);
5294 switch (gpio.shift) {
5296 tmp &= ~GNB_SLOW_MODE_MASK;
5297 tmp |= GNB_SLOW_MODE(1);
5300 tmp &= ~GNB_SLOW_MODE_MASK;
5301 tmp |= GNB_SLOW_MODE(2);
5307 tmp |= FORCE_NB_PS1;
5313 DRM_ERROR("Invalid PCC GPIO!");
5316 WREG32_SMC(CNB_PWRMGT_CNTL, tmp);
5319 pi->voltage_control = CISLANDS_VOLTAGE_CONTROL_NONE;
5320 pi->vddci_control = CISLANDS_VOLTAGE_CONTROL_NONE;
5321 pi->mvdd_control = CISLANDS_VOLTAGE_CONTROL_NONE;
5322 if (radeon_atom_is_voltage_gpio(rdev, VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_GPIO_LUT))
5323 pi->voltage_control = CISLANDS_VOLTAGE_CONTROL_BY_GPIO;
5324 else if (radeon_atom_is_voltage_gpio(rdev, VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_SVID2))
5325 pi->voltage_control = CISLANDS_VOLTAGE_CONTROL_BY_SVID2;
5327 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_VDDCI_CONTROL) {
5328 if (radeon_atom_is_voltage_gpio(rdev, VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT))
5329 pi->vddci_control = CISLANDS_VOLTAGE_CONTROL_BY_GPIO;
5330 else if (radeon_atom_is_voltage_gpio(rdev, VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_SVID2))
5331 pi->vddci_control = CISLANDS_VOLTAGE_CONTROL_BY_SVID2;
5333 rdev->pm.dpm.platform_caps &= ~ATOM_PP_PLATFORM_CAP_VDDCI_CONTROL;
5336 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_MVDDCONTROL) {
5337 if (radeon_atom_is_voltage_gpio(rdev, VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_GPIO_LUT))
5338 pi->mvdd_control = CISLANDS_VOLTAGE_CONTROL_BY_GPIO;
5339 else if (radeon_atom_is_voltage_gpio(rdev, VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_SVID2))
5340 pi->mvdd_control = CISLANDS_VOLTAGE_CONTROL_BY_SVID2;
5342 rdev->pm.dpm.platform_caps &= ~ATOM_PP_PLATFORM_CAP_MVDDCONTROL;
5345 pi->vddc_phase_shed_control = true;
5347 #if defined(CONFIG_ACPI)
5348 pi->pcie_performance_request =
5349 radeon_acpi_is_pcie_performance_request_supported(rdev);
5351 pi->pcie_performance_request = false;
5354 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
5355 &frev, &crev, &data_offset)) {
5356 pi->caps_sclk_ss_support = true;
5357 pi->caps_mclk_ss_support = true;
5358 pi->dynamic_ss = true;
5360 pi->caps_sclk_ss_support = false;
5361 pi->caps_mclk_ss_support = false;
5362 pi->dynamic_ss = true;
5365 if (rdev->pm.int_thermal_type != THERMAL_TYPE_NONE)
5366 pi->thermal_protection = true;
5368 pi->thermal_protection = false;
5370 pi->caps_dynamic_ac_timing = true;
5372 pi->uvd_power_gated = false;
5374 /* make sure dc limits are valid */
5375 if ((rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk == 0) ||
5376 (rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk == 0))
5377 rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc =
5378 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
5383 void ci_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
5386 struct ci_power_info *pi = ci_get_pi(rdev);
5387 struct radeon_ps *rps = &pi->current_rps;
5388 u32 sclk = ci_get_average_sclk_freq(rdev);
5389 u32 mclk = ci_get_average_mclk_freq(rdev);
5391 seq_printf(m, "uvd %sabled\n", pi->uvd_enabled ? "en" : "dis");
5392 seq_printf(m, "vce %sabled\n", rps->vce_active ? "en" : "dis");
5393 seq_printf(m, "power level avg sclk: %u mclk: %u\n",
5397 void ci_dpm_print_power_state(struct radeon_device *rdev,
5398 struct radeon_ps *rps)
5400 struct ci_ps *ps = ci_get_ps(rps);
5404 r600_dpm_print_class_info(rps->class, rps->class2);
5405 r600_dpm_print_cap_info(rps->caps);
5406 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
5407 for (i = 0; i < ps->performance_level_count; i++) {
5408 pl = &ps->performance_levels[i];
5409 printk("\t\tpower level %d sclk: %u mclk: %u pcie gen: %u pcie lanes: %u\n",
5410 i, pl->sclk, pl->mclk, pl->pcie_gen + 1, pl->pcie_lane);
5412 r600_dpm_print_ps_status(rdev, rps);
5415 u32 ci_dpm_get_sclk(struct radeon_device *rdev, bool low)
5417 struct ci_power_info *pi = ci_get_pi(rdev);
5418 struct ci_ps *requested_state = ci_get_ps(&pi->requested_rps);
5421 return requested_state->performance_levels[0].sclk;
5423 return requested_state->performance_levels[requested_state->performance_level_count - 1].sclk;
5426 u32 ci_dpm_get_mclk(struct radeon_device *rdev, bool low)
5428 struct ci_power_info *pi = ci_get_pi(rdev);
5429 struct ci_ps *requested_state = ci_get_ps(&pi->requested_rps);
5432 return requested_state->performance_levels[0].mclk;
5434 return requested_state->performance_levels[requested_state->performance_level_count - 1].mclk;