drivers/gpu/drm/radeon/ci_dpm.c

   1 /*
   2  * Copyright 2013 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/firmware.h>
  25 #include "drmP.h"
  26 #include "radeon.h"
  27 #include "radeon_asic.h"
  28 #include "radeon_ucode.h"
  29 #include "cikd.h"
  30 #include "r600_dpm.h"
  31 #include "ci_dpm.h"
  32 #include "atom.h"
  33 #include <linux/seq_file.h>
  34
  35 #define MC_CG_ARB_FREQ_F0           0x0a
  36 #define MC_CG_ARB_FREQ_F1           0x0b
  37 #define MC_CG_ARB_FREQ_F2           0x0c
  38 #define MC_CG_ARB_FREQ_F3           0x0d
  39
  40 #define SMC_RAM_END 0x40000
  41
  42 #define VOLTAGE_SCALE               4
  43 #define VOLTAGE_VID_OFFSET_SCALE1    625
  44 #define VOLTAGE_VID_OFFSET_SCALE2    100
  45
  46 static const struct ci_pt_defaults defaults_hawaii_xt =
  47 {
  48         1, 0xF, 0xFD, 0x19, 5, 0x14, 0, 0xB0000,
  49         { 0x84,  0x0,   0x0,   0x7F,  0x0,   0x0,   0x5A,  0x60,  0x51,  0x8E,  0x79,  0x6B,  0x5F,  0x90,  0x79  },
  50         { 0x1EA, 0x1EA, 0x1EA, 0x224, 0x224, 0x224, 0x24F, 0x24F, 0x24F, 0x28E, 0x28E, 0x28E, 0x2BC, 0x2BC, 0x2BC }
  51 };
  52
  53 static const struct ci_pt_defaults defaults_hawaii_pro =
  54 {
  55         1, 0xF, 0xFD, 0x19, 5, 0x14, 0, 0x65062,
  56         { 0x93,  0x0,   0x0,   0x97,  0x0,   0x0,   0x6B,  0x60,  0x51,  0x95,  0x79,  0x6B,  0x5F,  0x90,  0x79  },
  57         { 0x1EA, 0x1EA, 0x1EA, 0x224, 0x224, 0x224, 0x24F, 0x24F, 0x24F, 0x28E, 0x28E, 0x28E, 0x2BC, 0x2BC, 0x2BC }
  58 };
  59
  60 static const struct ci_pt_defaults defaults_bonaire_xt =
  61 {
  62         1, 0xF, 0xFD, 0x19, 5, 45, 0, 0xB0000,
  63         { 0x79,  0x253, 0x25D, 0xAE,  0x72,  0x80,  0x83,  0x86,  0x6F,  0xC8,  0xC9,  0xC9,  0x2F,  0x4D,  0x61  },
  64         { 0x17C, 0x172, 0x180, 0x1BC, 0x1B3, 0x1BD, 0x206, 0x200, 0x203, 0x25D, 0x25A, 0x255, 0x2C3, 0x2C5, 0x2B4 }
  65 };
  66
  67 static const struct ci_pt_defaults defaults_bonaire_pro =
  68 {
  69         1, 0xF, 0xFD, 0x19, 5, 45, 0, 0x65062,
  70         { 0x8C,  0x23F, 0x244, 0xA6,  0x83,  0x85,  0x86,  0x86,  0x83,  0xDB,  0xDB,  0xDA,  0x67,  0x60,  0x5F  },
  71         { 0x187, 0x193, 0x193, 0x1C7, 0x1D1, 0x1D1, 0x210, 0x219, 0x219, 0x266, 0x26C, 0x26C, 0x2C9, 0x2CB, 0x2CB }
  72 };
  73
  74 static const struct ci_pt_defaults defaults_saturn_xt =
  75 {
  76         1, 0xF, 0xFD, 0x19, 5, 55, 0, 0x70000,
  77         { 0x8C,  0x247, 0x249, 0xA6,  0x80,  0x81,  0x8B,  0x89,  0x86,  0xC9,  0xCA,  0xC9,  0x4D,  0x4D,  0x4D  },
  78         { 0x187, 0x187, 0x187, 0x1C7, 0x1C7, 0x1C7, 0x210, 0x210, 0x210, 0x266, 0x266, 0x266, 0x2C9, 0x2C9, 0x2C9 }
  79 };
  80
  81 static const struct ci_pt_defaults defaults_saturn_pro =
  82 {
  83         1, 0xF, 0xFD, 0x19, 5, 55, 0, 0x30000,
  84         { 0x96,  0x21D, 0x23B, 0xA1,  0x85,  0x87,  0x83,  0x84,  0x81,  0xE6,  0xE6,  0xE6,  0x71,  0x6A,  0x6A  },
  85         { 0x193, 0x19E, 0x19E, 0x1D2, 0x1DC, 0x1DC, 0x21A, 0x223, 0x223, 0x26E, 0x27E, 0x274, 0x2CF, 0x2D2, 0x2D2 }
  86 };
  87
  88 static const struct ci_pt_config_reg didt_config_ci[] =
  89 {
  90         { 0x10, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
  91         { 0x10, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
  92         { 0x10, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
  93         { 0x10, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
  94         { 0x11, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
  95         { 0x11, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
  96         { 0x11, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
  97         { 0x11, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
  98         { 0x12, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
  99         { 0x12, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 100         { 0x12, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 101         { 0x12, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 102         { 0x2, 0x00003fff, 0, 0x4, CISLANDS_CONFIGREG_DIDT_IND },
 103         { 0x2, 0x03ff0000, 16, 0x80, CISLANDS_CONFIGREG_DIDT_IND },
 104         { 0x2, 0x78000000, 27, 0x3, CISLANDS_CONFIGREG_DIDT_IND },
 105         { 0x1, 0x0000ffff, 0, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
 106         { 0x1, 0xffff0000, 16, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
 107         { 0x0, 0x00000001, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 108         { 0x30, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 109         { 0x30, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 110         { 0x30, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 111         { 0x30, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 112         { 0x31, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 113         { 0x31, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 114         { 0x31, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 115         { 0x31, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 116         { 0x32, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 117         { 0x32, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 118         { 0x32, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 119         { 0x32, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 120         { 0x22, 0x00003fff, 0, 0x4, CISLANDS_CONFIGREG_DIDT_IND },
 121         { 0x22, 0x03ff0000, 16, 0x80, CISLANDS_CONFIGREG_DIDT_IND },
 122         { 0x22, 0x78000000, 27, 0x3, CISLANDS_CONFIGREG_DIDT_IND },
 123         { 0x21, 0x0000ffff, 0, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
 124         { 0x21, 0xffff0000, 16, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
 125         { 0x20, 0x00000001, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 126         { 0x50, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 127         { 0x50, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 128         { 0x50, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 129         { 0x50, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 130         { 0x51, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 131         { 0x51, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 132         { 0x51, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 133         { 0x51, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 134         { 0x52, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 135         { 0x52, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 136         { 0x52, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 137         { 0x52, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 138         { 0x42, 0x00003fff, 0, 0x4, CISLANDS_CONFIGREG_DIDT_IND },
 139         { 0x42, 0x03ff0000, 16, 0x80, CISLANDS_CONFIGREG_DIDT_IND },
 140         { 0x42, 0x78000000, 27, 0x3, CISLANDS_CONFIGREG_DIDT_IND },
 141         { 0x41, 0x0000ffff, 0, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
 142         { 0x41, 0xffff0000, 16, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
 143         { 0x40, 0x00000001, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 144         { 0x70, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 145         { 0x70, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 146         { 0x70, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 147         { 0x70, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 148         { 0x71, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 149         { 0x71, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 150         { 0x71, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 151         { 0x71, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 152         { 0x72, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 153         { 0x72, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 154         { 0x72, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 155         { 0x72, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 156         { 0x62, 0x00003fff, 0, 0x4, CISLANDS_CONFIGREG_DIDT_IND },
 157         { 0x62, 0x03ff0000, 16, 0x80, CISLANDS_CONFIGREG_DIDT_IND },
 158         { 0x62, 0x78000000, 27, 0x3, CISLANDS_CONFIGREG_DIDT_IND },
 159         { 0x61, 0x0000ffff, 0, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
 160         { 0x61, 0xffff0000, 16, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
 161         { 0x60, 0x00000001, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 162         { 0xFFFFFFFF }
 163 };
 164
 165 extern u8 rv770_get_memory_module_index(struct radeon_device *rdev);
 166 extern int ni_copy_and_switch_arb_sets(struct radeon_device *rdev,
 167                                        u32 arb_freq_src, u32 arb_freq_dest);
 168 extern u8 si_get_ddr3_mclk_frequency_ratio(u32 memory_clock);
 169 extern u8 si_get_mclk_frequency_ratio(u32 memory_clock, bool strobe_mode);
 170 extern void si_trim_voltage_table_to_fit_state_table(struct radeon_device *rdev,
 171                                                      u32 max_voltage_steps,
 172                                                      struct atom_voltage_table *voltage_table);
 173 extern void cik_enter_rlc_safe_mode(struct radeon_device *rdev);
 174 extern void cik_exit_rlc_safe_mode(struct radeon_device *rdev);
 175 extern int ci_mc_load_microcode(struct radeon_device *rdev);
 176 extern void cik_update_cg(struct radeon_device *rdev,
 177                           u32 block, bool enable);
 178
 179 static int ci_get_std_voltage_value_sidd(struct radeon_device *rdev,
 180                                          struct atom_voltage_table_entry *voltage_table,
 181                                          u16 *std_voltage_hi_sidd, u16 *std_voltage_lo_sidd);
 182 static int ci_set_power_limit(struct radeon_device *rdev, u32 n);
 183 static int ci_set_overdrive_target_tdp(struct radeon_device *rdev,
 184                                        u32 target_tdp);
 185 static int ci_update_uvd_dpm(struct radeon_device *rdev, bool gate);
 186
 187 static struct ci_power_info *ci_get_pi(struct radeon_device *rdev)
 188 {
 189         struct ci_power_info *pi = rdev->pm.dpm.priv;
 190
 191         return pi;
 192 }
 193
 194 static struct ci_ps *ci_get_ps(struct radeon_ps *rps)
 195 {
 196         struct ci_ps *ps = rps->ps_priv;
 197
 198         return ps;
 199 }
 200
 201 static void ci_initialize_powertune_defaults(struct radeon_device *rdev)
 202 {
 203         struct ci_power_info *pi = ci_get_pi(rdev);
 204
 205         switch (rdev->pdev->device) {
 206         case 0x6649:
 207         case 0x6650:
 208         case 0x6651:
 209         case 0x6658:
 210         case 0x665C:
 211         case 0x665D:
 212         default:
 213                 pi->powertune_defaults = &defaults_bonaire_xt;
 214                 break;
 215         case 0x6640:
 216         case 0x6641:
 217         case 0x6646:
 218         case 0x6647:
 219                 pi->powertune_defaults = &defaults_saturn_xt;
 220                 break;
 221         case 0x67B8:
 222         case 0x67B0:
 223                 pi->powertune_defaults = &defaults_hawaii_xt;
 224                 break;
 225         case 0x67BA:
 226         case 0x67B1:
 227                 pi->powertune_defaults = &defaults_hawaii_pro;
 228                 break;
 229         case 0x67A0:
 230         case 0x67A1:
 231         case 0x67A2:
 232         case 0x67A8:
 233         case 0x67A9:
 234         case 0x67AA:
 235         case 0x67B9:
 236         case 0x67BE:
 237                 pi->powertune_defaults = &defaults_bonaire_xt;
 238                 break;
 239         }
 240
 241         pi->dte_tj_offset = 0;
 242
 243         pi->caps_power_containment = true;
 244         pi->caps_cac = false;
 245         pi->caps_sq_ramping = false;
 246         pi->caps_db_ramping = false;
 247         pi->caps_td_ramping = false;
 248         pi->caps_tcp_ramping = false;
 249
 250         if (pi->caps_power_containment) {
 251                 pi->caps_cac = true;
 252                 pi->enable_bapm_feature = true;
 253                 pi->enable_tdc_limit_feature = true;
 254                 pi->enable_pkg_pwr_tracking_feature = true;
 255         }
 256 }
 257
 258 static u8 ci_convert_to_vid(u16 vddc)
 259 {
 260         return (6200 - (vddc * VOLTAGE_SCALE)) / 25;
 261 }
 262
 263 static int ci_populate_bapm_vddc_vid_sidd(struct radeon_device *rdev)
 264 {
 265         struct ci_power_info *pi = ci_get_pi(rdev);
 266         u8 *hi_vid = pi->smc_powertune_table.BapmVddCVidHiSidd;
 267         u8 *lo_vid = pi->smc_powertune_table.BapmVddCVidLoSidd;
 268         u8 *hi2_vid = pi->smc_powertune_table.BapmVddCVidHiSidd2;
 269         u32 i;
 270
 271         if (rdev->pm.dpm.dyn_state.cac_leakage_table.entries == NULL)
 272                 return -EINVAL;
 273         if (rdev->pm.dpm.dyn_state.cac_leakage_table.count > 8)
 274                 return -EINVAL;
 275         if (rdev->pm.dpm.dyn_state.cac_leakage_table.count !=
 276             rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count)
 277                 return -EINVAL;
 278
 279         for (i = 0; i < rdev->pm.dpm.dyn_state.cac_leakage_table.count; i++) {
 280                 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_EVV) {
 281                         lo_vid[i] = ci_convert_to_vid(rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc1);
 282                         hi_vid[i] = ci_convert_to_vid(rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc2);
 283                         hi2_vid[i] = ci_convert_to_vid(rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc3);
 284                 } else {
 285                         lo_vid[i] = ci_convert_to_vid(rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc);
 286                         hi_vid[i] = ci_convert_to_vid((u16)rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].leakage);
 287                 }
 288         }
 289         return 0;
 290 }
 291
 292 static int ci_populate_vddc_vid(struct radeon_device *rdev)
 293 {
 294         struct ci_power_info *pi = ci_get_pi(rdev);
 295         u8 *vid = pi->smc_powertune_table.VddCVid;
 296         u32 i;
 297
 298         if (pi->vddc_voltage_table.count > 8)
 299                 return -EINVAL;
 300
 301         for (i = 0; i < pi->vddc_voltage_table.count; i++)
 302                 vid[i] = ci_convert_to_vid(pi->vddc_voltage_table.entries[i].value);
 303
 304         return 0;
 305 }
 306
 307 static int ci_populate_svi_load_line(struct radeon_device *rdev)
 308 {
 309         struct ci_power_info *pi = ci_get_pi(rdev);
 310         const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults;
 311
 312         pi->smc_powertune_table.SviLoadLineEn = pt_defaults->svi_load_line_en;
 313         pi->smc_powertune_table.SviLoadLineVddC = pt_defaults->svi_load_line_vddc;
 314         pi->smc_powertune_table.SviLoadLineTrimVddC = 3;
 315         pi->smc_powertune_table.SviLoadLineOffsetVddC = 0;
 316
 317         return 0;
 318 }
 319
 320 static int ci_populate_tdc_limit(struct radeon_device *rdev)
 321 {
 322         struct ci_power_info *pi = ci_get_pi(rdev);
 323         const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults;
 324         u16 tdc_limit;
 325
 326         tdc_limit = rdev->pm.dpm.dyn_state.cac_tdp_table->tdc * 256;
 327         pi->smc_powertune_table.TDC_VDDC_PkgLimit = cpu_to_be16(tdc_limit);
 328         pi->smc_powertune_table.TDC_VDDC_ThrottleReleaseLimitPerc =
 329                 pt_defaults->tdc_vddc_throttle_release_limit_perc;
 330         pi->smc_powertune_table.TDC_MAWt = pt_defaults->tdc_mawt;
 331
 332         return 0;
 333 }
 334
 335 static int ci_populate_dw8(struct radeon_device *rdev)
 336 {
 337         struct ci_power_info *pi = ci_get_pi(rdev);
 338         const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults;
 339         int ret;
 340
 341         ret = ci_read_smc_sram_dword(rdev,
 342                                      SMU7_FIRMWARE_HEADER_LOCATION +
 343                                      offsetof(SMU7_Firmware_Header, PmFuseTable) +
 344                                      offsetof(SMU7_Discrete_PmFuses, TdcWaterfallCtl),
 345                                      (u32 *)&pi->smc_powertune_table.TdcWaterfallCtl,
 346                                      pi->sram_end);
 347         if (ret)
 348                 return -EINVAL;
 349         else
 350                 pi->smc_powertune_table.TdcWaterfallCtl = pt_defaults->tdc_waterfall_ctl;
 351
 352         return 0;
 353 }
 354
 355 static int ci_min_max_v_gnbl_pm_lid_from_bapm_vddc(struct radeon_device *rdev)
 356 {
 357         struct ci_power_info *pi = ci_get_pi(rdev);
 358         u8 *hi_vid = pi->smc_powertune_table.BapmVddCVidHiSidd;
 359         u8 *lo_vid = pi->smc_powertune_table.BapmVddCVidLoSidd;
 360         int i, min, max;
 361
 362         min = max = hi_vid[0];
 363         for (i = 0; i < 8; i++) {
 364                 if (0 != hi_vid[i]) {
 365                         if (min > hi_vid[i])
 366                                 min = hi_vid[i];
 367                         if (max < hi_vid[i])
 368                                 max = hi_vid[i];
 369                 }
 370
 371                 if (0 != lo_vid[i]) {
 372                         if (min > lo_vid[i])
 373                                 min = lo_vid[i];
 374                         if (max < lo_vid[i])
 375                                 max = lo_vid[i];
 376                 }
 377         }
 378
 379         if ((min == 0) || (max == 0))
 380                 return -EINVAL;
 381         pi->smc_powertune_table.GnbLPMLMaxVid = (u8)max;
 382         pi->smc_powertune_table.GnbLPMLMinVid = (u8)min;
 383
 384         return 0;
 385 }
 386
 387 static int ci_populate_bapm_vddc_base_leakage_sidd(struct radeon_device *rdev)
 388 {
 389         struct ci_power_info *pi = ci_get_pi(rdev);
 390         u16 hi_sidd = pi->smc_powertune_table.BapmVddCBaseLeakageHiSidd;
 391         u16 lo_sidd = pi->smc_powertune_table.BapmVddCBaseLeakageLoSidd;
 392         struct radeon_cac_tdp_table *cac_tdp_table =
 393                 rdev->pm.dpm.dyn_state.cac_tdp_table;
 394
 395         hi_sidd = cac_tdp_table->high_cac_leakage / 100 * 256;
 396         lo_sidd = cac_tdp_table->low_cac_leakage / 100 * 256;
 397
 398         pi->smc_powertune_table.BapmVddCBaseLeakageHiSidd = cpu_to_be16(hi_sidd);
 399         pi->smc_powertune_table.BapmVddCBaseLeakageLoSidd = cpu_to_be16(lo_sidd);
 400
 401         return 0;
 402 }
 403
 404 static int ci_populate_bapm_parameters_in_dpm_table(struct radeon_device *rdev)
 405 {
 406         struct ci_power_info *pi = ci_get_pi(rdev);
 407         const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults;
 408         SMU7_Discrete_DpmTable  *dpm_table = &pi->smc_state_table;
 409         struct radeon_cac_tdp_table *cac_tdp_table =
 410                 rdev->pm.dpm.dyn_state.cac_tdp_table;
 411         struct radeon_ppm_table *ppm = rdev->pm.dpm.dyn_state.ppm_table;
 412         int i, j, k;
 413         const u16 *def1;
 414         const u16 *def2;
 415
 416         dpm_table->DefaultTdp = cac_tdp_table->tdp * 256;
 417         dpm_table->TargetTdp = cac_tdp_table->configurable_tdp * 256;
 418
 419         dpm_table->DTETjOffset = (u8)pi->dte_tj_offset;
 420         dpm_table->GpuTjMax =
 421                 (u8)(pi->thermal_temp_setting.temperature_high / 1000);
 422         dpm_table->GpuTjHyst = 8;
 423
 424         dpm_table->DTEAmbientTempBase = pt_defaults->dte_ambient_temp_base;
 425
 426         if (ppm) {
 427                 dpm_table->PPM_PkgPwrLimit = cpu_to_be16((u16)ppm->dgpu_tdp * 256 / 1000);
 428                 dpm_table->PPM_TemperatureLimit = cpu_to_be16((u16)ppm->tj_max * 256);
 429         } else {
 430                 dpm_table->PPM_PkgPwrLimit = cpu_to_be16(0);
 431                 dpm_table->PPM_TemperatureLimit = cpu_to_be16(0);
 432         }
 433
 434         dpm_table->BAPM_TEMP_GRADIENT = cpu_to_be32(pt_defaults->bapm_temp_gradient);
 435         def1 = pt_defaults->bapmti_r;
 436         def2 = pt_defaults->bapmti_rc;
 437
 438         for (i = 0; i < SMU7_DTE_ITERATIONS; i++) {
 439                 for (j = 0; j < SMU7_DTE_SOURCES; j++) {
 440                         for (k = 0; k < SMU7_DTE_SINKS; k++) {
 441                                 dpm_table->BAPMTI_R[i][j][k] = cpu_to_be16(*def1);
 442                                 dpm_table->BAPMTI_RC[i][j][k] = cpu_to_be16(*def2);
 443                                 def1++;
 444                                 def2++;
 445                         }
 446                 }
 447         }
 448
 449         return 0;
 450 }
 451
 452 static int ci_populate_pm_base(struct radeon_device *rdev)
 453 {
 454         struct ci_power_info *pi = ci_get_pi(rdev);
 455         u32 pm_fuse_table_offset;
 456         int ret;
 457
 458         if (pi->caps_power_containment) {
 459                 ret = ci_read_smc_sram_dword(rdev,
 460                                              SMU7_FIRMWARE_HEADER_LOCATION +
 461                                              offsetof(SMU7_Firmware_Header, PmFuseTable),
 462                                              &pm_fuse_table_offset, pi->sram_end);
 463                 if (ret)
 464                         return ret;
 465                 ret = ci_populate_bapm_vddc_vid_sidd(rdev);
 466                 if (ret)
 467                         return ret;
 468                 ret = ci_populate_vddc_vid(rdev);
 469                 if (ret)
 470                         return ret;
 471                 ret = ci_populate_svi_load_line(rdev);
 472                 if (ret)
 473                         return ret;
 474                 ret = ci_populate_tdc_limit(rdev);
 475                 if (ret)
 476                         return ret;
 477                 ret = ci_populate_dw8(rdev);
 478                 if (ret)
 479                         return ret;
 480                 ret = ci_min_max_v_gnbl_pm_lid_from_bapm_vddc(rdev);
 481                 if (ret)
 482                         return ret;
 483                 ret = ci_populate_bapm_vddc_base_leakage_sidd(rdev);
 484                 if (ret)
 485                         return ret;
 486                 ret = ci_copy_bytes_to_smc(rdev, pm_fuse_table_offset,
 487                                            (u8 *)&pi->smc_powertune_table,
 488                                            sizeof(SMU7_Discrete_PmFuses), pi->sram_end);
 489                 if (ret)
 490                         return ret;
 491         }
 492
 493         return 0;
 494 }
 495
 496 static void ci_do_enable_didt(struct radeon_device *rdev, const bool enable)
 497 {
 498         struct ci_power_info *pi = ci_get_pi(rdev);
 499         u32 data;
 500
 501         if (pi->caps_sq_ramping) {
 502                 data = RREG32_DIDT(DIDT_SQ_CTRL0);
 503                 if (enable)
 504                         data |= DIDT_CTRL_EN;
 505                 else
 506                         data &= ~DIDT_CTRL_EN;
 507                 WREG32_DIDT(DIDT_SQ_CTRL0, data);
 508         }
 509
 510         if (pi->caps_db_ramping) {
 511                 data = RREG32_DIDT(DIDT_DB_CTRL0);
 512                 if (enable)
 513                         data |= DIDT_CTRL_EN;
 514                 else
 515                         data &= ~DIDT_CTRL_EN;
 516                 WREG32_DIDT(DIDT_DB_CTRL0, data);
 517         }
 518
 519         if (pi->caps_td_ramping) {
 520                 data = RREG32_DIDT(DIDT_TD_CTRL0);
 521                 if (enable)
 522                         data |= DIDT_CTRL_EN;
 523                 else
 524                         data &= ~DIDT_CTRL_EN;
 525                 WREG32_DIDT(DIDT_TD_CTRL0, data);
 526         }
 527
 528         if (pi->caps_tcp_ramping) {
 529                 data = RREG32_DIDT(DIDT_TCP_CTRL0);
 530                 if (enable)
 531                         data |= DIDT_CTRL_EN;
 532                 else
 533                         data &= ~DIDT_CTRL_EN;
 534                 WREG32_DIDT(DIDT_TCP_CTRL0, data);
 535         }
 536 }
 537
 538 static int ci_program_pt_config_registers(struct radeon_device *rdev,
 539                                           const struct ci_pt_config_reg *cac_config_regs)
 540 {
 541         const struct ci_pt_config_reg *config_regs = cac_config_regs;
 542         u32 data;
 543         u32 cache = 0;
 544
 545         if (config_regs == NULL)
 546                 return -EINVAL;
 547
 548         while (config_regs->offset != 0xFFFFFFFF) {
 549                 if (config_regs->type == CISLANDS_CONFIGREG_CACHE) {
 550                         cache |= ((config_regs->value << config_regs->shift) & config_regs->mask);
 551                 } else {
 552                         switch (config_regs->type) {
 553                         case CISLANDS_CONFIGREG_SMC_IND:
 554                                 data = RREG32_SMC(config_regs->offset);
 555                                 break;
 556                         case CISLANDS_CONFIGREG_DIDT_IND:
 557                                 data = RREG32_DIDT(config_regs->offset);
 558                                 break;
 559                         default:
 560                                 data = RREG32(config_regs->offset << 2);
 561                                 break;
 562                         }
 563
 564                         data &= ~config_regs->mask;
 565                         data |= ((config_regs->value << config_regs->shift) & config_regs->mask);
 566                         data |= cache;
 567
 568                         switch (config_regs->type) {
 569                         case CISLANDS_CONFIGREG_SMC_IND:
 570                                 WREG32_SMC(config_regs->offset, data);
 571                                 break;
 572                         case CISLANDS_CONFIGREG_DIDT_IND:
 573                                 WREG32_DIDT(config_regs->offset, data);
 574                                 break;
 575                         default:
 576                                 WREG32(config_regs->offset << 2, data);
 577                                 break;
 578                         }
 579                         cache = 0;
 580                 }
 581                 config_regs++;
 582         }
 583         return 0;
 584 }
 585
 586 static int ci_enable_didt(struct radeon_device *rdev, bool enable)
 587 {
 588         struct ci_power_info *pi = ci_get_pi(rdev);
 589         int ret;
 590
 591         if (pi->caps_sq_ramping || pi->caps_db_ramping ||
 592             pi->caps_td_ramping || pi->caps_tcp_ramping) {
 593                 cik_enter_rlc_safe_mode(rdev);
 594
 595                 if (enable) {
 596                         ret = ci_program_pt_config_registers(rdev, didt_config_ci);
 597                         if (ret) {
 598                                 cik_exit_rlc_safe_mode(rdev);
 599                                 return ret;
 600                         }
 601                 }
 602
 603                 ci_do_enable_didt(rdev, enable);
 604
 605                 cik_exit_rlc_safe_mode(rdev);
 606         }
 607
 608         return 0;
 609 }
 610
 611 static int ci_enable_power_containment(struct radeon_device *rdev, bool enable)
 612 {
 613         struct ci_power_info *pi = ci_get_pi(rdev);
 614         PPSMC_Result smc_result;
 615         int ret = 0;
 616
 617         if (enable) {
 618                 pi->power_containment_features = 0;
 619                 if (pi->caps_power_containment) {
 620                         if (pi->enable_bapm_feature) {
 621                                 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_EnableDTE);
 622                                 if (smc_result != PPSMC_Result_OK)
 623                                         ret = -EINVAL;
 624                                 else
 625                                         pi->power_containment_features |= POWERCONTAINMENT_FEATURE_BAPM;
 626                         }
 627
 628                         if (pi->enable_tdc_limit_feature) {
 629                                 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_TDCLimitEnable);
 630                                 if (smc_result != PPSMC_Result_OK)
 631                                         ret = -EINVAL;
 632                                 else
 633                                         pi->power_containment_features |= POWERCONTAINMENT_FEATURE_TDCLimit;
 634                         }
 635
 636                         if (pi->enable_pkg_pwr_tracking_feature) {
 637                                 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_PkgPwrLimitEnable);
 638                                 if (smc_result != PPSMC_Result_OK) {
 639                                         ret = -EINVAL;
 640                                 } else {
 641                                         struct radeon_cac_tdp_table *cac_tdp_table =
 642                                                 rdev->pm.dpm.dyn_state.cac_tdp_table;
 643                                         u32 default_pwr_limit =
 644                                                 (u32)(cac_tdp_table->maximum_power_delivery_limit * 256);
 645
 646                                         pi->power_containment_features |= POWERCONTAINMENT_FEATURE_PkgPwrLimit;
 647
 648                                         ci_set_power_limit(rdev, default_pwr_limit);
 649                                 }
 650                         }
 651                 }
 652         } else {
 653                 if (pi->caps_power_containment && pi->power_containment_features) {
 654                         if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_TDCLimit)
 655                                 ci_send_msg_to_smc(rdev, PPSMC_MSG_TDCLimitDisable);
 656
 657                         if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_BAPM)
 658                                 ci_send_msg_to_smc(rdev, PPSMC_MSG_DisableDTE);
 659
 660                         if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_PkgPwrLimit)
 661                                 ci_send_msg_to_smc(rdev, PPSMC_MSG_PkgPwrLimitDisable);
 662                         pi->power_containment_features = 0;
 663                 }
 664         }
 665
 666         return ret;
 667 }
 668
 669 static int ci_enable_smc_cac(struct radeon_device *rdev, bool enable)
 670 {
 671         struct ci_power_info *pi = ci_get_pi(rdev);
 672         PPSMC_Result smc_result;
 673         int ret = 0;
 674
 675         if (pi->caps_cac) {
 676                 if (enable) {
 677                         smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_EnableCac);
 678                         if (smc_result != PPSMC_Result_OK) {
 679                                 ret = -EINVAL;
 680                                 pi->cac_enabled = false;
 681                         } else {
 682                                 pi->cac_enabled = true;
 683                         }
 684                 } else if (pi->cac_enabled) {
 685                         ci_send_msg_to_smc(rdev, PPSMC_MSG_DisableCac);
 686                         pi->cac_enabled = false;
 687                 }
 688         }
 689
 690         return ret;
 691 }
 692
 693 static int ci_power_control_set_level(struct radeon_device *rdev)
 694 {
 695         struct ci_power_info *pi = ci_get_pi(rdev);
 696         struct radeon_cac_tdp_table *cac_tdp_table =
 697                 rdev->pm.dpm.dyn_state.cac_tdp_table;
 698         s32 adjust_percent;
 699         s32 target_tdp;
 700         int ret = 0;
 701         bool adjust_polarity = false; /* ??? */
 702
 703         if (pi->caps_power_containment &&
 704             (pi->power_containment_features & POWERCONTAINMENT_FEATURE_BAPM)) {
 705                 adjust_percent = adjust_polarity ?
 706                         rdev->pm.dpm.tdp_adjustment : (-1 * rdev->pm.dpm.tdp_adjustment);
 707                 target_tdp = ((100 + adjust_percent) *
 708                               (s32)cac_tdp_table->configurable_tdp) / 100;
 709                 target_tdp *= 256;
 710
 711                 ret = ci_set_overdrive_target_tdp(rdev, (u32)target_tdp);
 712         }
 713
 714         return ret;
 715 }
 716
 717 void ci_dpm_powergate_uvd(struct radeon_device *rdev, bool gate)
 718 {
 719         struct ci_power_info *pi = ci_get_pi(rdev);
 720
 721         if (pi->uvd_power_gated == gate)
 722                 return;
 723
 724         pi->uvd_power_gated = gate;
 725
 726         ci_update_uvd_dpm(rdev, gate);
 727 }
 728
 729 bool ci_dpm_vblank_too_short(struct radeon_device *rdev)
 730 {
 731         struct ci_power_info *pi = ci_get_pi(rdev);
 732         u32 vblank_time = r600_dpm_get_vblank_time(rdev);
 733         u32 switch_limit = pi->mem_gddr5 ? 450 : 300;
 734
 735         if (vblank_time < switch_limit)
 736                 return true;
 737         else
 738                 return false;
 739
 740 }
 741
 742 static void ci_apply_state_adjust_rules(struct radeon_device *rdev,
 743                                         struct radeon_ps *rps)
 744 {
 745         struct ci_ps *ps = ci_get_ps(rps);
 746         struct ci_power_info *pi = ci_get_pi(rdev);
 747         struct radeon_clock_and_voltage_limits *max_limits;
 748         bool disable_mclk_switching;
 749         u32 sclk, mclk;
 750         int i;
 751
 752         if (rps->vce_active) {
 753                 rps->evclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].evclk;
 754                 rps->ecclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].ecclk;
 755         } else {
 756                 rps->evclk = 0;
 757                 rps->ecclk = 0;
 758         }
 759
 760         if ((rdev->pm.dpm.new_active_crtc_count > 1) ||
 761             ci_dpm_vblank_too_short(rdev))
 762                 disable_mclk_switching = true;
 763         else
 764                 disable_mclk_switching = false;
 765
 766         if ((rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) == ATOM_PPLIB_CLASSIFICATION_UI_BATTERY)
 767                 pi->battery_state = true;
 768         else
 769                 pi->battery_state = false;
 770
 771         if (rdev->pm.dpm.ac_power)
 772                 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
 773         else
 774                 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
 775
 776         if (rdev->pm.dpm.ac_power == false) {
 777                 for (i = 0; i < ps->performance_level_count; i++) {
 778                         if (ps->performance_levels[i].mclk > max_limits->mclk)
 779                                 ps->performance_levels[i].mclk = max_limits->mclk;
 780                         if (ps->performance_levels[i].sclk > max_limits->sclk)
 781                                 ps->performance_levels[i].sclk = max_limits->sclk;
 782                 }
 783         }
 784
 785         /* XXX validate the min clocks required for display */
 786
 787         if (disable_mclk_switching) {
 788                 mclk  = ps->performance_levels[ps->performance_level_count - 1].mclk;
 789                 sclk = ps->performance_levels[0].sclk;
 790         } else {
 791                 mclk = ps->performance_levels[0].mclk;
 792                 sclk = ps->performance_levels[0].sclk;
 793         }
 794
 795         if (rps->vce_active) {
 796                 if (sclk < rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].sclk)
 797                         sclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].sclk;
 798                 if (mclk < rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].mclk)
 799                         mclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].mclk;
 800         }
 801
 802         ps->performance_levels[0].sclk = sclk;
 803         ps->performance_levels[0].mclk = mclk;
 804
 805         if (ps->performance_levels[1].sclk < ps->performance_levels[0].sclk)
 806                 ps->performance_levels[1].sclk = ps->performance_levels[0].sclk;
 807
 808         if (disable_mclk_switching) {
 809                 if (ps->performance_levels[0].mclk < ps->performance_levels[1].mclk)
 810                         ps->performance_levels[0].mclk = ps->performance_levels[1].mclk;
 811         } else {
 812                 if (ps->performance_levels[1].mclk < ps->performance_levels[0].mclk)
 813                         ps->performance_levels[1].mclk = ps->performance_levels[0].mclk;
 814         }
 815 }
 816
 817 static int ci_thermal_set_temperature_range(struct radeon_device *rdev,
 818                                             int min_temp, int max_temp)
 819 {
 820         int low_temp = 0 * 1000;
 821         int high_temp = 255 * 1000;
 822         u32 tmp;
 823
 824         if (low_temp < min_temp)
 825                 low_temp = min_temp;
 826         if (high_temp > max_temp)
 827                 high_temp = max_temp;
 828         if (high_temp < low_temp) {
 829                 DRM_ERROR("invalid thermal range: %d - %d\n", low_temp, high_temp);
 830                 return -EINVAL;
 831         }
 832
 833         tmp = RREG32_SMC(CG_THERMAL_INT);
 834         tmp &= ~(CI_DIG_THERM_INTH_MASK | CI_DIG_THERM_INTL_MASK);
 835         tmp |= CI_DIG_THERM_INTH(high_temp / 1000) |
 836                 CI_DIG_THERM_INTL(low_temp / 1000);
 837         WREG32_SMC(CG_THERMAL_INT, tmp);
 838
 839 #if 0
 840         /* XXX: need to figure out how to handle this properly */
 841         tmp = RREG32_SMC(CG_THERMAL_CTRL);
 842         tmp &= DIG_THERM_DPM_MASK;
 843         tmp |= DIG_THERM_DPM(high_temp / 1000);
 844         WREG32_SMC(CG_THERMAL_CTRL, tmp);
 845 #endif
 846
 847         rdev->pm.dpm.thermal.min_temp = low_temp;
 848         rdev->pm.dpm.thermal.max_temp = high_temp;
 849
 850         return 0;
 851 }
 852
 853 static int ci_thermal_enable_alert(struct radeon_device *rdev,
 854                                    bool enable)
 855 {
 856         u32 thermal_int = RREG32_SMC(CG_THERMAL_INT);
 857         PPSMC_Result result;
 858
 859         if (enable) {
 860                 thermal_int &= ~(THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW);
 861                 rdev->irq.dpm_thermal = false;
 862                 result = ci_send_msg_to_smc(rdev, PPSMC_MSG_Thermal_Cntl_Enable);
 863                 if (result != PPSMC_Result_OK) {
 864                         DRM_DEBUG_KMS("Could not enable thermal interrupts.\n");
 865                         return -EINVAL;
 866                 }
 867         } else {
 868                 thermal_int |= THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW;
 869                 rdev->irq.dpm_thermal = true;
 870                 result = ci_send_msg_to_smc(rdev, PPSMC_MSG_Thermal_Cntl_Disable);
 871                 if (result != PPSMC_Result_OK) {
 872                         DRM_DEBUG_KMS("Could not disable thermal interrupts.\n");
 873                         return -EINVAL;
 874                 }
 875         }
 876
 877         WREG32_SMC(CG_THERMAL_INT, thermal_int);
 878
 879         return 0;
 880 }
 881
 882 #if 0
 883 static int ci_read_smc_soft_register(struct radeon_device *rdev,
 884                                      u16 reg_offset, u32 *value)
 885 {
 886         struct ci_power_info *pi = ci_get_pi(rdev);
 887
 888         return ci_read_smc_sram_dword(rdev,
 889                                       pi->soft_regs_start + reg_offset,
 890                                       value, pi->sram_end);
 891 }
 892 #endif
 893
 894 static int ci_write_smc_soft_register(struct radeon_device *rdev,
 895                                       u16 reg_offset, u32 value)
 896 {
 897         struct ci_power_info *pi = ci_get_pi(rdev);
 898
 899         return ci_write_smc_sram_dword(rdev,
 900                                        pi->soft_regs_start + reg_offset,
 901                                        value, pi->sram_end);
 902 }
 903
 904 static void ci_init_fps_limits(struct radeon_device *rdev)
 905 {
 906         struct ci_power_info *pi = ci_get_pi(rdev);
 907         SMU7_Discrete_DpmTable *table = &pi->smc_state_table;
 908
 909         if (pi->caps_fps) {
 910                 u16 tmp;
 911
 912                 tmp = 45;
 913                 table->FpsHighT = cpu_to_be16(tmp);
 914
 915                 tmp = 30;
 916                 table->FpsLowT = cpu_to_be16(tmp);
 917         }
 918 }
 919
 920 static int ci_update_sclk_t(struct radeon_device *rdev)
 921 {
 922         struct ci_power_info *pi = ci_get_pi(rdev);
 923         int ret = 0;
 924         u32 low_sclk_interrupt_t = 0;
 925
 926         if (pi->caps_sclk_throttle_low_notification) {
 927                 low_sclk_interrupt_t = cpu_to_be32(pi->low_sclk_interrupt_t);
 928
 929                 ret = ci_copy_bytes_to_smc(rdev,
 930                                            pi->dpm_table_start +
 931                                            offsetof(SMU7_Discrete_DpmTable, LowSclkInterruptT),
 932                                            (u8 *)&low_sclk_interrupt_t,
 933                                            sizeof(u32), pi->sram_end);
 934
 935         }
 936
 937         return ret;
 938 }
 939
 940 static void ci_get_leakage_voltages(struct radeon_device *rdev)
 941 {
 942         struct ci_power_info *pi = ci_get_pi(rdev);
 943         u16 leakage_id, virtual_voltage_id;
 944         u16 vddc, vddci;
 945         int i;
 946
 947         pi->vddc_leakage.count = 0;
 948         pi->vddci_leakage.count = 0;
 949
 950         if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_EVV) {
 951                 for (i = 0; i < CISLANDS_MAX_LEAKAGE_COUNT; i++) {
 952                         virtual_voltage_id = ATOM_VIRTUAL_VOLTAGE_ID0 + i;
 953                         if (radeon_atom_get_voltage_evv(rdev, virtual_voltage_id, &vddc) != 0)
 954                                 continue;
 955                         if (vddc != 0 && vddc != virtual_voltage_id) {
 956                                 pi->vddc_leakage.actual_voltage[pi->vddc_leakage.count] = vddc;
 957                                 pi->vddc_leakage.leakage_id[pi->vddc_leakage.count] = virtual_voltage_id;
 958                                 pi->vddc_leakage.count++;
 959                         }
 960                 }
 961         } else if (radeon_atom_get_leakage_id_from_vbios(rdev, &leakage_id) == 0) {
 962                 for (i = 0; i < CISLANDS_MAX_LEAKAGE_COUNT; i++) {
 963                         virtual_voltage_id = ATOM_VIRTUAL_VOLTAGE_ID0 + i;
 964                         if (radeon_atom_get_leakage_vddc_based_on_leakage_params(rdev, &vddc, &vddci,
 965                                                                                  virtual_voltage_id,
 966                                                                                  leakage_id) == 0) {
 967                                 if (vddc != 0 && vddc != virtual_voltage_id) {
 968                                         pi->vddc_leakage.actual_voltage[pi->vddc_leakage.count] = vddc;
 969                                         pi->vddc_leakage.leakage_id[pi->vddc_leakage.count] = virtual_voltage_id;
 970                                         pi->vddc_leakage.count++;
 971                                 }
 972                                 if (vddci != 0 && vddci != virtual_voltage_id) {
 973                                         pi->vddci_leakage.actual_voltage[pi->vddci_leakage.count] = vddci;
 974                                         pi->vddci_leakage.leakage_id[pi->vddci_leakage.count] = virtual_voltage_id;
 975                                         pi->vddci_leakage.count++;
 976                                 }
 977                         }
 978                 }
 979         }
 980 }
 981
 982 static void ci_set_dpm_event_sources(struct radeon_device *rdev, u32 sources)
 983 {
 984         struct ci_power_info *pi = ci_get_pi(rdev);
 985         bool want_thermal_protection;
 986         enum radeon_dpm_event_src dpm_event_src;
 987         u32 tmp;
 988
 989         switch (sources) {
 990         case 0:
 991         default:
 992                 want_thermal_protection = false;
 993                 break;
 994         case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL):
 995                 want_thermal_protection = true;
 996                 dpm_event_src = RADEON_DPM_EVENT_SRC_DIGITAL;
 997                 break;
 998         case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL):
 999                 want_thermal_protection = true;
1000                 dpm_event_src = RADEON_DPM_EVENT_SRC_EXTERNAL;
1001                 break;
1002         case ((1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL) |
1003               (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL)):
1004                 want_thermal_protection = true;
1005                 dpm_event_src = RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL;
1006                 break;
1007         }
1008
1009         if (want_thermal_protection) {
1010 #if 0
1011                 /* XXX: need to figure out how to handle this properly */
1012                 tmp = RREG32_SMC(CG_THERMAL_CTRL);
1013                 tmp &= DPM_EVENT_SRC_MASK;
1014                 tmp |= DPM_EVENT_SRC(dpm_event_src);
1015                 WREG32_SMC(CG_THERMAL_CTRL, tmp);
1016 #endif
1017
1018                 tmp = RREG32_SMC(GENERAL_PWRMGT);
1019                 if (pi->thermal_protection)
1020                         tmp &= ~THERMAL_PROTECTION_DIS;
1021                 else
1022                         tmp |= THERMAL_PROTECTION_DIS;
1023                 WREG32_SMC(GENERAL_PWRMGT, tmp);
1024         } else {
1025                 tmp = RREG32_SMC(GENERAL_PWRMGT);
1026                 tmp |= THERMAL_PROTECTION_DIS;
1027                 WREG32_SMC(GENERAL_PWRMGT, tmp);
1028         }
1029 }
1030
1031 static void ci_enable_auto_throttle_source(struct radeon_device *rdev,
1032                                            enum radeon_dpm_auto_throttle_src source,
1033                                            bool enable)
1034 {
1035         struct ci_power_info *pi = ci_get_pi(rdev);
1036
1037         if (enable) {
1038                 if (!(pi->active_auto_throttle_sources & (1 << source))) {
1039                         pi->active_auto_throttle_sources |= 1 << source;
1040                         ci_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources);
1041                 }
1042         } else {
1043                 if (pi->active_auto_throttle_sources & (1 << source)) {
1044                         pi->active_auto_throttle_sources &= ~(1 << source);
1045                         ci_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources);
1046                 }
1047         }
1048 }
1049
1050 static void ci_enable_vr_hot_gpio_interrupt(struct radeon_device *rdev)
1051 {
1052         if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REGULATOR_HOT)
1053                 ci_send_msg_to_smc(rdev, PPSMC_MSG_EnableVRHotGPIOInterrupt);
1054 }
1055
1056 static int ci_unfreeze_sclk_mclk_dpm(struct radeon_device *rdev)
1057 {
1058         struct ci_power_info *pi = ci_get_pi(rdev);
1059         PPSMC_Result smc_result;
1060
1061         if (!pi->need_update_smu7_dpm_table)
1062                 return 0;
1063
1064         if ((!pi->sclk_dpm_key_disabled) &&
1065             (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK))) {
1066                 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_SCLKDPM_UnfreezeLevel);
1067                 if (smc_result != PPSMC_Result_OK)
1068                         return -EINVAL;
1069         }
1070
1071         if ((!pi->mclk_dpm_key_disabled) &&
1072             (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) {
1073                 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_MCLKDPM_UnfreezeLevel);
1074                 if (smc_result != PPSMC_Result_OK)
1075                         return -EINVAL;
1076         }
1077
1078         pi->need_update_smu7_dpm_table = 0;
1079         return 0;
1080 }
1081
1082 static int ci_enable_sclk_mclk_dpm(struct radeon_device *rdev, bool enable)
1083 {
1084         struct ci_power_info *pi = ci_get_pi(rdev);
1085         PPSMC_Result smc_result;
1086
1087         if (enable) {
1088                 if (!pi->sclk_dpm_key_disabled) {
1089                         smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_DPM_Enable);
1090                         if (smc_result != PPSMC_Result_OK)
1091                                 return -EINVAL;
1092                 }
1093
1094                 if (!pi->mclk_dpm_key_disabled) {
1095                         smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_MCLKDPM_Enable);
1096                         if (smc_result != PPSMC_Result_OK)
1097                                 return -EINVAL;
1098
1099                         WREG32_P(MC_SEQ_CNTL_3, CAC_EN, ~CAC_EN);
1100
1101                         WREG32_SMC(LCAC_MC0_CNTL, 0x05);
1102                         WREG32_SMC(LCAC_MC1_CNTL, 0x05);
1103                         WREG32_SMC(LCAC_CPL_CNTL, 0x100005);
1104
1105                         udelay(10);
1106
1107                         WREG32_SMC(LCAC_MC0_CNTL, 0x400005);
1108                         WREG32_SMC(LCAC_MC1_CNTL, 0x400005);
1109                         WREG32_SMC(LCAC_CPL_CNTL, 0x500005);
1110                 }
1111         } else {
1112                 if (!pi->sclk_dpm_key_disabled) {
1113                         smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_DPM_Disable);
1114                         if (smc_result != PPSMC_Result_OK)
1115                                 return -EINVAL;
1116                 }
1117
1118                 if (!pi->mclk_dpm_key_disabled) {
1119                         smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_MCLKDPM_Disable);
1120                         if (smc_result != PPSMC_Result_OK)
1121                                 return -EINVAL;
1122                 }
1123         }
1124
1125         return 0;
1126 }
1127
1128 static int ci_start_dpm(struct radeon_device *rdev)
1129 {
1130         struct ci_power_info *pi = ci_get_pi(rdev);
1131         PPSMC_Result smc_result;
1132         int ret;
1133         u32 tmp;
1134
1135         tmp = RREG32_SMC(GENERAL_PWRMGT);
1136         tmp |= GLOBAL_PWRMGT_EN;
1137         WREG32_SMC(GENERAL_PWRMGT, tmp);
1138
1139         tmp = RREG32_SMC(SCLK_PWRMGT_CNTL);
1140         tmp |= DYNAMIC_PM_EN;
1141         WREG32_SMC(SCLK_PWRMGT_CNTL, tmp);
1142
1143         ci_write_smc_soft_register(rdev, offsetof(SMU7_SoftRegisters, VoltageChangeTimeout), 0x1000);
1144
1145         WREG32_P(BIF_LNCNT_RESET, 0, ~RESET_LNCNT_EN);
1146
1147         smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_Voltage_Cntl_Enable);
1148         if (smc_result != PPSMC_Result_OK)
1149                 return -EINVAL;
1150
1151         ret = ci_enable_sclk_mclk_dpm(rdev, true);
1152         if (ret)
1153                 return ret;
1154
1155         if (!pi->pcie_dpm_key_disabled) {
1156                 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_PCIeDPM_Enable);
1157                 if (smc_result != PPSMC_Result_OK)
1158                         return -EINVAL;
1159         }
1160
1161         return 0;
1162 }
1163
1164 static int ci_freeze_sclk_mclk_dpm(struct radeon_device *rdev)
1165 {
1166         struct ci_power_info *pi = ci_get_pi(rdev);
1167         PPSMC_Result smc_result;
1168
1169         if (!pi->need_update_smu7_dpm_table)
1170                 return 0;
1171
1172         if ((!pi->sclk_dpm_key_disabled) &&
1173             (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK))) {
1174                 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_SCLKDPM_FreezeLevel);
1175                 if (smc_result != PPSMC_Result_OK)
1176                         return -EINVAL;
1177         }
1178
1179         if ((!pi->mclk_dpm_key_disabled) &&
1180             (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) {
1181                 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_MCLKDPM_FreezeLevel);
1182                 if (smc_result != PPSMC_Result_OK)
1183                         return -EINVAL;
1184         }
1185
1186         return 0;
1187 }
1188
1189 static int ci_stop_dpm(struct radeon_device *rdev)
1190 {
1191         struct ci_power_info *pi = ci_get_pi(rdev);
1192         PPSMC_Result smc_result;
1193         int ret;
1194         u32 tmp;
1195
1196         tmp = RREG32_SMC(GENERAL_PWRMGT);
1197         tmp &= ~GLOBAL_PWRMGT_EN;
1198         WREG32_SMC(GENERAL_PWRMGT, tmp);
1199
1200         tmp = RREG32_SMC(SCLK_PWRMGT_CNTL);
1201         tmp &= ~DYNAMIC_PM_EN;
1202         WREG32_SMC(SCLK_PWRMGT_CNTL, tmp);
1203
1204         if (!pi->pcie_dpm_key_disabled) {
1205                 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_PCIeDPM_Disable);
1206                 if (smc_result != PPSMC_Result_OK)
1207                         return -EINVAL;
1208         }
1209
1210         ret = ci_enable_sclk_mclk_dpm(rdev, false);
1211         if (ret)
1212                 return ret;
1213
1214         smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_Voltage_Cntl_Disable);
1215         if (smc_result != PPSMC_Result_OK)
1216                 return -EINVAL;
1217
1218         return 0;
1219 }
1220
1221 static void ci_enable_sclk_control(struct radeon_device *rdev, bool enable)
1222 {
1223         u32 tmp = RREG32_SMC(SCLK_PWRMGT_CNTL);
1224
1225         if (enable)
1226                 tmp &= ~SCLK_PWRMGT_OFF;
1227         else
1228                 tmp |= SCLK_PWRMGT_OFF;
1229         WREG32_SMC(SCLK_PWRMGT_CNTL, tmp);
1230 }
1231
1232 #if 0
1233 static int ci_notify_hw_of_power_source(struct radeon_device *rdev,
1234                                         bool ac_power)
1235 {
1236         struct ci_power_info *pi = ci_get_pi(rdev);
1237         struct radeon_cac_tdp_table *cac_tdp_table =
1238                 rdev->pm.dpm.dyn_state.cac_tdp_table;
1239         u32 power_limit;
1240
1241         if (ac_power)
1242                 power_limit = (u32)(cac_tdp_table->maximum_power_delivery_limit * 256);
1243         else
1244                 power_limit = (u32)(cac_tdp_table->battery_power_limit * 256);
1245
1246         ci_set_power_limit(rdev, power_limit);
1247
1248         if (pi->caps_automatic_dc_transition) {
1249                 if (ac_power)
1250                         ci_send_msg_to_smc(rdev, PPSMC_MSG_RunningOnAC);
1251                 else
1252                         ci_send_msg_to_smc(rdev, PPSMC_MSG_Remove_DC_Clamp);
1253         }
1254
1255         return 0;
1256 }
1257 #endif
1258
1259 static PPSMC_Result ci_send_msg_to_smc_with_parameter(struct radeon_device *rdev,
1260                                                       PPSMC_Msg msg, u32 parameter)
1261 {
1262         WREG32(SMC_MSG_ARG_0, parameter);
1263         return ci_send_msg_to_smc(rdev, msg);
1264 }
1265
1266 static PPSMC_Result ci_send_msg_to_smc_return_parameter(struct radeon_device *rdev,
1267                                                         PPSMC_Msg msg, u32 *parameter)
1268 {
1269         PPSMC_Result smc_result;
1270
1271         smc_result = ci_send_msg_to_smc(rdev, msg);
1272
1273         if ((smc_result == PPSMC_Result_OK) && parameter)
1274                 *parameter = RREG32(SMC_MSG_ARG_0);
1275
1276         return smc_result;
1277 }
1278
1279 static int ci_dpm_force_state_sclk(struct radeon_device *rdev, u32 n)
1280 {
1281         struct ci_power_info *pi = ci_get_pi(rdev);
1282
1283         if (!pi->sclk_dpm_key_disabled) {
1284                 PPSMC_Result smc_result =
1285                         ci_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_DPM_ForceState, n);
1286                 if (smc_result != PPSMC_Result_OK)
1287                         return -EINVAL;
1288         }
1289
1290         return 0;
1291 }
1292
1293 static int ci_dpm_force_state_mclk(struct radeon_device *rdev, u32 n)
1294 {
1295         struct ci_power_info *pi = ci_get_pi(rdev);
1296
1297         if (!pi->mclk_dpm_key_disabled) {
1298                 PPSMC_Result smc_result =
1299                         ci_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_MCLKDPM_ForceState, n);
1300                 if (smc_result != PPSMC_Result_OK)
1301                         return -EINVAL;
1302         }
1303
1304         return 0;
1305 }
1306
1307 static int ci_dpm_force_state_pcie(struct radeon_device *rdev, u32 n)
1308 {
1309         struct ci_power_info *pi = ci_get_pi(rdev);
1310
1311         if (!pi->pcie_dpm_key_disabled) {
1312                 PPSMC_Result smc_result =
1313                         ci_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_PCIeDPM_ForceLevel, n);
1314                 if (smc_result != PPSMC_Result_OK)
1315                         return -EINVAL;
1316         }
1317
1318         return 0;
1319 }
1320
1321 static int ci_set_power_limit(struct radeon_device *rdev, u32 n)
1322 {
1323         struct ci_power_info *pi = ci_get_pi(rdev);
1324
1325         if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_PkgPwrLimit) {
1326                 PPSMC_Result smc_result =
1327                         ci_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_PkgPwrSetLimit, n);
1328                 if (smc_result != PPSMC_Result_OK)
1329                         return -EINVAL;
1330         }
1331
1332         return 0;
1333 }
1334
1335 static int ci_set_overdrive_target_tdp(struct radeon_device *rdev,
1336                                        u32 target_tdp)
1337 {
1338         PPSMC_Result smc_result =
1339                 ci_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_OverDriveSetTargetTdp, target_tdp);
1340         if (smc_result != PPSMC_Result_OK)
1341                 return -EINVAL;
1342         return 0;
1343 }
1344
1345 static int ci_set_boot_state(struct radeon_device *rdev)
1346 {
1347         return ci_enable_sclk_mclk_dpm(rdev, false);
1348 }
1349
1350 static u32 ci_get_average_sclk_freq(struct radeon_device *rdev)
1351 {
1352         u32 sclk_freq;
1353         PPSMC_Result smc_result =
1354                 ci_send_msg_to_smc_return_parameter(rdev,
1355                                                     PPSMC_MSG_API_GetSclkFrequency,
1356                                                     &sclk_freq);
1357         if (smc_result != PPSMC_Result_OK)
1358                 sclk_freq = 0;
1359
1360         return sclk_freq;
1361 }
1362
1363 static u32 ci_get_average_mclk_freq(struct radeon_device *rdev)
1364 {
1365         u32 mclk_freq;
1366         PPSMC_Result smc_result =
1367                 ci_send_msg_to_smc_return_parameter(rdev,
1368                                                     PPSMC_MSG_API_GetMclkFrequency,
1369                                                     &mclk_freq);
1370         if (smc_result != PPSMC_Result_OK)
1371                 mclk_freq = 0;
1372
1373         return mclk_freq;
1374 }
1375
1376 static void ci_dpm_start_smc(struct radeon_device *rdev)
1377 {
1378         int i;
1379
1380         ci_program_jump_on_start(rdev);
1381         ci_start_smc_clock(rdev);
1382         ci_start_smc(rdev);
1383         for (i = 0; i < rdev->usec_timeout; i++) {
1384                 if (RREG32_SMC(FIRMWARE_FLAGS) & INTERRUPTS_ENABLED)
1385                         break;
1386         }
1387 }
1388
1389 static void ci_dpm_stop_smc(struct radeon_device *rdev)
1390 {
1391         ci_reset_smc(rdev);
1392         ci_stop_smc_clock(rdev);
1393 }
1394
1395 static int ci_process_firmware_header(struct radeon_device *rdev)
1396 {
1397         struct ci_power_info *pi = ci_get_pi(rdev);
1398         u32 tmp;
1399         int ret;
1400
1401         ret = ci_read_smc_sram_dword(rdev,
1402                                      SMU7_FIRMWARE_HEADER_LOCATION +
1403                                      offsetof(SMU7_Firmware_Header, DpmTable),
1404                                      &tmp, pi->sram_end);
1405         if (ret)
1406                 return ret;
1407
1408         pi->dpm_table_start = tmp;
1409
1410         ret = ci_read_smc_sram_dword(rdev,
1411                                      SMU7_FIRMWARE_HEADER_LOCATION +
1412                                      offsetof(SMU7_Firmware_Header, SoftRegisters),
1413                                      &tmp, pi->sram_end);
1414         if (ret)
1415                 return ret;
1416
1417         pi->soft_regs_start = tmp;
1418
1419         ret = ci_read_smc_sram_dword(rdev,
1420                                      SMU7_FIRMWARE_HEADER_LOCATION +
1421                                      offsetof(SMU7_Firmware_Header, mcRegisterTable),
1422                                      &tmp, pi->sram_end);
1423         if (ret)
1424                 return ret;
1425
1426         pi->mc_reg_table_start = tmp;
1427
1428         ret = ci_read_smc_sram_dword(rdev,
1429                                      SMU7_FIRMWARE_HEADER_LOCATION +
1430                                      offsetof(SMU7_Firmware_Header, FanTable),
1431                                      &tmp, pi->sram_end);
1432         if (ret)
1433                 return ret;
1434
1435         pi->fan_table_start = tmp;
1436
1437         ret = ci_read_smc_sram_dword(rdev,
1438                                      SMU7_FIRMWARE_HEADER_LOCATION +
1439                                      offsetof(SMU7_Firmware_Header, mcArbDramTimingTable),
1440                                      &tmp, pi->sram_end);
1441         if (ret)
1442                 return ret;
1443
1444         pi->arb_table_start = tmp;
1445
1446         return 0;
1447 }
1448
1449 static void ci_read_clock_registers(struct radeon_device *rdev)
1450 {
1451         struct ci_power_info *pi = ci_get_pi(rdev);
1452
1453         pi->clock_registers.cg_spll_func_cntl =
1454                 RREG32_SMC(CG_SPLL_FUNC_CNTL);
1455         pi->clock_registers.cg_spll_func_cntl_2 =
1456                 RREG32_SMC(CG_SPLL_FUNC_CNTL_2);
1457         pi->clock_registers.cg_spll_func_cntl_3 =
1458                 RREG32_SMC(CG_SPLL_FUNC_CNTL_3);
1459         pi->clock_registers.cg_spll_func_cntl_4 =
1460                 RREG32_SMC(CG_SPLL_FUNC_CNTL_4);
1461         pi->clock_registers.cg_spll_spread_spectrum =
1462                 RREG32_SMC(CG_SPLL_SPREAD_SPECTRUM);
1463         pi->clock_registers.cg_spll_spread_spectrum_2 =
1464                 RREG32_SMC(CG_SPLL_SPREAD_SPECTRUM_2);
1465         pi->clock_registers.dll_cntl = RREG32(DLL_CNTL);
1466         pi->clock_registers.mclk_pwrmgt_cntl = RREG32(MCLK_PWRMGT_CNTL);
1467         pi->clock_registers.mpll_ad_func_cntl = RREG32(MPLL_AD_FUNC_CNTL);
1468         pi->clock_registers.mpll_dq_func_cntl = RREG32(MPLL_DQ_FUNC_CNTL);
1469         pi->clock_registers.mpll_func_cntl = RREG32(MPLL_FUNC_CNTL);
1470         pi->clock_registers.mpll_func_cntl_1 = RREG32(MPLL_FUNC_CNTL_1);
1471         pi->clock_registers.mpll_func_cntl_2 = RREG32(MPLL_FUNC_CNTL_2);
1472         pi->clock_registers.mpll_ss1 = RREG32(MPLL_SS1);
1473         pi->clock_registers.mpll_ss2 = RREG32(MPLL_SS2);
1474 }
1475
1476 static void ci_init_sclk_t(struct radeon_device *rdev)
1477 {
1478         struct ci_power_info *pi = ci_get_pi(rdev);
1479
1480         pi->low_sclk_interrupt_t = 0;
1481 }
1482
1483 static void ci_enable_thermal_protection(struct radeon_device *rdev,
1484                                          bool enable)
1485 {
1486         u32 tmp = RREG32_SMC(GENERAL_PWRMGT);
1487
1488         if (enable)
1489                 tmp &= ~THERMAL_PROTECTION_DIS;
1490         else
1491                 tmp |= THERMAL_PROTECTION_DIS;
1492         WREG32_SMC(GENERAL_PWRMGT, tmp);
1493 }
1494
1495 static void ci_enable_acpi_power_management(struct radeon_device *rdev)
1496 {
1497         u32 tmp = RREG32_SMC(GENERAL_PWRMGT);
1498
1499         tmp |= STATIC_PM_EN;
1500
1501         WREG32_SMC(GENERAL_PWRMGT, tmp);
1502 }
1503
1504 #if 0
1505 static int ci_enter_ulp_state(struct radeon_device *rdev)
1506 {
1507
1508         WREG32(SMC_MESSAGE_0, PPSMC_MSG_SwitchToMinimumPower);
1509
1510         udelay(25000);
1511
1512         return 0;
1513 }
1514
1515 static int ci_exit_ulp_state(struct radeon_device *rdev)
1516 {
1517         int i;
1518
1519         WREG32(SMC_MESSAGE_0, PPSMC_MSG_ResumeFromMinimumPower);
1520
1521         udelay(7000);
1522
1523         for (i = 0; i < rdev->usec_timeout; i++) {
1524                 if (RREG32(SMC_RESP_0) == 1)
1525                         break;
1526                 udelay(1000);
1527         }
1528
1529         return 0;
1530 }
1531 #endif
1532
1533 static int ci_notify_smc_display_change(struct radeon_device *rdev,
1534                                         bool has_display)
1535 {
1536         PPSMC_Msg msg = has_display ? PPSMC_MSG_HasDisplay : PPSMC_MSG_NoDisplay;
1537
1538         return (ci_send_msg_to_smc(rdev, msg) == PPSMC_Result_OK) ?  0 : -EINVAL;
1539 }
1540
1541 static int ci_enable_ds_master_switch(struct radeon_device *rdev,
1542                                       bool enable)
1543 {
1544         struct ci_power_info *pi = ci_get_pi(rdev);
1545
1546         if (enable) {
1547                 if (pi->caps_sclk_ds) {
1548                         if (ci_send_msg_to_smc(rdev, PPSMC_MSG_MASTER_DeepSleep_ON) != PPSMC_Result_OK)
1549                                 return -EINVAL;
1550                 } else {
1551                         if (ci_send_msg_to_smc(rdev, PPSMC_MSG_MASTER_DeepSleep_OFF) != PPSMC_Result_OK)
1552                                 return -EINVAL;
1553                 }
1554         } else {
1555                 if (pi->caps_sclk_ds) {
1556                         if (ci_send_msg_to_smc(rdev, PPSMC_MSG_MASTER_DeepSleep_OFF) != PPSMC_Result_OK)
1557                                 return -EINVAL;
1558                 }
1559         }
1560
1561         return 0;
1562 }
1563
1564 static void ci_program_display_gap(struct radeon_device *rdev)
1565 {
1566         u32 tmp = RREG32_SMC(CG_DISPLAY_GAP_CNTL);
1567         u32 pre_vbi_time_in_us;
1568         u32 frame_time_in_us;
1569         u32 ref_clock = rdev->clock.spll.reference_freq;
1570         u32 refresh_rate = r600_dpm_get_vrefresh(rdev);
1571         u32 vblank_time = r600_dpm_get_vblank_time(rdev);
1572
1573         tmp &= ~DISP_GAP_MASK;
1574         if (rdev->pm.dpm.new_active_crtc_count > 0)
1575                 tmp |= DISP_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM);
1576         else
1577                 tmp |= DISP_GAP(R600_PM_DISPLAY_GAP_IGNORE);
1578         WREG32_SMC(CG_DISPLAY_GAP_CNTL, tmp);
1579
1580         if (refresh_rate == 0)
1581                 refresh_rate = 60;
1582         if (vblank_time == 0xffffffff)
1583                 vblank_time = 500;
1584         frame_time_in_us = 1000000 / refresh_rate;
1585         pre_vbi_time_in_us =
1586                 frame_time_in_us - 200 - vblank_time;
1587         tmp = pre_vbi_time_in_us * (ref_clock / 100);
1588
1589         WREG32_SMC(CG_DISPLAY_GAP_CNTL2, tmp);
1590         ci_write_smc_soft_register(rdev, offsetof(SMU7_SoftRegisters, PreVBlankGap), 0x64);
1591         ci_write_smc_soft_register(rdev, offsetof(SMU7_SoftRegisters, VBlankTimeout), (frame_time_in_us - pre_vbi_time_in_us));
1592
1593
1594         ci_notify_smc_display_change(rdev, (rdev->pm.dpm.new_active_crtc_count == 1));
1595
1596 }
1597
1598 static void ci_enable_spread_spectrum(struct radeon_device *rdev, bool enable)
1599 {
1600         struct ci_power_info *pi = ci_get_pi(rdev);
1601         u32 tmp;
1602
1603         if (enable) {
1604                 if (pi->caps_sclk_ss_support) {
1605                         tmp = RREG32_SMC(GENERAL_PWRMGT);
1606                         tmp |= DYN_SPREAD_SPECTRUM_EN;
1607                         WREG32_SMC(GENERAL_PWRMGT, tmp);
1608                 }
1609         } else {
1610                 tmp = RREG32_SMC(CG_SPLL_SPREAD_SPECTRUM);
1611                 tmp &= ~SSEN;
1612                 WREG32_SMC(CG_SPLL_SPREAD_SPECTRUM, tmp);
1613
1614                 tmp = RREG32_SMC(GENERAL_PWRMGT);
1615                 tmp &= ~DYN_SPREAD_SPECTRUM_EN;
1616                 WREG32_SMC(GENERAL_PWRMGT, tmp);
1617         }
1618 }
1619
1620 static void ci_program_sstp(struct radeon_device *rdev)
1621 {
1622         WREG32_SMC(CG_SSP, (SSTU(R600_SSTU_DFLT) | SST(R600_SST_DFLT)));
1623 }
1624
1625 static void ci_enable_display_gap(struct radeon_device *rdev)
1626 {
1627         u32 tmp = RREG32_SMC(CG_DISPLAY_GAP_CNTL);
1628
1629         tmp &= ~(DISP_GAP_MASK | DISP_GAP_MCHG_MASK);
1630         tmp |= (DISP_GAP(R600_PM_DISPLAY_GAP_IGNORE) |
1631                 DISP_GAP_MCHG(R600_PM_DISPLAY_GAP_VBLANK));
1632
1633         WREG32_SMC(CG_DISPLAY_GAP_CNTL, tmp);
1634 }
1635
1636 static void ci_program_vc(struct radeon_device *rdev)
1637 {
1638         u32 tmp;
1639
1640         tmp = RREG32_SMC(SCLK_PWRMGT_CNTL);
1641         tmp &= ~(RESET_SCLK_CNT | RESET_BUSY_CNT);
1642         WREG32_SMC(SCLK_PWRMGT_CNTL, tmp);
1643
1644         WREG32_SMC(CG_FTV_0, CISLANDS_VRC_DFLT0);
1645         WREG32_SMC(CG_FTV_1, CISLANDS_VRC_DFLT1);
1646         WREG32_SMC(CG_FTV_2, CISLANDS_VRC_DFLT2);
1647         WREG32_SMC(CG_FTV_3, CISLANDS_VRC_DFLT3);
1648         WREG32_SMC(CG_FTV_4, CISLANDS_VRC_DFLT4);
1649         WREG32_SMC(CG_FTV_5, CISLANDS_VRC_DFLT5);
1650         WREG32_SMC(CG_FTV_6, CISLANDS_VRC_DFLT6);
1651         WREG32_SMC(CG_FTV_7, CISLANDS_VRC_DFLT7);
1652 }
1653
1654 static void ci_clear_vc(struct radeon_device *rdev)
1655 {
1656         u32 tmp;
1657
1658         tmp = RREG32_SMC(SCLK_PWRMGT_CNTL);
1659         tmp |= (RESET_SCLK_CNT | RESET_BUSY_CNT);
1660         WREG32_SMC(SCLK_PWRMGT_CNTL, tmp);
1661
1662         WREG32_SMC(CG_FTV_0, 0);
1663         WREG32_SMC(CG_FTV_1, 0);
1664         WREG32_SMC(CG_FTV_2, 0);
1665         WREG32_SMC(CG_FTV_3, 0);
1666         WREG32_SMC(CG_FTV_4, 0);
1667         WREG32_SMC(CG_FTV_5, 0);
1668         WREG32_SMC(CG_FTV_6, 0);
1669         WREG32_SMC(CG_FTV_7, 0);
1670 }
1671
1672 static int ci_upload_firmware(struct radeon_device *rdev)
1673 {
1674         struct ci_power_info *pi = ci_get_pi(rdev);
1675         int i, ret;
1676
1677         for (i = 0; i < rdev->usec_timeout; i++) {
1678                 if (RREG32_SMC(RCU_UC_EVENTS) & BOOT_SEQ_DONE)
1679                         break;
1680         }
1681         WREG32_SMC(SMC_SYSCON_MISC_CNTL, 1);
1682
1683         ci_stop_smc_clock(rdev);
1684         ci_reset_smc(rdev);
1685
1686         ret = ci_load_smc_ucode(rdev, pi->sram_end);
1687
1688         return ret;
1689
1690 }
1691
1692 static int ci_get_svi2_voltage_table(struct radeon_device *rdev,
1693                                      struct radeon_clock_voltage_dependency_table *voltage_dependency_table,
1694                                      struct atom_voltage_table *voltage_table)
1695 {
1696         u32 i;
1697
1698         if (voltage_dependency_table == NULL)
1699                 return -EINVAL;
1700
1701         voltage_table->mask_low = 0;
1702         voltage_table->phase_delay = 0;
1703
1704         voltage_table->count = voltage_dependency_table->count;
1705         for (i = 0; i < voltage_table->count; i++) {
1706                 voltage_table->entries[i].value = voltage_dependency_table->entries[i].v;
1707                 voltage_table->entries[i].smio_low = 0;
1708         }
1709
1710         return 0;
1711 }
1712
1713 static int ci_construct_voltage_tables(struct radeon_device *rdev)
1714 {
1715         struct ci_power_info *pi = ci_get_pi(rdev);
1716         int ret;
1717
1718         if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) {
1719                 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDC,
1720                                                     VOLTAGE_OBJ_GPIO_LUT,
1721                                                     &pi->vddc_voltage_table);
1722                 if (ret)
1723                         return ret;
1724         } else if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2) {
1725                 ret = ci_get_svi2_voltage_table(rdev,
1726                                                 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
1727                                                 &pi->vddc_voltage_table);
1728                 if (ret)
1729                         return ret;
1730         }
1731
1732         if (pi->vddc_voltage_table.count > SMU7_MAX_LEVELS_VDDC)
1733                 si_trim_voltage_table_to_fit_state_table(rdev, SMU7_MAX_LEVELS_VDDC,
1734                                                          &pi->vddc_voltage_table);
1735
1736         if (pi->vddci_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) {
1737                 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDCI,
1738                                                     VOLTAGE_OBJ_GPIO_LUT,
1739                                                     &pi->vddci_voltage_table);
1740                 if (ret)
1741                         return ret;
1742         } else if (pi->vddci_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2) {
1743                 ret = ci_get_svi2_voltage_table(rdev,
1744                                                 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
1745                                                 &pi->vddci_voltage_table);
1746                 if (ret)
1747                         return ret;
1748         }
1749
1750         if (pi->vddci_voltage_table.count > SMU7_MAX_LEVELS_VDDCI)
1751                 si_trim_voltage_table_to_fit_state_table(rdev, SMU7_MAX_LEVELS_VDDCI,
1752                                                          &pi->vddci_voltage_table);
1753
1754         if (pi->mvdd_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) {
1755                 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_MVDDC,
1756                                                     VOLTAGE_OBJ_GPIO_LUT,
1757                                                     &pi->mvdd_voltage_table);
1758                 if (ret)
1759                         return ret;
1760         } else if (pi->mvdd_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2) {
1761                 ret = ci_get_svi2_voltage_table(rdev,
1762                                                 &rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk,
1763                                                 &pi->mvdd_voltage_table);
1764                 if (ret)
1765                         return ret;
1766         }
1767
1768         if (pi->mvdd_voltage_table.count > SMU7_MAX_LEVELS_MVDD)
1769                 si_trim_voltage_table_to_fit_state_table(rdev, SMU7_MAX_LEVELS_MVDD,
1770                                                          &pi->mvdd_voltage_table);
1771
1772         return 0;
1773 }
1774
1775 static void ci_populate_smc_voltage_table(struct radeon_device *rdev,
1776                                           struct atom_voltage_table_entry *voltage_table,
1777                                           SMU7_Discrete_VoltageLevel *smc_voltage_table)
1778 {
1779         int ret;
1780
1781         ret = ci_get_std_voltage_value_sidd(rdev, voltage_table,
1782                                             &smc_voltage_table->StdVoltageHiSidd,
1783                                             &smc_voltage_table->StdVoltageLoSidd);
1784
1785         if (ret) {
1786                 smc_voltage_table->StdVoltageHiSidd = voltage_table->value * VOLTAGE_SCALE;
1787                 smc_voltage_table->StdVoltageLoSidd = voltage_table->value * VOLTAGE_SCALE;
1788         }
1789
1790         smc_voltage_table->Voltage = cpu_to_be16(voltage_table->value * VOLTAGE_SCALE);
1791         smc_voltage_table->StdVoltageHiSidd =
1792                 cpu_to_be16(smc_voltage_table->StdVoltageHiSidd);
1793         smc_voltage_table->StdVoltageLoSidd =
1794                 cpu_to_be16(smc_voltage_table->StdVoltageLoSidd);
1795 }
1796
1797 static int ci_populate_smc_vddc_table(struct radeon_device *rdev,
1798                                       SMU7_Discrete_DpmTable *table)
1799 {
1800         struct ci_power_info *pi = ci_get_pi(rdev);
1801         unsigned int count;
1802
1803         table->VddcLevelCount = pi->vddc_voltage_table.count;
1804         for (count = 0; count < table->VddcLevelCount; count++) {
1805                 ci_populate_smc_voltage_table(rdev,
1806                                               &pi->vddc_voltage_table.entries[count],
1807                                               &table->VddcLevel[count]);
1808
1809                 if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO)
1810                         table->VddcLevel[count].Smio |=
1811                                 pi->vddc_voltage_table.entries[count].smio_low;
1812                 else
1813                         table->VddcLevel[count].Smio = 0;
1814         }
1815         table->VddcLevelCount = cpu_to_be32(table->VddcLevelCount);
1816
1817         return 0;
1818 }
1819
1820 static int ci_populate_smc_vddci_table(struct radeon_device *rdev,
1821                                        SMU7_Discrete_DpmTable *table)
1822 {
1823         unsigned int count;
1824         struct ci_power_info *pi = ci_get_pi(rdev);
1825
1826         table->VddciLevelCount = pi->vddci_voltage_table.count;
1827         for (count = 0; count < table->VddciLevelCount; count++) {
1828                 ci_populate_smc_voltage_table(rdev,
1829                                               &pi->vddci_voltage_table.entries[count],
1830                                               &table->VddciLevel[count]);
1831
1832                 if (pi->vddci_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO)
1833                         table->VddciLevel[count].Smio |=
1834                                 pi->vddci_voltage_table.entries[count].smio_low;
1835                 else
1836                         table->VddciLevel[count].Smio = 0;
1837         }
1838         table->VddciLevelCount = cpu_to_be32(table->VddciLevelCount);
1839
1840         return 0;
1841 }
1842
1843 static int ci_populate_smc_mvdd_table(struct radeon_device *rdev,
1844                                       SMU7_Discrete_DpmTable *table)
1845 {
1846         struct ci_power_info *pi = ci_get_pi(rdev);
1847         unsigned int count;
1848
1849         table->MvddLevelCount = pi->mvdd_voltage_table.count;
1850         for (count = 0; count < table->MvddLevelCount; count++) {
1851                 ci_populate_smc_voltage_table(rdev,
1852                                               &pi->mvdd_voltage_table.entries[count],
1853                                               &table->MvddLevel[count]);
1854
1855                 if (pi->mvdd_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO)
1856                         table->MvddLevel[count].Smio |=
1857                                 pi->mvdd_voltage_table.entries[count].smio_low;
1858                 else
1859                         table->MvddLevel[count].Smio = 0;
1860         }
1861         table->MvddLevelCount = cpu_to_be32(table->MvddLevelCount);
1862
1863         return 0;
1864 }
1865
1866 static int ci_populate_smc_voltage_tables(struct radeon_device *rdev,
1867                                           SMU7_Discrete_DpmTable *table)
1868 {
1869         int ret;
1870
1871         ret = ci_populate_smc_vddc_table(rdev, table);
1872         if (ret)
1873                 return ret;
1874
1875         ret = ci_populate_smc_vddci_table(rdev, table);
1876         if (ret)
1877                 return ret;
1878
1879         ret = ci_populate_smc_mvdd_table(rdev, table);
1880         if (ret)
1881                 return ret;
1882
1883         return 0;
1884 }
1885
1886 static int ci_populate_mvdd_value(struct radeon_device *rdev, u32 mclk,
1887                                   SMU7_Discrete_VoltageLevel *voltage)
1888 {
1889         struct ci_power_info *pi = ci_get_pi(rdev);
1890         u32 i = 0;
1891
1892         if (pi->mvdd_control != CISLANDS_VOLTAGE_CONTROL_NONE) {
1893                 for (i = 0; i < rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.count; i++) {
1894                         if (mclk <= rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.entries[i].clk) {
1895                                 voltage->Voltage = pi->mvdd_voltage_table.entries[i].value;
1896                                 break;
1897                         }
1898                 }
1899
1900                 if (i >= rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.count)
1901                         return -EINVAL;
1902         }
1903
1904         return -EINVAL;
1905 }
1906
1907 static int ci_get_std_voltage_value_sidd(struct radeon_device *rdev,
1908                                          struct atom_voltage_table_entry *voltage_table,
1909                                          u16 *std_voltage_hi_sidd, u16 *std_voltage_lo_sidd)
1910 {
1911         u16 v_index, idx;
1912         bool voltage_found = false;
1913         *std_voltage_hi_sidd = voltage_table->value * VOLTAGE_SCALE;
1914         *std_voltage_lo_sidd = voltage_table->value * VOLTAGE_SCALE;
1915
1916         if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries == NULL)
1917                 return -EINVAL;
1918
1919         if (rdev->pm.dpm.dyn_state.cac_leakage_table.entries) {
1920                 for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {
1921                         if (voltage_table->value ==
1922                             rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) {
1923                                 voltage_found = true;
1924                                 if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count)
1925                                         idx = v_index;
1926                                 else
1927                                         idx = rdev->pm.dpm.dyn_state.cac_leakage_table.count - 1;
1928                                 *std_voltage_lo_sidd =
1929                                         rdev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].vddc * VOLTAGE_SCALE;
1930                                 *std_voltage_hi_sidd =
1931                                         rdev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].leakage * VOLTAGE_SCALE;
1932                                 break;
1933                         }
1934                 }
1935
1936                 if (!voltage_found) {
1937                         for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {
1938                                 if (voltage_table->value <=
1939                                     rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) {
1940                                         voltage_found = true;
1941                                         if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count)
1942                                                 idx = v_index;
1943                                         else
1944                                                 idx = rdev->pm.dpm.dyn_state.cac_leakage_table.count - 1;
1945                                         *std_voltage_lo_sidd =
1946                                                 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].vddc * VOLTAGE_SCALE;
1947                                         *std_voltage_hi_sidd =
1948                                                 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].leakage * VOLTAGE_SCALE;
1949                                         break;
1950                                 }
1951                         }
1952                 }
1953         }
1954
1955         return 0;
1956 }
1957
1958 static void ci_populate_phase_value_based_on_sclk(struct radeon_device *rdev,
1959                                                   const struct radeon_phase_shedding_limits_table *limits,
1960                                                   u32 sclk,
1961                                                   u32 *phase_shedding)
1962 {
1963         unsigned int i;
1964
1965         *phase_shedding = 1;
1966
1967         for (i = 0; i < limits->count; i++) {
1968                 if (sclk < limits->entries[i].sclk) {
1969                         *phase_shedding = i;
1970                         break;
1971                 }
1972         }
1973 }
1974
1975 static void ci_populate_phase_value_based_on_mclk(struct radeon_device *rdev,
1976                                                   const struct radeon_phase_shedding_limits_table *limits,
1977                                                   u32 mclk,
1978                                                   u32 *phase_shedding)
1979 {
1980         unsigned int i;
1981
1982         *phase_shedding = 1;
1983
1984         for (i = 0; i < limits->count; i++) {
1985                 if (mclk < limits->entries[i].mclk) {
1986                         *phase_shedding = i;
1987                         break;
1988                 }
1989         }
1990 }
1991
1992 static int ci_init_arb_table_index(struct radeon_device *rdev)
1993 {
1994         struct ci_power_info *pi = ci_get_pi(rdev);
1995         u32 tmp;
1996         int ret;
1997
1998         ret = ci_read_smc_sram_dword(rdev, pi->arb_table_start,
1999                                      &tmp, pi->sram_end);
2000         if (ret)
2001                 return ret;
2002
2003         tmp &= 0x00FFFFFF;
2004         tmp |= MC_CG_ARB_FREQ_F1 << 24;
2005
2006         return ci_write_smc_sram_dword(rdev, pi->arb_table_start,
2007                                        tmp, pi->sram_end);
2008 }
2009
2010 static int ci_get_dependency_volt_by_clk(struct radeon_device *rdev,
2011                                          struct radeon_clock_voltage_dependency_table *allowed_clock_voltage_table,
2012                                          u32 clock, u32 *voltage)
2013 {
2014         u32 i = 0;
2015
2016         if (allowed_clock_voltage_table->count == 0)
2017                 return -EINVAL;
2018
2019         for (i = 0; i < allowed_clock_voltage_table->count; i++) {
2020                 if (allowed_clock_voltage_table->entries[i].clk >= clock) {
2021                         *voltage = allowed_clock_voltage_table->entries[i].v;
2022                         return 0;
2023                 }
2024         }
2025
2026         *voltage = allowed_clock_voltage_table->entries[i-1].v;
2027
2028         return 0;
2029 }
2030
2031 static u8 ci_get_sleep_divider_id_from_clock(struct radeon_device *rdev,
2032                                              u32 sclk, u32 min_sclk_in_sr)
2033 {
2034         u32 i;
2035         u32 tmp;
2036         u32 min = (min_sclk_in_sr > CISLAND_MINIMUM_ENGINE_CLOCK) ?
2037                 min_sclk_in_sr : CISLAND_MINIMUM_ENGINE_CLOCK;
2038
2039         if (sclk < min)
2040                 return 0;
2041
2042         for (i = CISLAND_MAX_DEEPSLEEP_DIVIDER_ID;  ; i--) {
2043                 tmp = sclk / (1 << i);
2044                 if (tmp >= min || i == 0)
2045                         break;
2046         }
2047
2048         return (u8)i;
2049 }
2050
2051 static int ci_initial_switch_from_arb_f0_to_f1(struct radeon_device *rdev)
2052 {
2053         return ni_copy_and_switch_arb_sets(rdev, MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1);
2054 }
2055
2056 static int ci_reset_to_default(struct radeon_device *rdev)
2057 {
2058         return (ci_send_msg_to_smc(rdev, PPSMC_MSG_ResetToDefaults) == PPSMC_Result_OK) ?
2059                 0 : -EINVAL;
2060 }
2061
2062 static int ci_force_switch_to_arb_f0(struct radeon_device *rdev)
2063 {
2064         u32 tmp;
2065
2066         tmp = (RREG32_SMC(SMC_SCRATCH9) & 0x0000ff00) >> 8;
2067
2068         if (tmp == MC_CG_ARB_FREQ_F0)
2069                 return 0;
2070
2071         return ni_copy_and_switch_arb_sets(rdev, tmp, MC_CG_ARB_FREQ_F0);
2072 }
2073
2074 static int ci_populate_memory_timing_parameters(struct radeon_device *rdev,
2075                                                 u32 sclk,
2076                                                 u32 mclk,
2077                                                 SMU7_Discrete_MCArbDramTimingTableEntry *arb_regs)
2078 {
2079         u32 dram_timing;
2080         u32 dram_timing2;
2081         u32 burst_time;
2082
2083         radeon_atom_set_engine_dram_timings(rdev, sclk, mclk);
2084
2085         dram_timing  = RREG32(MC_ARB_DRAM_TIMING);
2086         dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2);
2087         burst_time = RREG32(MC_ARB_BURST_TIME) & STATE0_MASK;
2088
2089         arb_regs->McArbDramTiming  = cpu_to_be32(dram_timing);
2090         arb_regs->McArbDramTiming2 = cpu_to_be32(dram_timing2);
2091         arb_regs->McArbBurstTime = (u8)burst_time;
2092
2093         return 0;
2094 }
2095
2096 static int ci_do_program_memory_timing_parameters(struct radeon_device *rdev)
2097 {
2098         struct ci_power_info *pi = ci_get_pi(rdev);
2099         SMU7_Discrete_MCArbDramTimingTable arb_regs;
2100         u32 i, j;
2101         int ret =  0;
2102
2103         memset(&arb_regs, 0, sizeof(SMU7_Discrete_MCArbDramTimingTable));
2104
2105         for (i = 0; i < pi->dpm_table.sclk_table.count; i++) {
2106                 for (j = 0; j < pi->dpm_table.mclk_table.count; j++) {
2107                         ret = ci_populate_memory_timing_parameters(rdev,
2108                                                                    pi->dpm_table.sclk_table.dpm_levels[i].value,
2109                                                                    pi->dpm_table.mclk_table.dpm_levels[j].value,
2110                                                                    &arb_regs.entries[i][j]);
2111                         if (ret)
2112                                 break;
2113                 }
2114         }
2115
2116         if (ret == 0)
2117                 ret = ci_copy_bytes_to_smc(rdev,
2118                                            pi->arb_table_start,
2119                                            (u8 *)&arb_regs,
2120                                            sizeof(SMU7_Discrete_MCArbDramTimingTable),
2121                                            pi->sram_end);
2122
2123         return ret;
2124 }
2125
2126 static int ci_program_memory_timing_parameters(struct radeon_device *rdev)
2127 {
2128         struct ci_power_info *pi = ci_get_pi(rdev);
2129
2130         if (pi->need_update_smu7_dpm_table == 0)
2131                 return 0;
2132
2133         return ci_do_program_memory_timing_parameters(rdev);
2134 }
2135
2136 static void ci_populate_smc_initial_state(struct radeon_device *rdev,
2137                                           struct radeon_ps *radeon_boot_state)
2138 {
2139         struct ci_ps *boot_state = ci_get_ps(radeon_boot_state);
2140         struct ci_power_info *pi = ci_get_pi(rdev);
2141         u32 level = 0;
2142
2143         for (level = 0; level < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; level++) {
2144                 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[level].clk >=
2145                     boot_state->performance_levels[0].sclk) {
2146                         pi->smc_state_table.GraphicsBootLevel = level;
2147                         break;
2148                 }
2149         }
2150
2151         for (level = 0; level < rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk.count; level++) {
2152                 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk.entries[level].clk >=
2153                     boot_state->performance_levels[0].mclk) {
2154                         pi->smc_state_table.MemoryBootLevel = level;
2155                         break;
2156                 }
2157         }
2158 }
2159
2160 static u32 ci_get_dpm_level_enable_mask_value(struct ci_single_dpm_table *dpm_table)
2161 {
2162         u32 i;
2163         u32 mask_value = 0;
2164
2165         for (i = dpm_table->count; i > 0; i--) {
2166                 mask_value = mask_value << 1;
2167                 if (dpm_table->dpm_levels[i-1].enabled)
2168                         mask_value |= 0x1;
2169                 else
2170                         mask_value &= 0xFFFFFFFE;
2171         }
2172
2173         return mask_value;
2174 }
2175
2176 static void ci_populate_smc_link_level(struct radeon_device *rdev,
2177                                        SMU7_Discrete_DpmTable *table)
2178 {
2179         struct ci_power_info *pi = ci_get_pi(rdev);
2180         struct ci_dpm_table *dpm_table = &pi->dpm_table;
2181         u32 i;
2182
2183         for (i = 0; i < dpm_table->pcie_speed_table.count; i++) {
2184                 table->LinkLevel[i].PcieGenSpeed =
2185                         (u8)dpm_table->pcie_speed_table.dpm_levels[i].value;
2186                 table->LinkLevel[i].PcieLaneCount =
2187                         r600_encode_pci_lane_width(dpm_table->pcie_speed_table.dpm_levels[i].param1);
2188                 table->LinkLevel[i].EnabledForActivity = 1;
2189                 table->LinkLevel[i].DownT = cpu_to_be32(5);
2190                 table->LinkLevel[i].UpT = cpu_to_be32(30);
2191         }
2192
2193         pi->smc_state_table.LinkLevelCount = (u8)dpm_table->pcie_speed_table.count;
2194         pi->dpm_level_enable_mask.pcie_dpm_enable_mask =
2195                 ci_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table);
2196 }
2197
2198 static int ci_populate_smc_uvd_level(struct radeon_device *rdev,
2199                                      SMU7_Discrete_DpmTable *table)
2200 {
2201         u32 count;
2202         struct atom_clock_dividers dividers;
2203         int ret = -EINVAL;
2204
2205         table->UvdLevelCount =
2206                 rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count;
2207
2208         for (count = 0; count < table->UvdLevelCount; count++) {
2209                 table->UvdLevel[count].VclkFrequency =
2210                         rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[count].vclk;
2211                 table->UvdLevel[count].DclkFrequency =
2212                         rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[count].dclk;
2213                 table->UvdLevel[count].MinVddc =
2214                         rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[count].v * VOLTAGE_SCALE;
2215                 table->UvdLevel[count].MinVddcPhases = 1;
2216
2217                 ret = radeon_atom_get_clock_dividers(rdev,
2218                                                      COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
2219                                                      table->UvdLevel[count].VclkFrequency, false, &dividers);
2220                 if (ret)
2221                         return ret;
2222
2223                 table->UvdLevel[count].VclkDivider = (u8)dividers.post_divider;
2224
2225                 ret = radeon_atom_get_clock_dividers(rdev,
2226                                                      COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
2227                                                      table->UvdLevel[count].DclkFrequency, false, &dividers);
2228                 if (ret)
2229                         return ret;
2230
2231                 table->UvdLevel[count].DclkDivider = (u8)dividers.post_divider;
2232
2233                 table->UvdLevel[count].VclkFrequency = cpu_to_be32(table->UvdLevel[count].VclkFrequency);
2234                 table->UvdLevel[count].DclkFrequency = cpu_to_be32(table->UvdLevel[count].DclkFrequency);
2235                 table->UvdLevel[count].MinVddc = cpu_to_be16(table->UvdLevel[count].MinVddc);
2236         }
2237
2238         return ret;
2239 }
2240
2241 static int ci_populate_smc_vce_level(struct radeon_device *rdev,
2242                                      SMU7_Discrete_DpmTable *table)
2243 {
2244         u32 count;
2245         struct atom_clock_dividers dividers;
2246         int ret = -EINVAL;
2247
2248         table->VceLevelCount =
2249                 rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.count;
2250
2251         for (count = 0; count < table->VceLevelCount; count++) {
2252                 table->VceLevel[count].Frequency =
2253                         rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[count].evclk;
2254                 table->VceLevel[count].MinVoltage =
2255                         (u16)rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[count].v * VOLTAGE_SCALE;
2256                 table->VceLevel[count].MinPhases = 1;
2257
2258                 ret = radeon_atom_get_clock_dividers(rdev,
2259                                                      COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
2260                                                      table->VceLevel[count].Frequency, false, &dividers);
2261                 if (ret)
2262                         return ret;
2263
2264                 table->VceLevel[count].Divider = (u8)dividers.post_divider;
2265
2266                 table->VceLevel[count].Frequency = cpu_to_be32(table->VceLevel[count].Frequency);
2267                 table->VceLevel[count].MinVoltage = cpu_to_be16(table->VceLevel[count].MinVoltage);
2268         }
2269
2270         return ret;
2271
2272 }
2273
2274 static int ci_populate_smc_acp_level(struct radeon_device *rdev,
2275                                      SMU7_Discrete_DpmTable *table)
2276 {
2277         u32 count;
2278         struct atom_clock_dividers dividers;
2279         int ret = -EINVAL;
2280
2281         table->AcpLevelCount = (u8)
2282                 (rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.count);
2283
2284         for (count = 0; count < table->AcpLevelCount; count++) {
2285                 table->AcpLevel[count].Frequency =
2286                         rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries[count].clk;
2287                 table->AcpLevel[count].MinVoltage =
2288                         rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries[count].v;
2289                 table->AcpLevel[count].MinPhases = 1;
2290
2291                 ret = radeon_atom_get_clock_dividers(rdev,
2292                                                      COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
2293                                                      table->AcpLevel[count].Frequency, false, &dividers);
2294                 if (ret)
2295                         return ret;
2296
2297                 table->AcpLevel[count].Divider = (u8)dividers.post_divider;
2298
2299                 table->AcpLevel[count].Frequency = cpu_to_be32(table->AcpLevel[count].Frequency);
2300                 table->AcpLevel[count].MinVoltage = cpu_to_be16(table->AcpLevel[count].MinVoltage);
2301         }
2302
2303         return ret;
2304 }
2305
2306 static int ci_populate_smc_samu_level(struct radeon_device *rdev,
2307                                       SMU7_Discrete_DpmTable *table)
2308 {
2309         u32 count;
2310         struct atom_clock_dividers dividers;
2311         int ret = -EINVAL;
2312
2313         table->SamuLevelCount =
2314                 rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.count;
2315
2316         for (count = 0; count < table->SamuLevelCount; count++) {
2317                 table->SamuLevel[count].Frequency =
2318                         rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries[count].clk;
2319                 table->SamuLevel[count].MinVoltage =
2320                         rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries[count].v * VOLTAGE_SCALE;
2321                 table->SamuLevel[count].MinPhases = 1;
2322
2323                 ret = radeon_atom_get_clock_dividers(rdev,
2324                                                      COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
2325                                                      table->SamuLevel[count].Frequency, false, &dividers);
2326                 if (ret)
2327                         return ret;
2328
2329                 table->SamuLevel[count].Divider = (u8)dividers.post_divider;
2330
2331                 table->SamuLevel[count].Frequency = cpu_to_be32(table->SamuLevel[count].Frequency);
2332                 table->SamuLevel[count].MinVoltage = cpu_to_be16(table->SamuLevel[count].MinVoltage);
2333         }
2334
2335         return ret;
2336 }
2337
2338 static int ci_calculate_mclk_params(struct radeon_device *rdev,
2339                                     u32 memory_clock,
2340                                     SMU7_Discrete_MemoryLevel *mclk,
2341                                     bool strobe_mode,
2342                                     bool dll_state_on)
2343 {
2344         struct ci_power_info *pi = ci_get_pi(rdev);
2345         u32  dll_cntl = pi->clock_registers.dll_cntl;
2346         u32  mclk_pwrmgt_cntl = pi->clock_registers.mclk_pwrmgt_cntl;
2347         u32  mpll_ad_func_cntl = pi->clock_registers.mpll_ad_func_cntl;
2348         u32  mpll_dq_func_cntl = pi->clock_registers.mpll_dq_func_cntl;
2349         u32  mpll_func_cntl = pi->clock_registers.mpll_func_cntl;
2350         u32  mpll_func_cntl_1 = pi->clock_registers.mpll_func_cntl_1;
2351         u32  mpll_func_cntl_2 = pi->clock_registers.mpll_func_cntl_2;
2352         u32  mpll_ss1 = pi->clock_registers.mpll_ss1;
2353         u32  mpll_ss2 = pi->clock_registers.mpll_ss2;
2354         struct atom_mpll_param mpll_param;
2355         int ret;
2356
2357         ret = radeon_atom_get_memory_pll_dividers(rdev, memory_clock, strobe_mode, &mpll_param);
2358         if (ret)
2359                 return ret;
2360
2361         mpll_func_cntl &= ~BWCTRL_MASK;
2362         mpll_func_cntl |= BWCTRL(mpll_param.bwcntl);
2363
2364         mpll_func_cntl_1 &= ~(CLKF_MASK | CLKFRAC_MASK | VCO_MODE_MASK);
2365         mpll_func_cntl_1 |= CLKF(mpll_param.clkf) |
2366                 CLKFRAC(mpll_param.clkfrac) | VCO_MODE(mpll_param.vco_mode);
2367
2368         mpll_ad_func_cntl &= ~YCLK_POST_DIV_MASK;
2369         mpll_ad_func_cntl |= YCLK_POST_DIV(mpll_param.post_div);
2370
2371         if (pi->mem_gddr5) {
2372                 mpll_dq_func_cntl &= ~(YCLK_SEL_MASK | YCLK_POST_DIV_MASK);
2373                 mpll_dq_func_cntl |= YCLK_SEL(mpll_param.yclk_sel) |
2374                         YCLK_POST_DIV(mpll_param.post_div);
2375         }
2376
2377         if (pi->caps_mclk_ss_support) {
2378                 struct radeon_atom_ss ss;
2379                 u32 freq_nom;
2380                 u32 tmp;
2381                 u32 reference_clock = rdev->clock.mpll.reference_freq;
2382
2383                 if (pi->mem_gddr5)
2384                         freq_nom = memory_clock * 4;
2385                 else
2386                         freq_nom = memory_clock * 2;
2387
2388                 tmp = (freq_nom / reference_clock);
2389                 tmp = tmp * tmp;
2390                 if (radeon_atombios_get_asic_ss_info(rdev, &ss,
2391                                                      ASIC_INTERNAL_MEMORY_SS, freq_nom)) {
2392                         u32 clks = reference_clock * 5 / ss.rate;
2393                         u32 clkv = (u32)((((131 * ss.percentage * ss.rate) / 100) * tmp) / freq_nom);
2394
2395                         mpll_ss1 &= ~CLKV_MASK;
2396                         mpll_ss1 |= CLKV(clkv);
2397
2398                         mpll_ss2 &= ~CLKS_MASK;
2399                         mpll_ss2 |= CLKS(clks);
2400                 }
2401         }
2402
2403         mclk_pwrmgt_cntl &= ~DLL_SPEED_MASK;
2404         mclk_pwrmgt_cntl |= DLL_SPEED(mpll_param.dll_speed);
2405
2406         if (dll_state_on)
2407                 mclk_pwrmgt_cntl |= MRDCK0_PDNB | MRDCK1_PDNB;
2408         else
2409                 mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB);
2410
2411         mclk->MclkFrequency = memory_clock;
2412         mclk->MpllFuncCntl = mpll_func_cntl;
2413         mclk->MpllFuncCntl_1 = mpll_func_cntl_1;
2414         mclk->MpllFuncCntl_2 = mpll_func_cntl_2;
2415         mclk->MpllAdFuncCntl = mpll_ad_func_cntl;
2416         mclk->MpllDqFuncCntl = mpll_dq_func_cntl;
2417         mclk->MclkPwrmgtCntl = mclk_pwrmgt_cntl;
2418         mclk->DllCntl = dll_cntl;
2419         mclk->MpllSs1 = mpll_ss1;
2420         mclk->MpllSs2 = mpll_ss2;
2421
2422         return 0;
2423 }
2424
2425 static int ci_populate_single_memory_level(struct radeon_device *rdev,
2426                                            u32 memory_clock,
2427                                            SMU7_Discrete_MemoryLevel *memory_level)
2428 {
2429         struct ci_power_info *pi = ci_get_pi(rdev);
2430         int ret;
2431         bool dll_state_on;
2432
2433         if (rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk.entries) {
2434                 ret = ci_get_dependency_volt_by_clk(rdev,
2435                                                     &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
2436                                                     memory_clock, &memory_level->MinVddc);
2437                 if (ret)
2438                         return ret;
2439         }
2440
2441         if (rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk.entries) {
2442                 ret = ci_get_dependency_volt_by_clk(rdev,
2443                                                     &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
2444                                                     memory_clock, &memory_level->MinVddci);
2445                 if (ret)
2446                         return ret;
2447         }
2448
2449         if (rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.entries) {
2450                 ret = ci_get_dependency_volt_by_clk(rdev,
2451                                                     &rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk,
2452                                                     memory_clock, &memory_level->MinMvdd);
2453                 if (ret)
2454                         return ret;
2455         }
2456
2457         memory_level->MinVddcPhases = 1;
2458
2459         if (pi->vddc_phase_shed_control)
2460                 ci_populate_phase_value_based_on_mclk(rdev,
2461                                                       &rdev->pm.dpm.dyn_state.phase_shedding_limits_table,
2462                                                       memory_clock,
2463                                                       &memory_level->MinVddcPhases);
2464
2465         memory_level->EnabledForThrottle = 1;
2466         memory_level->EnabledForActivity = 1;
2467         memory_level->UpH = 0;
2468         memory_level->DownH = 100;
2469         memory_level->VoltageDownH = 0;
2470         memory_level->ActivityLevel = (u16)pi->mclk_activity_target;
2471
2472         memory_level->StutterEnable = false;
2473         memory_level->StrobeEnable = false;
2474         memory_level->EdcReadEnable = false;
2475         memory_level->EdcWriteEnable = false;
2476         memory_level->RttEnable = false;
2477
2478         memory_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
2479
2480         if (pi->mclk_stutter_mode_threshold &&
2481             (memory_clock <= pi->mclk_stutter_mode_threshold) &&
2482             (pi->uvd_enabled == false) &&
2483             (RREG32(DPG_PIPE_STUTTER_CONTROL) & STUTTER_ENABLE) &&
2484             (rdev->pm.dpm.new_active_crtc_count <= 2))
2485                 memory_level->StutterEnable = true;
2486
2487         if (pi->mclk_strobe_mode_threshold &&
2488             (memory_clock <= pi->mclk_strobe_mode_threshold))
2489                 memory_level->StrobeEnable = 1;
2490
2491         if (pi->mem_gddr5) {
2492                 memory_level->StrobeRatio =
2493                         si_get_mclk_frequency_ratio(memory_clock, memory_level->StrobeEnable);
2494                 if (pi->mclk_edc_enable_threshold &&
2495                     (memory_clock > pi->mclk_edc_enable_threshold))
2496                         memory_level->EdcReadEnable = true;
2497
2498                 if (pi->mclk_edc_wr_enable_threshold &&
2499                     (memory_clock > pi->mclk_edc_wr_enable_threshold))
2500                         memory_level->EdcWriteEnable = true;
2501
2502                 if (memory_level->StrobeEnable) {
2503                         if (si_get_mclk_frequency_ratio(memory_clock, true) >=
2504                             ((RREG32(MC_SEQ_MISC7) >> 16) & 0xf))
2505                                 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
2506                         else
2507                                 dll_state_on = ((RREG32(MC_SEQ_MISC6) >> 1) & 0x1) ? true : false;
2508                 } else {
2509                         dll_state_on = pi->dll_default_on;
2510                 }
2511         } else {
2512                 memory_level->StrobeRatio = si_get_ddr3_mclk_frequency_ratio(memory_clock);
2513                 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
2514         }
2515
2516         ret = ci_calculate_mclk_params(rdev, memory_clock, memory_level, memory_level->StrobeEnable, dll_state_on);
2517         if (ret)
2518                 return ret;
2519
2520         memory_level->MinVddc = cpu_to_be32(memory_level->MinVddc * VOLTAGE_SCALE);
2521         memory_level->MinVddcPhases = cpu_to_be32(memory_level->MinVddcPhases);
2522         memory_level->MinVddci = cpu_to_be32(memory_level->MinVddci * VOLTAGE_SCALE);
2523         memory_level->MinMvdd = cpu_to_be32(memory_level->MinMvdd * VOLTAGE_SCALE);
2524
2525         memory_level->MclkFrequency = cpu_to_be32(memory_level->MclkFrequency);
2526         memory_level->ActivityLevel = cpu_to_be16(memory_level->ActivityLevel);
2527         memory_level->MpllFuncCntl = cpu_to_be32(memory_level->MpllFuncCntl);
2528         memory_level->MpllFuncCntl_1 = cpu_to_be32(memory_level->MpllFuncCntl_1);
2529         memory_level->MpllFuncCntl_2 = cpu_to_be32(memory_level->MpllFuncCntl_2);
2530         memory_level->MpllAdFuncCntl = cpu_to_be32(memory_level->MpllAdFuncCntl);
2531         memory_level->MpllDqFuncCntl = cpu_to_be32(memory_level->MpllDqFuncCntl);
2532         memory_level->MclkPwrmgtCntl = cpu_to_be32(memory_level->MclkPwrmgtCntl);
2533         memory_level->DllCntl = cpu_to_be32(memory_level->DllCntl);
2534         memory_level->MpllSs1 = cpu_to_be32(memory_level->MpllSs1);
2535         memory_level->MpllSs2 = cpu_to_be32(memory_level->MpllSs2);
2536
2537         return 0;
2538 }
2539
2540 static int ci_populate_smc_acpi_level(struct radeon_device *rdev,
2541                                       SMU7_Discrete_DpmTable *table)
2542 {
2543         struct ci_power_info *pi = ci_get_pi(rdev);
2544         struct atom_clock_dividers dividers;
2545         SMU7_Discrete_VoltageLevel voltage_level;
2546         u32 spll_func_cntl = pi->clock_registers.cg_spll_func_cntl;
2547         u32 spll_func_cntl_2 = pi->clock_registers.cg_spll_func_cntl_2;
2548         u32 dll_cntl = pi->clock_registers.dll_cntl;
2549         u32 mclk_pwrmgt_cntl = pi->clock_registers.mclk_pwrmgt_cntl;
2550         int ret;
2551
2552         table->ACPILevel.Flags &= ~PPSMC_SWSTATE_FLAG_DC;
2553
2554         if (pi->acpi_vddc)
2555                 table->ACPILevel.MinVddc = cpu_to_be32(pi->acpi_vddc * VOLTAGE_SCALE);
2556         else
2557                 table->ACPILevel.MinVddc = cpu_to_be32(pi->min_vddc_in_pp_table * VOLTAGE_SCALE);
2558
2559         table->ACPILevel.MinVddcPhases = pi->vddc_phase_shed_control ? 0 : 1;
2560
2561         table->ACPILevel.SclkFrequency = rdev->clock.spll.reference_freq;
2562
2563         ret = radeon_atom_get_clock_dividers(rdev,
2564                                              COMPUTE_GPUCLK_INPUT_FLAG_SCLK,
2565                                              table->ACPILevel.SclkFrequency, false, &dividers);
2566         if (ret)
2567                 return ret;
2568
2569         table->ACPILevel.SclkDid = (u8)dividers.post_divider;
2570         table->ACPILevel.DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
2571         table->ACPILevel.DeepSleepDivId = 0;
2572
2573         spll_func_cntl &= ~SPLL_PWRON;
2574         spll_func_cntl |= SPLL_RESET;
2575
2576         spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK;
2577         spll_func_cntl_2 |= SCLK_MUX_SEL(4);
2578
2579         table->ACPILevel.CgSpllFuncCntl = spll_func_cntl;
2580         table->ACPILevel.CgSpllFuncCntl2 = spll_func_cntl_2;
2581         table->ACPILevel.CgSpllFuncCntl3 = pi->clock_registers.cg_spll_func_cntl_3;
2582         table->ACPILevel.CgSpllFuncCntl4 = pi->clock_registers.cg_spll_func_cntl_4;
2583         table->ACPILevel.SpllSpreadSpectrum = pi->clock_registers.cg_spll_spread_spectrum;
2584         table->ACPILevel.SpllSpreadSpectrum2 = pi->clock_registers.cg_spll_spread_spectrum_2;
2585         table->ACPILevel.CcPwrDynRm = 0;
2586         table->ACPILevel.CcPwrDynRm1 = 0;
2587
2588         table->ACPILevel.Flags = cpu_to_be32(table->ACPILevel.Flags);
2589         table->ACPILevel.MinVddcPhases = cpu_to_be32(table->ACPILevel.MinVddcPhases);
2590         table->ACPILevel.SclkFrequency = cpu_to_be32(table->ACPILevel.SclkFrequency);
2591         table->ACPILevel.CgSpllFuncCntl = cpu_to_be32(table->ACPILevel.CgSpllFuncCntl);
2592         table->ACPILevel.CgSpllFuncCntl2 = cpu_to_be32(table->ACPILevel.CgSpllFuncCntl2);
2593         table->ACPILevel.CgSpllFuncCntl3 = cpu_to_be32(table->ACPILevel.CgSpllFuncCntl3);
2594         table->ACPILevel.CgSpllFuncCntl4 = cpu_to_be32(table->ACPILevel.CgSpllFuncCntl4);
2595         table->ACPILevel.SpllSpreadSpectrum = cpu_to_be32(table->ACPILevel.SpllSpreadSpectrum);
2596         table->ACPILevel.SpllSpreadSpectrum2 = cpu_to_be32(table->ACPILevel.SpllSpreadSpectrum2);
2597         table->ACPILevel.CcPwrDynRm = cpu_to_be32(table->ACPILevel.CcPwrDynRm);
2598         table->ACPILevel.CcPwrDynRm1 = cpu_to_be32(table->ACPILevel.CcPwrDynRm1);
2599
2600         table->MemoryACPILevel.MinVddc = table->ACPILevel.MinVddc;
2601         table->MemoryACPILevel.MinVddcPhases = table->ACPILevel.MinVddcPhases;
2602
2603         if (pi->vddci_control != CISLANDS_VOLTAGE_CONTROL_NONE) {
2604                 if (pi->acpi_vddci)
2605                         table->MemoryACPILevel.MinVddci =
2606                                 cpu_to_be32(pi->acpi_vddci * VOLTAGE_SCALE);
2607                 else
2608                         table->MemoryACPILevel.MinVddci =
2609                                 cpu_to_be32(pi->min_vddci_in_pp_table * VOLTAGE_SCALE);
2610         }
2611
2612         if (ci_populate_mvdd_value(rdev, 0, &voltage_level))
2613                 table->MemoryACPILevel.MinMvdd = 0;
2614         else
2615                 table->MemoryACPILevel.MinMvdd =
2616                         cpu_to_be32(voltage_level.Voltage * VOLTAGE_SCALE);
2617
2618         mclk_pwrmgt_cntl |= MRDCK0_RESET | MRDCK1_RESET;
2619         mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB);
2620
2621         dll_cntl &= ~(MRDCK0_BYPASS | MRDCK1_BYPASS);
2622
2623         table->MemoryACPILevel.DllCntl = cpu_to_be32(dll_cntl);
2624         table->MemoryACPILevel.MclkPwrmgtCntl = cpu_to_be32(mclk_pwrmgt_cntl);
2625         table->MemoryACPILevel.MpllAdFuncCntl =
2626                 cpu_to_be32(pi->clock_registers.mpll_ad_func_cntl);
2627         table->MemoryACPILevel.MpllDqFuncCntl =
2628                 cpu_to_be32(pi->clock_registers.mpll_dq_func_cntl);
2629         table->MemoryACPILevel.MpllFuncCntl =
2630                 cpu_to_be32(pi->clock_registers.mpll_func_cntl);
2631         table->MemoryACPILevel.MpllFuncCntl_1 =
2632                 cpu_to_be32(pi->clock_registers.mpll_func_cntl_1);
2633         table->MemoryACPILevel.MpllFuncCntl_2 =
2634                 cpu_to_be32(pi->clock_registers.mpll_func_cntl_2);
2635         table->MemoryACPILevel.MpllSs1 = cpu_to_be32(pi->clock_registers.mpll_ss1);
2636         table->MemoryACPILevel.MpllSs2 = cpu_to_be32(pi->clock_registers.mpll_ss2);
2637
2638         table->MemoryACPILevel.EnabledForThrottle = 0;
2639         table->MemoryACPILevel.EnabledForActivity = 0;
2640         table->MemoryACPILevel.UpH = 0;
2641         table->MemoryACPILevel.DownH = 100;
2642         table->MemoryACPILevel.VoltageDownH = 0;
2643         table->MemoryACPILevel.ActivityLevel =
2644                 cpu_to_be16((u16)pi->mclk_activity_target);
2645
2646         table->MemoryACPILevel.StutterEnable = false;
2647         table->MemoryACPILevel.StrobeEnable = false;
2648         table->MemoryACPILevel.EdcReadEnable = false;
2649         table->MemoryACPILevel.EdcWriteEnable = false;
2650         table->MemoryACPILevel.RttEnable = false;
2651
2652         return 0;
2653 }
2654
2655
2656 static int ci_enable_ulv(struct radeon_device *rdev, bool enable)
2657 {
2658         struct ci_power_info *pi = ci_get_pi(rdev);
2659         struct ci_ulv_parm *ulv = &pi->ulv;
2660
2661         if (ulv->supported) {
2662                 if (enable)
2663                         return (ci_send_msg_to_smc(rdev, PPSMC_MSG_EnableULV) == PPSMC_Result_OK) ?
2664                                 0 : -EINVAL;
2665                 else
2666                         return (ci_send_msg_to_smc(rdev, PPSMC_MSG_DisableULV) == PPSMC_Result_OK) ?
2667                                 0 : -EINVAL;
2668         }
2669
2670         return 0;
2671 }
2672
2673 static int ci_populate_ulv_level(struct radeon_device *rdev,
2674                                  SMU7_Discrete_Ulv *state)
2675 {
2676         struct ci_power_info *pi = ci_get_pi(rdev);
2677         u16 ulv_voltage = rdev->pm.dpm.backbias_response_time;
2678
2679         state->CcPwrDynRm = 0;
2680         state->CcPwrDynRm1 = 0;
2681
2682         if (ulv_voltage == 0) {
2683                 pi->ulv.supported = false;
2684                 return 0;
2685         }
2686
2687         if (pi->voltage_control != CISLANDS_VOLTAGE_CONTROL_BY_SVID2) {
2688                 if (ulv_voltage > rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v)
2689                         state->VddcOffset = 0;
2690                 else
2691                         state->VddcOffset =
2692                                 rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v - ulv_voltage;
2693         } else {
2694                 if (ulv_voltage > rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v)
2695                         state->VddcOffsetVid = 0;
2696                 else
2697                         state->VddcOffsetVid = (u8)
2698                                 ((rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v - ulv_voltage) *
2699                                  VOLTAGE_VID_OFFSET_SCALE2 / VOLTAGE_VID_OFFSET_SCALE1);
2700         }
2701         state->VddcPhase = pi->vddc_phase_shed_control ? 0 : 1;
2702
2703         state->CcPwrDynRm = cpu_to_be32(state->CcPwrDynRm);
2704         state->CcPwrDynRm1 = cpu_to_be32(state->CcPwrDynRm1);
2705         state->VddcOffset = cpu_to_be16(state->VddcOffset);
2706
2707         return 0;
2708 }
2709
2710 static int ci_calculate_sclk_params(struct radeon_device *rdev,
2711                                     u32 engine_clock,
2712                                     SMU7_Discrete_GraphicsLevel *sclk)
2713 {
2714         struct ci_power_info *pi = ci_get_pi(rdev);
2715         struct atom_clock_dividers dividers;
2716         u32 spll_func_cntl_3 = pi->clock_registers.cg_spll_func_cntl_3;
2717         u32 spll_func_cntl_4 = pi->clock_registers.cg_spll_func_cntl_4;
2718         u32 cg_spll_spread_spectrum = pi->clock_registers.cg_spll_spread_spectrum;
2719         u32 cg_spll_spread_spectrum_2 = pi->clock_registers.cg_spll_spread_spectrum_2;
2720         u32 reference_clock = rdev->clock.spll.reference_freq;
2721         u32 reference_divider;
2722         u32 fbdiv;
2723         int ret;
2724
2725         ret = radeon_atom_get_clock_dividers(rdev,
2726                                              COMPUTE_GPUCLK_INPUT_FLAG_SCLK,
2727                                              engine_clock, false, &dividers);
2728         if (ret)
2729                 return ret;
2730
2731         reference_divider = 1 + dividers.ref_div;
2732         fbdiv = dividers.fb_div & 0x3FFFFFF;
2733
2734         spll_func_cntl_3 &= ~SPLL_FB_DIV_MASK;
2735         spll_func_cntl_3 |= SPLL_FB_DIV(fbdiv);
2736         spll_func_cntl_3 |= SPLL_DITHEN;
2737
2738         if (pi->caps_sclk_ss_support) {
2739                 struct radeon_atom_ss ss;
2740                 u32 vco_freq = engine_clock * dividers.post_div;
2741
2742                 if (radeon_atombios_get_asic_ss_info(rdev, &ss,
2743                                                      ASIC_INTERNAL_ENGINE_SS, vco_freq)) {
2744                         u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate);
2745                         u32 clk_v = 4 * ss.percentage * fbdiv / (clk_s * 10000);
2746
2747                         cg_spll_spread_spectrum &= ~CLK_S_MASK;
2748                         cg_spll_spread_spectrum |= CLK_S(clk_s);
2749                         cg_spll_spread_spectrum |= SSEN;
2750
2751                         cg_spll_spread_spectrum_2 &= ~CLK_V_MASK;
2752                         cg_spll_spread_spectrum_2 |= CLK_V(clk_v);
2753                 }
2754         }
2755
2756         sclk->SclkFrequency = engine_clock;
2757         sclk->CgSpllFuncCntl3 = spll_func_cntl_3;
2758         sclk->CgSpllFuncCntl4 = spll_func_cntl_4;
2759         sclk->SpllSpreadSpectrum = cg_spll_spread_spectrum;
2760         sclk->SpllSpreadSpectrum2  = cg_spll_spread_spectrum_2;
2761         sclk->SclkDid = (u8)dividers.post_divider;
2762
2763         return 0;
2764 }
2765
2766 static int ci_populate_single_graphic_level(struct radeon_device *rdev,
2767                                             u32 engine_clock,
2768                                             u16 sclk_activity_level_t,
2769                                             SMU7_Discrete_GraphicsLevel *graphic_level)
2770 {
2771         struct ci_power_info *pi = ci_get_pi(rdev);
2772         int ret;
2773
2774         ret = ci_calculate_sclk_params(rdev, engine_clock, graphic_level);
2775         if (ret)
2776                 return ret;
2777
2778         ret = ci_get_dependency_volt_by_clk(rdev,
2779                                             &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk,
2780                                             engine_clock, &graphic_level->MinVddc);
2781         if (ret)
2782                 return ret;
2783
2784         graphic_level->SclkFrequency = engine_clock;
2785
2786         graphic_level->Flags =  0;
2787         graphic_level->MinVddcPhases = 1;
2788
2789         if (pi->vddc_phase_shed_control)
2790                 ci_populate_phase_value_based_on_sclk(rdev,
2791                                                       &rdev->pm.dpm.dyn_state.phase_shedding_limits_table,
2792                                                       engine_clock,
2793                                                       &graphic_level->MinVddcPhases);
2794
2795         graphic_level->ActivityLevel = sclk_activity_level_t;
2796
2797         graphic_level->CcPwrDynRm = 0;
2798         graphic_level->CcPwrDynRm1 = 0;
2799         graphic_level->EnabledForActivity = 1;
2800         graphic_level->EnabledForThrottle = 1;
2801         graphic_level->UpH = 0;
2802         graphic_level->DownH = 0;
2803         graphic_level->VoltageDownH = 0;
2804         graphic_level->PowerThrottle = 0;
2805
2806         if (pi->caps_sclk_ds)
2807                 graphic_level->DeepSleepDivId = ci_get_sleep_divider_id_from_clock(rdev,
2808                                                                                    engine_clock,
2809                                                                                    CISLAND_MINIMUM_ENGINE_CLOCK);
2810
2811         graphic_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
2812
2813         graphic_level->Flags = cpu_to_be32(graphic_level->Flags);
2814         graphic_level->MinVddc = cpu_to_be32(graphic_level->MinVddc * VOLTAGE_SCALE);
2815         graphic_level->MinVddcPhases = cpu_to_be32(graphic_level->MinVddcPhases);
2816         graphic_level->SclkFrequency = cpu_to_be32(graphic_level->SclkFrequency);
2817         graphic_level->ActivityLevel = cpu_to_be16(graphic_level->ActivityLevel);
2818         graphic_level->CgSpllFuncCntl3 = cpu_to_be32(graphic_level->CgSpllFuncCntl3);
2819         graphic_level->CgSpllFuncCntl4 = cpu_to_be32(graphic_level->CgSpllFuncCntl4);
2820         graphic_level->SpllSpreadSpectrum = cpu_to_be32(graphic_level->SpllSpreadSpectrum);
2821         graphic_level->SpllSpreadSpectrum2 = cpu_to_be32(graphic_level->SpllSpreadSpectrum2);
2822         graphic_level->CcPwrDynRm = cpu_to_be32(graphic_level->CcPwrDynRm);
2823         graphic_level->CcPwrDynRm1 = cpu_to_be32(graphic_level->CcPwrDynRm1);
2824
2825         return 0;
2826 }
2827
2828 static int ci_populate_all_graphic_levels(struct radeon_device *rdev)
2829 {
2830         struct ci_power_info *pi = ci_get_pi(rdev);
2831         struct ci_dpm_table *dpm_table = &pi->dpm_table;
2832         u32 level_array_address = pi->dpm_table_start +
2833                 offsetof(SMU7_Discrete_DpmTable, GraphicsLevel);
2834         u32 level_array_size = sizeof(SMU7_Discrete_GraphicsLevel) *
2835                 SMU7_MAX_LEVELS_GRAPHICS;
2836         SMU7_Discrete_GraphicsLevel *levels = pi->smc_state_table.GraphicsLevel;
2837         u32 i, ret;
2838
2839         memset(levels, 0, level_array_size);
2840
2841         for (i = 0; i < dpm_table->sclk_table.count; i++) {
2842                 ret = ci_populate_single_graphic_level(rdev,
2843                                                        dpm_table->sclk_table.dpm_levels[i].value,
2844                                                        (u16)pi->activity_target[i],
2845                                                        &pi->smc_state_table.GraphicsLevel[i]);
2846                 if (ret)
2847                         return ret;
2848                 if (i == (dpm_table->sclk_table.count - 1))
2849                         pi->smc_state_table.GraphicsLevel[i].DisplayWatermark =
2850                                 PPSMC_DISPLAY_WATERMARK_HIGH;
2851         }
2852
2853         pi->smc_state_table.GraphicsDpmLevelCount = (u8)dpm_table->sclk_table.count;
2854         pi->dpm_level_enable_mask.sclk_dpm_enable_mask =
2855                 ci_get_dpm_level_enable_mask_value(&dpm_table->sclk_table);
2856
2857         ret = ci_copy_bytes_to_smc(rdev, level_array_address,
2858                                    (u8 *)levels, level_array_size,
2859                                    pi->sram_end);
2860         if (ret)
2861                 return ret;
2862
2863         return 0;
2864 }
2865
2866 static int ci_populate_ulv_state(struct radeon_device *rdev,
2867                                  SMU7_Discrete_Ulv *ulv_level)
2868 {
2869         return ci_populate_ulv_level(rdev, ulv_level);
2870 }
2871
2872 static int ci_populate_all_memory_levels(struct radeon_device *rdev)
2873 {
2874         struct ci_power_info *pi = ci_get_pi(rdev);
2875         struct ci_dpm_table *dpm_table = &pi->dpm_table;
2876         u32 level_array_address = pi->dpm_table_start +
2877                 offsetof(SMU7_Discrete_DpmTable, MemoryLevel);
2878         u32 level_array_size = sizeof(SMU7_Discrete_MemoryLevel) *
2879                 SMU7_MAX_LEVELS_MEMORY;
2880         SMU7_Discrete_MemoryLevel *levels = pi->smc_state_table.MemoryLevel;
2881         u32 i, ret;
2882
2883         memset(levels, 0, level_array_size);
2884
2885         for (i = 0; i < dpm_table->mclk_table.count; i++) {
2886                 if (dpm_table->mclk_table.dpm_levels[i].value == 0)
2887                         return -EINVAL;
2888                 ret = ci_populate_single_memory_level(rdev,
2889                                                       dpm_table->mclk_table.dpm_levels[i].value,
2890                                                       &pi->smc_state_table.MemoryLevel[i]);
2891                 if (ret)
2892                         return ret;
2893         }
2894
2895         pi->smc_state_table.MemoryLevel[0].ActivityLevel = cpu_to_be16(0x1F);
2896
2897         pi->smc_state_table.MemoryDpmLevelCount = (u8)dpm_table->mclk_table.count;
2898         pi->dpm_level_enable_mask.mclk_dpm_enable_mask =
2899                 ci_get_dpm_level_enable_mask_value(&dpm_table->mclk_table);
2900
2901         pi->smc_state_table.MemoryLevel[dpm_table->mclk_table.count - 1].DisplayWatermark =
2902                 PPSMC_DISPLAY_WATERMARK_HIGH;
2903
2904         ret = ci_copy_bytes_to_smc(rdev, level_array_address,
2905                                    (u8 *)levels, level_array_size,
2906                                    pi->sram_end);
2907         if (ret)
2908                 return ret;
2909
2910         return 0;
2911 }
2912
2913 static void ci_reset_single_dpm_table(struct radeon_device *rdev,
2914                                       struct ci_single_dpm_table* dpm_table,
2915                                       u32 count)
2916 {
2917         u32 i;
2918
2919         dpm_table->count = count;
2920         for (i = 0; i < MAX_REGULAR_DPM_NUMBER; i++)
2921                 dpm_table->dpm_levels[i].enabled = false;
2922 }
2923
2924 static void ci_setup_pcie_table_entry(struct ci_single_dpm_table* dpm_table,
2925                                       u32 index, u32 pcie_gen, u32 pcie_lanes)
2926 {
2927         dpm_table->dpm_levels[index].value = pcie_gen;
2928         dpm_table->dpm_levels[index].param1 = pcie_lanes;
2929         dpm_table->dpm_levels[index].enabled = true;
2930 }
2931
2932 static int ci_setup_default_pcie_tables(struct radeon_device *rdev)
2933 {
2934         struct ci_power_info *pi = ci_get_pi(rdev);
2935
2936         if (!pi->use_pcie_performance_levels && !pi->use_pcie_powersaving_levels)
2937                 return -EINVAL;
2938
2939         if (pi->use_pcie_performance_levels && !pi->use_pcie_powersaving_levels) {
2940                 pi->pcie_gen_powersaving = pi->pcie_gen_performance;
2941                 pi->pcie_lane_powersaving = pi->pcie_lane_performance;
2942         } else if (!pi->use_pcie_performance_levels && pi->use_pcie_powersaving_levels) {
2943                 pi->pcie_gen_performance = pi->pcie_gen_powersaving;
2944                 pi->pcie_lane_performance = pi->pcie_lane_powersaving;
2945         }
2946
2947         ci_reset_single_dpm_table(rdev,
2948                                   &pi->dpm_table.pcie_speed_table,
2949                                   SMU7_MAX_LEVELS_LINK);
2950
2951         ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 0,
2952                                   pi->pcie_gen_powersaving.min,
2953                                   pi->pcie_lane_powersaving.min);
2954         ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 1,
2955                                   pi->pcie_gen_performance.min,
2956                                   pi->pcie_lane_performance.min);
2957         ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 2,
2958                                   pi->pcie_gen_powersaving.min,
2959                                   pi->pcie_lane_powersaving.max);
2960         ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 3,
2961                                   pi->pcie_gen_performance.min,
2962                                   pi->pcie_lane_performance.max);
2963         ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 4,
2964                                   pi->pcie_gen_powersaving.max,
2965                                   pi->pcie_lane_powersaving.max);
2966         ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 5,
2967                                   pi->pcie_gen_performance.max,
2968                                   pi->pcie_lane_performance.max);
2969
2970         pi->dpm_table.pcie_speed_table.count = 6;
2971
2972         return 0;
2973 }
2974
2975 static int ci_setup_default_dpm_tables(struct radeon_device *rdev)
2976 {
2977         struct ci_power_info *pi = ci_get_pi(rdev);
2978         struct radeon_clock_voltage_dependency_table *allowed_sclk_vddc_table =
2979                 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
2980         struct radeon_clock_voltage_dependency_table *allowed_mclk_table =
2981                 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk;
2982         struct radeon_cac_leakage_table *std_voltage_table =
2983                 &rdev->pm.dpm.dyn_state.cac_leakage_table;
2984         u32 i;
2985
2986         if (allowed_sclk_vddc_table == NULL)
2987                 return -EINVAL;
2988         if (allowed_sclk_vddc_table->count < 1)
2989                 return -EINVAL;
2990         if (allowed_mclk_table == NULL)
2991                 return -EINVAL;
2992         if (allowed_mclk_table->count < 1)
2993                 return -EINVAL;
2994
2995         memset(&pi->dpm_table, 0, sizeof(struct ci_dpm_table));
2996
2997         ci_reset_single_dpm_table(rdev,
2998                                   &pi->dpm_table.sclk_table,
2999                                   SMU7_MAX_LEVELS_GRAPHICS);
3000         ci_reset_single_dpm_table(rdev,
3001                                   &pi->dpm_table.mclk_table,
3002                                   SMU7_MAX_LEVELS_MEMORY);
3003         ci_reset_single_dpm_table(rdev,
3004                                   &pi->dpm_table.vddc_table,
3005                                   SMU7_MAX_LEVELS_VDDC);
3006         ci_reset_single_dpm_table(rdev,
3007                                   &pi->dpm_table.vddci_table,
3008                                   SMU7_MAX_LEVELS_VDDCI);
3009         ci_reset_single_dpm_table(rdev,
3010                                   &pi->dpm_table.mvdd_table,
3011                                   SMU7_MAX_LEVELS_MVDD);
3012
3013         pi->dpm_table.sclk_table.count = 0;
3014         for (i = 0; i < allowed_sclk_vddc_table->count; i++) {
3015                 if ((i == 0) ||
3016                     (pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count-1].value !=
3017                      allowed_sclk_vddc_table->entries[i].clk)) {
3018                         pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count].value =
3019                                 allowed_sclk_vddc_table->entries[i].clk;
3020                         pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count].enabled = true;
3021                         pi->dpm_table.sclk_table.count++;
3022                 }
3023         }
3024
3025         pi->dpm_table.mclk_table.count = 0;
3026         for (i = 0; i < allowed_mclk_table->count; i++) {
3027                 if ((i==0) ||
3028                     (pi->dpm_table.mclk_table.dpm_levels[pi->dpm_table.mclk_table.count-1].value !=
3029                      allowed_mclk_table->entries[i].clk)) {
3030                         pi->dpm_table.mclk_table.dpm_levels[pi->dpm_table.mclk_table.count].value =
3031                                 allowed_mclk_table->entries[i].clk;
3032                         pi->dpm_table.mclk_table.dpm_levels[pi->dpm_table.mclk_table.count].enabled = true;
3033                         pi->dpm_table.mclk_table.count++;
3034                 }
3035         }
3036
3037         for (i = 0; i < allowed_sclk_vddc_table->count; i++) {
3038                 pi->dpm_table.vddc_table.dpm_levels[i].value =
3039                         allowed_sclk_vddc_table->entries[i].v;
3040                 pi->dpm_table.vddc_table.dpm_levels[i].param1 =
3041                         std_voltage_table->entries[i].leakage;
3042                 pi->dpm_table.vddc_table.dpm_levels[i].enabled = true;
3043         }
3044         pi->dpm_table.vddc_table.count = allowed_sclk_vddc_table->count;
3045
3046         allowed_mclk_table = &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk;
3047         if (allowed_mclk_table) {
3048                 for (i = 0; i < allowed_mclk_table->count; i++) {
3049                         pi->dpm_table.vddci_table.dpm_levels[i].value =
3050                                 allowed_mclk_table->entries[i].v;
3051                         pi->dpm_table.vddci_table.dpm_levels[i].enabled = true;
3052                 }
3053                 pi->dpm_table.vddci_table.count = allowed_mclk_table->count;
3054         }
3055
3056         allowed_mclk_table = &rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk;
3057         if (allowed_mclk_table) {
3058                 for (i = 0; i < allowed_mclk_table->count; i++) {
3059                         pi->dpm_table.mvdd_table.dpm_levels[i].value =
3060                                 allowed_mclk_table->entries[i].v;
3061                         pi->dpm_table.mvdd_table.dpm_levels[i].enabled = true;
3062                 }
3063                 pi->dpm_table.mvdd_table.count = allowed_mclk_table->count;
3064         }
3065
3066         ci_setup_default_pcie_tables(rdev);
3067
3068         return 0;
3069 }
3070
3071 static int ci_find_boot_level(struct ci_single_dpm_table *table,
3072                               u32 value, u32 *boot_level)
3073 {
3074         u32 i;
3075         int ret = -EINVAL;
3076
3077         for(i = 0; i < table->count; i++) {
3078                 if (value == table->dpm_levels[i].value) {
3079                         *boot_level = i;
3080                         ret = 0;
3081                 }
3082         }
3083
3084         return ret;
3085 }
3086
3087 static int ci_init_smc_table(struct radeon_device *rdev)
3088 {
3089         struct ci_power_info *pi = ci_get_pi(rdev);
3090         struct ci_ulv_parm *ulv = &pi->ulv;
3091         struct radeon_ps *radeon_boot_state = rdev->pm.dpm.boot_ps;
3092         SMU7_Discrete_DpmTable *table = &pi->smc_state_table;
3093         int ret;
3094
3095         ret = ci_setup_default_dpm_tables(rdev);
3096         if (ret)
3097                 return ret;
3098
3099         if (pi->voltage_control != CISLANDS_VOLTAGE_CONTROL_NONE)
3100                 ci_populate_smc_voltage_tables(rdev, table);
3101
3102         ci_init_fps_limits(rdev);
3103
3104         if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC)
3105                 table->SystemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC;
3106
3107         if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC)
3108                 table->SystemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;
3109
3110         if (pi->mem_gddr5)
3111                 table->SystemFlags |= PPSMC_SYSTEMFLAG_GDDR5;
3112
3113         if (ulv->supported) {
3114                 ret = ci_populate_ulv_state(rdev, &pi->smc_state_table.Ulv);
3115                 if (ret)
3116                         return ret;
3117                 WREG32_SMC(CG_ULV_PARAMETER, ulv->cg_ulv_parameter);
3118         }
3119
3120         ret = ci_populate_all_graphic_levels(rdev);
3121         if (ret)
3122                 return ret;
3123
3124         ret = ci_populate_all_memory_levels(rdev);
3125         if (ret)
3126                 return ret;
3127
3128         ci_populate_smc_link_level(rdev, table);
3129
3130         ret = ci_populate_smc_acpi_level(rdev, table);
3131         if (ret)
3132                 return ret;
3133
3134         ret = ci_populate_smc_vce_level(rdev, table);
3135         if (ret)
3136                 return ret;
3137
3138         ret = ci_populate_smc_acp_level(rdev, table);
3139         if (ret)
3140                 return ret;
3141
3142         ret = ci_populate_smc_samu_level(rdev, table);
3143         if (ret)
3144                 return ret;
3145
3146         ret = ci_do_program_memory_timing_parameters(rdev);
3147         if (ret)
3148                 return ret;
3149
3150         ret = ci_populate_smc_uvd_level(rdev, table);
3151         if (ret)
3152                 return ret;
3153
3154         table->UvdBootLevel  = 0;
3155         table->VceBootLevel  = 0;
3156         table->AcpBootLevel  = 0;
3157         table->SamuBootLevel  = 0;
3158         table->GraphicsBootLevel  = 0;
3159         table->MemoryBootLevel  = 0;
3160
3161         ret = ci_find_boot_level(&pi->dpm_table.sclk_table,
3162                                  pi->vbios_boot_state.sclk_bootup_value,
3163                                  (u32 *)&pi->smc_state_table.GraphicsBootLevel);
3164
3165         ret = ci_find_boot_level(&pi->dpm_table.mclk_table,
3166                                  pi->vbios_boot_state.mclk_bootup_value,
3167                                  (u32 *)&pi->smc_state_table.MemoryBootLevel);
3168
3169         table->BootVddc = pi->vbios_boot_state.vddc_bootup_value;
3170         table->BootVddci = pi->vbios_boot_state.vddci_bootup_value;
3171         table->BootMVdd = pi->vbios_boot_state.mvdd_bootup_value;
3172
3173         ci_populate_smc_initial_state(rdev, radeon_boot_state);
3174
3175         ret = ci_populate_bapm_parameters_in_dpm_table(rdev);
3176         if (ret)
3177                 return ret;
3178
3179         table->UVDInterval = 1;
3180         table->VCEInterval = 1;
3181         table->ACPInterval = 1;
3182         table->SAMUInterval = 1;
3183         table->GraphicsVoltageChangeEnable = 1;
3184         table->GraphicsThermThrottleEnable = 1;
3185         table->GraphicsInterval = 1;
3186         table->VoltageInterval = 1;
3187         table->ThermalInterval = 1;
3188         table->TemperatureLimitHigh = (u16)((pi->thermal_temp_setting.temperature_high *
3189                                              CISLANDS_Q88_FORMAT_CONVERSION_UNIT) / 1000);
3190         table->TemperatureLimitLow = (u16)((pi->thermal_temp_setting.temperature_low *
3191                                             CISLANDS_Q88_FORMAT_CONVERSION_UNIT) / 1000);
3192         table->MemoryVoltageChangeEnable = 1;
3193         table->MemoryInterval = 1;
3194         table->VoltageResponseTime = 0;
3195         table->VddcVddciDelta = 4000;
3196         table->PhaseResponseTime = 0;
3197         table->MemoryThermThrottleEnable = 1;
3198         table->PCIeBootLinkLevel = 0;
3199         table->PCIeGenInterval = 1;
3200         if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2)
3201                 table->SVI2Enable  = 1;
3202         else
3203                 table->SVI2Enable  = 0;
3204
3205         table->ThermGpio = 17;
3206         table->SclkStepSize = 0x4000;
3207
3208         table->SystemFlags = cpu_to_be32(table->SystemFlags);
3209         table->SmioMaskVddcVid = cpu_to_be32(table->SmioMaskVddcVid);
3210         table->SmioMaskVddcPhase = cpu_to_be32(table->SmioMaskVddcPhase);
3211         table->SmioMaskVddciVid = cpu_to_be32(table->SmioMaskVddciVid);
3212         table->SmioMaskMvddVid = cpu_to_be32(table->SmioMaskMvddVid);
3213         table->SclkStepSize = cpu_to_be32(table->SclkStepSize);
3214         table->TemperatureLimitHigh = cpu_to_be16(table->TemperatureLimitHigh);
3215         table->TemperatureLimitLow = cpu_to_be16(table->TemperatureLimitLow);
3216         table->VddcVddciDelta = cpu_to_be16(table->VddcVddciDelta);
3217         table->VoltageResponseTime = cpu_to_be16(table->VoltageResponseTime);
3218         table->PhaseResponseTime = cpu_to_be16(table->PhaseResponseTime);
3219         table->BootVddc = cpu_to_be16(table->BootVddc * VOLTAGE_SCALE);
3220         table->BootVddci = cpu_to_be16(table->BootVddci * VOLTAGE_SCALE);
3221         table->BootMVdd = cpu_to_be16(table->BootMVdd * VOLTAGE_SCALE);
3222
3223         ret = ci_copy_bytes_to_smc(rdev,
3224                                    pi->dpm_table_start +
3225                                    offsetof(SMU7_Discrete_DpmTable, SystemFlags),
3226                                    (u8 *)&table->SystemFlags,
3227                                    sizeof(SMU7_Discrete_DpmTable) - 3 * sizeof(SMU7_PIDController),
3228                                    pi->sram_end);
3229         if (ret)
3230                 return ret;
3231
3232         return 0;
3233 }
3234
3235 static void ci_trim_single_dpm_states(struct radeon_device *rdev,
3236                                       struct ci_single_dpm_table *dpm_table,
3237                                       u32 low_limit, u32 high_limit)
3238 {
3239         u32 i;
3240
3241         for (i = 0; i < dpm_table->count; i++) {
3242                 if ((dpm_table->dpm_levels[i].value < low_limit) ||
3243                     (dpm_table->dpm_levels[i].value > high_limit))
3244                         dpm_table->dpm_levels[i].enabled = false;
3245                 else
3246                         dpm_table->dpm_levels[i].enabled = true;
3247         }
3248 }
3249
3250 static void ci_trim_pcie_dpm_states(struct radeon_device *rdev,
3251                                     u32 speed_low, u32 lanes_low,
3252                                     u32 speed_high, u32 lanes_high)
3253 {
3254         struct ci_power_info *pi = ci_get_pi(rdev);
3255         struct ci_single_dpm_table *pcie_table = &pi->dpm_table.pcie_speed_table;
3256         u32 i, j;
3257
3258         for (i = 0; i < pcie_table->count; i++) {
3259                 if ((pcie_table->dpm_levels[i].value < speed_low) ||
3260                     (pcie_table->dpm_levels[i].param1 < lanes_low) ||
3261                     (pcie_table->dpm_levels[i].value > speed_high) ||
3262                     (pcie_table->dpm_levels[i].param1 > lanes_high))
3263                         pcie_table->dpm_levels[i].enabled = false;
3264                 else
3265                         pcie_table->dpm_levels[i].enabled = true;
3266         }
3267
3268         for (i = 0; i < pcie_table->count; i++) {
3269                 if (pcie_table->dpm_levels[i].enabled) {
3270                         for (j = i + 1; j < pcie_table->count; j++) {
3271                                 if (pcie_table->dpm_levels[j].enabled) {
3272                                         if ((pcie_table->dpm_levels[i].value == pcie_table->dpm_levels[j].value) &&
3273                                             (pcie_table->dpm_levels[i].param1 == pcie_table->dpm_levels[j].param1))
3274                                                 pcie_table->dpm_levels[j].enabled = false;
3275                                 }
3276                         }
3277                 }
3278         }
3279 }
3280
3281 static int ci_trim_dpm_states(struct radeon_device *rdev,
3282                               struct radeon_ps *radeon_state)
3283 {
3284         struct ci_ps *state = ci_get_ps(radeon_state);
3285         struct ci_power_info *pi = ci_get_pi(rdev);
3286         u32 high_limit_count;
3287
3288         if (state->performance_level_count < 1)
3289                 return -EINVAL;
3290
3291         if (state->performance_level_count == 1)
3292                 high_limit_count = 0;
3293         else
3294                 high_limit_count = 1;
3295
3296         ci_trim_single_dpm_states(rdev,
3297                                   &pi->dpm_table.sclk_table,
3298                                   state->performance_levels[0].sclk,
3299                                   state->performance_levels[high_limit_count].sclk);
3300
3301         ci_trim_single_dpm_states(rdev,
3302                                   &pi->dpm_table.mclk_table,
3303                                   state->performance_levels[0].mclk,
3304                                   state->performance_levels[high_limit_count].mclk);
3305
3306         ci_trim_pcie_dpm_states(rdev,
3307                                 state->performance_levels[0].pcie_gen,
3308                                 state->performance_levels[0].pcie_lane,
3309                                 state->performance_levels[high_limit_count].pcie_gen,
3310                                 state->performance_levels[high_limit_count].pcie_lane);
3311
3312         return 0;
3313 }
3314
3315 static int ci_apply_disp_minimum_voltage_request(struct radeon_device *rdev)
3316 {
3317         struct radeon_clock_voltage_dependency_table *disp_voltage_table =
3318                 &rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk;
3319         struct radeon_clock_voltage_dependency_table *vddc_table =
3320                 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
3321         u32 requested_voltage = 0;
3322         u32 i;
3323
3324         if (disp_voltage_table == NULL)
3325                 return -EINVAL;
3326         if (!disp_voltage_table->count)
3327                 return -EINVAL;
3328
3329         for (i = 0; i < disp_voltage_table->count; i++) {
3330                 if (rdev->clock.current_dispclk == disp_voltage_table->entries[i].clk)
3331                         requested_voltage = disp_voltage_table->entries[i].v;
3332         }
3333
3334         for (i = 0; i < vddc_table->count; i++) {
3335                 if (requested_voltage <= vddc_table->entries[i].v) {
3336                         requested_voltage = vddc_table->entries[i].v;
3337                         return (ci_send_msg_to_smc_with_parameter(rdev,
3338                                                                   PPSMC_MSG_VddC_Request,
3339                                                                   requested_voltage * VOLTAGE_SCALE) == PPSMC_Result_OK) ?
3340                                 0 : -EINVAL;
3341                 }
3342         }
3343
3344         return -EINVAL;
3345 }
3346
3347 static int ci_upload_dpm_level_enable_mask(struct radeon_device *rdev)
3348 {
3349         struct ci_power_info *pi = ci_get_pi(rdev);
3350         PPSMC_Result result;
3351
3352         if (!pi->sclk_dpm_key_disabled) {
3353                 if (pi->dpm_level_enable_mask.sclk_dpm_enable_mask) {
3354                         result = ci_send_msg_to_smc_with_parameter(rdev,
3355                                                                    PPSMC_MSG_SCLKDPM_SetEnabledMask,
3356                                                                    pi->dpm_level_enable_mask.sclk_dpm_enable_mask);
3357                         if (result != PPSMC_Result_OK)
3358                                 return -EINVAL;
3359                 }
3360         }
3361
3362         if (!pi->mclk_dpm_key_disabled) {
3363                 if (pi->dpm_level_enable_mask.mclk_dpm_enable_mask) {
3364                         result = ci_send_msg_to_smc_with_parameter(rdev,
3365                                                                    PPSMC_MSG_MCLKDPM_SetEnabledMask,
3366                                                                    pi->dpm_level_enable_mask.mclk_dpm_enable_mask);
3367                         if (result != PPSMC_Result_OK)
3368                                 return -EINVAL;
3369                 }
3370         }
3371
3372         if (!pi->pcie_dpm_key_disabled) {
3373                 if (pi->dpm_level_enable_mask.pcie_dpm_enable_mask) {
3374                         result = ci_send_msg_to_smc_with_parameter(rdev,
3375                                                                    PPSMC_MSG_PCIeDPM_SetEnabledMask,
3376                                                                    pi->dpm_level_enable_mask.pcie_dpm_enable_mask);
3377                         if (result != PPSMC_Result_OK)
3378                                 return -EINVAL;
3379                 }
3380         }
3381
3382         ci_apply_disp_minimum_voltage_request(rdev);
3383
3384         return 0;
3385 }
3386
3387 static void ci_find_dpm_states_clocks_in_dpm_table(struct radeon_device *rdev,
3388                                                    struct radeon_ps *radeon_state)
3389 {
3390         struct ci_power_info *pi = ci_get_pi(rdev);
3391         struct ci_ps *state = ci_get_ps(radeon_state);
3392         struct ci_single_dpm_table *sclk_table = &pi->dpm_table.sclk_table;
3393         u32 sclk = state->performance_levels[state->performance_level_count-1].sclk;
3394         struct ci_single_dpm_table *mclk_table = &pi->dpm_table.mclk_table;
3395         u32 mclk = state->performance_levels[state->performance_level_count-1].mclk;
3396         u32 i;
3397
3398         pi->need_update_smu7_dpm_table = 0;
3399
3400         for (i = 0; i < sclk_table->count; i++) {
3401                 if (sclk == sclk_table->dpm_levels[i].value)
3402                         break;
3403         }
3404
3405         if (i >= sclk_table->count) {
3406                 pi->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_SCLK;
3407         } else {
3408                 /* XXX check display min clock requirements */
3409                 if (0 != CISLAND_MINIMUM_ENGINE_CLOCK)
3410                         pi->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_SCLK;
3411         }
3412
3413         for (i = 0; i < mclk_table->count; i++) {
3414                 if (mclk == mclk_table->dpm_levels[i].value)
3415                         break;
3416         }
3417
3418         if (i >= mclk_table->count)
3419                 pi->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_MCLK;
3420
3421         if (rdev->pm.dpm.current_active_crtc_count !=
3422             rdev->pm.dpm.new_active_crtc_count)
3423                 pi->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_MCLK;
3424 }
3425
3426 static int ci_populate_and_upload_sclk_mclk_dpm_levels(struct radeon_device *rdev,
3427                                                        struct radeon_ps *radeon_state)
3428 {
3429         struct ci_power_info *pi = ci_get_pi(rdev);
3430         struct ci_ps *state = ci_get_ps(radeon_state);
3431         u32 sclk = state->performance_levels[state->performance_level_count-1].sclk;
3432         u32 mclk = state->performance_levels[state->performance_level_count-1].mclk;
3433         struct ci_dpm_table *dpm_table = &pi->dpm_table;
3434         int ret;
3435
3436         if (!pi->need_update_smu7_dpm_table)
3437                 return 0;
3438
3439         if (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_SCLK)
3440                 dpm_table->sclk_table.dpm_levels[dpm_table->sclk_table.count-1].value = sclk;
3441
3442         if (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)
3443                 dpm_table->mclk_table.dpm_levels[dpm_table->mclk_table.count-1].value = mclk;
3444
3445         if (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK)) {
3446                 ret = ci_populate_all_graphic_levels(rdev);
3447                 if (ret)
3448                         return ret;
3449         }
3450
3451         if (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_MCLK | DPMTABLE_UPDATE_MCLK)) {
3452                 ret = ci_populate_all_memory_levels(rdev);
3453                 if (ret)
3454                         return ret;
3455         }
3456
3457         return 0;
3458 }
3459
3460 static int ci_enable_uvd_dpm(struct radeon_device *rdev, bool enable)
3461 {
3462         struct ci_power_info *pi = ci_get_pi(rdev);
3463         const struct radeon_clock_and_voltage_limits *max_limits;
3464         int i;
3465
3466         if (rdev->pm.dpm.ac_power)
3467                 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
3468         else
3469                 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
3470
3471         if (enable) {
3472                 pi->dpm_level_enable_mask.uvd_dpm_enable_mask = 0;
3473
3474                 for (i = rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count - 1; i >= 0; i--) {
3475                         if (rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) {
3476                                 pi->dpm_level_enable_mask.uvd_dpm_enable_mask |= 1 << i;
3477
3478                                 if (!pi->caps_uvd_dpm)
3479                                         break;
3480                         }
3481                 }
3482
3483                 ci_send_msg_to_smc_with_parameter(rdev,
3484                                                   PPSMC_MSG_UVDDPM_SetEnabledMask,
3485                                                   pi->dpm_level_enable_mask.uvd_dpm_enable_mask);
3486
3487                 if (pi->last_mclk_dpm_enable_mask & 0x1) {
3488                         pi->uvd_enabled = true;
3489                         pi->dpm_level_enable_mask.mclk_dpm_enable_mask &= 0xFFFFFFFE;
3490                         ci_send_msg_to_smc_with_parameter(rdev,
3491                                                           PPSMC_MSG_MCLKDPM_SetEnabledMask,
3492                                                           pi->dpm_level_enable_mask.mclk_dpm_enable_mask);
3493                 }
3494         } else {
3495                 if (pi->last_mclk_dpm_enable_mask & 0x1) {
3496                         pi->uvd_enabled = false;
3497                         pi->dpm_level_enable_mask.mclk_dpm_enable_mask |= 1;
3498                         ci_send_msg_to_smc_with_parameter(rdev,
3499                                                           PPSMC_MSG_MCLKDPM_SetEnabledMask,
3500                                                           pi->dpm_level_enable_mask.mclk_dpm_enable_mask);
3501                 }
3502         }
3503
3504         return (ci_send_msg_to_smc(rdev, enable ?
3505                                    PPSMC_MSG_UVDDPM_Enable : PPSMC_MSG_UVDDPM_Disable) == PPSMC_Result_OK) ?
3506                 0 : -EINVAL;
3507 }
3508
3509 static int ci_enable_vce_dpm(struct radeon_device *rdev, bool enable)
3510 {
3511         struct ci_power_info *pi = ci_get_pi(rdev);
3512         const struct radeon_clock_and_voltage_limits *max_limits;
3513         int i;
3514
3515         if (rdev->pm.dpm.ac_power)
3516                 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
3517         else
3518                 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
3519
3520         if (enable) {
3521                 pi->dpm_level_enable_mask.vce_dpm_enable_mask = 0;
3522                 for (i = rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.count - 1; i >= 0; i--) {
3523                         if (rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) {
3524                                 pi->dpm_level_enable_mask.vce_dpm_enable_mask |= 1 << i;
3525
3526                                 if (!pi->caps_vce_dpm)
3527                                         break;
3528                         }
3529                 }
3530
3531                 ci_send_msg_to_smc_with_parameter(rdev,
3532                                                   PPSMC_MSG_VCEDPM_SetEnabledMask,
3533                                                   pi->dpm_level_enable_mask.vce_dpm_enable_mask);
3534         }
3535
3536         return (ci_send_msg_to_smc(rdev, enable ?
3537                                    PPSMC_MSG_VCEDPM_Enable : PPSMC_MSG_VCEDPM_Disable) == PPSMC_Result_OK) ?
3538                 0 : -EINVAL;
3539 }
3540
3541 #if 0
3542 static int ci_enable_samu_dpm(struct radeon_device *rdev, bool enable)
3543 {
3544         struct ci_power_info *pi = ci_get_pi(rdev);
3545         const struct radeon_clock_and_voltage_limits *max_limits;
3546         int i;
3547
3548         if (rdev->pm.dpm.ac_power)
3549                 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
3550         else
3551                 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
3552
3553         if (enable) {
3554                 pi->dpm_level_enable_mask.samu_dpm_enable_mask = 0;
3555                 for (i = rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.count - 1; i >= 0; i--) {
3556                         if (rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) {
3557                                 pi->dpm_level_enable_mask.samu_dpm_enable_mask |= 1 << i;
3558
3559                                 if (!pi->caps_samu_dpm)
3560                                         break;
3561                         }
3562                 }
3563
3564                 ci_send_msg_to_smc_with_parameter(rdev,
3565                                                   PPSMC_MSG_SAMUDPM_SetEnabledMask,
3566                                                   pi->dpm_level_enable_mask.samu_dpm_enable_mask);
3567         }
3568         return (ci_send_msg_to_smc(rdev, enable ?
3569                                    PPSMC_MSG_SAMUDPM_Enable : PPSMC_MSG_SAMUDPM_Disable) == PPSMC_Result_OK) ?
3570                 0 : -EINVAL;
3571 }
3572
3573 static int ci_enable_acp_dpm(struct radeon_device *rdev, bool enable)
3574 {
3575         struct ci_power_info *pi = ci_get_pi(rdev);
3576         const struct radeon_clock_and_voltage_limits *max_limits;
3577         int i;
3578
3579         if (rdev->pm.dpm.ac_power)
3580                 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
3581         else
3582                 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
3583
3584         if (enable) {
3585                 pi->dpm_level_enable_mask.acp_dpm_enable_mask = 0;
3586                 for (i = rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.count - 1; i >= 0; i--) {
3587                         if (rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) {
3588                                 pi->dpm_level_enable_mask.acp_dpm_enable_mask |= 1 << i;
3589
3590                                 if (!pi->caps_acp_dpm)
3591                                         break;
3592                         }
3593                 }
3594
3595                 ci_send_msg_to_smc_with_parameter(rdev,
3596                                                   PPSMC_MSG_ACPDPM_SetEnabledMask,
3597                                                   pi->dpm_level_enable_mask.acp_dpm_enable_mask);
3598         }
3599
3600         return (ci_send_msg_to_smc(rdev, enable ?
3601                                    PPSMC_MSG_ACPDPM_Enable : PPSMC_MSG_ACPDPM_Disable) == PPSMC_Result_OK) ?
3602                 0 : -EINVAL;
3603 }
3604 #endif
3605
3606 static int ci_update_uvd_dpm(struct radeon_device *rdev, bool gate)
3607 {
3608         struct ci_power_info *pi = ci_get_pi(rdev);
3609         u32 tmp;
3610
3611         if (!gate) {
3612                 if (pi->caps_uvd_dpm ||
3613                     (rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count <= 0))
3614                         pi->smc_state_table.UvdBootLevel = 0;
3615                 else
3616                         pi->smc_state_table.UvdBootLevel =
3617                                 rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count - 1;
3618
3619                 tmp = RREG32_SMC(DPM_TABLE_475);
3620                 tmp &= ~UvdBootLevel_MASK;
3621                 tmp |= UvdBootLevel(pi->smc_state_table.UvdBootLevel);
3622                 WREG32_SMC(DPM_TABLE_475, tmp);
3623         }
3624
3625         return ci_enable_uvd_dpm(rdev, !gate);
3626 }
3627
3628 static u8 ci_get_vce_boot_level(struct radeon_device *rdev)
3629 {
3630         u8 i;
3631         u32 min_evclk = 30000; /* ??? */
3632         struct radeon_vce_clock_voltage_dependency_table *table =
3633                 &rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
3634
3635         for (i = 0; i < table->count; i++) {
3636                 if (table->entries[i].evclk >= min_evclk)
3637                         return i;
3638         }
3639
3640         return table->count - 1;
3641 }
3642
3643 static int ci_update_vce_dpm(struct radeon_device *rdev,
3644                              struct radeon_ps *radeon_new_state,
3645                              struct radeon_ps *radeon_current_state)
3646 {
3647         struct ci_power_info *pi = ci_get_pi(rdev);
3648         int ret = 0;
3649         u32 tmp;
3650
3651         if (radeon_current_state->evclk != radeon_new_state->evclk) {
3652                 if (radeon_new_state->evclk) {
3653                         /* turn the clocks on when encoding */
3654                         cik_update_cg(rdev, RADEON_CG_BLOCK_VCE, false);
3655
3656                         pi->smc_state_table.VceBootLevel = ci_get_vce_boot_level(rdev);
3657                         tmp = RREG32_SMC(DPM_TABLE_475);
3658                         tmp &= ~VceBootLevel_MASK;
3659                         tmp |= VceBootLevel(pi->smc_state_table.VceBootLevel);
3660                         WREG32_SMC(DPM_TABLE_475, tmp);
3661
3662                         ret = ci_enable_vce_dpm(rdev, true);
3663                 } else {
3664                         /* turn the clocks off when not encoding */
3665                         cik_update_cg(rdev, RADEON_CG_BLOCK_VCE, true);
3666
3667                         ret = ci_enable_vce_dpm(rdev, false);
3668                 }
3669         }
3670         return ret;
3671 }
3672
3673 #if 0
3674 static int ci_update_samu_dpm(struct radeon_device *rdev, bool gate)
3675 {
3676         return ci_enable_samu_dpm(rdev, gate);
3677 }
3678
3679 static int ci_update_acp_dpm(struct radeon_device *rdev, bool gate)
3680 {
3681         struct ci_power_info *pi = ci_get_pi(rdev);
3682         u32 tmp;
3683
3684         if (!gate) {
3685                 pi->smc_state_table.AcpBootLevel = 0;
3686
3687                 tmp = RREG32_SMC(DPM_TABLE_475);
3688                 tmp &= ~AcpBootLevel_MASK;
3689                 tmp |= AcpBootLevel(pi->smc_state_table.AcpBootLevel);
3690                 WREG32_SMC(DPM_TABLE_475, tmp);
3691         }
3692
3693         return ci_enable_acp_dpm(rdev, !gate);
3694 }
3695 #endif
3696
3697 static int ci_generate_dpm_level_enable_mask(struct radeon_device *rdev,
3698                                              struct radeon_ps *radeon_state)
3699 {
3700         struct ci_power_info *pi = ci_get_pi(rdev);
3701         int ret;
3702
3703         ret = ci_trim_dpm_states(rdev, radeon_state);
3704         if (ret)
3705                 return ret;
3706
3707         pi->dpm_level_enable_mask.sclk_dpm_enable_mask =
3708                 ci_get_dpm_level_enable_mask_value(&pi->dpm_table.sclk_table);
3709         pi->dpm_level_enable_mask.mclk_dpm_enable_mask =
3710                 ci_get_dpm_level_enable_mask_value(&pi->dpm_table.mclk_table);
3711         pi->last_mclk_dpm_enable_mask =
3712                 pi->dpm_level_enable_mask.mclk_dpm_enable_mask;
3713         if (pi->uvd_enabled) {
3714                 if (pi->dpm_level_enable_mask.mclk_dpm_enable_mask & 1)
3715                         pi->dpm_level_enable_mask.mclk_dpm_enable_mask &= 0xFFFFFFFE;
3716         }
3717         pi->dpm_level_enable_mask.pcie_dpm_enable_mask =
3718                 ci_get_dpm_level_enable_mask_value(&pi->dpm_table.pcie_speed_table);
3719
3720         return 0;
3721 }
3722
3723 static u32 ci_get_lowest_enabled_level(struct radeon_device *rdev,
3724                                        u32 level_mask)
3725 {
3726         u32 level = 0;
3727
3728         while ((level_mask & (1 << level)) == 0)
3729                 level++;
3730
3731         return level;
3732 }
3733
3734
3735 int ci_dpm_force_performance_level(struct radeon_device *rdev,
3736                                    enum radeon_dpm_forced_level level)
3737 {
3738         struct ci_power_info *pi = ci_get_pi(rdev);
3739         PPSMC_Result smc_result;
3740         u32 tmp, levels, i;
3741         int ret;
3742
3743         if (level == RADEON_DPM_FORCED_LEVEL_HIGH) {
3744                 if ((!pi->sclk_dpm_key_disabled) &&
3745                     pi->dpm_level_enable_mask.sclk_dpm_enable_mask) {
3746                         levels = 0;
3747                         tmp = pi->dpm_level_enable_mask.sclk_dpm_enable_mask;
3748                         while (tmp >>= 1)
3749                                 levels++;
3750                         if (levels) {
3751                                 ret = ci_dpm_force_state_sclk(rdev, levels);
3752                                 if (ret)
3753                                         return ret;
3754                                 for (i = 0; i < rdev->usec_timeout; i++) {
3755                                         tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX) &
3756                                                CURR_SCLK_INDEX_MASK) >> CURR_SCLK_INDEX_SHIFT;
3757                                         if (tmp == levels)
3758                                                 break;
3759                                         udelay(1);
3760                                 }
3761                         }
3762                 }
3763                 if ((!pi->mclk_dpm_key_disabled) &&
3764                     pi->dpm_level_enable_mask.mclk_dpm_enable_mask) {
3765                         levels = 0;
3766                         tmp = pi->dpm_level_enable_mask.mclk_dpm_enable_mask;
3767                         while (tmp >>= 1)
3768                                 levels++;
3769                         if (levels) {
3770                                 ret = ci_dpm_force_state_mclk(rdev, levels);
3771                                 if (ret)
3772                                         return ret;
3773                                 for (i = 0; i < rdev->usec_timeout; i++) {
3774                                         tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX) &
3775                                                CURR_MCLK_INDEX_MASK) >> CURR_MCLK_INDEX_SHIFT;
3776                                         if (tmp == levels)
3777                                                 break;
3778                                         udelay(1);
3779                                 }
3780                         }
3781                 }
3782                 if ((!pi->pcie_dpm_key_disabled) &&
3783                     pi->dpm_level_enable_mask.pcie_dpm_enable_mask) {
3784                         levels = 0;
3785                         tmp = pi->dpm_level_enable_mask.pcie_dpm_enable_mask;
3786                         while (tmp >>= 1)
3787                                 levels++;
3788                         if (levels) {
3789                                 ret = ci_dpm_force_state_pcie(rdev, level);
3790                                 if (ret)
3791                                         return ret;
3792                                 for (i = 0; i < rdev->usec_timeout; i++) {
3793                                         tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX_1) &
3794                                                CURR_PCIE_INDEX_MASK) >> CURR_PCIE_INDEX_SHIFT;
3795                                         if (tmp == levels)
3796                                                 break;
3797                                         udelay(1);
3798                                 }
3799                         }
3800                 }
3801         } else if (level == RADEON_DPM_FORCED_LEVEL_LOW) {
3802                 if ((!pi->sclk_dpm_key_disabled) &&
3803                     pi->dpm_level_enable_mask.sclk_dpm_enable_mask) {
3804                         levels = ci_get_lowest_enabled_level(rdev,
3805                                                              pi->dpm_level_enable_mask.sclk_dpm_enable_mask);
3806                         ret = ci_dpm_force_state_sclk(rdev, levels);
3807                         if (ret)
3808                                 return ret;
3809                         for (i = 0; i < rdev->usec_timeout; i++) {
3810                                 tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX) &
3811                                        CURR_SCLK_INDEX_MASK) >> CURR_SCLK_INDEX_SHIFT;
3812                                 if (tmp == levels)
3813                                         break;
3814                                 udelay(1);
3815                         }
3816                 }
3817                 if ((!pi->mclk_dpm_key_disabled) &&
3818                     pi->dpm_level_enable_mask.mclk_dpm_enable_mask) {
3819                         levels = ci_get_lowest_enabled_level(rdev,
3820                                                              pi->dpm_level_enable_mask.mclk_dpm_enable_mask);
3821                         ret = ci_dpm_force_state_mclk(rdev, levels);
3822                         if (ret)
3823                                 return ret;
3824                         for (i = 0; i < rdev->usec_timeout; i++) {
3825                                 tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX) &
3826                                        CURR_MCLK_INDEX_MASK) >> CURR_MCLK_INDEX_SHIFT;
3827                                 if (tmp == levels)
3828                                         break;
3829                                 udelay(1);
3830                         }
3831                 }
3832                 if ((!pi->pcie_dpm_key_disabled) &&
3833                     pi->dpm_level_enable_mask.pcie_dpm_enable_mask) {
3834                         levels = ci_get_lowest_enabled_level(rdev,
3835                                                              pi->dpm_level_enable_mask.pcie_dpm_enable_mask);
3836                         ret = ci_dpm_force_state_pcie(rdev, levels);
3837                         if (ret)
3838                                 return ret;
3839                         for (i = 0; i < rdev->usec_timeout; i++) {
3840                                 tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX_1) &
3841                                        CURR_PCIE_INDEX_MASK) >> CURR_PCIE_INDEX_SHIFT;
3842                                 if (tmp == levels)
3843                                         break;
3844                                 udelay(1);
3845                         }
3846                 }
3847         } else if (level == RADEON_DPM_FORCED_LEVEL_AUTO) {
3848                 if (!pi->sclk_dpm_key_disabled) {
3849                         smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_NoForcedLevel);
3850                         if (smc_result != PPSMC_Result_OK)
3851                                 return -EINVAL;
3852                 }
3853                 if (!pi->mclk_dpm_key_disabled) {
3854                         smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_MCLKDPM_NoForcedLevel);
3855                         if (smc_result != PPSMC_Result_OK)
3856                                 return -EINVAL;
3857                 }
3858                 if (!pi->pcie_dpm_key_disabled) {
3859                         smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_PCIeDPM_UnForceLevel);
3860                         if (smc_result != PPSMC_Result_OK)
3861                                 return -EINVAL;
3862                 }
3863         }
3864
3865         rdev->pm.dpm.forced_level = level;
3866
3867         return 0;
3868 }
3869
3870 static int ci_set_mc_special_registers(struct radeon_device *rdev,
3871                                        struct ci_mc_reg_table *table)
3872 {
3873         struct ci_power_info *pi = ci_get_pi(rdev);
3874         u8 i, j, k;
3875         u32 temp_reg;
3876
3877         for (i = 0, j = table->last; i < table->last; i++) {
3878                 if (j >= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
3879                         return -EINVAL;
3880                 switch(table->mc_reg_address[i].s1 << 2) {
3881                 case MC_SEQ_MISC1:
3882                         temp_reg = RREG32(MC_PMG_CMD_EMRS);
3883                         table->mc_reg_address[j].s1 = MC_PMG_CMD_EMRS >> 2;
3884                         table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_EMRS_LP >> 2;
3885                         for (k = 0; k < table->num_entries; k++) {
3886                                 table->mc_reg_table_entry[k].mc_data[j] =
3887                                         ((temp_reg & 0xffff0000)) | ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16);
3888                         }
3889                         j++;
3890                         if (j >= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
3891                                 return -EINVAL;
3892
3893                         temp_reg = RREG32(MC_PMG_CMD_MRS);
3894                         table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS >> 2;
3895                         table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS_LP >> 2;
3896                         for (k = 0; k < table->num_entries; k++) {
3897                                 table->mc_reg_table_entry[k].mc_data[j] =
3898                                         (temp_reg & 0xffff0000) | (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
3899                                 if (!pi->mem_gddr5)
3900                                         table->mc_reg_table_entry[k].mc_data[j] |= 0x100;
3901                         }
3902                         j++;
3903                         if (j > SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
3904                                 return -EINVAL;
3905
3906                         if (!pi->mem_gddr5) {
3907                                 table->mc_reg_address[j].s1 = MC_PMG_AUTO_CMD >> 2;
3908                                 table->mc_reg_address[j].s0 = MC_PMG_AUTO_CMD >> 2;
3909                                 for (k = 0; k < table->num_entries; k++) {
3910                                         table->mc_reg_table_entry[k].mc_data[j] =
3911                                                 (table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16;
3912                                 }
3913                                 j++;
3914                                 if (j > SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
3915                                         return -EINVAL;
3916                         }
3917                         break;
3918                 case MC_SEQ_RESERVE_M:
3919                         temp_reg = RREG32(MC_PMG_CMD_MRS1);
3920                         table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS1 >> 2;
3921                         table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS1_LP >> 2;
3922                         for (k = 0; k < table->num_entries; k++) {
3923                                 table->mc_reg_table_entry[k].mc_data[j] =
3924                                         (temp_reg & 0xffff0000) | (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
3925                         }
3926                         j++;
3927                         if (j > SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
3928                                 return -EINVAL;
3929                         break;
3930                 default:
3931                         break;
3932                 }
3933
3934         }
3935
3936         table->last = j;
3937
3938         return 0;
3939 }
3940
3941 static bool ci_check_s0_mc_reg_index(u16 in_reg, u16 *out_reg)
3942 {
3943         bool result = true;
3944
3945         switch(in_reg) {
3946         case MC_SEQ_RAS_TIMING >> 2:
3947                 *out_reg = MC_SEQ_RAS_TIMING_LP >> 2;
3948                 break;
3949         case MC_SEQ_DLL_STBY >> 2:
3950                 *out_reg = MC_SEQ_DLL_STBY_LP >> 2;
3951                 break;
3952         case MC_SEQ_G5PDX_CMD0 >> 2:
3953                 *out_reg = MC_SEQ_G5PDX_CMD0_LP >> 2;
3954                 break;
3955         case MC_SEQ_G5PDX_CMD1 >> 2:
3956                 *out_reg = MC_SEQ_G5PDX_CMD1_LP >> 2;
3957                 break;
3958         case MC_SEQ_G5PDX_CTRL >> 2:
3959                 *out_reg = MC_SEQ_G5PDX_CTRL_LP >> 2;
3960                 break;
3961         case MC_SEQ_CAS_TIMING >> 2:
3962                 *out_reg = MC_SEQ_CAS_TIMING_LP >> 2;
3963             break;
3964         case MC_SEQ_MISC_TIMING >> 2:
3965                 *out_reg = MC_SEQ_MISC_TIMING_LP >> 2;
3966                 break;
3967         case MC_SEQ_MISC_TIMING2 >> 2:
3968                 *out_reg = MC_SEQ_MISC_TIMING2_LP >> 2;
3969                 break;
3970         case MC_SEQ_PMG_DVS_CMD >> 2:
3971                 *out_reg = MC_SEQ_PMG_DVS_CMD_LP >> 2;
3972                 break;
3973         case MC_SEQ_PMG_DVS_CTL >> 2:
3974                 *out_reg = MC_SEQ_PMG_DVS_CTL_LP >> 2;
3975                 break;
3976         case MC_SEQ_RD_CTL_D0 >> 2:
3977                 *out_reg = MC_SEQ_RD_CTL_D0_LP >> 2;
3978                 break;
3979         case MC_SEQ_RD_CTL_D1 >> 2:
3980                 *out_reg = MC_SEQ_RD_CTL_D1_LP >> 2;
3981                 break;
3982         case MC_SEQ_WR_CTL_D0 >> 2:
3983                 *out_reg = MC_SEQ_WR_CTL_D0_LP >> 2;
3984                 break;
3985         case MC_SEQ_WR_CTL_D1 >> 2:
3986                 *out_reg = MC_SEQ_WR_CTL_D1_LP >> 2;
3987                 break;
3988         case MC_PMG_CMD_EMRS >> 2:
3989                 *out_reg = MC_SEQ_PMG_CMD_EMRS_LP >> 2;
3990                 break;
3991         case MC_PMG_CMD_MRS >> 2:
3992                 *out_reg = MC_SEQ_PMG_CMD_MRS_LP >> 2;
3993                 break;
3994         case MC_PMG_CMD_MRS1 >> 2:
3995                 *out_reg = MC_SEQ_PMG_CMD_MRS1_LP >> 2;
3996                 break;
3997         case MC_SEQ_PMG_TIMING >> 2:
3998                 *out_reg = MC_SEQ_PMG_TIMING_LP >> 2;
3999                 break;
4000         case MC_PMG_CMD_MRS2 >> 2:
4001                 *out_reg = MC_SEQ_PMG_CMD_MRS2_LP >> 2;
4002                 break;
4003         case MC_SEQ_WR_CTL_2 >> 2:
4004                 *out_reg = MC_SEQ_WR_CTL_2_LP >> 2;
4005                 break;
4006         default:
4007                 result = false;
4008                 break;
4009         }
4010
4011         return result;
4012 }
4013
4014 static void ci_set_valid_flag(struct ci_mc_reg_table *table)
4015 {
4016         u8 i, j;
4017
4018         for (i = 0; i < table->last; i++) {
4019                 for (j = 1; j < table->num_entries; j++) {
4020                         if (table->mc_reg_table_entry[j-1].mc_data[i] !=
4021                             table->mc_reg_table_entry[j].mc_data[i]) {
4022                                 table->valid_flag |= 1 << i;
4023                                 break;
4024                         }
4025                 }
4026         }
4027 }
4028
4029 static void ci_set_s0_mc_reg_index(struct ci_mc_reg_table *table)
4030 {
4031         u32 i;
4032         u16 address;
4033
4034         for (i = 0; i < table->last; i++) {
4035                 table->mc_reg_address[i].s0 =
4036                         ci_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address) ?
4037                         address : table->mc_reg_address[i].s1;
4038         }
4039 }
4040
4041 static int ci_copy_vbios_mc_reg_table(const struct atom_mc_reg_table *table,
4042                                       struct ci_mc_reg_table *ci_table)
4043 {
4044         u8 i, j;
4045
4046         if (table->last > SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
4047                 return -EINVAL;
4048         if (table->num_entries > MAX_AC_TIMING_ENTRIES)
4049                 return -EINVAL;
4050
4051         for (i = 0; i < table->last; i++)
4052                 ci_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1;
4053
4054         ci_table->last = table->last;
4055
4056         for (i = 0; i < table->num_entries; i++) {
4057                 ci_table->mc_reg_table_entry[i].mclk_max =
4058                         table->mc_reg_table_entry[i].mclk_max;
4059                 for (j = 0; j < table->last; j++)
4060                         ci_table->mc_reg_table_entry[i].mc_data[j] =
4061                                 table->mc_reg_table_entry[i].mc_data[j];
4062         }
4063         ci_table->num_entries = table->num_entries;
4064
4065         return 0;
4066 }
4067
4068 static int ci_initialize_mc_reg_table(struct radeon_device *rdev)
4069 {
4070         struct ci_power_info *pi = ci_get_pi(rdev);
4071         struct atom_mc_reg_table *table;
4072         struct ci_mc_reg_table *ci_table = &pi->mc_reg_table;
4073         u8 module_index = rv770_get_memory_module_index(rdev);
4074         int ret;
4075
4076         table = kzalloc(sizeof(struct atom_mc_reg_table), GFP_KERNEL);
4077         if (!table)
4078                 return -ENOMEM;
4079
4080         WREG32(MC_SEQ_RAS_TIMING_LP, RREG32(MC_SEQ_RAS_TIMING));
4081         WREG32(MC_SEQ_CAS_TIMING_LP, RREG32(MC_SEQ_CAS_TIMING));
4082         WREG32(MC_SEQ_DLL_STBY_LP, RREG32(MC_SEQ_DLL_STBY));
4083         WREG32(MC_SEQ_G5PDX_CMD0_LP, RREG32(MC_SEQ_G5PDX_CMD0));
4084         WREG32(MC_SEQ_G5PDX_CMD1_LP, RREG32(MC_SEQ_G5PDX_CMD1));
4085         WREG32(MC_SEQ_G5PDX_CTRL_LP, RREG32(MC_SEQ_G5PDX_CTRL));
4086         WREG32(MC_SEQ_PMG_DVS_CMD_LP, RREG32(MC_SEQ_PMG_DVS_CMD));
4087         WREG32(MC_SEQ_PMG_DVS_CTL_LP, RREG32(MC_SEQ_PMG_DVS_CTL));
4088         WREG32(MC_SEQ_MISC_TIMING_LP, RREG32(MC_SEQ_MISC_TIMING));
4089         WREG32(MC_SEQ_MISC_TIMING2_LP, RREG32(MC_SEQ_MISC_TIMING2));
4090         WREG32(MC_SEQ_PMG_CMD_EMRS_LP, RREG32(MC_PMG_CMD_EMRS));
4091         WREG32(MC_SEQ_PMG_CMD_MRS_LP, RREG32(MC_PMG_CMD_MRS));
4092         WREG32(MC_SEQ_PMG_CMD_MRS1_LP, RREG32(MC_PMG_CMD_MRS1));
4093         WREG32(MC_SEQ_WR_CTL_D0_LP, RREG32(MC_SEQ_WR_CTL_D0));
4094         WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1));
4095         WREG32(MC_SEQ_RD_CTL_D0_LP, RREG32(MC_SEQ_RD_CTL_D0));
4096         WREG32(MC_SEQ_RD_CTL_D1_LP, RREG32(MC_SEQ_RD_CTL_D1));
4097         WREG32(MC_SEQ_PMG_TIMING_LP, RREG32(MC_SEQ_PMG_TIMING));
4098         WREG32(MC_SEQ_PMG_CMD_MRS2_LP, RREG32(MC_PMG_CMD_MRS2));
4099         WREG32(MC_SEQ_WR_CTL_2_LP, RREG32(MC_SEQ_WR_CTL_2));
4100
4101         ret = radeon_atom_init_mc_reg_table(rdev, module_index, table);
4102         if (ret)
4103                 goto init_mc_done;
4104
4105         ret = ci_copy_vbios_mc_reg_table(table, ci_table);
4106         if (ret)
4107                 goto init_mc_done;
4108
4109         ci_set_s0_mc_reg_index(ci_table);
4110
4111         ret = ci_set_mc_special_registers(rdev, ci_table);
4112         if (ret)
4113                 goto init_mc_done;
4114
4115         ci_set_valid_flag(ci_table);
4116
4117 init_mc_done:
4118         kfree(table);
4119
4120         return ret;
4121 }
4122
4123 static int ci_populate_mc_reg_addresses(struct radeon_device *rdev,
4124                                         SMU7_Discrete_MCRegisters *mc_reg_table)
4125 {
4126         struct ci_power_info *pi = ci_get_pi(rdev);
4127         u32 i, j;
4128
4129         for (i = 0, j = 0; j < pi->mc_reg_table.last; j++) {
4130                 if (pi->mc_reg_table.valid_flag & (1 << j)) {
4131                         if (i >= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
4132                                 return -EINVAL;
4133                         mc_reg_table->address[i].s0 = cpu_to_be16(pi->mc_reg_table.mc_reg_address[j].s0);
4134                         mc_reg_table->address[i].s1 = cpu_to_be16(pi->mc_reg_table.mc_reg_address[j].s1);
4135                         i++;
4136                 }
4137         }
4138
4139         mc_reg_table->last = (u8)i;
4140
4141         return 0;
4142 }
4143
4144 static void ci_convert_mc_registers(const struct ci_mc_reg_entry *entry,
4145                                     SMU7_Discrete_MCRegisterSet *data,
4146                                     u32 num_entries, u32 valid_flag)
4147 {
4148         u32 i, j;
4149
4150         for (i = 0, j = 0; j < num_entries; j++) {
4151                 if (valid_flag & (1 << j)) {
4152                         data->value[i] = cpu_to_be32(entry->mc_data[j]);
4153                         i++;
4154                 }
4155         }
4156 }
4157
4158 static void ci_convert_mc_reg_table_entry_to_smc(struct radeon_device *rdev,
4159                                                  const u32 memory_clock,
4160                                                  SMU7_Discrete_MCRegisterSet *mc_reg_table_data)
4161 {
4162         struct ci_power_info *pi = ci_get_pi(rdev);
4163         u32 i = 0;
4164
4165         for(i = 0; i < pi->mc_reg_table.num_entries; i++) {
4166                 if (memory_clock <= pi->mc_reg_table.mc_reg_table_entry[i].mclk_max)
4167                         break;
4168         }
4169
4170         if ((i == pi->mc_reg_table.num_entries) && (i > 0))
4171                 --i;
4172
4173         ci_convert_mc_registers(&pi->mc_reg_table.mc_reg_table_entry[i],
4174                                 mc_reg_table_data, pi->mc_reg_table.last,
4175                                 pi->mc_reg_table.valid_flag);
4176 }
4177
4178 static void ci_convert_mc_reg_table_to_smc(struct radeon_device *rdev,
4179                                            SMU7_Discrete_MCRegisters *mc_reg_table)
4180 {
4181         struct ci_power_info *pi = ci_get_pi(rdev);
4182         u32 i;
4183
4184         for (i = 0; i < pi->dpm_table.mclk_table.count; i++)
4185                 ci_convert_mc_reg_table_entry_to_smc(rdev,
4186                                                      pi->dpm_table.mclk_table.dpm_levels[i].value,
4187                                                      &mc_reg_table->data[i]);
4188 }
4189
4190 static int ci_populate_initial_mc_reg_table(struct radeon_device *rdev)
4191 {
4192         struct ci_power_info *pi = ci_get_pi(rdev);
4193         int ret;
4194
4195         memset(&pi->smc_mc_reg_table, 0, sizeof(SMU7_Discrete_MCRegisters));
4196
4197         ret = ci_populate_mc_reg_addresses(rdev, &pi->smc_mc_reg_table);
4198         if (ret)
4199                 return ret;
4200         ci_convert_mc_reg_table_to_smc(rdev, &pi->smc_mc_reg_table);
4201
4202         return ci_copy_bytes_to_smc(rdev,
4203                                     pi->mc_reg_table_start,
4204                                     (u8 *)&pi->smc_mc_reg_table,
4205                                     sizeof(SMU7_Discrete_MCRegisters),
4206                                     pi->sram_end);
4207 }
4208
4209 static int ci_update_and_upload_mc_reg_table(struct radeon_device *rdev)
4210 {
4211         struct ci_power_info *pi = ci_get_pi(rdev);
4212
4213         if (!(pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK))
4214                 return 0;
4215
4216         memset(&pi->smc_mc_reg_table, 0, sizeof(SMU7_Discrete_MCRegisters));
4217
4218         ci_convert_mc_reg_table_to_smc(rdev, &pi->smc_mc_reg_table);
4219
4220         return ci_copy_bytes_to_smc(rdev,
4221                                     pi->mc_reg_table_start +
4222                                     offsetof(SMU7_Discrete_MCRegisters, data[0]),
4223                                     (u8 *)&pi->smc_mc_reg_table.data[0],
4224                                     sizeof(SMU7_Discrete_MCRegisterSet) *
4225                                     pi->dpm_table.mclk_table.count,
4226                                     pi->sram_end);
4227 }
4228
4229 static void ci_enable_voltage_control(struct radeon_device *rdev)
4230 {
4231         u32 tmp = RREG32_SMC(GENERAL_PWRMGT);
4232
4233         tmp |= VOLT_PWRMGT_EN;
4234         WREG32_SMC(GENERAL_PWRMGT, tmp);
4235 }
4236
4237 static enum radeon_pcie_gen ci_get_maximum_link_speed(struct radeon_device *rdev,
4238                                                       struct radeon_ps *radeon_state)
4239 {
4240         struct ci_ps *state = ci_get_ps(radeon_state);
4241         int i;
4242         u16 pcie_speed, max_speed = 0;
4243
4244         for (i = 0; i < state->performance_level_count; i++) {
4245                 pcie_speed = state->performance_levels[i].pcie_gen;
4246                 if (max_speed < pcie_speed)
4247                         max_speed = pcie_speed;
4248         }
4249
4250         return max_speed;
4251 }
4252
4253 static u16 ci_get_current_pcie_speed(struct radeon_device *rdev)
4254 {
4255         u32 speed_cntl = 0;
4256
4257         speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL) & LC_CURRENT_DATA_RATE_MASK;
4258         speed_cntl >>= LC_CURRENT_DATA_RATE_SHIFT;
4259
4260         return (u16)speed_cntl;
4261 }
4262
4263 static int ci_get_current_pcie_lane_number(struct radeon_device *rdev)
4264 {
4265         u32 link_width = 0;
4266
4267         link_width = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL) & LC_LINK_WIDTH_RD_MASK;
4268         link_width >>= LC_LINK_WIDTH_RD_SHIFT;
4269
4270         switch (link_width) {
4271         case RADEON_PCIE_LC_LINK_WIDTH_X1:
4272                 return 1;
4273         case RADEON_PCIE_LC_LINK_WIDTH_X2:
4274                 return 2;
4275         case RADEON_PCIE_LC_LINK_WIDTH_X4:
4276                 return 4;
4277         case RADEON_PCIE_LC_LINK_WIDTH_X8:
4278                 return 8;
4279         case RADEON_PCIE_LC_LINK_WIDTH_X12:
4280                 /* not actually supported */
4281                 return 12;
4282         case RADEON_PCIE_LC_LINK_WIDTH_X0:
4283         case RADEON_PCIE_LC_LINK_WIDTH_X16:
4284         default:
4285                 return 16;
4286         }
4287 }
4288
4289 static void ci_request_link_speed_change_before_state_change(struct radeon_device *rdev,
4290                                                              struct radeon_ps *radeon_new_state,
4291                                                              struct radeon_ps *radeon_current_state)
4292 {
4293         struct ci_power_info *pi = ci_get_pi(rdev);
4294         enum radeon_pcie_gen target_link_speed =
4295                 ci_get_maximum_link_speed(rdev, radeon_new_state);
4296         enum radeon_pcie_gen current_link_speed;
4297
4298         if (pi->force_pcie_gen == RADEON_PCIE_GEN_INVALID)
4299                 current_link_speed = ci_get_maximum_link_speed(rdev, radeon_current_state);
4300         else
4301                 current_link_speed = pi->force_pcie_gen;
4302
4303         pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID;
4304         pi->pspp_notify_required = false;
4305         if (target_link_speed > current_link_speed) {
4306                 switch (target_link_speed) {
4307 #ifdef CONFIG_ACPI
4308                 case RADEON_PCIE_GEN3:
4309                         if (radeon_acpi_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN3, false) == 0)
4310                                 break;
4311                         pi->force_pcie_gen = RADEON_PCIE_GEN2;
4312                         if (current_link_speed == RADEON_PCIE_GEN2)
4313                                 break;
4314                 case RADEON_PCIE_GEN2:
4315                         if (radeon_acpi_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN2, false) == 0)
4316                                 break;
4317 #endif
4318                 default:
4319                         pi->force_pcie_gen = ci_get_current_pcie_speed(rdev);
4320                         break;
4321                 }
4322         } else {
4323                 if (target_link_speed < current_link_speed)
4324                         pi->pspp_notify_required = true;
4325         }
4326 }
4327
4328 static void ci_notify_link_speed_change_after_state_change(struct radeon_device *rdev,
4329                                                            struct radeon_ps *radeon_new_state,
4330                                                            struct radeon_ps *radeon_current_state)
4331 {
4332         struct ci_power_info *pi = ci_get_pi(rdev);
4333         enum radeon_pcie_gen target_link_speed =
4334                 ci_get_maximum_link_speed(rdev, radeon_new_state);
4335         u8 request;
4336
4337         if (pi->pspp_notify_required) {
4338                 if (target_link_speed == RADEON_PCIE_GEN3)
4339                         request = PCIE_PERF_REQ_PECI_GEN3;
4340                 else if (target_link_speed == RADEON_PCIE_GEN2)
4341                         request = PCIE_PERF_REQ_PECI_GEN2;
4342                 else
4343                         request = PCIE_PERF_REQ_PECI_GEN1;
4344
4345                 if ((request == PCIE_PERF_REQ_PECI_GEN1) &&
4346                     (ci_get_current_pcie_speed(rdev) > 0))
4347                         return;
4348
4349 #ifdef CONFIG_ACPI
4350                 radeon_acpi_pcie_performance_request(rdev, request, false);
4351 #endif
4352         }
4353 }
4354
4355 static int ci_set_private_data_variables_based_on_pptable(struct radeon_device *rdev)
4356 {
4357         struct ci_power_info *pi = ci_get_pi(rdev);
4358         struct radeon_clock_voltage_dependency_table *allowed_sclk_vddc_table =
4359                 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
4360         struct radeon_clock_voltage_dependency_table *allowed_mclk_vddc_table =
4361                 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk;
4362         struct radeon_clock_voltage_dependency_table *allowed_mclk_vddci_table =
4363                 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk;
4364
4365         if (allowed_sclk_vddc_table == NULL)
4366                 return -EINVAL;
4367         if (allowed_sclk_vddc_table->count < 1)
4368                 return -EINVAL;
4369         if (allowed_mclk_vddc_table == NULL)
4370                 return -EINVAL;
4371         if (allowed_mclk_vddc_table->count < 1)
4372                 return -EINVAL;
4373         if (allowed_mclk_vddci_table == NULL)
4374                 return -EINVAL;
4375         if (allowed_mclk_vddci_table->count < 1)
4376                 return -EINVAL;
4377
4378         pi->min_vddc_in_pp_table = allowed_sclk_vddc_table->entries[0].v;
4379         pi->max_vddc_in_pp_table =
4380                 allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].v;
4381
4382         pi->min_vddci_in_pp_table = allowed_mclk_vddci_table->entries[0].v;
4383         pi->max_vddci_in_pp_table =
4384                 allowed_mclk_vddci_table->entries[allowed_mclk_vddci_table->count - 1].v;
4385
4386         rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk =
4387                 allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].clk;
4388         rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk =
4389                 allowed_mclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].clk;
4390         rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc =
4391                 allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].v;
4392         rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddci =
4393                 allowed_mclk_vddci_table->entries[allowed_mclk_vddci_table->count - 1].v;
4394
4395         return 0;
4396 }
4397
4398 static void ci_patch_with_vddc_leakage(struct radeon_device *rdev, u16 *vddc)
4399 {
4400         struct ci_power_info *pi = ci_get_pi(rdev);
4401         struct ci_leakage_voltage *leakage_table = &pi->vddc_leakage;
4402         u32 leakage_index;
4403
4404         for (leakage_index = 0; leakage_index < leakage_table->count; leakage_index++) {
4405                 if (leakage_table->leakage_id[leakage_index] == *vddc) {
4406                         *vddc = leakage_table->actual_voltage[leakage_index];
4407                         break;
4408                 }
4409         }
4410 }
4411
4412 static void ci_patch_with_vddci_leakage(struct radeon_device *rdev, u16 *vddci)
4413 {
4414         struct ci_power_info *pi = ci_get_pi(rdev);
4415         struct ci_leakage_voltage *leakage_table = &pi->vddci_leakage;
4416         u32 leakage_index;
4417
4418         for (leakage_index = 0; leakage_index < leakage_table->count; leakage_index++) {
4419                 if (leakage_table->leakage_id[leakage_index] == *vddci) {
4420                         *vddci = leakage_table->actual_voltage[leakage_index];
4421                         break;
4422                 }
4423         }
4424 }
4425
4426 static void ci_patch_clock_voltage_dependency_table_with_vddc_leakage(struct radeon_device *rdev,
4427                                                                       struct radeon_clock_voltage_dependency_table *table)
4428 {
4429         u32 i;
4430
4431         if (table) {
4432                 for (i = 0; i < table->count; i++)
4433                         ci_patch_with_vddc_leakage(rdev, &table->entries[i].v);
4434         }
4435 }
4436
4437 static void ci_patch_clock_voltage_dependency_table_with_vddci_leakage(struct radeon_device *rdev,
4438                                                                        struct radeon_clock_voltage_dependency_table *table)
4439 {
4440         u32 i;
4441
4442         if (table) {
4443                 for (i = 0; i < table->count; i++)
4444                         ci_patch_with_vddci_leakage(rdev, &table->entries[i].v);
4445         }
4446 }
4447
4448 static void ci_patch_vce_clock_voltage_dependency_table_with_vddc_leakage(struct radeon_device *rdev,
4449                                                                           struct radeon_vce_clock_voltage_dependency_table *table)
4450 {
4451         u32 i;
4452
4453         if (table) {
4454                 for (i = 0; i < table->count; i++)
4455                         ci_patch_with_vddc_leakage(rdev, &table->entries[i].v);
4456         }
4457 }
4458
4459 static void ci_patch_uvd_clock_voltage_dependency_table_with_vddc_leakage(struct radeon_device *rdev,
4460                                                                           struct radeon_uvd_clock_voltage_dependency_table *table)
4461 {
4462         u32 i;
4463
4464         if (table) {
4465                 for (i = 0; i < table->count; i++)
4466                         ci_patch_with_vddc_leakage(rdev, &table->entries[i].v);
4467         }
4468 }
4469
4470 static void ci_patch_vddc_phase_shed_limit_table_with_vddc_leakage(struct radeon_device *rdev,
4471                                                                    struct radeon_phase_shedding_limits_table *table)
4472 {
4473         u32 i;
4474
4475         if (table) {
4476                 for (i = 0; i < table->count; i++)
4477                         ci_patch_with_vddc_leakage(rdev, &table->entries[i].voltage);
4478         }
4479 }
4480
4481 static void ci_patch_clock_voltage_limits_with_vddc_leakage(struct radeon_device *rdev,
4482                                                             struct radeon_clock_and_voltage_limits *table)
4483 {
4484         if (table) {
4485                 ci_patch_with_vddc_leakage(rdev, (u16 *)&table->vddc);
4486                 ci_patch_with_vddci_leakage(rdev, (u16 *)&table->vddci);
4487         }
4488 }
4489
4490 static void ci_patch_cac_leakage_table_with_vddc_leakage(struct radeon_device *rdev,
4491                                                          struct radeon_cac_leakage_table *table)
4492 {
4493         u32 i;
4494
4495         if (table) {
4496                 for (i = 0; i < table->count; i++)
4497                         ci_patch_with_vddc_leakage(rdev, &table->entries[i].vddc);
4498         }
4499 }
4500
4501 static void ci_patch_dependency_tables_with_leakage(struct radeon_device *rdev)
4502 {
4503
4504         ci_patch_clock_voltage_dependency_table_with_vddc_leakage(rdev,
4505                                                                   &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk);
4506         ci_patch_clock_voltage_dependency_table_with_vddc_leakage(rdev,
4507                                                                   &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk);
4508         ci_patch_clock_voltage_dependency_table_with_vddc_leakage(rdev,
4509                                                                   &rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk);
4510         ci_patch_clock_voltage_dependency_table_with_vddci_leakage(rdev,
4511                                                                    &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk);
4512         ci_patch_vce_clock_voltage_dependency_table_with_vddc_leakage(rdev,
4513                                                                       &rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table);
4514         ci_patch_uvd_clock_voltage_dependency_table_with_vddc_leakage(rdev,
4515                                                                       &rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table);
4516         ci_patch_clock_voltage_dependency_table_with_vddc_leakage(rdev,
4517                                                                   &rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table);
4518         ci_patch_clock_voltage_dependency_table_with_vddc_leakage(rdev,
4519                                                                   &rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table);
4520         ci_patch_vddc_phase_shed_limit_table_with_vddc_leakage(rdev,
4521                                                                &rdev->pm.dpm.dyn_state.phase_shedding_limits_table);
4522         ci_patch_clock_voltage_limits_with_vddc_leakage(rdev,
4523                                                         &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac);
4524         ci_patch_clock_voltage_limits_with_vddc_leakage(rdev,
4525                                                         &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc);
4526         ci_patch_cac_leakage_table_with_vddc_leakage(rdev,
4527                                                      &rdev->pm.dpm.dyn_state.cac_leakage_table);
4528
4529 }
4530
4531 static void ci_get_memory_type(struct radeon_device *rdev)
4532 {
4533         struct ci_power_info *pi = ci_get_pi(rdev);
4534         u32 tmp;
4535
4536         tmp = RREG32(MC_SEQ_MISC0);
4537
4538         if (((tmp & MC_SEQ_MISC0_GDDR5_MASK) >> MC_SEQ_MISC0_GDDR5_SHIFT) ==
4539             MC_SEQ_MISC0_GDDR5_VALUE)
4540                 pi->mem_gddr5 = true;
4541         else
4542                 pi->mem_gddr5 = false;
4543
4544 }
4545
4546 static void ci_update_current_ps(struct radeon_device *rdev,
4547                                  struct radeon_ps *rps)
4548 {
4549         struct ci_ps *new_ps = ci_get_ps(rps);
4550         struct ci_power_info *pi = ci_get_pi(rdev);
4551
4552         pi->current_rps = *rps;
4553         pi->current_ps = *new_ps;
4554         pi->current_rps.ps_priv = &pi->current_ps;
4555 }
4556
4557 static void ci_update_requested_ps(struct radeon_device *rdev,
4558                                    struct radeon_ps *rps)
4559 {
4560         struct ci_ps *new_ps = ci_get_ps(rps);
4561         struct ci_power_info *pi = ci_get_pi(rdev);
4562
4563         pi->requested_rps = *rps;
4564         pi->requested_ps = *new_ps;
4565         pi->requested_rps.ps_priv = &pi->requested_ps;
4566 }
4567
4568 int ci_dpm_pre_set_power_state(struct radeon_device *rdev)
4569 {
4570         struct ci_power_info *pi = ci_get_pi(rdev);
4571         struct radeon_ps requested_ps = *rdev->pm.dpm.requested_ps;
4572         struct radeon_ps *new_ps = &requested_ps;
4573
4574         ci_update_requested_ps(rdev, new_ps);
4575
4576         ci_apply_state_adjust_rules(rdev, &pi->requested_rps);
4577
4578         return 0;
4579 }
4580
4581 void ci_dpm_post_set_power_state(struct radeon_device *rdev)
4582 {
4583         struct ci_power_info *pi = ci_get_pi(rdev);
4584         struct radeon_ps *new_ps = &pi->requested_rps;
4585
4586         ci_update_current_ps(rdev, new_ps);
4587 }
4588
4589
4590 void ci_dpm_setup_asic(struct radeon_device *rdev)
4591 {
4592         int r;
4593
4594         r = ci_mc_load_microcode(rdev);
4595         if (r)
4596                 DRM_ERROR("Failed to load MC firmware!\n");
4597         ci_read_clock_registers(rdev);
4598         ci_get_memory_type(rdev);
4599         ci_enable_acpi_power_management(rdev);
4600         ci_init_sclk_t(rdev);
4601 }
4602
4603 int ci_dpm_enable(struct radeon_device *rdev)
4604 {
4605         struct ci_power_info *pi = ci_get_pi(rdev);
4606         struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;
4607         int ret;
4608
4609         if (ci_is_smc_running(rdev))
4610                 return -EINVAL;
4611         if (pi->voltage_control != CISLANDS_VOLTAGE_CONTROL_NONE) {
4612                 ci_enable_voltage_control(rdev);
4613                 ret = ci_construct_voltage_tables(rdev);
4614                 if (ret) {
4615                         DRM_ERROR("ci_construct_voltage_tables failed\n");
4616                         return ret;
4617                 }
4618         }
4619         if (pi->caps_dynamic_ac_timing) {
4620                 ret = ci_initialize_mc_reg_table(rdev);
4621                 if (ret)
4622                         pi->caps_dynamic_ac_timing = false;
4623         }
4624         if (pi->dynamic_ss)
4625                 ci_enable_spread_spectrum(rdev, true);
4626         if (pi->thermal_protection)
4627                 ci_enable_thermal_protection(rdev, true);
4628         ci_program_sstp(rdev);
4629         ci_enable_display_gap(rdev);
4630         ci_program_vc(rdev);
4631         ret = ci_upload_firmware(rdev);
4632         if (ret) {
4633                 DRM_ERROR("ci_upload_firmware failed\n");
4634                 return ret;
4635         }
4636         ret = ci_process_firmware_header(rdev);
4637         if (ret) {
4638                 DRM_ERROR("ci_process_firmware_header failed\n");
4639                 return ret;
4640         }
4641         ret = ci_initial_switch_from_arb_f0_to_f1(rdev);
4642         if (ret) {
4643                 DRM_ERROR("ci_initial_switch_from_arb_f0_to_f1 failed\n");
4644                 return ret;
4645         }
4646         ret = ci_init_smc_table(rdev);
4647         if (ret) {
4648                 DRM_ERROR("ci_init_smc_table failed\n");
4649                 return ret;
4650         }
4651         ret = ci_init_arb_table_index(rdev);
4652         if (ret) {
4653                 DRM_ERROR("ci_init_arb_table_index failed\n");
4654                 return ret;
4655         }
4656         if (pi->caps_dynamic_ac_timing) {
4657                 ret = ci_populate_initial_mc_reg_table(rdev);
4658                 if (ret) {
4659                         DRM_ERROR("ci_populate_initial_mc_reg_table failed\n");
4660                         return ret;
4661                 }
4662         }
4663         ret = ci_populate_pm_base(rdev);
4664         if (ret) {
4665                 DRM_ERROR("ci_populate_pm_base failed\n");
4666                 return ret;
4667         }
4668         ci_dpm_start_smc(rdev);
4669         ci_enable_vr_hot_gpio_interrupt(rdev);
4670         ret = ci_notify_smc_display_change(rdev, false);
4671         if (ret) {
4672                 DRM_ERROR("ci_notify_smc_display_change failed\n");
4673                 return ret;
4674         }
4675         ci_enable_sclk_control(rdev, true);
4676         ret = ci_enable_ulv(rdev, true);
4677         if (ret) {
4678                 DRM_ERROR("ci_enable_ulv failed\n");
4679                 return ret;
4680         }
4681         ret = ci_enable_ds_master_switch(rdev, true);
4682         if (ret) {
4683                 DRM_ERROR("ci_enable_ds_master_switch failed\n");
4684                 return ret;
4685         }
4686         ret = ci_start_dpm(rdev);
4687         if (ret) {
4688                 DRM_ERROR("ci_start_dpm failed\n");
4689                 return ret;
4690         }
4691         ret = ci_enable_didt(rdev, true);
4692         if (ret) {
4693                 DRM_ERROR("ci_enable_didt failed\n");
4694                 return ret;
4695         }
4696         ret = ci_enable_smc_cac(rdev, true);
4697         if (ret) {
4698                 DRM_ERROR("ci_enable_smc_cac failed\n");
4699                 return ret;
4700         }
4701         ret = ci_enable_power_containment(rdev, true);
4702         if (ret) {
4703                 DRM_ERROR("ci_enable_power_containment failed\n");
4704                 return ret;
4705         }
4706
4707         ci_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, true);
4708
4709         ci_update_current_ps(rdev, boot_ps);
4710
4711         return 0;
4712 }
4713
4714 static int ci_set_temperature_range(struct radeon_device *rdev)
4715 {
4716         int ret;
4717
4718         ret = ci_thermal_enable_alert(rdev, false);
4719         if (ret)
4720                 return ret;
4721         ret = ci_thermal_set_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
4722         if (ret)
4723                 return ret;
4724         ret = ci_thermal_enable_alert(rdev, true);
4725         if (ret)
4726                 return ret;
4727
4728         return ret;
4729 }
4730
4731 int ci_dpm_late_enable(struct radeon_device *rdev)
4732 {
4733         int ret;
4734
4735         ret = ci_set_temperature_range(rdev);
4736         if (ret)
4737                 return ret;
4738
4739         ci_dpm_powergate_uvd(rdev, true);
4740
4741         return 0;
4742 }
4743
4744 void ci_dpm_disable(struct radeon_device *rdev)
4745 {
4746         struct ci_power_info *pi = ci_get_pi(rdev);
4747         struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;
4748
4749         ci_dpm_powergate_uvd(rdev, false);
4750
4751         if (!ci_is_smc_running(rdev))
4752                 return;
4753
4754         if (pi->thermal_protection)
4755                 ci_enable_thermal_protection(rdev, false);
4756         ci_enable_power_containment(rdev, false);
4757         ci_enable_smc_cac(rdev, false);
4758         ci_enable_didt(rdev, false);
4759         ci_enable_spread_spectrum(rdev, false);
4760         ci_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, false);
4761         ci_stop_dpm(rdev);
4762         ci_enable_ds_master_switch(rdev, false);
4763         ci_enable_ulv(rdev, false);
4764         ci_clear_vc(rdev);
4765         ci_reset_to_default(rdev);
4766         ci_dpm_stop_smc(rdev);
4767         ci_force_switch_to_arb_f0(rdev);
4768
4769         ci_update_current_ps(rdev, boot_ps);
4770 }
4771
4772 int ci_dpm_set_power_state(struct radeon_device *rdev)
4773 {
4774         struct ci_power_info *pi = ci_get_pi(rdev);
4775         struct radeon_ps *new_ps = &pi->requested_rps;
4776         struct radeon_ps *old_ps = &pi->current_rps;
4777         int ret;
4778
4779         ci_find_dpm_states_clocks_in_dpm_table(rdev, new_ps);
4780         if (pi->pcie_performance_request)
4781                 ci_request_link_speed_change_before_state_change(rdev, new_ps, old_ps);
4782         ret = ci_freeze_sclk_mclk_dpm(rdev);
4783         if (ret) {
4784                 DRM_ERROR("ci_freeze_sclk_mclk_dpm failed\n");
4785                 return ret;
4786         }
4787         ret = ci_populate_and_upload_sclk_mclk_dpm_levels(rdev, new_ps);
4788         if (ret) {
4789                 DRM_ERROR("ci_populate_and_upload_sclk_mclk_dpm_levels failed\n");
4790                 return ret;
4791         }
4792         ret = ci_generate_dpm_level_enable_mask(rdev, new_ps);
4793         if (ret) {
4794                 DRM_ERROR("ci_generate_dpm_level_enable_mask failed\n");
4795                 return ret;
4796         }
4797
4798         ret = ci_update_vce_dpm(rdev, new_ps, old_ps);
4799         if (ret) {
4800                 DRM_ERROR("ci_update_vce_dpm failed\n");
4801                 return ret;
4802         }
4803
4804         ret = ci_update_sclk_t(rdev);
4805         if (ret) {
4806                 DRM_ERROR("ci_update_sclk_t failed\n");
4807                 return ret;
4808         }
4809         if (pi->caps_dynamic_ac_timing) {
4810                 ret = ci_update_and_upload_mc_reg_table(rdev);
4811                 if (ret) {
4812                         DRM_ERROR("ci_update_and_upload_mc_reg_table failed\n");
4813                         return ret;
4814                 }
4815         }
4816         ret = ci_program_memory_timing_parameters(rdev);
4817         if (ret) {
4818                 DRM_ERROR("ci_program_memory_timing_parameters failed\n");
4819                 return ret;
4820         }
4821         ret = ci_unfreeze_sclk_mclk_dpm(rdev);
4822         if (ret) {
4823                 DRM_ERROR("ci_unfreeze_sclk_mclk_dpm failed\n");
4824                 return ret;
4825         }
4826         ret = ci_upload_dpm_level_enable_mask(rdev);
4827         if (ret) {
4828                 DRM_ERROR("ci_upload_dpm_level_enable_mask failed\n");
4829                 return ret;
4830         }
4831         if (pi->pcie_performance_request)
4832                 ci_notify_link_speed_change_after_state_change(rdev, new_ps, old_ps);
4833
4834         return 0;
4835 }
4836
4837 int ci_dpm_power_control_set_level(struct radeon_device *rdev)
4838 {
4839         return ci_power_control_set_level(rdev);
4840 }
4841
4842 void ci_dpm_reset_asic(struct radeon_device *rdev)
4843 {
4844         ci_set_boot_state(rdev);
4845 }
4846
4847 void ci_dpm_display_configuration_changed(struct radeon_device *rdev)
4848 {
4849         ci_program_display_gap(rdev);
4850 }
4851
4852 union power_info {
4853         struct _ATOM_POWERPLAY_INFO info;
4854         struct _ATOM_POWERPLAY_INFO_V2 info_2;
4855         struct _ATOM_POWERPLAY_INFO_V3 info_3;
4856         struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
4857         struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
4858         struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
4859 };
4860
4861 union pplib_clock_info {
4862         struct _ATOM_PPLIB_R600_CLOCK_INFO r600;
4863         struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780;
4864         struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
4865         struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo;
4866         struct _ATOM_PPLIB_SI_CLOCK_INFO si;
4867         struct _ATOM_PPLIB_CI_CLOCK_INFO ci;
4868 };
4869
4870 union pplib_power_state {
4871         struct _ATOM_PPLIB_STATE v1;
4872         struct _ATOM_PPLIB_STATE_V2 v2;
4873 };
4874
4875 static void ci_parse_pplib_non_clock_info(struct radeon_device *rdev,
4876                                           struct radeon_ps *rps,
4877                                           struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info,
4878                                           u8 table_rev)
4879 {
4880         rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings);
4881         rps->class = le16_to_cpu(non_clock_info->usClassification);
4882         rps->class2 = le16_to_cpu(non_clock_info->usClassification2);
4883
4884         if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) {
4885                 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK);
4886                 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK);
4887         } else {
4888                 rps->vclk = 0;
4889                 rps->dclk = 0;
4890         }
4891
4892         if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT)
4893                 rdev->pm.dpm.boot_ps = rps;
4894         if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE)
4895                 rdev->pm.dpm.uvd_ps = rps;
4896 }
4897
4898 static void ci_parse_pplib_clock_info(struct radeon_device *rdev,
4899                                       struct radeon_ps *rps, int index,
4900                                       union pplib_clock_info *clock_info)
4901 {
4902         struct ci_power_info *pi = ci_get_pi(rdev);
4903         struct ci_ps *ps = ci_get_ps(rps);
4904         struct ci_pl *pl = &ps->performance_levels[index];
4905
4906         ps->performance_level_count = index + 1;
4907
4908         pl->sclk = le16_to_cpu(clock_info->ci.usEngineClockLow);
4909         pl->sclk |= clock_info->ci.ucEngineClockHigh << 16;
4910         pl->mclk = le16_to_cpu(clock_info->ci.usMemoryClockLow);
4911         pl->mclk |= clock_info->ci.ucMemoryClockHigh << 16;
4912
4913         pl->pcie_gen = r600_get_pcie_gen_support(rdev,
4914                                                  pi->sys_pcie_mask,
4915                                                  pi->vbios_boot_state.pcie_gen_bootup_value,
4916                                                  clock_info->ci.ucPCIEGen);
4917         pl->pcie_lane = r600_get_pcie_lane_support(rdev,
4918                                                    pi->vbios_boot_state.pcie_lane_bootup_value,
4919                                                    le16_to_cpu(clock_info->ci.usPCIELane));
4920
4921         if (rps->class & ATOM_PPLIB_CLASSIFICATION_ACPI) {
4922                 pi->acpi_pcie_gen = pl->pcie_gen;
4923         }
4924
4925         if (rps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV) {
4926                 pi->ulv.supported = true;
4927                 pi->ulv.pl = *pl;
4928                 pi->ulv.cg_ulv_parameter = CISLANDS_CGULVPARAMETER_DFLT;
4929         }
4930
4931         /* patch up boot state */
4932         if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) {
4933                 pl->mclk = pi->vbios_boot_state.mclk_bootup_value;
4934                 pl->sclk = pi->vbios_boot_state.sclk_bootup_value;
4935                 pl->pcie_gen = pi->vbios_boot_state.pcie_gen_bootup_value;
4936                 pl->pcie_lane = pi->vbios_boot_state.pcie_lane_bootup_value;
4937         }
4938
4939         switch (rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) {
4940         case ATOM_PPLIB_CLASSIFICATION_UI_BATTERY:
4941                 pi->use_pcie_powersaving_levels = true;
4942                 if (pi->pcie_gen_powersaving.max < pl->pcie_gen)
4943                         pi->pcie_gen_powersaving.max = pl->pcie_gen;
4944                 if (pi->pcie_gen_powersaving.min > pl->pcie_gen)
4945                         pi->pcie_gen_powersaving.min = pl->pcie_gen;
4946                 if (pi->pcie_lane_powersaving.max < pl->pcie_lane)
4947                         pi->pcie_lane_powersaving.max = pl->pcie_lane;
4948                 if (pi->pcie_lane_powersaving.min > pl->pcie_lane)
4949                         pi->pcie_lane_powersaving.min = pl->pcie_lane;
4950                 break;
4951         case ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE:
4952                 pi->use_pcie_performance_levels = true;
4953                 if (pi->pcie_gen_performance.max < pl->pcie_gen)
4954                         pi->pcie_gen_performance.max = pl->pcie_gen;
4955                 if (pi->pcie_gen_performance.min > pl->pcie_gen)
4956                         pi->pcie_gen_performance.min = pl->pcie_gen;
4957                 if (pi->pcie_lane_performance.max < pl->pcie_lane)
4958                         pi->pcie_lane_performance.max = pl->pcie_lane;
4959                 if (pi->pcie_lane_performance.min > pl->pcie_lane)
4960                         pi->pcie_lane_performance.min = pl->pcie_lane;
4961                 break;
4962         default:
4963                 break;
4964         }
4965 }
4966
4967 static int ci_parse_power_table(struct radeon_device *rdev)
4968 {
4969         struct radeon_mode_info *mode_info = &rdev->mode_info;
4970         struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
4971         union pplib_power_state *power_state;
4972         int i, j, k, non_clock_array_index, clock_array_index;
4973         union pplib_clock_info *clock_info;
4974         struct _StateArray *state_array;
4975         struct _ClockInfoArray *clock_info_array;
4976         struct _NonClockInfoArray *non_clock_info_array;
4977         union power_info *power_info;
4978         int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
4979         u16 data_offset;
4980         u8 frev, crev;
4981         u8 *power_state_offset;
4982         struct ci_ps *ps;
4983
4984         if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
4985                                    &frev, &crev, &data_offset))
4986                 return -EINVAL;
4987         power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
4988
4989         state_array = (struct _StateArray *)
4990                 (mode_info->atom_context->bios + data_offset +
4991                  le16_to_cpu(power_info->pplib.usStateArrayOffset));
4992         clock_info_array = (struct _ClockInfoArray *)
4993                 (mode_info->atom_context->bios + data_offset +
4994                  le16_to_cpu(power_info->pplib.usClockInfoArrayOffset));
4995         non_clock_info_array = (struct _NonClockInfoArray *)
4996                 (mode_info->atom_context->bios + data_offset +
4997                  le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset));
4998
4999         rdev->pm.dpm.ps = kzalloc(sizeof(struct radeon_ps) *
5000                                   state_array->ucNumEntries, GFP_KERNEL);
5001         if (!rdev->pm.dpm.ps)
5002                 return -ENOMEM;
5003         power_state_offset = (u8 *)state_array->states;
5004         for (i = 0; i < state_array->ucNumEntries; i++) {
5005                 u8 *idx;
5006                 power_state = (union pplib_power_state *)power_state_offset;
5007                 non_clock_array_index = power_state->v2.nonClockInfoIndex;
5008                 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
5009                         &non_clock_info_array->nonClockInfo[non_clock_array_index];
5010                 if (!rdev->pm.power_state[i].clock_info)
5011                         return -EINVAL;
5012                 ps = kzalloc(sizeof(struct ci_ps), GFP_KERNEL);
5013                 if (ps == NULL) {
5014                         kfree(rdev->pm.dpm.ps);
5015                         return -ENOMEM;
5016                 }
5017                 rdev->pm.dpm.ps[i].ps_priv = ps;
5018                 ci_parse_pplib_non_clock_info(rdev, &rdev->pm.dpm.ps[i],
5019                                               non_clock_info,
5020                                               non_clock_info_array->ucEntrySize);
5021                 k = 0;
5022                 idx = (u8 *)&power_state->v2.clockInfoIndex[0];
5023                 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) {
5024                         clock_array_index = idx[j];
5025                         if (clock_array_index >= clock_info_array->ucNumEntries)
5026                                 continue;
5027                         if (k >= CISLANDS_MAX_HARDWARE_POWERLEVELS)
5028                                 break;
5029                         clock_info = (union pplib_clock_info *)
5030                                 ((u8 *)&clock_info_array->clockInfo[0] +
5031                                  (clock_array_index * clock_info_array->ucEntrySize));
5032                         ci_parse_pplib_clock_info(rdev,
5033                                                   &rdev->pm.dpm.ps[i], k,
5034                                                   clock_info);
5035                         k++;
5036                 }
5037                 power_state_offset += 2 + power_state->v2.ucNumDPMLevels;
5038         }
5039         rdev->pm.dpm.num_ps = state_array->ucNumEntries;
5040
5041         /* fill in the vce power states */
5042         for (i = 0; i < RADEON_MAX_VCE_LEVELS; i++) {
5043                 u32 sclk, mclk;
5044                 clock_array_index = rdev->pm.dpm.vce_states[i].clk_idx;
5045                 clock_info = (union pplib_clock_info *)
5046                         &clock_info_array->clockInfo[clock_array_index * clock_info_array->ucEntrySize];
5047                 sclk = le16_to_cpu(clock_info->ci.usEngineClockLow);
5048                 sclk |= clock_info->ci.ucEngineClockHigh << 16;
5049                 mclk = le16_to_cpu(clock_info->ci.usMemoryClockLow);
5050                 mclk |= clock_info->ci.ucMemoryClockHigh << 16;
5051                 rdev->pm.dpm.vce_states[i].sclk = sclk;
5052                 rdev->pm.dpm.vce_states[i].mclk = mclk;
5053         }
5054
5055         return 0;
5056 }
5057
5058 static int ci_get_vbios_boot_values(struct radeon_device *rdev,
5059                                     struct ci_vbios_boot_state *boot_state)
5060 {
5061         struct radeon_mode_info *mode_info = &rdev->mode_info;
5062         int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
5063         ATOM_FIRMWARE_INFO_V2_2 *firmware_info;
5064         u8 frev, crev;
5065         u16 data_offset;
5066
5067         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
5068                                    &frev, &crev, &data_offset)) {
5069                 firmware_info =
5070                         (ATOM_FIRMWARE_INFO_V2_2 *)(mode_info->atom_context->bios +
5071                                                     data_offset);
5072                 boot_state->mvdd_bootup_value = le16_to_cpu(firmware_info->usBootUpMVDDCVoltage);
5073                 boot_state->vddc_bootup_value = le16_to_cpu(firmware_info->usBootUpVDDCVoltage);
5074                 boot_state->vddci_bootup_value = le16_to_cpu(firmware_info->usBootUpVDDCIVoltage);
5075                 boot_state->pcie_gen_bootup_value = ci_get_current_pcie_speed(rdev);
5076                 boot_state->pcie_lane_bootup_value = ci_get_current_pcie_lane_number(rdev);
5077                 boot_state->sclk_bootup_value = le32_to_cpu(firmware_info->ulDefaultEngineClock);
5078                 boot_state->mclk_bootup_value = le32_to_cpu(firmware_info->ulDefaultMemoryClock);
5079
5080                 return 0;
5081         }
5082         return -EINVAL;
5083 }
5084
5085 void ci_dpm_fini(struct radeon_device *rdev)
5086 {
5087         int i;
5088
5089         for (i = 0; i < rdev->pm.dpm.num_ps; i++) {
5090                 kfree(rdev->pm.dpm.ps[i].ps_priv);
5091         }
5092         kfree(rdev->pm.dpm.ps);
5093         kfree(rdev->pm.dpm.priv);
5094         kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries);
5095         r600_free_extended_power_table(rdev);
5096 }
5097
5098 int ci_dpm_init(struct radeon_device *rdev)
5099 {
5100         int index = GetIndexIntoMasterTable(DATA, ASIC_InternalSS_Info);
5101         u16 data_offset, size;
5102         u8 frev, crev;
5103         struct ci_power_info *pi;
5104         int ret;
5105         u32 mask;
5106
5107         pi = kzalloc(sizeof(struct ci_power_info), GFP_KERNEL);
5108         if (pi == NULL)
5109                 return -ENOMEM;
5110         rdev->pm.dpm.priv = pi;
5111
5112         ret = drm_pcie_get_speed_cap_mask(rdev->ddev, &mask);
5113         if (ret)
5114                 pi->sys_pcie_mask = 0;
5115         else
5116                 pi->sys_pcie_mask = mask;
5117         pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID;
5118
5119         pi->pcie_gen_performance.max = RADEON_PCIE_GEN1;
5120         pi->pcie_gen_performance.min = RADEON_PCIE_GEN3;
5121         pi->pcie_gen_powersaving.max = RADEON_PCIE_GEN1;
5122         pi->pcie_gen_powersaving.min = RADEON_PCIE_GEN3;
5123
5124         pi->pcie_lane_performance.max = 0;
5125         pi->pcie_lane_performance.min = 16;
5126         pi->pcie_lane_powersaving.max = 0;
5127         pi->pcie_lane_powersaving.min = 16;
5128
5129         ret = ci_get_vbios_boot_values(rdev, &pi->vbios_boot_state);
5130         if (ret) {
5131                 ci_dpm_fini(rdev);
5132                 return ret;
5133         }
5134
5135         ret = r600_get_platform_caps(rdev);
5136         if (ret) {
5137                 ci_dpm_fini(rdev);
5138                 return ret;
5139         }
5140
5141         ret = r600_parse_extended_power_table(rdev);
5142         if (ret) {
5143                 ci_dpm_fini(rdev);
5144                 return ret;
5145         }
5146
5147         ret = ci_parse_power_table(rdev);
5148         if (ret) {
5149                 ci_dpm_fini(rdev);
5150                 return ret;
5151         }
5152
5153         pi->dll_default_on = false;
5154         pi->sram_end = SMC_RAM_END;
5155
5156         pi->activity_target[0] = CISLAND_TARGETACTIVITY_DFLT;
5157         pi->activity_target[1] = CISLAND_TARGETACTIVITY_DFLT;
5158         pi->activity_target[2] = CISLAND_TARGETACTIVITY_DFLT;
5159         pi->activity_target[3] = CISLAND_TARGETACTIVITY_DFLT;
5160         pi->activity_target[4] = CISLAND_TARGETACTIVITY_DFLT;
5161         pi->activity_target[5] = CISLAND_TARGETACTIVITY_DFLT;
5162         pi->activity_target[6] = CISLAND_TARGETACTIVITY_DFLT;
5163         pi->activity_target[7] = CISLAND_TARGETACTIVITY_DFLT;
5164
5165         pi->mclk_activity_target = CISLAND_MCLK_TARGETACTIVITY_DFLT;
5166
5167         pi->sclk_dpm_key_disabled = 0;
5168         pi->mclk_dpm_key_disabled = 0;
5169         pi->pcie_dpm_key_disabled = 0;
5170
5171         /* mclk dpm is unstable on some R7 260X cards with the old mc ucode */
5172         if ((rdev->pdev->device == 0x6658) &&
5173             (rdev->mc_fw->size == (BONAIRE_MC_UCODE_SIZE * 4))) {
5174                 pi->mclk_dpm_key_disabled = 1;
5175         }
5176
5177         pi->caps_sclk_ds = true;
5178
5179         pi->mclk_strobe_mode_threshold = 40000;
5180         pi->mclk_stutter_mode_threshold = 40000;
5181         pi->mclk_edc_enable_threshold = 40000;
5182         pi->mclk_edc_wr_enable_threshold = 40000;
5183
5184         ci_initialize_powertune_defaults(rdev);
5185
5186         pi->caps_fps = false;
5187
5188         pi->caps_sclk_throttle_low_notification = false;
5189
5190         pi->caps_uvd_dpm = true;
5191         pi->caps_vce_dpm = true;
5192
5193         ci_get_leakage_voltages(rdev);
5194         ci_patch_dependency_tables_with_leakage(rdev);
5195         ci_set_private_data_variables_based_on_pptable(rdev);
5196
5197         rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries =
5198                 kzalloc(4 * sizeof(struct radeon_clock_voltage_dependency_entry), GFP_KERNEL);
5199         if (!rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries) {
5200                 ci_dpm_fini(rdev);
5201                 return -ENOMEM;
5202         }
5203         rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count = 4;
5204         rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].clk = 0;
5205         rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].v = 0;
5206         rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].clk = 36000;
5207         rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].v = 720;
5208         rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].clk = 54000;
5209         rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].v = 810;
5210         rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].clk = 72000;
5211         rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].v = 900;
5212
5213         rdev->pm.dpm.dyn_state.mclk_sclk_ratio = 4;
5214         rdev->pm.dpm.dyn_state.sclk_mclk_delta = 15000;
5215         rdev->pm.dpm.dyn_state.vddc_vddci_delta = 200;
5216
5217         rdev->pm.dpm.dyn_state.valid_sclk_values.count = 0;
5218         rdev->pm.dpm.dyn_state.valid_sclk_values.values = NULL;
5219         rdev->pm.dpm.dyn_state.valid_mclk_values.count = 0;
5220         rdev->pm.dpm.dyn_state.valid_mclk_values.values = NULL;
5221
5222         if (rdev->family == CHIP_HAWAII) {
5223                 pi->thermal_temp_setting.temperature_low = 94500;
5224                 pi->thermal_temp_setting.temperature_high = 95000;
5225                 pi->thermal_temp_setting.temperature_shutdown = 104000;
5226         } else {
5227                 pi->thermal_temp_setting.temperature_low = 99500;
5228                 pi->thermal_temp_setting.temperature_high = 100000;
5229                 pi->thermal_temp_setting.temperature_shutdown = 104000;
5230         }
5231
5232         pi->uvd_enabled = false;
5233
5234         pi->voltage_control = CISLANDS_VOLTAGE_CONTROL_NONE;
5235         pi->vddci_control = CISLANDS_VOLTAGE_CONTROL_NONE;
5236         pi->mvdd_control = CISLANDS_VOLTAGE_CONTROL_NONE;
5237         if (radeon_atom_is_voltage_gpio(rdev, VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_GPIO_LUT))
5238                 pi->voltage_control = CISLANDS_VOLTAGE_CONTROL_BY_GPIO;
5239         else if (radeon_atom_is_voltage_gpio(rdev, VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_SVID2))
5240                 pi->voltage_control = CISLANDS_VOLTAGE_CONTROL_BY_SVID2;
5241
5242         if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_VDDCI_CONTROL) {
5243                 if (radeon_atom_is_voltage_gpio(rdev, VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT))
5244                         pi->vddci_control = CISLANDS_VOLTAGE_CONTROL_BY_GPIO;
5245                 else if (radeon_atom_is_voltage_gpio(rdev, VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_SVID2))
5246                         pi->vddci_control = CISLANDS_VOLTAGE_CONTROL_BY_SVID2;
5247                 else
5248                         rdev->pm.dpm.platform_caps &= ~ATOM_PP_PLATFORM_CAP_VDDCI_CONTROL;
5249         }
5250
5251         if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_MVDDCONTROL) {
5252                 if (radeon_atom_is_voltage_gpio(rdev, VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_GPIO_LUT))
5253                         pi->mvdd_control = CISLANDS_VOLTAGE_CONTROL_BY_GPIO;
5254                 else if (radeon_atom_is_voltage_gpio(rdev, VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_SVID2))
5255                         pi->mvdd_control = CISLANDS_VOLTAGE_CONTROL_BY_SVID2;
5256                 else
5257                         rdev->pm.dpm.platform_caps &= ~ATOM_PP_PLATFORM_CAP_MVDDCONTROL;
5258         }
5259
5260         pi->vddc_phase_shed_control = true;
5261
5262 #if defined(CONFIG_ACPI)
5263         pi->pcie_performance_request =
5264                 radeon_acpi_is_pcie_performance_request_supported(rdev);
5265 #else
5266         pi->pcie_performance_request = false;
5267 #endif
5268
5269         if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
5270                                    &frev, &crev, &data_offset)) {
5271                 pi->caps_sclk_ss_support = true;
5272                 pi->caps_mclk_ss_support = true;
5273                 pi->dynamic_ss = true;
5274         } else {
5275                 pi->caps_sclk_ss_support = false;
5276                 pi->caps_mclk_ss_support = false;
5277                 pi->dynamic_ss = true;
5278         }
5279
5280         if (rdev->pm.int_thermal_type != THERMAL_TYPE_NONE)
5281                 pi->thermal_protection = true;
5282         else
5283                 pi->thermal_protection = false;
5284
5285         pi->caps_dynamic_ac_timing = true;
5286
5287         pi->uvd_power_gated = false;
5288
5289         /* make sure dc limits are valid */
5290         if ((rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk == 0) ||
5291             (rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk == 0))
5292                 rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc =
5293                         rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
5294
5295         return 0;
5296 }
5297
5298 void ci_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
5299                                                     struct seq_file *m)
5300 {
5301         struct ci_power_info *pi = ci_get_pi(rdev);
5302         struct radeon_ps *rps = &pi->current_rps;
5303         u32 sclk = ci_get_average_sclk_freq(rdev);
5304         u32 mclk = ci_get_average_mclk_freq(rdev);
5305
5306         seq_printf(m, "uvd    %sabled\n", pi->uvd_enabled ? "en" : "dis");
5307         seq_printf(m, "vce    %sabled\n", rps->vce_active ? "en" : "dis");
5308         seq_printf(m, "power level avg    sclk: %u mclk: %u\n",
5309                    sclk, mclk);
5310 }
5311
5312 void ci_dpm_print_power_state(struct radeon_device *rdev,
5313                               struct radeon_ps *rps)
5314 {
5315         struct ci_ps *ps = ci_get_ps(rps);
5316         struct ci_pl *pl;
5317         int i;
5318
5319         r600_dpm_print_class_info(rps->class, rps->class2);
5320         r600_dpm_print_cap_info(rps->caps);
5321         printk("\tuvd    vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
5322         for (i = 0; i < ps->performance_level_count; i++) {
5323                 pl = &ps->performance_levels[i];
5324                 printk("\t\tpower level %d    sclk: %u mclk: %u pcie gen: %u pcie lanes: %u\n",
5325                        i, pl->sclk, pl->mclk, pl->pcie_gen + 1, pl->pcie_lane);
5326         }
5327         r600_dpm_print_ps_status(rdev, rps);
5328 }
5329
5330 u32 ci_dpm_get_sclk(struct radeon_device *rdev, bool low)
5331 {
5332         struct ci_power_info *pi = ci_get_pi(rdev);
5333         struct ci_ps *requested_state = ci_get_ps(&pi->requested_rps);
5334
5335         if (low)
5336                 return requested_state->performance_levels[0].sclk;
5337         else
5338                 return requested_state->performance_levels[requested_state->performance_level_count - 1].sclk;
5339 }
5340
5341 u32 ci_dpm_get_mclk(struct radeon_device *rdev, bool low)
5342 {
5343         struct ci_power_info *pi = ci_get_pi(rdev);
5344         struct ci_ps *requested_state = ci_get_ps(&pi->requested_rps);
5345
5346         if (low)
5347                 return requested_state->performance_levels[0].mclk;
5348         else
5349                 return requested_state->performance_levels[requested_state->performance_level_count - 1].mclk;
5350 }